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Technical content
GROSS DIE PER 5 INCH WAFER 102,852 PROCESS CP388X Small Signal Transistor NPN - Low Noise Amplifier Transistor Chip Process EPITAXIAL PLANAR Die Size 13 x 13 MILS Die Thickness 5.9 MILS Base Bonding Pad Area 3.9 x 3.9 MILS Emitter Bonding Pad Area 5.4 x 5.4 MILS Top Side Metalization Al-Si - 17,000Å Back Side Metalization Au - 12,000Å BACKSIDE COLLECTOR R0 www.centralsemi.com R2 (29-April 2010)
Typical Electrical Characteristics www.centralsemi.com R2 (29-April 2010)