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Technical content
GROSS DIE PER 5 INCH WAFER 25,536 PROCESS CP382X Small Signal Transistor NPN - Low VCE(SAT) Transistor Chip PROCESS DETAILS Die Size 26 x 26 MILS Die Thickness 5.9 MILS Base Bonding Pad Area 5.5 x 5.5 MILS Emitter Bonding Pad Area 5.5 x 5.5 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 12,000Å www.centralsemi.com R0 (9-September 2010)
Typical Electrical Characteristics www.centralsemi.com R0 (9-September 2010)