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Technical content
GROSS DIE PER 4 INCH WAFER 1,462 PROCESS CP319 Power Transistor NPN - Silicon Power Transistor Chip Process EPITAXIAL PLANAR Die Size 87 x 87 MILS Die Thickness 9.0 MILS Base Bonding Pad Area 24 x 15 MILS Emitter Bonding Pad Area 38 x 16 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Ti/Ni/Ag - 11,000Å BACKSIDE COLLECTOR www.centralsemi.com R3 (22-March 2010)
Typical Electrical Characteristics www.centralsemi.com R3 (22-March 2010)