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Technical content
GROSS DIE PER 5 INCH WAFER 10,583 PROCESS CP314V Small Signal Transistor NPN - High Current Transistor Chip Process EPITAXIAL PLANAR Die Size 40 x 40 MILS Die Thickness 7.1 MILS Base Bonding Pad Area 7.9 x 8.7 MILS Emitter Bonding Pad Area 9.0 x 14 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au-As - 13,000Å www.centralsemi.com R1 (22-March 2010)
Typical Electrical Characteristics www.centralsemi.com R1 (22-March 2010)