CP210 CENTRAL | Alldatasheet
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Die Thickness 8.0 MILS Drain Bonding Pad Area 3.2 X 4.0 MILS Source Bonding Pad Area 3.2 X 4.0 MILS Gate Bonding Pad Area 3.2 X 4.0 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 6,000Å PROCESS DETAILS BACKSIDE GATE GEOMETRY
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Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (9 -September 2003) GROSS DIE PER 4 INCH WAFER 53,730 Central Semiconductor Corp. TM PROCESS CP210 Small Signal Transistors N - Channel Silicon Amplifer J FET Chip
Typical Electrical Characteristics 0 4 8 12 16 20 VDS, Drain-Source Voltage (V) VGS = 0V -0.5V -1.0V -1.5V -2.0V -2.5V -3.0V -3.5V -4.0V TA = 25°C TYP. VGS(OFF) = -5.0V 0.5 1.5 2.5 3.5 4.5 0 0.2 0.4 0.6 0.8 1 VDS, Drain-Source Voltage (V) -4.0V -3.5V -3.0V -2.5V -2.0V -1.5V VGS = 0V -0.5V -1.0VTA = 25°C TYP. VGS(OFF) = -5.0V 0.4 0.8 1.2 1.6 0 4 8 12 16 20 VDS, Drain-Source Voltage (V) VGS = 0V -0.1V -0.2V -0.3V -0.4V -0.5V -0.6V TA = 25°C TYP. VGS(OFF) = -1.2V 0.2 0.4 0.6 0.8 1.2 0 0.4 0.8 1.2 1.6 2 VDS, Drain-Source Voltage (V) TA = 25°C TYP. VGS(OFF) = -1.2V VGS = 0V -0.1V -0.2V -0.3V -0.4V -0.5V -0.6V 0.1 1 10 ID, Drain Current (mA) TA = -55°C TA = 25°C TA = 125°C VDG = 15V f = 1kHz VGS(OFF) = -5.0V Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (9 -September 2003) Central Semiconductor Corp. TM
Typical Electrical Characteristics 0 0.8 1.6 2.4 3.2 4 VGS, Gate-Source Voltage (-V) VGS(OFF) = -5.0V -1.2V VDS = 15V TA = 25°C -2.3V 100 200 300 400 500 600 700 800 900 -50 0 50 100 150 TA, Ambient Temperature (°C) VGS(OFF) = -1.2V -2.3V -5.0V VDS = 100mV VGS = 0 Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R3 (9 -September 2003) Central Semiconductor Corp. TM