CN809J

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Features

 Precise Reset Threshold: ±2.5%  CMOS Output(CN809/810) and Open Drain Output(CN803)  140ms min Reset Pulse Width  3.2µA Supply Current @VCC=3V  Guaranteed Reset Valid to VCC = +1.15V  Power Supply Transient Immunity  Operating Temperature Range -40°C to +85°C  Available in SOT23-3 Pin Assignment CN803 CN809 CN810 GND RESET (RESET) VCC SOT23-3 ( ) is for CN810 only

R e v 1 . 2 2 Device Function Reference Table: Part No. Reset threshold Reset active Low or High Output Type Marking CN809L 4.63V Low CMOS AAAA CN810L 4.63V High CMOS AGAA CN809M 4.38V Low CMOS ABAA CN810M 4.38V High CMOS AHAA CN809J 4.00V Low CMOS CWAA CN809T 3.08V Low CMOS ACAA CN803S 2.93V Low Open Drain ABC CN809S 2.93V Low CMOS ADAA CN810S 2.93V High CMOS AKAA CN803R 2.63V Low Open Drain ABD CN809R 2.63V Low CMOS AFAA Block Diagram Delay Generator 1.25V GND VCC RESET (RESET) OSC COMP VCC Fig.1 Block Diagram For CMOS Output

R e v 1 . 2 3 Pin Description Pin No. Symbol Description

1 GND Ground terminal

(CN809) CMOS Output . This output remains low if V CC drops below VRES, and for at least 140ms after V CC rises above VRES + VHYST . RESET (CN810) CMOS Output . This output remains high if V CC drops below VRES, and for at least 140ms after V CC rises above VRES + VHYST. (CN803) Open Drain Output . This output remains low if V CC drops below V RES, and for at least 140ms after V CC rises above VRES + VHYST . 3 VCC Analog Input . This pin is both the power supply to internal circuit and the voltage to be monitored. ABSOLUTE MAXIMUM RATINGS Terminal Voltage (With respect to GND) Input/Output Current Maximum Junction Temperature... +150°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

R e v 1 . 2 4 Electrical Characteristics (VCC=3V , TA= －40℃ to 85 ℃, Typical values are at TA=25℃, unless otherwise noted.) Parameters Symbol Test Conditions M i n T y p M a x U n i t Maximum input voltage VCCMAX 5.5 V Minimum input voltage VCCMIN 1.15 V VCC=2.0V 2 . 8 5 . 5 VCC=3.0V 3 . 2 6 Supply current IVCC VCC=5.0V 4 . 0 7 . 5 uA CN8__L 4.51 4.63 4.75 CN8__M 4.25 4.38 4.5 CN8__J 3.89 4.00 4.11 CN8__T 3.0 3.08 3.15 CN8__S 2.86 2.93 3.0 CN8__R 2.56 2.63 2.7 Reset Threshold VRES CN8__Z 2.26 2.32 2.38 V Reset Threshold hysteresis VHYST 0.013VRES V VCC to Delay(CN803/809) VCC transitions from VRES+0.1V to VRES－0.1V 20 us VCC to RESET Delay(CN810) VCC transitions from VRES+0.1V to VRES－0.1V 20 us VRES>VCC=2V ,ISINK=1.5mA 0.3 VRES>VCC=3V ,ISINK=3.2mA 0 . 3 Output V oltage Low (CN803/809) VOL VRES>VCC=4V ,ISINK=5mA 0 . 3 V VRES<VCC=3V ,ISRC=1.2mA V CC-0.4 VRES<VCC=4V ,ISRC=2mA V CC-0.4 Output V oltage High (CN809) VOH VRES<VCC=5V ,ISRC=2.5mA V CC-0.4 V VRES<VCC=3V ,ISINK=3.2mA 0 . 3 VRES<VCC=4V ,ISINK=5mA 0 . 3 RESET Output V oltage Low (CN810) V OL VRES<VCC=5V ,ISINK=6mA 0 . 3 V VRES>VCC=2V ,ISRC=600uA V CC-0.4 VRES>VCC=3V , ISRC=1.2mA V CC-0.4 RESET Output V oltage High (CN810) V OH VRES>VCC=4V , ISRC=2mA V CC-0.4 V Reset Pulse Width TRES 140 240 400 ms Note : Parts are 100% production tested at 25 oC. Specifications over full temperature range are guaranteed by design

R e v 1 . 2 5 Detailed Description A microprocessor’s (µP’s) reset input starts the µP in a known state. The CN803/809/810 series assert reset to prevent code-execution errors during power-up, power-down, or brownout conditions. The device consists of a comparator, a low current high precision voltage reference, voltage divider, output delay circuit and output driver. They assert a reset signal whenever the V CC supply voltage declines below a preset threshold, keeping it asserted for at least 140ms after VCC has risen above the reset threshold. The CN809/810 have a CMOS output stage, the CN803 has an open drain output stage. The CN803/809 have an active-low output, while the CN810 has an active-high RESET output. The reset comparator is designed to ignore fast transients on VCC, and the outputs are guaranteed to be in the correct logic state for VCC down to 1.15V over the temperature range. The operation of the device can be best understood by referring to figure 3. VCC RESET VRES VCCMIN VCCMIN TRES VRES + VHYST Fig.2 Timing waveform Applications Information Negative-Going VCC Transients In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, the CN803/809/810 series are relatively immune to short-duration negative-going VCC transients (glitches). As the magnitude of the transient increases (goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 10µs or less will not cause a reset pulse. A 0.1µF bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity. Ensuring a Valid Reset Output Down to VCC = 0 When VCC falls below 1.15V, the CN809 output no longer sinks current—it becomes an open circuit. Therefore, high-impedance CMOS logic inputs connected to can drift to undetermined voltages. This presents no problem in most applications, since most µP and other circuitry is inoperative with VCC below 1.15V. However, in applications where must be valid down to 0V, a pull-down resistor is needed from pin to GND as shown in Figure 4, then output will be held at low state. The resistor’s value is not critical, it should be about 100KΩ, large enough not to load

R e v 1 . 2 6 small enough to pull to ground. A 100KΩ pull-up resistor to V CC is also recommended for the CN810 if active high RESET is required to remain valid for VCC < 1.15V. RESET CN809 Fig.3 RESET Valid to Ground Circuit

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Package Information

Consonance Electronics does not assume any responsibility for use of any circuitry described. Consonance reserves the right to change the circuitry and specifications without notice at any time.