CN705

CN705 CONSONANCE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Low Power Microprocessor Supervisory Circuits CN705/706/707/708/813 Description： CN705/706/707/708/813 se ries is a fam ily of microprocessor (uP) supe rvisory circ uit that monitors microprocessor’s supply voltage and battery vo ltage. CN 705/706/707/708/813 series in tegrates u P re set c ircuit wi th 200 ms delay, W atchdog, m anual reset c ircuit a nd a power fail c omparator w ith 1.2 2V thresh old. These device s reduce syste m com plexity, hence improve system reliability. CN705/706/707/708/813 s eries has se veral functional op tions. Eac h de vice generates a reset si gnal when VCC is lower than reset threshold. I n ad dition, CN705, CN 706 a nd CN813 have a watchdog timer whose timeout period is 1.6 s. CN707 an d CN708 provide both active low and active high reset signals, but ha ve no w atchdog function. CN 813 are same as CN705/706 except active high reset is provided instead of active low. CN705/706/707/708/813 s eries is id eal for applications in automotive systems, computers, controllers and i ntelligent i nstruments. All devices are available in 8 pin DIP and 8 pin SOP package. Applications： z Computers z Controllers z Intelligent instruments z Automotive systems Features： z Guaranteed re set valid a t VCC=1.15V z Reset threshold can be from 2.6V to 5.0V with 0.1V step. z Low operating current: 52uA @5V z Reset pulse width: 200ms z Independent watchdog ti mer, 1.6s timeout(CN705/706/813) z Voltage monitor for power fail or low battery warning z Pin-to-pin c ompatible wi th in dustry standard 705/706/707/708/813 z Available in DIP8 and SOP8 Pin Assignment: PFO WDI VCC PFI MR GND CN705 CN706 CN813 4 5

8 WDO

(RESET) PFO NC VCC PFI MR GND CN707 CN708

8 RESET

R ev.1 1

Typical Application Circuit: PFO WDO WDI RESET MCU RESET I/O NMI INT VCC VCC PFI MR GND CN705/6/813 Figure 1 T ypical Application Circuit Device Function Reference Table Part No. Reset threshold Reset active Low or High Watchdog Function Operating Temperature CN705 4.65V Low Yes －40℃--85℃ CN707 4.65V Low and High No －40℃--85℃ CN813L 4.65V High Yes －40℃--85℃ CN706 4.4V Low Yes －40℃--85℃ CN708 4.4V Low and High No －40℃--85℃ CN813M 4.4V High Yes －40℃--85℃ CN706J 4.0V Low Yes －40℃--85℃ CN708J 4.0V Low and High No －40℃--85℃ CN813J 4.0V High Yes －40℃--85℃ CN706T 3.08V Low Yes －40℃--85℃ CN708T 3.08V Low and High No －40℃--85℃ CN813T 3.08V High Yes －40℃--85℃ CN706S 2.93V Low Yes －40℃--85℃ CN708S 2.93V Low and High No －40℃--85℃ CN813S 2.93V High Yes －40℃--85℃ CN706R 2.63V Low Yes －40℃--85℃ CN708R 2.63V Low and High No －40℃--85℃ CN813R (CN706P) 2.63V High Yes －40℃--85℃ Note: Please contact our sales office for other reset threshold from 2.6V to 5.0V R ev.1 2

Ordering Information: Ordering Code = Part No. + Package Code P: stands for DIP8 S: stands for SOP8 Refer to Device Function Reference Table on Page 2 Block Diagram: WDI Detector Watchdog Timer OSC RESET Generator1.22V 1.22V VCC PFI PFO GND VCC MR RESET (RESET) WDI WDO ( ) for CN813X and CN706P CN705 CN706 CN813 Figure 2 CN705/706/813 block Diagram R ev.1 3

1.22V 1.22V VCC PFI PFO GND VCC MR RESET CN707 CN708 RESET Figure 3 CN707/708 Block Diagram R ev.1 4

Pin Description： Pin No. CN705 CN706X CN707 CN708X CN813X CN706P Name Function Description 1 1 1 MR Manual r eset inp ut. Whe n vol tage a t is pulled low, a reset pulse will be triggered. The active low input has a pull up current. It can be driven by T TL or CMO S log ic as well as shorted to GND with a switch. 2 2 2 VCC Positive supply input 3 3 3 GND Negative supply input 4 4 4 PFI Power fail monitor i nput. When t he vol tage at PFI is bel ow 1.22V，PFO goes low . Connect PFI to GND or VCC when not used. 5 5 5 PFO Power fail monitor output. When the voltage at PFI is less than 1.22V, PFO goes low; otherwise PFO goes high. 6 6 WDI Watchdog in put. If WDI remai ns h igh or l ow for 1.6s , t he on chip w atchdog timer ru ns o ut and WD O goes l ow. Floating W DI or connecting WDI t o high impedance three state buffer disables watchd og fun ction. Th e watchdog tim er clears whene ver RESE T is asserted, or WDI is three stated, or WDI sees a rising or falling edge. 7 7 RESET Active low reset output. stays in low if VCC is lower than reset threshold; it remains in low for 200 ms after VCC becom es higher than reset t hreshold or goes fro m low to high.(Figure 5） 8 8 WDO Watchdog output. WDO go es low if w atchdog timer finishes its 1 .6s count, a nd will not g o high again until the watchdog timer is cl eared. Whenever VCC is below reset threshold, WDO stays low, and as soon as VCC rises above reset threshold, WDO goes high without delay. 8 7 RESET Active high reset output. RESET stays in high if VCC is lower than reset threshold; it remains in high for 200ms after VCC b ecomes hig her than reset t hreshold or goes fro m low to high.(Figure 5) R ev.1 5

Absolute Maximum Ratings： Terminal Voltage(With respect to GND)： Thermal Resistance (DIP8)………120 ℃/W Terminal Current Operating Temperature… ...－40℃ to 85℃ Stresses beyond those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Ra ting Conditions for extended periods may affect device reliability.

Electrical Characteristics

(VCC=5V, TA=－40℃ to 85℃, Typical values are measured at TA=25℃,unless otherwise noted) Parameters Symbol Test Conditions Min T yp Max Unit Operating V oltage Range VCC 1.15 5.5 V CN705/706X/813X 52 10 5 Supply Current IVCC CN707/708X 30 60 uA CN705/707/813L 4.5 4 .65 4. 75 CN706/708/813M 4.25 4.4 4.5 CN706J/708J/813J 3.9 4 .0 4. 1 CN706T/708T/813T 3.0 3.08 3 .15 CN706S/708S/813S 2.85 2 .93 3. 0 Reset Threshold VRES CN706P/706R/708R/813R 2.55 2 .63 2. 70 V Reset Thr eshold Hysteresis HVRES 0.01VRES V Reset Pulse Width tRES 140 20 0 28 0 ms VOH1 ISOURCE=800uA ISOURCE=8uA,VCC=1.2V VCC-1.2 1.0 V or RESET Output Voltage VOL1 ISINK=3.2mA ISINK=150uA,VCC=1.2V 0.3 0.3 V Watchdog t imeout period tWD 1 1.6 2.25 s VCC=5V 50 WDI Pulse Width tWP VCC<4.5V 120 ns Low 0 .16VCC VCC=5V 3.5 WDI Inpu t Threshold High VCC<4.5V 0.75VCC V R ev.1 6

Electrical Characteristics (Continued) Parameters Symbol Test Conditions Min. T yp. M ax. Unit WDI Pull up Resistance VCC>VRES 125 25 0 500 KΩ WDI Pull d own Resistance VCC>VRES 88 175 3 50 KΩ VOH2 ISOURCE=800uA VCC-1.2 WDO Ou tput Voltage VOL2 ISINK=3.2mA 0 .3 V VCC=5V 100 25 0 600 VCC=4V 60 152 3 60 uA VCC=3V 32 7 5 1 80 MR Pu ll up Current MR=0V VCC=2.5V 20 4 4 1 05 VCC=5V 150 MR Pulse Width TMR VCC<4.5V 500 ns Low 0 .8 VCC=5V High 2.0 Low 0.16VCC MR I nput Threshold VCC<4.5V High 0.65VCC V VCC=5V 250 MR’s Delay to RESET tMD VCC<4.5V 750 ns PFI I nput Threshold VPFI 1.184 1.22 1.256 V PFI Input Current IPFI 0 nA VOH3 ISOURCE=800uA VCC-1.2 PFO Ou tput Voltage VOL3 ISINK=3.2mA 0.3 V Note : Part s are 1 00% production t ested at 25oC. Specifi cations over ful l temperature range ar e guaranteed by 6-sigma statistical process control and by design R ev.1 7

Typical Operating Characteristics CN706 Operating Current vs. Temperature CN706 Operating Current vs. Operating Voltage -40 0-20 20 10040 60 80 Temperature Operating Current(uA) Operating Current(uA) Operating Voltage(V) 54.545 .520 3.52.5 32 +1.30V +1.20V PFI OV PFO PFI +5V PFO 300pF 1K +1.22V 300pF +1.22V PFI +5V 1KPFO PFO +1.30V PFI OV +1.20V Power-fail Comparator assertion Response Time Power-fail Comparator De-assertion Response Time 200ns/div400ns/div VCC=5V Detailed Description： CN705/706/707/708/813 series is a microprocessor supervisory circuit that monitors the p ower supply to digital circuits such as microprocessor, controller and memory . These devices assert reset during power up, power down or brownout condition to prevent code execution errors. RESET output On power up, once VC C r eaches 1.15V, CN705/ 706/707/708/813 se ries out put a reset si gnal . As VCC increases, the reset si gnal s tays va lid; When VCC r ises above rese t thresh old, an int ernal timer releases RESET ( ) after 200m s. RESET ( ) becomes valid once VCC dips below reset threshold during power down or in brownout condition. If brownout occurs in the middle of a previously initiated R ev.1 8

reset pulse, the pulse will continue for at least another 140ms. On power down , once VCC falls below reset threshold, RESET stays valid and is guaranteed in the correct logic state until VCC drops below 1.15V for the whole temperature range. Please refer to Figure 5. CN705/706 series provide active low signa l；CN707/708 series provide both active high and active low RESET signals；CN813 series provide active high RESET signal. Watchdog Timer CN705/706/813 series have an independent watchdog timer that can monitor uP’s activity. If uP does not toggle the watchdog input (WDI) within 1.6s and WDI is not three-stated, WDO g oes low. As long as RESET is asserted, or WDI is three-stated, or WDI is left floating, the watchdog timer stays cleared and will not count, in this case WDO is in high sta te. When VCC stays below reset threshold, WDO goes low whether or not the watchdog timer has timed out yet. Please refer to figure 4. Manual Reset Manual reset input allows reset signal to be triggered by push button or switch. The push button or switch is effectively debounced by 140ms minimum reset pulse width. is TTL/CMOS logic compatible. can be used to force a w atchdog timeout to generate a reset pulse in CN705/706/813 series by connecting WDO to Please refer to Figure 5. Power fail Comparator The power fail comparator can be used for various purpose because its output and noninverting input are not internally connected. The inverting input is internally connected to a 1.22V reference voltage. WDI WDO RESET RESET Note 1: RESET (RESET) is triggered by MR Note 2: RESET is for CN813X and CN706P only Figure 4 Watchdog Timing tWD tWD tWD tRES R ev.1 9

between the RESET output and the uP reset I/O as sh own in Fi gure 9. Buf fer the RESET output to other system components. RESET CN705/6/7/8 Figure 9 Interfacing to uPs with Bidirectional Reset I/O VCC 4.7K GND VCC GND RESET uP Buffered RESET to other system components R ev.1 1 2

Package Information

R ev.1 1 3

R ev.1 1 4