CMV20000

CMV20000 AMSOSRAM | Alldatasheet

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Technical content

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Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 4 / 69 CMV20000 20MP CMOS machine vision image sensor

1 General description

The CMV20000 is a global shutter CMOS image sensor with 5120 by 3840 pixels. The image array consists of 6.4μm x 6.4μm pipelined global shutter pixels, which allow exposure during read out while performing CDS operation. The image sensor has sixteen 12-bit digital LVDS outputs (serial). The image sensor also integrates a programmable gain amplifier and offset regulation. Each channel runs at 480 Mbps maximum which results in 30 fps frame rate at full resolution. Higher frame rates can be achieved in row-windowing mode or row-subsampling mode. These modes are all programmable using the SPI interface. A programmable on-board sequencer generates all internal exposure and read out timings. External triggering and exposure programming is possible. Extended optical dynamic range can be achieved by multiple integrated high dynamic range modes.

1.1 Key benefits & features

The benefits and features of CMV20000, 20MP CMOS machine vision image sensor are listed below: Table 1: Added value of using CMV20000 Benefits Features Capture fast moving objects Capture fast moving objects 8T global shutter pixel with true Correlated 8T global shutter pixel with true Correlated Double Sampling (true-CDS) Double Sampling (true-CDS)

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1.2 Applications

• Machine vision
• Video and broadcast
• High resolution display inspection
• Medical
• Scientific Information:
• The CMV20000 is not allowed to be used in traffic applications.

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1.3 Block diagram

The functional blocks of this device are shown below: Figure 1: Functional blocks of CMV20000 Active pixel area 5120 rows 3840 columns Analog front end (AFE) (gain, offset, ADCs) LVDS block (drivers, multiplexers) 8 outputs sequencer SPI Temp sensor Input clock SPI signals External driving signals Pixel (0,0) Pixel (4095,3071) Analog front end (AFE) (gain, offset, ADCs) LVDS block (drivers, multiplexers) 8 outputs

Ordering information

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2 Ordering information

Product type/Marking Ordering code Mono/color Glass type Package Delivery quantity CMV20000-1E5M1PA Q65114A0051 Mono AR coating PGA 10 pcs/reel CMV20000-1E5C1PA Q65114A0050 Color AR coating PGA 10 pcs/tray Figure 2: Product type description

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3 Pin assignment

3.1 Pin diagram

Figure 3: Pin diagram of CMV20000 TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A B C D E F G H J K L M N P R T

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3.2 Pin description

Table 2: Pin description of CMV20000 Pin Pin name Pin type Description A2 OUTE1_P LVDS Output LVDS positive output data even rows channel1 bottom A3 VDD20 Supply Digital blocks A4 OUTE2_P LVDS Output LVDS positive output data even rows channel2 bottom A5 VDD20 Supply Digital blocks A6 OUTE3_P LVDS Output LVDS positive output data even rows channel3 bottom A7 VDDPIX Supply Pixel array power supply A8 OUTE4_P LVDS Output LVDS positive output data even rows channel4 bottom A9 GND Ground Ground pin A10 OUTE5_N LVDS Output LVDS negative output data even rows channel5 bottom A11 VDD20 Supply Digital blocks A12 OUTE6_N LVDS Output LVDS negative output data even rows channel6 bottom A13 VDDPIX Supply Pixel array power supply A14 OUTE7_N LVDS Output LVDS negative output data even rows channel7 bottom A15 GND Ground Ground pin A16 OUTE8_N LVDS Output LVDS negative output data even rows channel8 bottom A17 VDD20 Supply Digital blocks A18 CMD_LVDS Bias Decouple with 470 nF to ground B1 DIO2 Test Diode 2 for test (connect to GND) B2 OUTE1_N LVDS Output LVDS negative output data even rows channel1 bottom B3 GND Ground Ground pin B4 OUTE2_N LVDS Output LVDS negative output data even rows channel2 bottom B5 GND Ground Ground pin B6 OUTE3_N LVDS Output LVDS negative output data even rows channel3 bottom B7 GND Ground Ground pin B8 OUTE4_N LVDS Output LVDS negative output data even rows channel4 bottom B9 VDD33 Supply Digital and analog B10 OUTE5_P LVDS Output LVDS positive output data even rows channel5 bottom B11 GND Ground Ground pin B12 OUTE6_P LVDS Output LVDS positive output data even rows channel6 bottom B13 GND Ground Ground pin B14 OUTE7_P LVDS Output LVDS positive output data even rows channel7 bottom B15 VDD33 Supply Digital and analog

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 10 / 69 Pin Pin name Pin type Description B16 OUTE8_P LVDS Output LVDS positive output data even rows channel8 bottom B17 GND Ground Ground pin B18 CMD_COL_AMPL Bias Decouple with 470 nF to ground C1 TANA Analog Output Test pin for analog signals (can be left floating) C2 OUTCTR_N LVDS Output LVDS negative control output channel C3 DIO1 Test Diode 1 for test (connect to GND) C16 GND Ground Ground pin C17 CMDN Bias Decouple with 470 nF to ground C18 CMD_COL_PC Bias Decouple with 470 nF to ground D1 TDIG2 Digital Output Test pin for digital signals (can be left floating or route to an input pin of the FPGA) D2 OUTCTR_P LVDS Output LVDS positive control output channel D3 TDIG1 Digital Output Test pin for digital signals (can be left floating or route to an input pin of the FPGA) D16 CMDP Bias Decouple with 470 nF to VDD33 D17 CMDP_INV Bias Decouple with 470 nF to VDD33 D18 CMD_ADC Bias Decouple with 470 nF to VDD33 E1 Extra1 Leave floating E2 Extra2 Connect to GND E3 FRAME_REQ Digital Input Frame request E16 VBGAP Bias Decouple with 470 nF to VBGAP_LOW E17 VBGAP_LOW Bias Decouple to VBGAP see pin E16 E18 CMD_COL_LOAD Bias Decouple with 470 nF to ground F1 STRB_EXP1 Digital Output Output strobe pin for the exposure time F2 VDD20 Supply Digital blocks F3 GND Ground Ground pin F16 GND Ground Ground pin F17 VDD20 Supply Digital blocks F18 REF_ADC Bias Ref for ADC testing (decouple with 470 nF to ground) G1 VDDPIX Supply Pixel array power supply G2 GND Ground Ground pin G3 VDD33 Supply Digital and analog G16 VDD33 Supply Digital and analog G17 GND Ground Ground pin G18 VDDPIX Supply Pixel array power supply H1 Extra6 Connect to GND

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 11 / 69 Pin Pin name Pin type Description H2 T_EXP1 Digital Input Input pin for external exposure mode H3 GND Ground Ground pin H16 GND Ground Ground pin H17 VREF Bias Ref for column amps (decouple with 470 nF to ground) H18 CMD_RAMP Bias Decouple with 470 nF to VDD33 J1 PLL_REF Bias Decouple with 470 nF to PLL_REF_LOW J2 PLL_REF_LOW Bias Decouple to PLL_REF see pin J1 J3 GND Ground Ground pin J16 GND Ground Ground pin J17 VRAMP2 Bias Start voltage second ramp (decouple with 470 nF to ground) J18 VRAMP1 Bias Start voltage first ramp (decouple with 470 nF to ground) K1 VDDPIX Supply Pixel array power supply K2 GND Ground Ground pin K3 VDD33 Supply Digital and analog K16 VDD33 Supply Digital and analog K17 GND Ground Ground pin K18 VDDPIX Supply Pixel array power supply L1 LVDS_CLK_P LVDS Input LVDS input clock P L2 VDD20 Supply Digital blocks L3 GND Ground Ground pin L16 GND Ground Ground pin L17 VDD20 Supply Digital blocks L18 SIG_ADC Bias Sig for ADC testing (decouple with 470 nF to ground) M1 LVDS_CLK_N LVDS Input LVDS input clock N M2 CLK_IN Digital Input Master input clock M3 SYS_RES_N Digital Input Input pin for sequencer reset M16 VTF_LOW3 Bias Transfer low voltage 3 (decouple with 470 nF to ground) M17 VTF_LOW2 Bias Transfer low voltage 2 (decouple with 470 nF to ground) M18 VTF_LOW1 Bias Transfer low voltage 1 (decouple with 470 nF to ground) N1 Extra3 Connect to GND N2 OUTCLK_P LVDS Output LVDS positive clock output channel N3 Extra4 Connect to GND N16 VRES_L Bias Res low voltage (decouple with 470 nF to ground) N17 VRES_H Supply Pixel reset pulse N18 VPCH_L Bias Precharge low voltage (decouple with 470 nF to ground)

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 12 / 69 Pin Pin name Pin type Description P1 SPI_EN Digital Input SPI enable P2 OUTCLK_N LVDS Output LVDS negative clock output channel P3 SPI_IN Digital Input SPI data input pin P16 GND Ground Ground pin P17 GND Ground Ground pin P18 VPCH_H Bias Precharge high voltage (decouple with 470 nF to ground) R1 SPI_CLK Digital Input SPI clock input pin R2 OUTO1_N LVDS Output LVDS negative output data odd rows channel1 top R3 GND Ground Ground pin R4 OUTO2_N LVDS Output LVDS negative output data odd rows channel2 top R5 GND Ground Ground pin R6 OUTO3_N LVDS Output LVDS negative output data odd rows channel3 top R7 GND Ground Ground pin R8 OUTO4_N LVDS Output LVDS negative output data odd rows channel4 top R9 VDD33 Supply Digital and analog R10 OUTO5_P LVDS Output LVDS positive output data odd rows channel5 top R11 GND Ground Ground pin R12 OUTO6_P LVDS Output LVDS positive output data odd rows channel6 top R13 GND Ground Ground pin R14 OUTO7_P LVDS Output LVDS positive output data odd rows channel7 top R15 VDD33 Supply Digital and analog R16 OUTO8_P LVDS Output LVDS positive output data odd rows channel8 top R17 GND Ground Ground pin R18 SPI_OUT_RIGHT Digital Output SPI data output pin at the right, this is a backup SPI data output pin. Only the SPI output data of register >= address 103 is available at this pin. Should be routed to the FPGA as well T1 SPI_OUT_LEFT Digital Output SPI data output pin at the left, this is the main SPI data output pin containing the SPI output data of all registers. T2 OUTO1_P LVDS Output LVDS positive output data odd rows channel1 top T3 VDD20 Supply Digital blocks T4 OUTO2_P LVDS Output LVDS positive output data odd rows channel2 top T5 VDD20 Supply Digital blocks T6 OUTO3_P LVDS Output LVDS positive output data odd rows channel3 top T7 VDDPIX Supply Pixel array power supply T8 OUTO4_P LVDS Output LVDS positive output data odd rows channel4 top T9 GND Ground Ground pin

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 13 / 69 Pin Pin name Pin type Description T10 OUTO5_N LVDS Output LVDS negative output data odd rows channel5 top T11 VDD20 Supply Digital blocks T12 OUTO6_N LVDS Output LVDS negative output data odd rows channel6 top T13 VDDPIX Supply Pixel array power supply T14 OUTO7_N LVDS Output LVDS negative output data odd rows channel7 top T15 GND Ground Ground pin T16 OUTO8_N LVDS Output LVDS negative output data odd rows channel8 top T17 VDD20 Supply Digital blocks T18 Extra5 Connect to GND

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4 Absolute maximum ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3: Absolute maximum ratings of CMV20000 Symbol Parameter Min Max Unit Comments Electrical parameters VDD20 Digital blocks 1.7 2.2 V VDD33 Digital and analog 2.9 3.6 V VDDPIX Pixel array power supply 2.6 3.6 V VRES_H Pixel reset power 2.9 3.6 V ISCR Input current (latch-up immunity) ± 100 mA JEDEC JESD78D Nov 2011 Electrostatic discharge ESDHBM Electrostatic discharge HBM ± 2000 V JS-001-2012 Temperature ranges and storage conditions TA Operating ambient temperature -20 70 °C TSTRG Storage temperature range -20 50 °C RHNC Relative humidity (non-condensing) 60 % MSL Moisture sensitivity level 3 Represents a maximum floor time of 168h

Electrical characteristics

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5 Electrical characteristics

All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Table 4: Electrical characteristics of CMV20000 Symbol Parameter Conditions Min Typ Max Unit Power supplies VDD20 Digital blocks 2.0 2.1 2.2 V VDD33 Digital and analog 3.2 3.3 3.4 V VDDPIX Pixel array power supply 2.9 3.0 3.1 V VRES_H Pixel reset pulse 3.2 3.3 3.4 V IDD20 Supply current Normal Peak 800 1000 mA IDD33 Supply current Normal Peak 170 600 mA IDDPIX Supply current Normal Peak 20 8000 mA IRES_H Supply current Normal Peak 5 100 mA Ptot Total power consumption 1100 mW Digital I/O VIH High level input voltage 2.0 VDD33 V VIL Low level input voltage GND 0.8 V VOH High level output voltage VDD33 = 3.3 V IOH = 2 mA 2.4 V VOL Low level output voltage VDD33 = 3.3 V IOL = 2 mA 0.4 V fCLK_IN CLK_IN frequency 10 40 MHz fLVDS_CLK LVDS_CLK frequency 120 480 MHz DCLVDS_CLK LVDS_CLK duty cycle 45 50 55 % fSPI_CLK SPI_CLK frequency 20 MHz LVDS receiver VID Differential input voltage Steady state 100 350 600 mV VIC Receiver input range Steady state 0.0 2.4 V IID Receiver input current VINP|INN=1.2 V±50 mV, 0 ≤ VINP|INN ≤ 2.4V 20 µA ΔIID Receiver input current difference |IINP-IINN| 6 µA

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 16 / 69 Symbol Parameter Conditions Min Typ Max Unit LVDS driver VOD Differential output voltage Steady Stage, RL = 100 Ω 247 350 454 mV ΔVOD Difference in VOD between complementary output states Steady Stage, RL = 100 Ω 50 mV VOC Common mode voltage Steady Stage, RL = 100 Ω 1.125 1.25 1.375 V ΔVOC Difference in VOC between complementary output states Steady Stage, RL = 100 Ω 50 mV IOS,GND Output short circuit current to ground VOUTP = VOUTN = GND 24 mA IOS,PN Output short circuit current VOUTP = VOUTN 12 mA

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6 Typical operating characteristics

6.1 Electro-optical characteristics

Below are the typical electro-optical specifications of the CMV20000. These are the typical values for the whole operating range. Table 5: Specification overview Parameter Value Remark Effective pixels 5120 x 3840 Pixel pitch 6.4 µm x 6.4 µm Optical size 32.77 mm x 24.58 mm Full frame Pixel type Global Shutter with true CDS Allows fixed pattern noise correction and reset (kTC) noise cancelling by true correlated double sampling Shutter type Pipelined global shutter Exposure of next image during readout of the previous image Full well charge 15000 e- Pinned photodiode pixel Conversion gain 0.25 DN/e- At recommended settings Responsivity 0.29 A/W @ 550 nm with micro lenses Temporal noise 8 e- Pipelined global shutter (GS) with correlated double sampling (CDS) Dynamic range 66 dB SNRMAX 41.8 dB PLS 1/50000 DC 125 e-/s At room temperature FPN < 0.2% RMS of full swing DSNU 10 e-/s PRNU 1% RMS Color filters Optional RGB Bayer QE 64,5% @ 550 nm with micro lenses LVDS outputs 16 Each data output running at 480 Mbit/s. 8 outputs selectable at half frame rate. Frame rate 30 fps Using a 12-bit/pixel and 480 Mbit/s LVDS. Higher frame rate possible in row windowing mode. Timing generation On-chip Possibility to control exposure time through external pin. PGA Yes 4 analog gain settings

Typical operating characteristics Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 18 / 69 Parameter Value Remark Programmable registers Sensor parameters Window coordinates, timing parameters, gain & offset, exposure time, flipped readout in X and Y direction. HDR mode Multi-slope Multiple slopes with partial reset of the pixel. ADC 12-bit Column ADC Interface LVDS Serial output data + synchronization signals I/O Logic levels LVDS = 2.1 V Logic levels = 3.3 V Cover glass D263Teco 2 sides AR coating, no IR cut-off filter R < 2.2% abs, 400 nm – 900 nm, per surface, AOI = 15°

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6.2 Spectral characteristics

Figure 4: Quantum efficiency Figure 5: Spectral response 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Spectral Response [A\\W] Wavelength [nm] BLUE GREEN1 GREEN2 RED Mono

Typical operating characteristics Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 20 / 69 Figure 6: Angular response

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7 Functional description

7.1 Sensor architecture

Figure 1 shows the image sensor architecture. The internal sequencer generates the necessary signals for image acquisition. The image is stored in the pixel (global shutter) and they are read out sequentially, row-by-row into the analog front-end electronics (AFE) of the 1.9, 2.25, 2.55 when column calibration is on). The pixel value then passes to a column ADC cell, in which ADC conversion is performed. The digital signals are then read out over multiple LVDS channels. Each LVDS channel reads out 640 adjacent columns of the array. The AFE and LVDS drivers are doubled on opposite sides of the sensor, resulting in 2 rows being read out at the same when all 16 outputs are used. In the Y-direction, rows of interest are selected through a row-decoder which allows a flexible windowing. Control registers are foreseen for the programming of the sensor. These register parameters are uploaded via a four-wire SPI interface. A temperature sensor which can be read out over the SPI interface is also included.

7.1.1 Pixel array

The sensor has 5120 by 3840 active pixels with a 6.4 µm pitch surrounded by two dummy rows and columns. These dummy pixels at the side will ensure that the optical performance of the active pixels at the edge, is the same as the one in the active array. These dummy pixels cannot be read out and will be set permanently to the reset voltage. The pixels are designed to achieve maximum sensitivity with low noise and low PLS specification. Micro lenses are placed on top of the pixels for improved fill factor and quantum efficiency.

7.1.2 Analog front-end electronics (AFE)

The analog front-end consists of two major parts: a column amplifier block and a column ADC block. The column amplifier prepares the pixel signal for the column ADC and applies analog gain if desired (programmable using the SPI interface). The column ADC converts the analog pixel value to a 12-bit value and can adjust its ramp to compensate for small gain differences. All gain and offset settings can be programmed using the SPI interface.

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7.1.3 LVDS block

The LVDS block converts the digital data coming from the ADC into standard LVDS data running at maximum 480 Mbps. The sensor has 18 LVDS output pairs.

• 16 data channels
• 1 control channel
• 1 clock channel The 16 data channels are used to transfer 12-bit data words from sensor to receiver. The output clock channel transports a DDR clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving end to sample the data. The data on the control channel contains status information on the validity of the data on the data channels and other useful sensor status information.

7.1.4 Sequencer

The on-chip sequencer will generate all required control signals to operate the sensor from only a few external control clocks. This sequencer can be activated and programmed through the SPI interface.

7.1.5 SPI

The SPI interface is used to load the sequencer registers with data. The data in these registers is used by the sequencer while driving and reading out the image sensor. Features like windowing, sub sampling, gain and offset are programmed using this interface. The data in the on-chip registers can also be read back for test and debug of the surrounding system.

7.1.6 Temperature sensor

A 16-bit digital temperature sensor is included in the image sensor and can be controlled by the SPI interface. The on-chip temperature can be obtained by reading out a dedicated SPI register (address 101-102). A calibration of the temperature sensor is needed by the surrounding system (for absolute temperature measurements).

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7.2 Operating the sensor

7.2.1 Power supplies

7.2.1.1 External power supplies

The peak current of VDD20 is drawn during read out, while the other supplies draw it during FOT. All supplies should have enough decoupling, especially VDDPIX. Also, VDD18 switches a lot of power per LVAL and should be equipped with a decent supply and decoupling. Noise on the VDD33 will be transferred to the image as row noise, so keep this supply as ‘clean’ as possible.

7.2.1.2 Biasing

For optimal performance, some pins need to be decoupled to ground or to VDD. Please refer to the pin list for a detailed description for every pin and the appropriate decoupling if applicable.

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7.2.2 Startup sequence

The following sequence should be followed when the device is started up in default output mode (480 Mbps, 12-bit resolution). Figure 7: Startup sequence for 480 Mbps @12-bit The CLK_IN and LVDS_CLK_N/P should only start after the rise time of the supplies (VDD33, VDD20, VDDPIX and VRES_H go high together). The external reset pin should be released at least 1μs after the supplies have become stable. The first frame can be requested 1 μs after the reset pin has been released. An optional SPI upload (to program the sequencer) is possible 1 μs after the reset pin has been released. In this case the FRAME_REQ pulse must be postponed until after the SPI upload has been completed. 1μs 1μs Stable time Supply CLK_IN SYS_RES_N FRAME_REQ

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7.2.3 Reset sequence

If a sensor reset is necessary while the sensor is running, the following sequence should be followed. Figure 8: Reset sequence The on-board sequencer will be reset and all programming registers will return to their default start-up values when a falling edge is detected on the SYS_RES_N pin. After the reset there is a minimum time of 1 μs needed before a FRAME_REQ pulse can be sent. All recommended register settings must be reloaded after a reset sequence.

7.2.4 SPI programming

Programming the sensor is done by writing the appropriate values to the on-board registers. These registers can be written over a simple serial interface (SPI). The details of the timing and data format are described below. The data written to the programming registers can also be read out over this same SPI interface. The SPI out does not have a tri-state, so multiple SPI outputs cannot be on the same bus without a buffer. 1μs CLK_IN SYS_RES_N FRAME_REQ

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7.2.4.1 SPI write

The timing to write data over the SPI interface can be found below. Figure 9: SPI write The data is sampled by the device on the rising edge of the SPI_CLK. The SPI_CLK has a maximum frequency of 20 MHz. The SPI_EN signal has to be high for half a clock period before the first data bit is sampled. SPI_EN has to remain high for 1 clock period after the last data bit is sampled. One write action contains 16 data bits:

• One control bit: First bit to be sent, indicates whether a read (‘0’) or write (‘1’) will occur on the SPI interface.
• 7 address bits: These bits form the address of the programming register that needs to be written. The address is sent MSB first.
• 8 data bits: These bits form the actual data that will be written in the register selected with the address bits. The data is written MSB first. When several sensor registers need to be written, the timing above can be repeated with SPI_EN remaining high all the time. See the figure below for an example of 2 registers being written in burst. Figure 10: SPI write of 2 registers in burst The sample and hold time is 1/4th of the SPI clock period. SPI_EN SPI_IN SPI_CLK C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ½ CLK 1 CLK SPI_EN SPI_IN SPI_CLK C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C=’1' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ½ CLK 1 CLK

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7.2.4.2 SPI read

The timing to read data from the registers over the SPI interface can be found below. Figure 11: SPI read To indicate a read action over the SPI interface, the control bit on the SPI_IN pin is made ‘0’. The address of the register being read out is sent immediately after this control bit (MSB first). After the LSB of the address bits, the data is launched on the SPI_OUT pin on the falling edge of the SPI_CLK. This means that the data should be sampled by the receiving system on the rising edge of the SPI_CLK. The data comes over the SPI_OUT with MSB first. The device has two SPI read out pins: SPI_OUT_LEFT (pin T1) and SPI_OUT_RIGHT (pin R18). SPI_OUT_LEFT will read out every register, while SPI_OUT_RIGHT will only read out registers 103 to 126. Because of the large sensor there is some SPI read out delay. This delay is fixed and independent of the sensor or SPI clock. Figure 12: SPI delay SPI_EN SPI_IN SPI_CLK C=’0' A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0SPI_OUT ½ CLK 1 CLK

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 28 / 69 Therefore, when sampling on the rising SPI_CLK edge it is advised to have a SPI_CLK of 10 MHz maximum.

7.2.5 Requesting a frame

After starting up the sensor (see section 7.2.2), a number of frames can be requested by sending a FRAME_REQ pulse. The number of frames can be set by programming the appropriate register (addresses 22 and 23). The default number of frames to be grabbed is 1. In internal exposure mode, the exposure time will start after this FRAME_REQ pulse. In the external exposure mode, the read-out will start after the FRAME_REQ pulse. Both modes are explained into detail in the sections below.

7.2.5.1 Internal exposure control

In this mode, the exposure time is set by programming the appropriate registers (address 32- 33) of the device. After the high state of the FRAME_REQ pulse is detected, the exposure time will start immediately. When the exposure time ends (as programmed in the registers), the pixels are being sampled and prepared for read-out. This sequence is called the frame overhead time (FOT). Immediately after the FOT, the frame is read out automatically. If more than one frame is requested, the exposure of the next frame starts already during the read-out of the previous one. See the diagram below for more details. Figure 13: Internal exposure request for 2 frames When the exposure time is shorter than the read-out time, the FOT and read-out of the next frame will start immediately after the read-out of the previous frame. FRAME_REQ Exposure timeFrame1_cycle FOT Read-out time Exposure timeFrame2_cycle FOT Read-out time

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 29 / 69 Figure 14: Internal exposure request for 2 frames with exposure time < read-out time

7.2.5.2 External exposure mode

The exposure time can also be programmed externally by using the T_EXP1 input pin. This mode needs to be enabled by setting the appropriate register (address 81). In this case, the exposure starts when a high state is detected on the T_EXP1 pin. When a high state is detected on the FRAME_REQ input, the exposure time stops and the read-out will start automatically. A new exposure can start by sending a pulse to the T_EXP1 pin during or after the read-out of the previous frame. Figure 15: External exposure request for 2 frames FRAME_REQ Frame1_cycle FOT Read-out time Exposure timeFrame2_cycle FOT Read-out time Exposure time FRAME_REQ Exposure timeFrame1_cycle FOT Read-out time Exposure timeFrame2_cycle FOT Read-out time T_EXP1

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7.3 Sensor readout formats

7.3.1 LVDS outputs

The device has LVDS (low voltage differential signaling) outputs to transport the image data to the surrounding system. Next to 16 data channels, the sensor also has two other LVDS channels for control and synchronization of the image data. In total, the sensor has 18 LVDS output pairs (2 pins for each LVDS channel):

• 16 Data channels
• 1 Control channel
• 1 Clock channel This means that a total of 36 pins of the device are used for the LVDS outputs (32 for data + 2 for LVDS clock + 2 for control channel). See the pin list for the exact pin numbers of the LVDS outputs. The 16 data channels are used to transfer the 12-bit pixel data from the sensor to the receiver in the surrounding system. The output clock channel transports a clock, synchronous to the data on the other LVDS channels. This clock can be used at the receiving end to sample the data. This clock is a DDR clock which means that the frequency will be half of the output data rate. When 480 Mbps output data rate is used, the LVDS output clock will be 240 MHz. The data on the control channel contains status information on the validity of the data on the data channels. Information on the control channel is grouped in 12-bit words that are transferred synchronous to the 16 data channels.

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7.3.2 Low-level readout format

The figure below shows the timing for transfer of 12-bit pixel data over one LVDS output. The figure shows only the p-channel of each LVDS pair. The data is transferred LSB first, with the transfer of bit D[0] during the high phase of the DDR output clock. Figure 16: 12-bit pixel data on an LVDS channel The time T1 in the diagram above is 1/12th of the period of the input clock (CLK_IN) of the device. If a frequency of 40 MHz is used for CLK_IN (max), this results in a 240 MHz LVDS_CLOCK_OUT.

7.3.3 Pixel readout format

The readout of image data is grouped in bursts of 640 pixels per channel (2 rows at the same time). Each pixel is 12 bits of data. One complete pixel period equals one period of the master clock input. An overhead time exists between two bursts of 640 pixels. This overhead time has the length of one pixel read-out (i.e. the length of 12 bits at the selected data rate) or one master clock cycle. LVDS_CLOCK_OUT DATA_OUT D(10) D(11) D(0) D(1) D2) D(3)

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 32 / 69 7.3.3.1 16 outputs By default, all 16 data output channels are used to transmit the image data. This means that two entire rows of image data are transferred in one slot of 640 pixel periods (16/2 x 640 = 5120). Figure 17 shows the timing for the top and bottom LVDS channels. Figure 17: Data output timing with 16 channels Only when 16 data outputs, running at 480 Mbps, are used, the frame rate of 30 fps can be achieved (default). 7.3.3.2 8 output channels The device has the possibility to use only 8 LVDS output channels. This setting can be programmed in the register with address 80 (see section 7.5.1). In such multiplexed output mode, only the 8 bottom LVDS channels are used. The readout of one row takes 1*640 periods. This means that the entire rows of image data are transferred in one slot of 640 pixel periods (8 x 640 = 5120). Figure 18shows the timing for the bottom LVDS channels. Figure 18: Data output timing with 8 channels In this 8 channel mode, the frame rate is reduced with a factor of 2 compared to 16 channel mode. IDLE OH 640 OH DATA_OUT_TOP

640 OH 640

DATA_OUT_BOTTOM DATA_OUT_BOTTOM

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7.3.4 Pixel remapping

Depending on the number of output channels, the pixels are read out by different channels and come out at a different moment in time. With the details from the next sections, the end user is able to remap the pixel values at the output to their correct image array location. 7.3.4.1 16 outputs Figure 19 shows the location of the image pixels versus the output channel of the image sensor. 16 bursts (8 x 2) of 640 pixels happen in parallel on the data outputs. This means that two complete rows are read out in one burst. The amount of rows that will be read out depends on the value in the corresponding register. By default, there are 3840 rows being read out. Figure 19: Pixel mapping using 16 output channels IDLE Pixel 0 to 639Channel 1 bot IDLE Pixel 0 to 639 Channel 2 bot Pixel 640 to 1279 Pixel 640 to 1279 Row 0 IDLEChannel 8 bot Pixel 4480 to 5119 Pixel 4480 to 5119 Row 2 IDLE Pixel 0 to 639Channel 1 top IDLE Pixel 0 to 639 Channel 2 top Pixel 640 to 1279 Pixel 640 to 1279 Row 1 IDLEChannel 8 top Pixel 4480 to 5119 Pixel 4480 to 5119 Row 3 … …… … ……

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 34 / 69 7.3.4.2 8 outputs When only 8 outputs are used, the pixel data is placed on the outputs as detailed in the figure below. 8 bursts of 640 pixels happen in parallel on the data outputs. This means that one complete row is read out in one burst. The time needed to read out two rows is doubled compared to when 16 outputs are used. The top LVDS channels are not being used in this mode, so they can be turned off by setting the correct bits in the register with address 95-97. Turning off these channels will reduce the power consumption of the chip. The amount of rows that will be read out depends on the value in the corresponding register. By default, there are 3840 rows being read out. Figure 20: Pixel mapping using 8 output channels IDLE Pixel 0 to 639Channel 1 bot IDLE Pixel 0 to 639 Channel 2 bot Pixel 640 to 1279 Pixel 640 to 1279 Row 0 IDLEChannel 8 bot Pixel 4480 to 5119 Pixel 4480 to 5119 Row 1 … ……

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7.3.5 Control channel

The device has one LVDS output channel dedicated for the valid data synchronization and timing of the output channels. The end user must use this channel to know when valid image data or training data is available on the data output channels. The control channel transfers status information in 12-bit word format. Every bit of the word has a specific function. Next figure describes the function of the individual bits. Table 6: Control channel status bits Bit Function Description [0] DVAL Indicates valid pixel data on the outputs [1] LVAL Indicates validity of the readout of a row [2] FVAL Indicates the validity of the readout of a frame [3] ‘0’ Constant zero [4] ‘0’ Constant zero [5] FOT Indicates when the sensor is in FOT (sampling of image data in pixels)(1) [6] INTE1 Indicates when pixels of integration block 1 are integrating(1) [7] INTE2 Indicates when pixels of integration block 2 are integrating(1) [8] ‘0’ Constant zero [9] ‘1’ Constant one [10] ‘0’ Constant zero [11] ‘0’ Constant zero (1) The status bits are purely informational. These bits are not required to know when the data is valid. The DVAL, LVAL and FVAL signals are sufficient to know when to sample the image data.

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7.3.5.1 DVAL, LVAL, FVAL

The first three bits of the control word must be used to identify valid data and the readout status. Next figure shows the timing of the DVAL, LVAL and FVAL bits of the control channel with an example of the read-out of a frame of 6 rows (default is 3840 rows). This example uses the default mode of 16 outputs (8 outputs on each side). Figure 21: xVAL timing in 16 output mode

7.3.5.2 Digital test pins

Pins D1 (Tdig2) and D3 (Tdig1) can be used as digital outputs to monitor the state of the sensor. Register 92 can be used to select a signal on these pins. Table 7: Digital test pin D1 REG98[6:4] TDIG2

0 LVAL

3 INTE_1

7 CLK_OUT (= LVDS_CLK/12)

Table 8: Digital test pin D2 REG92[3:0] TDIG1

0 FVAL

2 FOT

3 INTE_2

IDLE OH 640 OH 640 OH 640DATA_OUT DVAL LVAL FVAL

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7.3.6 Training data

To synchronize the receiving side with the LVDS outputs of the device, a known data pattern can be put on the output channels. This pattern can be used to “train” the LVDS receiver of the surrounding system to achieve correct word alignment of the image data. Such a training pattern is put on all 16 data channel outputs when there is no valid image data to be sent (so, also in between bursts of 640 pixels). The training pattern is a 12-bit data word that replaces the pixel data. The sensor has a 12-bit sequencer register (address 90-90) that can be loaded through the SPI to change the contents of the 12-bit training pattern. The control channel does not send a training pattern, because it is used to send control information at all time. Word alignment can be done on this channel when the sensor is idle (not exposing or sending image data). In this case all bits of the control word are zero, except for bit [9]. The figure below shows the location of the training pattern (TP) on the data channels and control channels when the sensor is in idle mode and when a frame of 6 rows is read out. The default mode of 16 outputs is selected. Figure 22: Training pattern timing The LVDS outputs are not aligned with the LVDS output clock. Every channel (per odd/even side) has a skew of 600 ps compared to the previous channel. The control channel and both odd and even channels 1 are aligned with the clock. This skew will become larger than a LVDS clock period and therefore bit and word alignment is needed at the receiving side. Training pattern TP 640 TP 640 TP 640Data channels DVAL LVAL FVAL Control channel Training pattern Control information Sensor in idle mode

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 38 / 69 Figure 23: LVDS output skew LVDS CLOCK_OUT CTR OUT1E OUT1O OUT2E OUT2O D(0) D(1) D2) D(0) D(1) D2) D(0) D(1) D2) D(0) D(1) D2) D(0) D(1) D2) 600ps 600ps OUT3E OUT3O D(0) D(1) D2) D(0) D(1) D2) 1200ps 1200ps OUT8E OUT8O D(0) D(0) 4200ps ... 4200ps

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7.3.7 Test pattern

Instead of sending image data, the sensor can generate a fixed two-dimensional test image (after sending a frame request), if the test pattern mode is enabled. This setting can be programmed in the register by setting register 83[0] to 1. The test pattern is the sum of the row number, the pixel number and the data output channel number. Figure 24 shows an example of the test pattern data. Figure 24: Test pattern data IDLE TP 0,1,...639 TPDATA_OUT_ Row 0 Row 2 Row 4 Row 6 IDLE TP 1,2,...640 TPDATA_OUT_ Row 1 Row 3 Row 5 Row 7 IDLE TP 1,2,...640 TPDATA_OUT_ Row 0 Row 2 Row 4 Row 6 IDLE TP 2,3,...641 TPDATA_OUT_ Row 1 Row 3 Row 5 Row 7 IDLE TP 7,8,...646 TPDATA_OUT_ Row 0 Row 2 Row 4 Row 6 IDLE TP 8,9,...647 TPDATA_OUT_ Row 1 Row 3 Row 5 Row 7

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 40 / 69 Figure 25: Test pattern image

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7.4 Configuring readout and exposure

This section explains how the CMV20000 can be programmed using the on-board sequencer registers.

7.4.1 Exposure modes

The exposure time can be programmed in two ways, externally or internally. Externally, the exposure time is defined as the time between the rising edge of T_EXP1 and the rising edge of FRAME_REQ (see section 7.2.5 for more details). Internally, the exposure time is set by uploading the desired value to the corresponding sequencer register. Table 9 gives an overview of the registers involved in the exposure mode. Table 9: Exposure modes Reg. name Address Default Description Exp_ext 81[0] 0 0: Exposure time is defined by the value uploaded in register 32-33. 1: Exposure time is defined by the pulses applied to the T_EXP1 and FRAME_REQ pins. Exp_time 32-33 3840 When the Exp_ext register is set to ‘0’, the value in this register defines the exposure time according to the formula below. Minimum =1 Equation 1: 𝐴𝑐𝑡𝑢𝑎𝑙 𝐸𝑥𝑝𝑜𝑠𝑢𝑟𝑒 𝑇𝑖𝑚𝑒 = (((𝐸𝑥𝑝_𝑡𝑖𝑚𝑒) − 1) ∗ 641) + 1 + (47 ∗ 𝑟𝑒𝑔82)) ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟 Here clk_per is the period of the input LVDS_CLK multiplied by 12 (so for 480 MHz this is 25 ns). The minimum exposure time then becomes 94 µs. A detailed view of the frame timing can be seen below.

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 42 / 69 Figure 26: Frame timing

7.4.2 Frame timing

The frame rate of the CMV20000 is defined by 2 main factors.

• Exposure time
• Read out time For ease of use we will assume that the exposure time is shorter than the read out time. By assuming this, the frame rate is completely defined by the read out time (because the exposure time happens in parallel with the read-out time). The read-out time (and thus the frame rate) is defined by:
• Output clock speed: max 480 Mbps
• Number of lines read-out
• Number of outputs used: Max 16 LVDS outputs (8 on the top and 8 on the bottom) This means that if any of the parameters above are changed, it will have an impact on the frame rate of the sensor. In normal operation (16 outputs @ 480 Mbps, 12-bit and full resolution) this will result in 30 fps. The total readout time is composed of two parts:
• FOT (frame overhead time)
• Image readout time Frame_REQ INTE_1 (Exp_time - 1) * 641 + 1) * clk_per 47*80*clk_per Actual exposure time 6410 * clk_per 1282 * clk_per 641 * (#lines / #sides) * clk_per Actual FOT FOT FVAL

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 43 / 69 The FOT is defined as Equation 2: 𝐹𝑂𝑇 = ((80 ∗ 𝑟𝑒𝑔82 + 𝑟𝑒𝑔82 Therefore, for REG82 = 80 and running at 480 MHZ this becomes: Equation 3: 𝐹𝑂𝑇 = (6410 + 1282) ∗ 25 𝑛𝑠 = 192.3 𝜇𝑠 The image readout time equals to Equation 4: 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑇𝑖𝑚𝑒 = 641 ∗ 𝑐𝑙𝑘_𝑝𝑒𝑟 ∗ 𝑛𝑟_𝑙𝑖𝑛𝑒𝑠 #𝑠𝑖𝑑𝑒𝑠 𝑢𝑠𝑒𝑑 So, for full resolution and running at 480 MHz with both output sides used this becomes: Equation 5: 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑇𝑖𝑚𝑒 = 641 ∗ 25 𝑛𝑠 ∗ 3840 2 = 30.768 𝑚𝑠 This results in a total frame time of: Equation 6: 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 𝐹𝑂𝑇 + 𝑅𝑒𝑎𝑑 𝑂𝑢𝑡 𝑇𝑖𝑚𝑒 So, for the default settings this becomes: Equation 7: 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 192.3 𝜇𝑠 + 30.768 𝑚𝑠 = 30.968 𝑚𝑠 And the frame rate becomes: Equation 8: 𝐹𝑟𝑎𝑚𝑒 𝑟𝑎𝑡𝑒 = 1 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 1 30.968 𝑚𝑠 = 32.3 𝐹𝑃𝑆 See section 7.4.1 for detailed frame timing. Clk_per is the period of the pixel clock. This pixel clock frequency is equal to 1/12th (40 MHz) of the LVDS input clock frequency (480 MHz).

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7.4.3 High dynamic range modes

7.4.3.1 Piecewise linear response

The device has the possibility to achieve a high optical dynamic range by using a piecewise linear response. This feature will clip illuminated pixels which reach a programmable voltage, while leaving the darker pixels untouched. The clipping level can be adjusted 2 times within one exposure time to achieve a maximum of 3 slopes in the response curve. More details can be found on Figure 27. Figure 27: Piecewise linear response details In the figure above, the red lines represent a pixel on which a large amount of light is falling. The blue line represents a pixel on which less light is falling. As shown in the figure, the bright pixel is held to a programmable voltage for a programmable time during the exposure time. This happens two times to make sure that at the end of the exposure time the pixel is not saturated. The darker pixel is not influenced and will have a normal response. The Vlevel_s2/3 voltages and different exposure times are programmable using the sequencer registers. Using this feature, a response as detailed in Figure 28 can be achieved. The placement of the kneepoints in X is controlled by the Vlevel_s2/3 programming, while the slope of the segments is controlled by the programmed exposure times. Vhigh Vlevel_s2 Vlevel_s3 Vlow Total exposure time Exp_s2 Exp_s3 Pixel reset Pixel sample

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 45 / 69 Figure 28: Piecewise linear response Saturation level Kneepoint slope 2 Kneepoint slope 3 # of electrons Output signal

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7.4.3.2 Piecewise linear response with internal exposure mode

The following registers need to be programmed when a piecewise linear response in internal exposure mode is desired. Table 10: HDR settings - PLR with internal exposure mode Reg. name Address Default Description Exp_time 32-33 3840 The value in this register defines the total exposure time according to the following formula: ((Exp_time - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. Nr_slopes 37[1:0] 1 The value in this register defines the number of slopes (min=1, max=3). Exp_s2 39-40 0 The value in this register defines the exposure time from the start of the second slope to the end of the total exposure time. Formula: ((Exp_s2 - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. Exp_s3 42-43 0 The value in this register defines the exposure time from the start of the third slope to the end of the total exposure time. Formula: ((Exp_s3 - 1) x 641 + 1 + 47 x FOT_mult) x clk_per, where clk_per is the period of the master input clock. Vlevel_s2 114[6:0] 64 Bit [6] = Enable Bit [5:0] = DAC value Low level voltage during dual slope operation. The value in this register defines the Vlevel_s2 voltage (DAC setting). The DAC range goes from 0 to 2.1 V. Vlevel_s3 115[6:0] 64 Bit [6] = Enable Bit [5:0] DAC value Low level voltage during triple slope operation. The value in this register defines the Vlevel_s3 voltage (DAC setting). The DAC range goes from 0 to 2.1 V.

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7.4.3.3 Piecewise linear response with external exposure mode

When external exposure time is used and a piecewise linear response is desired, the following registers should be programmed. Table 11: HDR settings - PLR with external exposure mode Reg. name Address Default Description Nr_slopes_ex 15[1:0] 1 The value in this register defines the number of slopes (min=1, max=3). Vlevel_s2_ex 112[6:0] 64 Bit [6] = Enable Bit [5:0] = DAC value Low level voltage during dual slope operation. The value in this register defines the Vlevel_s2 voltage (DAC setting). The DAC range goes from 0 to 2.1 V. Vlevel_s3_ex 113[6:0] 64 Bit [6] = Enable Bit [5:0] = DAC value Low level voltage during triple slope operation. The value in this register defines the Vlevel_s3 voltage (DAC setting). The DAC range goes from 0 to 2.1 V. The timing that needs to be applied in this external exposure mode looks like the one in Figure 29: PLR with external exposure mode FRAME_RE Q T_EXP1 Total exposure time Exposure s2 Exposure s3

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7.4.4 Windowing

To limit the amount of data or to increase the frame rate of the sensor, windowing in Y direction is possible. The number of lines and start address can be set by programming the appropriate registers. The CMV20000 has the possibility to read out multiple (max=8) predefined sub-windows in one readout cycle. The default mode is to read-out one window with the full frame size (5120 x 3840).

7.4.4.1 Single window

When a single window is read out, the start address and size can be uploaded in the corresponding registers. The default start address is 0 and the default size is 3840 (full frame). Table 12: Single window settings Reg. name Address Default Description Start_single 24-25 0 The value in this register defines the start address of the window in Y (min=0, max=3839) Number_lines_single 26-27 3840 The value in this register defines the number of lines read out by the sensor (min=1, max=3840) Figure 30: Single window 5120 3840 Number_lines_single Start_single

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7.4.4.2 Multiple windows

The CMV20000 can read out a maximum of 8 different sub-windows in one read-out cycle. The location and length of these sub-windows must be programmed in the correct registers. The total number of lines to be read-out (sum of all windows) needs to be specified in the Number_lines register. The registers which need to be programmed for the multiple windows can be found in the table below. Table 13: Multiple window settings Reg. name Address Default Description Multwin_en 44 0 0: Multiple windows mode disabled 1: Multiple windows mode enabled Number_lines 45-46 0 The value in this register defines the total number of lines read-out by the sensor (min=1, max=3840) Start1 47-48 0 The value in this register defines the start address of the first window in Y (min=0, max=3839) Number_lines1 63-64 0 The value in this register defines the number of lines of the first window (min=1, max=3840) Start2 49-50 0 The value in this register defines the start address of the second window in Y (min=0, max=3839) Number_lines2 65-66 0 The value in this register defines the number of lines of the second window (min=1, max=3840) Start3 51-52 0 The value in this register defines the start address of the third window in Y (min=0, max=3839) Number_lines3 67-68 0 The value in this register defines the number of lines of the third window (min=1, max=3840) Start4 53-54 0 The value in this register defines the start address of the fourth window in Y (min=0, max=3839) Number_lines4 69-70 0 The value in this register defines the number of lines of the fourth window (min=1, max=3840) Start5 55-56 0 The value in this register defines the start address of the fifth window in Y (min=0, max=3839) Number_lines5 71-72 0 The value in this register defines the number of lines of the fifth window (min=1, max=3840) Start6 57-58 0 The value in this register defines the start address of the sixth window in Y (min=0, max=3839) Number_lines6 73-74 0 The value in this register defines the number of lines of the sixth window (min=1, max=3840) Start7 59-60 0 The value in this register defines the start address of the seventh window in Y (min=0, max=3839) Number_lines7 75-76 0 The value in this register defines the number of lines of the seventh window (min=1, max=3840) Start8 61-62 0 The value in this register defines the start address of the eighth window in Y (min=0, max=3839)

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 50 / 69 Reg. name Address Default Description Number_lines8 77-78 0 The value in this register defines the number of lines of the eighth window (min=1, max=3840) Figure 31: Example of 4 sub-windows read-out 5120 3840 Number_lines4 start4 Number_lines3 start3 Number_lines2 start2 Number_lines1 start1 Number_lines = Number_lines1 + Number_lines2 + Number_lines3 + Number_lines4

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7.4.5 Image flipping

The image coming out of the image sensor, can be flipped in X and/or Y direction. This means that if flipping is enabled in both directions the upper right pixel is read out first (instead of lower left). The following registers are involved in image flipping. Table 14: Image flipping Reg. name Address Default Description Image_flipping 85[1:0] 0 0: No image flipping 1: Image flipping in X 2: Image flipping in Y 3: Image flipping in X and Y

7.4.6 Image subsampling

To maintain the same field of view but reduce the amount of data coming out of the sensor, a subsampling mode is implemented on the chip. Different subsampling schemes can be programmed by setting the appropriate registers. These subsampling schemes can take into account whether a color or monochrome sensor is used to preserve the Bayer pattern information. The registers involved in subsampling are detailed below. A distinction is made between a simple and advanced mode (can be used for color devices). Subsampling can be enabled in every windowing mode.

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7.4.6.1 Simple subsampling

Table 15: Simple subsampling Reg. name Address Default Description Number_lines_single 26-27 3840 The value in this register defines the total number of lines read out by the sensor (min=1, max=3840) Sub_s 28-29 0 Number of rows to skip (min=0, max=3839) Sub_a 30-31 0 Identical to Sub_s Figure 32 give two subsampling examples (skip 4x and skip 1x). Figure 32: Subsampling examples in simple mode (Left: Skip 4x and Right: Skip 1x) Sub_s = 4 Sub_a = 4 Number_lines = sum of red lines Sub_s = 1 Sub_a = 1 Number_lines = sum of red lines

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7.4.6.2 Advanced subsampling

When a color sensor is used, the subsampling scheme should take into account that a Bayer color filter is applied on the sensor. This Bayer pattern should be preserved when subsampling is used. This means that the number of rows to be skipped should always be a multiple of two. An advanced subsampling scheme can be programmed to achieve these requirements. Of course, this advanced subsampling scheme can also be programmed in a monochrome sensor. See the table of registers in Table 16 for more details. Table 16: Advanced subsampling Reg. name Address Default Description Number_lines_single 26-27 3840 The value in this register defines the total number of lines read out by the sensor (min=1, max=3840) Sub_s 28-29 0 Should be ‘0’ at all times Sub_a 30-31 0 Number of rows to skip, it should be an even number between 0 and 3839 Figure 33 shows two subsampling examples (skip 4x and skip 2x) in advanced mode. Figure 33: Subsampling examples in advanced mode (Left: Skip 4x and Right: Skip 2x) Sub_s = 0 Sub_a = 4 Number_lines = sum of red lines Sub_s = 0 Sub_a = 2 Number_lines = sum of red lines

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7.4.7 Number of frames

When internal exposure mode is selected, the number of frames sent by the sensor after a frame request can be programmed in the corresponding sequencer register. Table 17: Number of frames Reg. name Address Default Description Number_frames 22-23 1 The value in this register defines the number of frames grabbed and sent by the image sensor in internal exposure mode (min =1, max = 65535)

7.4.8 FOT multiplier

The length of the FOT can be programmed using the register below. It is not recommended to set it below 80 as loss in swing and increase in FPN can occur. Table 18: FOT multiplier Reg. name Address Default Description FOT_mult 82 80 The value in this register defines the length of the FOT according to the following formula: (80 x FOT_mult + FOT_mult/8) x clk_per, Wwhere clk_per is the period of the master input clock (min=8, max=248, multiple of 8)

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7.5 Configuring output dana format

7.5.1 Output mode

When LVDS output mode is selected, the number of LVDS channels can be selected by programming the appropriate sequencer register. The pixel remapping scheme and the read- out timing for each mode can be found in section 7.3 of this document. Table 19: Output mode Reg. name Address Default Description Output_mode 80 0 0: 16 outputs 1: 8 outputs

7.5.2 Training pattern

As detailed in section 7.3.6, a training pattern is sent over the LVDS data channels whenever no valid image data is sent. This training pattern can be programmed using the sequencer register. Table 20: Training pattern Reg. name Address Default Description Training_pattern 90-91 85 The 12 LSBs of this 16-bit word are sent

7.5.3 Test pattern

As detailed in section 7.3.7, a test pattern can be generated whenever no training data is sent. This test pattern can be enabled using the register below. Table 21: Test Pattern Reg. Name Address Default Description Testpattern_en 83 0 0: Test pattern disabled 1: Test pattern enabled

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7.5.4 Data rate

During start-up or after a sequencer reset, the data rate can be changed if a lower speed than 480 Mbps is desired. This can be done by applying a lower master input clock (CLK_IN) and lower LVDS_CLK_N/P to the sensor. See section 5 for more details on the input clock. See

7.5.5 Power control

The power consumption of the device can be regulated by disabling the LVDS data channels when they are not used (in 8 channel mode). Table 22: Power control Reg. name Address Default Description Channel_en 95-96 262143 Bits 0-7 : Enable/disable the bottom data output channels Bits 8-15 : Enable/disable the top data output channels Bit 16 : Enables/disables the clock channel Bit 17 : Enables/disables the control channel Bit 18 : Enables/disables the clock receiver 0: Disabled 1: Enabled

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7.6 Configuring on-chip data processing

7.6.1 Offset

A digital offset can be applied to the output signal. The dark level offset can be programmed by setting the desired value in the sequencer registers. The offset register is a 12-bit 2’s complement representation of the actual desired offset to be added or subtracted from a fixed value of 1296. The default offset register value of 2840 is the 2’s complement representation of -1256. Hence, the default dark level is 1296 + (-1256) = 40. Table 23: Offset Reg. name Address Default Description Offset 88-89 2840 The value in this register defines the dark level offset applied to the output signal

7.6.2 Gain

An analog gain and ADC gain can be applied to the output signal. The analog gain is applied by a PGA in every column. The digital gain is applied by the ADC. The ADC gain has to be changed when changing the clock speed from 480 MHz. Table 24: Gain settings Reg. name Address Default Description PGA_gain 93[3:2] 0 0: x0.8 1: x1 (recommended) 2: x1.2 4: x1.4 ADC_gain 126[5:0] 32 32 Figure 34 illustrates the ADC_gain setting vs. the actual gain. When for example you run the sensor at 240 MHz, you have to use an actual gain of 480/240 = x2 or value 48 to compensate (the ADC conversion is dependent on the clock speed).

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 58 / 69 Figure 34: ADC gain vs. actual gain

7.7 Additional features

7.7.1 Temperature

The register below contains the temperature data. Table 25: Temperature Reg. name Address Default Description Temperature 101-102 0 This register contains the temperature data ADC Value

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8 Register description

8.1 Register overview

The table below gives an overview of all the sensor registers. The registers with the remark “Do not change” should not be overwritten. Table 26: Register overview Address Register name(s) Default value Fixed value(1) 0 1 Do not change 1 0 Do not change 2 0 Do not change 3 0 Do not change 4 0 Do not change 5 15 Do not change 6 0 Do not change 7 0 Do not change 8 0 Do not change 9 0 Do not change 10 32 Do not change 11 0 Do not change 12 32 Do not change 13 0 Do not change 14 0 Do not change

15 Nr_slopes_ex[1:0] 1

22 Number_frames[7:0] 1

23 Number_frames[15:8] 0

24 Start_single[7:0] 0

25 Start_single[15:8] 0

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26 Number_lines_single[7:0] 0

27 Number_lines_single[15:8] 15

28 Sub_s[7:0] 0

29 Sub_s[15:8] 0

30 Sub_a[7:0] 0

31 Sub_a[15:8] 0

32 Exp_time[7:0] 0

33 Exp_time[15:8] 15

37 Nr_slopes[1:0] 1

39 Exp_s2[7:0] 0

40 Exp_s2[15:8] 0

42 Exp_s3[7:0] 0

43 Exp_s3[15:8] 0

44 Multwin_en 0

45 Number_lines[7:0] 0

46 Number_lines[15:8] 0

47 Start1[7:0] 0

48 Start1[15:8] 0

49 Start2[7:0] 0

50 Start2[15:8] 0

51 Start3[7:0] 0

52 Start3[15:8] 0

53 Start4[7:0] 0

54 Start4[15:8] 0

55 Start5[7:0] 0

56 Start5[15:8] 0

57 Start6[7:0] 0

58 Start6[15:8] 0

59 Start7[7:0] 0

60 Start7[15:8] 0

61 Start8[7:0] 0

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62 Start8[15:8] 0

63 Number_lines1[7:0] 0

64 Number_lines1[15:8] 0

65 Number_lines2[7:0] 0

67 Number_lines2[15:8] 0

68 Number_lines3[7:0] 0

69 Number_lines3[15:8] 0

70 Number_lines4[7:0] 0

71 Number_lines4[15:8] 0

72 Number_lines5[7:0] 0

73 Number_lines5[15:8] 0

74 Number_lines6[7:0] 0

75 Number_lines6[15:8] 0

76 Number_lines7[7:0] 0

77 Number_lines7[15:8] 0

78 Number_lines8[7:0] 0

80 Output_mode 0

81 Exp_ext 0

82 FOT_mult[7:0] 80

83 Testpattern_en 0

85 Image_flipping[1:0] 0

88 Offset[7:0] 24

89 Offset[11:8] 11

90 Training_pattern[7:0] 85

91 Training_pattern[15:8] 0

93 PGA_Gain[3:2] 0

95 Channel_en[7:0] 255

96 Channel_en[15:8] 255

97 Channel_en[18:16] 3 7

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101 Temp[7:0] 0 Do not change

102 Temp[15:8] 0 Do not change

112 Vlevel_s2_ex[6:0] 64

113 Vlevel_s3_ex[6:0] 64

114 Vlevel_s2[6:0] 64

115 Vlevel_s3[6:0] 64

(1) Addresses with a fixed value other than the startup value need to be set to the fixed value after startup.

Application information

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9 Application information

9.1 Cover glass

The cover glass of the CMV20000 has following specifications:

• Reflection(abs) <= 1.5% @ 400 – 900 nm (per surface), Angle Off Interest = 15º
• 2 sides AR-coated When a color sensor is used an IR-cutoff filter should be placed in the optical path of the sensor.

9.2 Color filter

When a color version of the CMV20000 is used, the color filters are applied in a Bayer pattern. The color version of the CMV20000 always has micro lenses. The use of an IR cut-off filter in the optical path of the CMV20000 image sensor is necessary to obtain good color separation when using light with an IR component. A RGB Bayer pattern is used on the CMV20000 image sensor. The order of the RGB filter can be found in the drawing below. Figure 35: RGB bayer pattern order

Package drawings & markings Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 64 / 69 Figure 36: Package drawings (1) All dimensions are in millimeters. Angles in degrees. (2) Dimensioning and tolerancing conform to ASME Y14.5M-1994. (3) N is the total number of terminals. (4) This package contains no lead (Pb). (5) This drawing is subject to change without notice.

Package drawings & markings Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 65 / 69 Figure 37: Assembly outline drawing (1) All dimensions are in mm

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11 Soldering & storage information

CMV20000 is shipped in a moisture barrier package. We recommend to keep the moisture barrier package closed and stored under the conditions shown in Table . Only open the moisture barrier package before the usage of the devices. Please avoid environments with dust, radiation, electromagnetic fields, ESD and mechanical stress. The CMV20000 device has passed MSL3 testing. Attention:

• Image sensors with color filter arrays (CFA) and micro-lenses are especially sensitive to high temperatures. Prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. Best solution will be flow soldering or manual soldering of a socket (through hole or BGA) and plug in the sensor at latest stage of the assembly/test process.

11.1 Wave soldering

Wave soldering is possible but not recommended. Solder dipping can cause damage to the glass and harm the imaging capability of the device. See the figure below for the wave soldering profile. Figure 38: Wave soldering profile Temperature (C) Time (s) 260 Max 10 s

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11.2 Image sensor storing

Image sensors should be stored under the following conditions.

• Dust free
• Avoid radiation, electromagnetic fields, ESD, mechanical stress
• See section 4 for storage limits

11.3 Handling the image sensor

General application note AN03 contains more details and procedures.

11.3.1 ESD

The following are the recommended minimum ESD requirements when handling image sensors.

• Ground workspace (tables, floors…)
• Ground handling personnel (wrist straps, special footwear…)
• Minimize static charging (control humidity, use ionized air, wear gloves…)

11.3.2 Glass cleaning

When cleaning of the cover glass is needed, we recommend the following two methods.

• Blowing off the particles with ionized nitrogen
• Wipe clean using IPA (isopropyl alcohol) and ESD protective wipes.

11.3.3 Excessive light

Excessive light falling on the sensor can cause heating up the micro lenses and color filters. This heat can cause deforming of the lenses and/or deterioration of the lenses and color filters by making them more opaque, increasing the heat up even more. Avoid shining high intensity light upon the sensors for extended periods of time. In case of lasers, they can cause heat up but can also damage the silicon die itself.

Datasheet • PUBLIC • Document Feedback DS000440 • v3-00 • 2026-Mar-13 68 / 69 Document status Product status Definition Product Preview Pre-development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Other definitions Draft / Preliminary: The draft / preliminary status of a document indicates that the content is still under internal review and subject to change without notice. ams-OSRAM AG does not give any warranties as to the accuracy or completeness of information included in a draft / p reliminary version of a document and shall have no liability for the consequences of use of such information. Short datasheet: A short datasheet is intended for quick reference only, it is an extract from a full datasheet with the same product number(s ) and title. For detailed and full information always see the relevant full datasheet. In case of any inconsistency or conflict wit h the short datasheet, the full datasheet shall prevail. Changes from previous released version to current revision v3-00 Page Document contents transferred to ams OSRAM datasheet template Updated description under chapter 11 66

• Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
• Correction of typographical errors is not explicitly mentioned.

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13 Legal information

Copyright & disclaimer Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria -Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams - OSRAM AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams -OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended fo r use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life -support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, propert y damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third part y shall arise or flow out of ams- OSRAM AG rendering of technical or other services. Product and functional safety devices/applications or medical devices/applications: ams-OSRAM AG components are not developed, constructed or tested for the application as safety relevant component or for the appl ication in medical devices. ams-OSRAM AG products are not qualified at module and system level for such application. In case buyer – or customer supplied by buyer – considers using ams-OSRAM AG components in product safety devices/applications or medical devices/applications, buyer and/or customer has to inform the local sales partner of ams -OSRAM AG immediately and ams-OSRAM AG and buyer and /or customer will analyze and coordinate the customer -specific request between ams-OSRAM AG and buyer and/or customer. ams OSRAM RoHS and REACH compliance statements for semiconductor products RoHS compliant: The term “RoHS compliant” means that semiconductor products from ams OSRAM fully comply with current RoHS directives, and China RoHS. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substanc e categories (per amendment EU2015/863) above the defined threshold limit in the Annex II. REACH compliant: Semiconductor products from ams OSRAM are free of Substances of Very High Concern (SVHC) according Article 33 of the REACH Regulation 2006/1907/EC; please refer to the Candidate List of Substances of ECHA here. Important information: The information provided in this statement represents ams OSRAM knowledge and belief as of the date that it is provided. ams OSRAM bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. We are undertaking efforts to better integrate information from third parties. ams OSRAM has taken and will continue to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams OSRAM and its suppliers consider certain information to be proprietary, and thus CAS nu mbers and other limited information may not be available for release. Headquarters ams-OSRAM AG Tobelbader Strasse 30

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