CMV50000

CMV50000 AMSOSRAM | Alldatasheet

Document overview

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Technical content

47.5MP CMOS Machine Vision Image Sensor v4-00 • 2023-Aug-03

Document Feedback CMV50000 Content Guide Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 2 Content Guide

6 Typical Operating

7.7 Configuring the On-Chip Data Processing . 88

Document Feedback CMV50000 General Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 3

1 General Description

The CMV50000 is a high speed CMOS image sensor with 7920 × 6004 effective pixels (47.5Mp) developed for machine vision and video applications. The image array consists of 4.6µm pipelined 8T global shutter pixels which allow exposure during read out, while performing true CDS (Correlated Double Sampling) operation. The image sensor also integrates a programmable analog gain amplifier and offset regulation. The image sensor has 22 digital sub-LVDS data output channels. Each output channel runs up to 830 Mbit/s, which results in a frame rate of 30 fps at full resolution. Higher frame rates can be achieved in row-windowing mode or row-subsampling mode. These modes are all programmable using the SPI interface. All internal exposure and read out timings are generated by a programmable on-chip sequencer. External triggering and exposure programming is also possible. Extended optical dynamic range can be achieved by a dual exposure HDR mode.

1.1 Key Benefits & Features

The benefits and features of CMV50000, 47.5MP CMOS Machine Vision Image Sensor, are listed below: Figure 1: Added Value of Using CMV50000 Benefits Features Designed for high performance applications Resolution of 7920 × 6004 at 30 frames per second Capture fast moving objects 8T global shutter pixel with true Correlated Double Sampling (true-CDS) Use in low light conditions Low noise (8.8e) and high sensitivity (QE=60%), with on-chip noise reduction. Use in bright light conditions In binning mode the full well capacity reaches 58000e- with an SNR of 47.6dB and DR=68dB Standard optics can be used 35 mm Full Frame optical format Easy to operate On-chip digital sequencer which handles all the sensor controls, over SPI

Document Feedback CMV50000 General Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 4

1.2 Applications

• Machine vision
• Video/Broadcast
• Security
• High-end inspection
• Aerial mapping
• Document scanning
• ITS
• Scientific
• 3D imaging

1.3 Block Diagram

The functional blocks of this device are shown below: Figure 2: Functional Blocks of CMV50000 Pixel array 7920 x 6004 (effective) active pixels AFE AFE AFE ADC ADC ADC Thermal sensor PLL Digital sequencer AFE ADC CLK_OUT channel

22 DATAx_OUT

SPI, sensor control OBR_OUT channel ... ... ... DPP DPP DPP DPP

98 OB +

OBL _OUT channel CTR_OUT channel sLVDS sLVDS sLVDS sLVDS sLVDS sLVDS

Document Feedback CMV50000

Ordering Information

Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 5

2 Ordering Information

Ordering Code Package Chroma Options Delivery Quantity CMV50000-1E3M1PA QA PGA Mono 10 Pcs / Tray CMV50000-1E3C1PA QA PGA Color 10 Pcs / Tray

Document Feedback CMV50000 Pin Assignment Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 6

3 Pin Assignment

3.1 Pin Diagram

Figure 3: Pin Numbering (bottom view)

3.2 Pin Description

Figure 4: Pin Description of CMV50000 Pin Number Pin Name Pin Type Description A2 SPI_CSN Digital input SPI Chip Select A3 VSSA Analog ground Analog ground A5 REQ_FRAME Digital input Request frame (stop exposure) A6 VDDARRAY Analog supply Pixel array supply A7 VDDARRAY Analog supply Pixel array supply A8 NC1 Analog Do Not Connect

Document Feedback CMV50000 Pin Assignment Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 7 Pin Number Pin Name Pin Type Description A9 NC2 Analog Do Not Connect A10 CTRL_P sub-LVDS Control channel output A11 CTRL_N sub-LVDS Control channel output A13 VSSA Analog ground Main analog ground A14 DOBL_P sub-LVDS Left Optical Black output A15 DOBL_N sub-LVDS Left Optical Black output B1 SPI_MISO Digital output SPI Master In/Slave Out data B2 SPI_MOSI Digital input SPI Master Out/Slave In data B3 SPI_CLK Digital input SPI clock B4 CLK_IN Digital input Sensor input clock B5 RST_N Digital input Asynchronous hard reset input pin B6 VDD33 Analog supply On-chip regulators supply B7 VSELHREG Analog On-chip regulator output B8 VS2HREG Analog On-chip regulator output B9 VS1HREG Analog On-chip regulator output B10 VTXHREG Analog On-chip regulator output B11 VRESHREG Analog On-chip regulator output B12 VDD27 Analog supply Main analog supply B13 D00_P sub-LVDS Channel 0 output B14 D00_N sub-LVDS Channel 0 output B15 D02_P sub-LVDS Channel 2 output C1 VDDD12PLL1 Digital supply Digital supply for PLL1 C2 VDDD12PLL2 Digital supply Digital supply for PLL2 C3 REQ_EXP Digital input Request exposure (start exposure) C4 VDD27 Analog supply Main analog supply C5 VSSD Digital ground Digital ground C6 VSSD Digital ground Digital ground C7 VSELH Analog Bias C8 VS2H Analog Bias C9 VS1H Analog Bias C10 VTXH Analog Bias C11 VRESH Analog Bias C12 D01_P sub-LVDS Channel 1 output C13 D01_N sub-LVDS Channel 1 output C14 D03_P sub-LVDS Channel 3 output

Document Feedback CMV50000 Pin Assignment Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 8 Pin Number Pin Name Pin Type Description C15 D02_N sub-LVDS Channel 2 output D1 VDD12C Digital supply Logic supply for ADC D2 VSSD Digital ground Main digital ground D14 D03_N sub-LVDS Channel 3 output D15 D04_P sub-LVDS Channel 4 output E1 VSSDPLL1 Digital ground Digital ground for PLL1 E2 VSSDPLL2 Digital ground Digital ground for PLL2 E14 D05_P sub-LVDS Channel 0 output E15 D04_N sub-LVDS Channel 0 output F1 VSSAPLL1 Analog ground Analog ground for PLL1 F2 VSSAPLL2 Analog ground Analog ground for PLL2 F14 D05_N sub-LVDS Channel 5 output F15 D06_P sub-LVDS Channel 6 output G1 VDDA12PLL1 Analog supply Analog supply for PLL1 G2 VDDA12PLL2 Analog supply Analog supply for PLL2 G14 D07_P sub-LVDS Channel 7 output G15 D06_N sub-LVDS Channel 6 output H1 VDD12 Digital supply Logic supply for core logic H2 VSSD Digital ground Main digital ground H14 D07_N sub-LVDS Channel 7 output H15 D08_P sub-LVDS Channel 8 output J1 VDD12 Digital supply Logic supply for core logic J2 VSSA Analog ground Main analog ground J14 D09_P sub-LVDS Channel 9 output J15 D08_N sub-LVDS Channel 8 output K1 VDD12C Digital supply Logic supply for ADC K2 VSSA Analog ground Main analog ground K14 D09_N sub-LVDS Channel 9 output K15 D10_P sub-LVDS Channel 10 output L1 VSSDC Digital ground Digital ground for ADC L2 VDDARRAY Analog supply Pixel array supply L14 D11_P sub-LVDS Channel 11 output L15 D10_N sub-LVDS Channel 10 output M1 VSSDC Digital ground Digital ground for ADC M2 VDDARRAY Analog supply Pixel array supply

Document Feedback CMV50000 Pin Assignment Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 9 Pin Number Pin Name Pin Type Description M14 D11_N sub-LVDS Channel 11 output M15 D12_P sub-LVDS Channel 12 output N1 VSSDC Digital ground Digital ground N2 VSSD Digital ground Digital ground N14 D13_P sub-LVDS Channel 13 output N15 D12_N sub-LVDS Channel 12 output P1 VDD18 Digital supply I/O supply for CMOS and I/O’s P2 VDD27 Analog supply Main analog supply P14 D13_N sub-LVDS Channel 13 output P15 D14_P sub-LVDS Channel 14 output R1 VDD18 Digital supply I/O supply for CMOS and I/O’s R2 VDD27 Analog supply Main analog supply R14 D15_P sub-LVDS Channel 15 output R15 D14_N sub-LVDS Channel 14 output S1 VDD27CP Analog supply Connect to VDD27 S2 VSSACP Analog ground Analog ground S14 D15_N sub-LVDS Channel 15 output S15 D16_P sub-LVDS Channel 16 output T1 VDD12C Digital supply Logic supply for ADC T2 VSSD Digital ground Main digital ground T14 D17_P sub-LVDS Channel 17 output T15 D16_N sub-LVDS Channel 16 output U1 EXTRA1 Analog ground Connect to analog ground U2 TDIGO1 Digital output Digital test output U3 TANAI1 Analog Do Not Connect U4 TANAI2 Analog Do Not Connect U5 VSELLNEG12 Analog On-chip regulator output U6 VS2LNEG12 Analog On-chip regulator output U7 VPCLNEG12 Analog On-chip regulator output U8 VS1LNEG12 Analog On-chip regulator output U9 VABNEG12 Analog On-chip regulator output U10 VRESLNEG12 Analog On-chip regulator output U11 VRESL Analog Bias U12 D19_N sub-LVDS Channel 19 output U13 D19_P sub-LVDS Channel 19 output

Document Feedback CMV50000 Pin Assignment Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 10 Pin Number Pin Name Pin Type Description U14 D17_N sub-LVDS Channel 17 output U15 D18_P sub-LVDS Channel 18 output V1 REF2 Analog Do Not Connect V2 JTAG_MODE Digital input JTAG Mode select. Connect to VSSD if JTAG is not used. V3 REF3 Analog Bias V4 TANAO Analog Do Not Connect V5 VSELL Analog Bias V6 VS2L Analog Bias V7 VPCL Analog Bias V8 VS1L Analog Bias V9 VABREG Analog On-chip regulator output V10 VRESLREG Analog On-chip regulator output V11 DOBR_P sub-LVDS Right Optical Black output V12 DOBR_N sub-LVDS Right Optical Black output V13 D20_N sub-LVDS Channel 20 output V14 D20_P sub-LVDS Channel 20 output V15 D18_N sub-LVDS Channel 18 output W1 REF1 Analog Do Not Connect W2 REF0 Analog Bias W3 VSSA Analog ground Analog ground W5 VSELLREG Analog On-chip regulator output W6 VS2LREG Analog On-chip regulator output W7 VPCLREG Analog On-chip regulator output W8 VS1LREG Analog On-chip regulator output W9 VAB Analog Bias W10 CLK_N sub-LVDS Clock output W11 CLK_P sub-LVDS Clock output W13 VSSA Analog ground Main analog ground W14 D21_N sub-LVDS Channel 21 output W15 D21_P sub-LVDS Channel 21 output

Document Feedback CMV50000 Absolute Maximum Ratings Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 11

4 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 5: Symbol Parameter Min Max Unit Comments Electrical Parameters ISCR Input Current (latch-up immunity) ±100 mA JEDEC JESD78D Nov 2011 Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ±2000 V JEDEC JS-001-2014 ESDCDM Electrostatic Discharge CDM ±250 V JEDEC JS-002-2014 Temperature Ranges and Storage Conditions TJ Operating Junction Temperature -30 70 °C TSTRG Storage Temperature Range -30 70 °C RHNC Relative Humidity (non- condensing) 30 60 % Storage condition

Document Feedback CMV50000

Electrical Characteristics

Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 12

5 Electrical Characteristics

All limits are guaranteed. The parameters with Min and Max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Symbol Parameter Conditions Min Typ Max Unit Power Supplies VDD12 Logic Supply Voltage of digital core, PLL 1.10 1.20 1.30 V VDD12C Logic Supply Voltage of ADC 1.10 1.20 1.30 V VDD18 I/O Supply Voltage for sub-LVDS, CMOS I/O’s 1.70 1.80 1.90 V VDD27 Main Analog Supply Voltage; Supply Voltage for negative regulators 2.60 2.70 2.80 V VDDARRAY Pixel Array Supply Voltage 2.60 2.70 2.80 V VDD33 Internal Regulator Supply Voltage 3.20 3.30 3.40 V IDD12 Supply Current Idle Running 350 375 mA IDD12C Supply Current Idle Running 10 410 mA IDD18 Supply Current Idle Running 130 115 mA IDD27 Supply Current Idle Running 550 550 mA IDDARRAY Supply Current Idle Running 130 130 (1) mA IDD33 Supply Current Idle Running 20 20 mA Ptot Total Power Consumption Idle Running 2.5 3.0 W Digital I/O VIH High level input voltage 0.7 × VDD18 VDD18 +0.5 V VIL Low level input voltage -0.5 0.3 × VDD18 V VOH High level output voltage IOH=4mA VDD18 -0.15 - V VOL Low level output voltage IOL=4mA - 0.15 V CI Input load - 10 pF CO Output load - 20 pF Ttran Input transition time 0.1 5.0 ns fCLK_IN CLK_IN frequency 6 96 MHz DCCLK_IN CLK_IN duty cycle 40 60 %

Document Feedback CMV50000 Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 13 Symbol Parameter Conditions Min Typ Max Unit fSPI_CLK SPI input clock frequency - 10 MHz tsetup SPI setup time 0.25 × TSPI_CLK - ns thold SPI hold time 0 - ns tREQ REQ_FRAME/EXP pulse width 2 × TCLK_PIX - ns Sub-LVDS Interface VCM Common mode voltage 0.8 0.9 1.0 V VOD Differential voltage swing 100 150 200 mV RO Output impedance (2) 40 240 Ohm DR0 Impedance mismatch 10 % DC Clock duty cycle 45 50 55 % f Operating frequency 60 415 MHz IOD Drive current 1 1.5 2 mA ∆IOD IOD variation over Temp. 15 % IDC DC current consumption 3.7 mA IAC AC current consumption 7.2 µA/MHz (1) VDDARRAY draws high peak currents (>1A) during GLOB. Enough decoupling is needed to suppress these peaks. (2) Unused sub-LVDS channels must be terminated the same way as the used channels.

Document Feedback CMV50000 Typical Operating Characteristics Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 14

6 Typical Operating Characteristics

6.1 Electro-Optical Characteristics

Below are the typical electro-optical specifications of the CMV50000. These are typical values for the whole operating temperature range. Figure 7: Electro-Optical Characteristics of CMV50000 Parameter Value Remark Effective pixels 7920 × 6004 Pixel pitch 4.6 × 4.6 µm2 Optical format 35mm full frame Pixel type Global shutter with true CDS Allows fixed pattern noise correction and reset (kTC) noise canceling by true correlated double sampling (true-CDS). Shutter type Pipelined global shutter Exposure of next image during readout of the previous image. Full well charge 14500 e- 58000 e- Normal mode Binning mode Conversion gain 0.27 DN/e-

0.068 DN/ e-

Normal mode, unity gain Binning mode, unity gain Responsivity 0.16 DN/photon

0.25 A/W @ 510nm (with micro-lenses)

Temporal noise 8.8 e- 22 e- Normal mode Binning mode Dynamic range 64 dB 68 dB Normal mode Binning mode SNRMAX 41.6 dB 47.6dB Normal mode Binning mode Shutter efficiency 1/PLS 1/18000 At 520nm, f/8. DC 0.24 e-/s 66.2 e-/s @ 20°C sensor temperature @ 60°C sensor temperature Dark Current doubles every 5.1°C increase DCNU 0.72 e-/s 14.2 e-/s @ 20°C sensor temperature @ 60°C sensor temperature DC Non-Uniformity doubles every 10°C increase DSNU 24.5 e- Dark Signal Non Uniformity (FPN) <0.2%rms of saturation PRNU < 1.0% RMS Photo Response Non Uniformity RMS of signal Color filters Optional RGB Bayer pattern

Document Feedback CMV50000 Typical Operating Characteristics Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 15 Parameter Value Remark QE 58 / 61 / 53 / 14.5 % 49 / 55 / 45 % Quantum Efficiency (with micro-lenses) @ 450 / 510 / 600 / 850nm (mono device) @ 450 / 510 / 600nm (color device) Sub-LVDS outputs

22 Data

1 Control

1 Clock

Each data output running @ 830 Mbit/s. Less outputs selectable at reduced frame rate Frame rate 30 fps Using 830 Mbit/s sub-LVDS in pixel-based output Higher frame rate possible in row windowing mode Timing generation On-chip Possibility to control exposure time through external pin PGA Yes x1, x1.33, x2, x4 analog gain settings Programmable registers Sensor parameters Window coordinates, Timing parameters, Gain & offset, Exposure time HDR mode Interleaved 2 exposure times for odd/even columns ADC 12-bit Column ADC Interface sub-LVDS; 830 Mbit/s Serial output data + synchronization signals I/O logic levels Dig. I/O = 1.8 V Cover glass D263T eco Double sided AR coating R<1.5 % abs, 400 - 900nm, per surface, AOI=15° Mass 20gr

6.2 Spectral Characteristics

Figure 8: Quantum Efficiency 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 QE [%] wavelength [nm] QE QE_mono QE_B QE_G1 QE_G2 QE_R

Document Feedback CMV50000 Typical Operating Characteristics Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 18 Figure 13: Angular Response 100 -40 -30 -20 -10 0 10 20 30 40 Relative response [%] Angle [°] Ver_470nm Ver_520nm Ver_625nm Hor_470nm Hor_520nm Hor_625nm

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 19

7 Functional Description

7.1 Sensor Architecture

Figure 2 shows a high-level representation of the chip architecture for the CMV50000 sensor. The drawing shows the active pixel array and the periphery around it that enables the control and readout of the pixels. The core of the image sensor is made up from the pixel array, which is driven from two sides by 2 instances of the row logic and drivers. The pixel control signals are created globally by the global drivers and distributed to the sides of the sensor. The pixel data is read out row by row using a data path consisting of an analog front-end (AFE), analog-to-digital converter (ADC) and a digital data post- processing (DPP) block. The converted data is sent, pixel by pixel, to a set of sub-LVDS drivers. An additional control (CTR) channel provides synchronization information about the data on the data channels, while a specific CLK channel can be used to sample the data channels. The data path is organized in kernels of 360 columns. Between kernels, control signals are repeated. There is one sub-LVDS driver for every kernel. At the left and right side of the pixel array, an additional kernel of OB pixels is added. An on-chip sequencer controls the sensor operation and contains a register bank that is programmable over an SPI interface. There is also an on-chip temperature sensor available. A low- frequency CMOS input clock is transformed using an on-chip PLL to a set of high-frequency signals used in the sensor.

7.1.1 Pixel Array

Figure 14 shows the complete pixel array.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 20 Figure 14: Pixel Array The pixel array can be split up in 3 parts: Optical black (OB) pixels (left and right side), buffer pixels (around effective array perimeter) and effective pixels. Only the 68 effective OB pixels are used for internal row clamping, which improves row noise and allows setting a pre-defined black level. The buffer pixels form a guard ring around the effective pixels. The buffer pixels are optically active, but are not guaranteed to meet the optical specifications. The 98 OB and 22 buffer pixels are read out via the sub-LVDS OB-L/R outputs. The full resolution of the pixel array is 8160 × 6048 pixels. This results in an effective resolution of 7920 × 6004 pixels or 47.5Mpixels. The effective array is 36.4mm × 27.6mm which is slightly larger than the 35mm full frame optical format (= 36mm × 24mm; which would correspond to a window of 7826 × 5217). Because of the large sensor area, a wafer process called mask stitching is done. The vertical stitch line is located exactly in the middle of the array. Therefor a small offset between the pixels left and right of the stitch line might be present. Micro-lenses are placed on the pixels for improved quantum efficiency and fill factor.

7.1.2 Analog Front End

The analog front end consists of the PGA (programmable gain amplifier) and circuitry to prepare the signal for ADC conversion. Effective Pixels Black Columns Black Columns Buffer Pixels Buffer Pixels Buffer Pixels Buffer Pixels 22 buffer pixels 98 OB pixels (68 eff. OB) 7920 (effective) 8160 6004 (effective) 6048 22 buffer pixels 98 OB pixels (68 eff. OB) 120 120 STITCH 15 68 15 buffer Effective OB Pixel (0,0)

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 21

7.1.3 ADC

The column ADC converts the analog pixel value to a 12-bit value.

7.1.4 DPP

The DPP blocks perform digital operations on the visible pixel data: digital offset, digital gain, row noise correction.

7.1.5 Sub-LVDS Outputs

The sensor has 22 sub-LVDS data channels to output the processed data. Each data channel outputs the data of 360 columns. Readout modes using less parallel channels at reduced framerate are supported as well.

7.1.6 Sequencer

The on-chip sequencer will generate all required control signals to operate the sensor from only a few external control clocks. This sequencer can be activated and programmed through the SPI interface. Among the different features that the sequencer has implemented are the following:

• SPI protocol and register banks management.
• Exposure and frame timing generation based on external inputs or internal settings.
• Dual exposure HDR mode.
• Y-windowing, subsampling and binning.

7.1.7 SPI Interface

The SPI interface is used to load the sequencer registers with settings to configure the image sensor. Features like windowing, subsampling, gain and offset are programmed using this interface. The settings in the on-chip registers can also be read back for test and debug of the surrounding system.

7.1.8 Temperature Sensor

An on-chip thermal sensor is included. The temperature data is read out through the SPI interface.

7.1.9 PLL

Various clock frequencies are required internally to operate the sensor. These are derived from a single input frequency using an on-chip PLL. Through configuration over SPI, a range of input clock frequencies is supported.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 22 The 3 main internal clocks are CLK_ADC, CLK_SER and CLK_PIX:

• CLK_ADC is the PLL output clock and is equal to the data rate (830MHz for 830Mbit/s).
• CLK_SER is 1:2 of CLK_ADC and equal to the sub-LVDS output clock.
• CLK_PIX is the pixel clock and has a ratio of 1:12 of CLK_ADC.

7.1.10 OTP Memory

A non-volatile, one time programmable memory is included on-chip. This is programmed with unique device ID and temperature sensor calibration data which the user can use.

7.2 Operating the Sensor

This section explains how to connect and power the sensor, as well as basic recipes of how to configure the sensor in a certain operation mode.

7.2.1 Power Supplies

To power the sensor, six externally generated supplies are required as listed in Figure 6. A distinction is made between digital supplies (VDD12, VDD12C, VDD18) and analog supplies (VDD27, VDDARRAY, VDD33). Avoid using switching power supplies when possible, especially for the analog supplies. Sufficient bulk (at the regulators) and local (at the sensor pins) decoupling is needed. In case of multiple pins for the same supply, local decoupling must be foreseen for each pin (e.g. four capacitors for the four VDDARRAY pins). Separate ground planes must be provided to minimize coupling. For optimal noise performance, it is advised to keep the analog and digital ground nets separated and connect them together as close as possible to the external supply regulators.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 23 Figure 15: Power Supply Decoupling and Grounding Diagram Biasing (on-chip regulators) Operating the pixel array requires multiple different biasing supply levels. These supply levels can be generated using on-chip regulators. The chip contains 2 types of regulators, for positive supply levels and negative supply levels. The regulator output voltages are controlled using the SPI interface. The supply regulators are internally not connected to the actual image sensor. Connections have to be made on PCB level (from a VxxREG pin to a Vyy pin). Also, each supply regulator requires to be VDD27 VDD27CP -VDD27 VDDD12PLL2 VDDA12PLL2+ -VDD12 VDDA12PLL1 VDDD12PLL1 VDD12 VDD12C -VDD12C VDD18 -VDD18 VDDARRAY -VDDARRAY VDD33 +-VDD33 ≥100uF/supply single 100nF ceramic capacitor as close as possible to each physical pin VSSDPLL2 VSSAPLL2 VSSAPLL1 VSSDPLL1 VSSD VSSDC VSSA VSSACP Analog ground Digital ground (A/D Converters) Digital ground (Periphery)

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 24 decoupled by a 100µF and 100nF capacitor. The negative supply regulators also require a decoupling of 1µF on a separate output pin (which will settle to -1.2V). Next figure shows the positive and negative voltage regulator as well as the bias connections. Figure 16: On-Chip Regulators Connection Diagram For the 100nF and 1µF capacitors, ceramic types can be used. Capacitances of 100µF can be electrolytic types (beware of the polarity on the negative supplies!). The maximal specified ESR and ESL of these 100µF capacitors are 0.1Ω and 10nH respectively.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 25 A resistor network is necessary between VS1H and VS1L (±5% tolerance). To obtain an accurate current bias reference in the sensor, an external bias resistor of 15kOhm (±5%) must be placed between REF0 and ground. No decoupling is required in parallel with this resistor. A maximal capacitance of 1nF on this node is allowed. After power-up of the sensor, the recommended register settings will set the correct supply levels for these regulators (see section 7.4). Next table gives an overview of the available supply regulators, the connection to the bias pin and the required voltage on that pin. Figure 17: Bias Voltages Regulator Pin Type Bias Pin Voltage (V) VRESHREG Positive VRESH 3.2 VTXHREG Positive VTXH 3.0 VS1HREG Positive VS1H 3.0 VS2HREG Positive VS2H 3.0 VSELHREG Positive VSELH 3.0 VABREG Negative VAB -0.8 VPCLREG Negative VPCL -0.3 VSELLREG Negative VSELL -0.6 - Positive VS1L 0.25 - Ground VS2L 0 - Ground VRESL 0 VRESLREG Negative - 0 VS1LREG Negative - 0 VS2LREG Negative - 0 VRESLNEG12 Negative VABNEG12 -1.2 VS1LNEG12 Negative VPCLNEG12 -1.2 VS2LNEG12 Negative VSELLNEG12 -1.2

7.2.2 Power-Up/Down Sequence

To avoid peak currents and guarantee a proper power-up/down of the sensor, following supply order and timing must be applied.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 26 Figure 18: Supply Power-Up and Power-Down Sequences

7.2.3 Startup Sequence

After the supply power-up sequence, the general sequence below must be followed to configure and start operating the sensor. Deviating from the order or timing can lead to the sensor being in an unknown or unstable state. The sensor hard reset pin, RST_N, must be asserted (‘0’) during the supply ramp-up to initialize the sensor in the hard reset state. By releasing RST_N (‘1’), the sensor moves to soft reset state. CLK_IN can be started during either the hard reset or during soft reset state. During the soft reset state, the recommended SPI uploads must be executed (see section 7.4). One of them enables the PLL. After maximally 200µs, the PLL will lock. After the PLL has locked the sensor can be moved from soft reset state to idle state through a short SPI upload. In idle state, the sensor waits for an exposure request to begin grabbing, for example with REQ_EXP pin (depending on the configured sensor control mode). As indicated in the figure, a non-overlap of 1µs must be respected between each sensor state change and the next action. VDD18 VDD12 VDD12C VDD27 VDDARRAY VDD33 RST_N ≥100us ≥100us ≥100us ≥100us ≥100us ≥100us ≥100us ≥100us ≥100us ≥100us

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 27 Figure 19: Power-Up Sequence (not to scale)

7.2.4 Clocking

The sensor has two CMOS clock inputs: SPI_CLK and CLK_IN. SPI_CLK is part of the SPI interface used to configure the sensor. All other internal sensor clocks are derived from two PLLs running on CLK_IN. Refer to section 5 for the electrical specifications of the input clocks and to section 7.1.9 for the configuration procedure of the PLL.

7.2.5 SPI and Register Access

The sensor operation must be configured by uploading register settings. These static register values control the behavior of the sequencer on the chip, but also of all the analog and mixed-signal blocks. To write and read register settings the SPI interface is used. The SPI (Serial Peripheral Interface) consists of four wires, as shown in Figure 21. The CMV50000 image sensor always operates as the SPI slave. A single SPI access always consists of:

• Transfer of a control bit from master to slave to specify transfer direction (read or write)
• Transfer of 7-bit register address from master to slave
• Transfer of 8-bit data from master to slave (write operation) or from slave to master (read operation) Supplies CLK_IN RST_N SPI uploads PLL_LOCK REQ_EXP sensor state hard reset soft reset idle ≥1µs ≥1µs ≤ 200µs

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 30 SPI Write The SPI_MOSI data is sampled by the CMV image sensor on the rising edge of the SPI_CLK. The SPI_CSN signal shall be low for ½ a SPI_CLK period before the first data bit is sampled. SPI_CSN shall remain low for ½ a SPI_CLK period after the last falling edge of SPI_CLK. The first bit transferred is a control bit indicating a write operation (‘1’). Both the subsequent address (A<6:0>) and data (D<7:0>) are sent MSB-first. The address is that of the 1st register to be written to and the sequencer will automatically shift to the next register after 8 data bits. SPI_CSN shall stay low the entire time. The actual register value is updated with the new value on the falling edge of SPI_CLK on every D[0] bit. I.e. SPI_CLK shall go low at the end of D[0] for the write sequence to be completed. The timing of both write modes is illustrated below. Figure 24: SPI Write Timing SPI Read The timing of the SPI read sequence is similar to the SPI write sequence. The main differences are the control bit and the use of SPI_MISO. An SPI read is indicated by setting the control bit to ‘0’. After the control bit, the address of the register to read shall be transmitted MSB first. At the end of the LSB of the address, the data is launched on the SPI_MISO pin on the falling edge of the SPI_CLK. This means that the data can be sampled by the SPI master on the rising edge of the SPI_CLK. The data D<7:0> is transmitted MSB first on SPI_MISO. When not transmitting data, the SPI_MISO output is in high-Z state. Sequential SPI register addresses can also be read out in burst mode by keeping SPI_CSN low and clocking out additional bytes. The timing of both read modes is illustrated below. ctrl address data (N) Hi-Z Internal reg updated data (N+1) Internal reg updated ctrl address data Hi-Z Internal reg updated Tspi WRITE, SINGLEWRITE, BURST SPI_CLK SPI_CSN SPI_MOSI SPI_MISO SPI_CLK SPI_CSN SPI_MOSI SPI_MISO ½ Tspi ½ Tspi

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 31 Figure 25: SPI Read Timing Register Banks The sensor’s configuration registers are organized in four banks. Each bank contains 127 8-bit registers. To select a certain register bank, the register at address 0 is used. This register is accessible regardless of the currently selected register bank, of course. Figure 26: Bank Selection Register Register Name Bit Name Bank Addr Pos Description BANK_SEL BANK_SEL N/A 0 [1:0] 0: Bank 0 1: Bank 1 2: Bank 2 3: Bank 3 The value of BANK_SEL selects which register bank the current SPI access will have an effect on. An example is given below. ‘Addr’ is the address of the register being written to or read from and ‘D’ is the data being written. Figure 27: Bank Selection Example Sequence # Action Effect

1 WRITE(Addr=0, D=0) Set BANK_SEL to 0 (Point to BANK 0)

2 WRITE(Addr=12, D=3) BANK_SEL points to bank 0

Write value 3 to NROF_FRAMES register

3 WRITE(Addr=79,D=1) BANK_SEL points to bank 0

Write value of 1 to 8 lowest bits of TRAINING_WORD SPI_CLK SPI_CSN SPI_MOSI C=’0' A[6] A[5] A[4] A[3] A[2] A[1] A[0] ctrl address data (N) SPI_MISO Hi-Z D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] data (N+1) Hi-Z ctrl address data Hi-Z Hi-Z READ, SINGLEREAD, BURST SPI_CLK SPI_CSN SPI_MOSI SPI_MISO x x ½ Tspi½ Tspi

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 32 # Action Effect

4 WRITE(Addr=80,D=2)

BANK_SEL points to bank 0 Write value of 2 to highest bits of TRAINING_WORD Completes full 14-bit register: TRAINING_WORD = 513

5 WRITE(Addr=79, D=8;1;3)

BANK_SEL points to bank 0 Write 8 to LSBs of TRAINING_WORD Write 1 to MSBs of TRAINING_WORD Write 3 to TEST_LVDS

6 WRITE(Addr=0, D=0) Set BANK_SEL to 0 (Point to BANK 0)

7 READ(Addr=81) Reads TEST_LVDS (result = 3)

The registers are grouped into various categories, based on when they may or may not be updated. The category for every individual register can be found in section 8. The table below explains the details of the various categories. Figure 28: Register Categories Category Description - Registers without category can be changed at any time, but might directly influence the sensor execution. SYNC Registers are internally synchronized to start of frame (at the start of the GLOB state), so an entire frame is always read with the same SYNC configuration. This means that the registers may be updated at any time. FRAME Registers controlling the frame and exposure timing. These are only checked at the rising edge of REQ_EXP and may be updated at any time during operation. DC Can only be changed when sensor is in IDLE state, or in soft reset state. RST Only to be changed when sensor is in soft reset state. RO Read-only register. All write operations are ignored. Reading from a register is always allowed. When reading registers of category 'SYNC', the last previously uploaded value is read. This is NOT necessarily the same as the active frame-synchronized value. Figure 29: Frame Sync Reg. Name Bank Addr Bits Def. Description DISABLE_FRAMESYNC 0 1 [0] 0 0: Enable 1: Disable PARAM_HOLD 0 2 [0] 0 0: Frame sync 1: During SPI upload

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 33 The upload of 'SYNC' type registers can be constrained with the following registers: If DISABLE_FRAMESYNC is set to '1', frame synchronization is disabled. Any uploads will take effect immediately. Frame synchronization only happens if PARAM_HOLD is '0'. When uploading a bunch of SYNC-type registers together (for example, change a number of different YWIN settings), it's advised to set PARAM_HOLD to '1' during the entire upload. This prevents a frame from being started with only half of the required updates in case the frame start happened when the entire upload had not completed.

7.2.6 Soft Reset

Figure 30: Soft Reset Register Reg. name B Addr Bits Description CMD_REGS. CMD_RST_SOFT_N 0 3 [0] Use calculated value The sensor has an asynchronous reset input pin (RST_N) and an asynchronous reset register (CMD_RST_SOFT_N). Both are active-low. When combined, they have the following function:

• RST_N: Reset the entire sensor when low. This is considered a hard reset.
• CMD_RST_SOFT_N: Reset the entire sensor, except the SPI interface and register bank when low. This is considered a soft reset. As long as RST_N is high, all registers retain their value when CMD_RST_SOFT_N is low. The procedures to assert and release soft reset are described in detail in section 7.4.2.

7.2.7 Controlling Exposure and Readout

This section explains the different ways the exposure of a frame can be started and ended. First some important concepts of the frame timing model are explained. Basic Frame Timing During operation, the sensor can be in any of the following states:

• RESET: Asynchronous sensor reset is low, disabling the sensor entirely
• IDLE: Sensor is not doing anything while waiting for external requests
• EXPOSURE: Light is being integrated in the pixels
• GLOB: Closing global shutter by sampling all integrated pixel values
• READOUT: Reading out the acquired frame plus meta data and mandatory overhead

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 34 The sensor always exits a general sensor RESET condition in the IDLE state. This means that the sensor always acts as a slave, responding to external controls. A distinction can be made between two basic frame timing operations (sequential and pipelined operation), as detailed in the following two sections. Sequential Operation In sequential operation, the sensor goes through a sequential succession of EXPOSURE - GLOB - READOUT to grab a single image, as indicated in the figure below. When a cycle like this has been completed, the sensor is again in an IDLE state, waiting for new commands. Figure 31: State Chart: Sequential Operation Pipelined Operation The main property of pipelined operation is that the sensor can be in the EXPOSURE state and READOUT state at the same time. This basically means that the readout of frame N can be busy while the EXPOSURE state of frame N+1 has already started. The EXPOSURE can fully or partially overlap with a READOUT state. EXPOSURE GLOB IDLE RESET READOUT

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 36 Figure 34: State Diagram: Sequential Operation with Shutter Lag The distinction is important because:

• The EXPOSURE state is the direct response of external control (through sensor I/O requests or register settings),
• Yet it is the actual exposure that really matters to the user In the remainder of the document, when the concept of exposure or exposure time is mentioned, it will always be about the EXPOSURE state, unless stated otherwise. The reader should always bear in mind that the actual exposure is delayed in time with respect to this EXPOSURE state due to the shutter lag mechanism. In Figure 34 the shutter lag is shown under sequential operating conditions only, but note however that the shutter lag is present in all operation modes. The shutter lag is always present at the end of the EXPOSURE period: part of the actual exposure time will always extend into the GLOB state (sometimes called "exposure overlap"). The shutter lag at the beginning of the EXPOSURE periods is introduced artificially to compensate for this exposure overlap. If the shutter lag at the start of EXPOSURE is not allowed in certain applications, it can be disabled by setting register NO_SHUTTER_LAG high. This means that the actual exposure will start together with the start of the EXPOSURE state (practically: "immediately after an exposure request"). The disadvantage of this is obviously that the length of the actual exposure time is not the same as the length of the EXPOSURE state (the "exposure overlap" needs to be added). EXPOSURE GLOB IDLE RESET READOUT Actual exposure Δt = shutter lag

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 37 Figure 35: State Diagram: Sequential Operation, no Shutter Lag at Start

7.2.8 Sensor Control Modes

Figure 36: Control Mode Register Reg. Name Bank Addr Bits Def. Description CTRL_MODE 0 9 [2:0] 0 0: Full external 1: Programmed external 2: Triggered internal 3: Streaming The travel through the state diagrams of Figure 34 and Figure 35 can be externally controlled with the sensor inputs REQ_EXP and REQ_FRAME and a bunch of register settings (which will be detailed in further sections). This can be done in a number of different modes (each varying slightly in behavior and level of dependency on I/O control versus register configuration). The control mode is set with the CTRL_MODE register, as listed in Figure 37. Figure 37: Control Modes CTRL MODE Name External Control Internal Control 0 Full external Start of exposure. End of exposure (starting readout). Readout details. EXPOSURE GLOB IDLE RESET READOUT Actual exposure

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 38 CTRL MODE Name External Control Internal Control 1 Programmed external Start of exposure. Length of exposure. Readout details. 2 Triggered internal A finite sequence of 1 or more consecutive frames. Length of exposure. Frame rate. Sequence length. Readout details. 3 Streaming An infinite sequence of consecutive frames. Length of exposure. Frame rate. Readout details. Each of these control modes is introduced in one of the following sections. Control Mode 0: Full External In the Full External control mode, the exposure timing is fully controlled with the sensor input pins:

• A rising edge on REQ_EXP moves the sensor to the EXPOSURE state
• A rising edge on REQ_FRAME moves the sensor to the GLOB state, which will be automatically followed by READOUT. The length of the EXPOSURE state will exactly match the time between the rising edges of both triggers. In the figure below, the state diagrams of sequential and pipelined operation are annotated with the external control events. Figure 38: State Diagram: Full External Mode EXPOSURE GLOB IDLE RESET READOUT rising (REQ_EXP) rising (REQ_FRAME) 1st EXPOSURE GLOB IDLE RESET READOUT (N) EXPOSURE (N+1) (no new exposure) rising (REQ_EXP) rising (REQ_FRAME) rising (REQ_EXP) rising (REQ_FRAME)

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 41 Figure 43: State Diagram: Programmed External Mode Expanding this to a timing diagram gives similar timings to the ones shown in Figure 39 with REQ_FRAME continuously low. Since this mode is so similar to the Full External mode, also the lists of invalid and special control timing are quite similar. EXPOSURE GLOB IDLE RESET READOUT rising (REQ_EXP) after (exposure time) 1st EXPOSURE GLOB IDLE RESET READOUT (N) EXPOSURE (N+1) (no new exposure) rising (REQ_EXP) rising (REQ_EXP) after (exposure time) after (exposure time)

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 42 Figure 44: Programmed External Mode: Invalid and Special Control Timing # Invalid Control Timing Sensor Response PE_i0 REQ_EXP during GLOB Same response as FE_i0 PE_i1 EXPOSURE time expires during GLOB Same response as FE_i1 # Special Control Timing Sensor Response PE_s0 REQ_EXP during EXPOSURE Same response as FE_s0 PE_s1 EXPOSURE time expires during READOUT Same response as FE_s1 PE_s2 Any pulse on REQ_FRAME Will be ignored Control Mode 2: Triggered Internal Both external control modes have in common that every external request results in exactly one sensor response:

• In Full External mode:
• Each REQ_EXP initiates 1 EXPOSURE period
• Each REQ_FRAME initiates 1 GLOB period, followed by READOUT
• In Programmed External mode:
• Each REQ_EXP initiates the complete readout of 1 frame (EXPOSURE, GLOB and READOUT). This means that in those two modes, the frame rate is fully controlled externally by timing the requests. In the Triggered Internal mode, a single request is followed by a programmable number of frames, at a frame rate also set by register upload.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 43 Figure 45: State Diagram: Triggered Internal Mode When exiting IDLE mode, the behavior is identical to Programmed External mode: a rising edge on REQ_EXP will initiate the EXPOSURE state, which ends after a register defined exposure time. When the exposure time expires, a GLOB state is started, followed by READOUT. The behavior during the READOUT phase depends on the number of frames that were requested (also set by register) and the amount of frames that have already been read during the active sequence:

• Last READOUT of requested sequence:
• Finish active READOUT and move back to IDLE state
• All other READOUT:
• Restart EXPOSURE for the next frame. EXPOSURE is started at the correct moment to make it finish exactly 'frame time' later than the GLOB period was started.
• The end of this EXPOSURE will initiate a new GLOB phase.
• Because a GLOB period immediately follows the EXPOSURE period, there will be exactly 'frame time' delay between two consecutive frames. An example (with 3 frames requested) is shown in the figure below. EXPOSURE GLOB IDLE RESET READOUT rising (REQ_EXP) after (exposure time) 1st EXPOSURE GLOB IDLE RESET READOUT (N) EXPOSURE (N+1) rising (REQ_EXP) after (exposure time) after (frame time)last frame read out after (ExpDelay) ** => ExpDelay = frame time – exp time => No new EXPOSURE during last READOUT 1 frame read out

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 45

• The frame rate will not change: the first GLOB of the new sequence will be exactly 'frame time' after the last GLOB of the active sequence.
• If (1) > (2)
• The new EXPOSURE will start immediately.
• Because (1) is larger than (2), this EXPOSURE will end after the last frame would have finished.
• This causes a temporary drop in frame rate. The figure below shows the following cases (in all cases, the requested sequence is 2 frames long): Figure 48: Timing Diagram: Special Control Timing in Triggered Internal Mode (a) Normal timing → Capture 2 frames and go back to idle when done (b) TI_s0 → New request before last frame is active; extend sequence length to 4 (c) TI_s1, (1) < (2) → New EXPOSURE delayed to guarantee programmed frame rate (d) TI_s1, (1) > (2) → Temporary frame rate decrease to guarantee complete exposure time Programmed External vs Triggered Internal The attentive reader may have noticed that the Triggered Internal mode with a sequence length of 1 is quite similar to the Programmed External mode. This is mainly true, yet both differ in the way they handle new REQ_EXP requests if the sensor is not IDLE. EXPOSURE (2) EXPOSURE (3) EXPOSURE (1) REQ_EXP SENSOR STATE EXPOSURE (0) IDLE GLOB READOUT (0) GLOB READOUT (1) IDLE > Frame time (a) EXPOSURE (1) REQ_EXP SENSOR STATE EXPOSURE (0) IDLE GLOB READOUT (0) GLOB READOUT (1) (b) GLOB READOUT (2) GLOB READOUT (3) IDLE EXPOSURE (2) EXPOSURE (3)EXPOSURE (1) REQ_EXP SENSOR STATE EXPOSURE (0) IDLE GLOB READOUT (0) GLOB READOUT (1) (c) GLOB READOUT (2) GLOB READOUT (3) IDLE EXPOSURE (2) EXPOSURE (3)EXPOSURE (1) REQ_EXP SENSOR STATE EXPOSURE (0) IDLE GLOB READOUT (0) GLOB READOUT (1) (d) GLOB READOUT (2) GLOB READOUT (3) IDLE

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 46 Figure 49: Special Control Timing: PE and TI Comparison # Special Timing Programmed External Response Triggered Internal Response PE_i0 REQ_EXP during GLOB Will corrupt next frame = TI_s0 Sequence length extended by 1 frame with every new request PE_s0 REQ_EXP during EXPOSURE Will stop EXPOSURE and start new one Impossible situation: EXPOSURE by construction never finishes during READOUT or GLOB PE_i1 EXPOSURE time expires during GLOB Will corrupt next frame PE_s1 EXPOSURE time expires during READOUT Will stop READOUT and start new GLOB TI_s0 REQ_EXP before last READOUT of sequence has started = PE_i0 or PE_s0 Extend sequence length TI_s1 REQ_EXP after last READOUT of sequence has started Will start new exposure immediately, resulting in default behavior or PE_s1 Will start new exposure (directly or after delay, see Figure 48) In summary:

• Triggered Internal is the more forgiving mode. It adjusts the actual timing and scheduling of events as needed to always yield complete and correct images.
• Programmed External mode (and by extend also Full External mode) however directly responds to external requests at the cost of possibly corrupting or interrupting images but no missing higher priority exposures. Control Mode 3: Streaming Streaming mode is nothing else than Triggered Internal mode with an infinite sequence length. After starting the Streaming mode with a rising edge on REQ_EXP, it will keep on generating a continuous stream of frames forever until stopped explicitly (via sensor reset or HALT command; see section 7.2.9). As in Triggered Internal mode, the entire frame configuration is done by register upload. Next figure shows the state diagram of the Streaming mode.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 47 Figure 50: State Diagram: Streaming Mode Because of the nature of the streaming mode, there is no such thing as invalid or special control timing. Once started, it will be forever looping and all further REQ_EXP and REQ_FRAME pulses are ignored.

7.2.9 Software Commands

Figure 51: Software Command Registers Reg. Name Bank Addr Bits CMD_REGS.CMD_RST_SOFT_N 0 3 [0] CMD_REGS.CMD_REQ_EXP 0 3 [1] CMD_REGS.CMD_REQ_FRAME 0 3 [2] CMD_REGS.CMD_HALT_BLOCK 0 3 [3] CMD_REGS.CMD_HALT_NBLOCK 0 3 [4] The register bits CMD_REQ_EXP and CMD_REQ_FRAME are equivalent to their sensor input counterparts REQ_EXP and REQ_FRAME. The sensor REQ_EXP and REQ_FRAME inputs can therefore be tied low to use the register uploads for frame timing control. Just like with the sensor inputs, the rising edges of the register bits are considered. 1st EXPOSURE GLOB IDLE RESET READOUT (N) EXPOSURE (N+1) rising (REQ_EXP) after (exposure time) after (frame time) after (ExpDelay) ** => ExpDelay = frame time – exp time

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 48 By using the three registers defined above, the sensor can in theory be controlled with just the SPI interface plus 2 timing inputs (RST_N and CLK_IN) at the cost of a slightly reduced timing accuracy (because the registers are loaded via the SPI interface). The two HALT commands can be used to stop any active sensor operation and return the sensor to the IDLE state, waiting for new requests. The difference between the two is:

• CMD_HALT_BLOCK: When asserted, the active READOUT is finished before moving to IDLE state
• CMD_HALT_NBLOCK: when asserted, all operation is immediately stopped and the sensor directly moves to IDLE state. The HALT commands are a good way to get the sensor out of the Streaming control mode without asserting any reset.

7.3 Sensor Readout Format

7.3.1 Sub-LVDS Outputs

The CMV50000 has sub-LVDS (low voltage differential signaling) outputs to transport the image data to the surrounding system. In total, the sensor has 26 sub-LVDS output pairs (2 pins for each sub- LVDS channel):

• 22 Data channels
• 2 OB data channels
• 1 Control channel
• 1 Clock channel This means that a total of 52 pins of the CMV50000 are used for the sub-LVDS outputs. See the pin list for the exact pin numbers of the sub-LVDS outputs. The data channels are used to transfer the pixel data from the sensor to the receiver in the surrounding system. The output clock channel transports a clock, synchronous to the data on the other sub-LVDS channels. This clock should be used at the receiving end to sample the data. This clock is a DDR clock which means that the frequency will be half of the output data rate. When 830 Mbit/s output data rate is used, the sub-LVDS output clock will be 415MHz. The data on the control channel contains status information on the validity of the data on the data channels. Information on the control channel is grouped in 12-bit words that are transferred synchronous to the data channels. The figure below shows the data output interface.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 50

7.3.2 Pixel-Based Readout Format

Similar to other products in the CMV family, the data readout can be organized in pixels aligned using a side-band control channel. This mode is also referred to as CMV-like readout. Low-Level Pixel Timing

• Data is transferred serially over each channel, one complete word at a time.
• Data is transferred LSB first.
• All channels are word aligned (LSB of all channels sent during same CLK_OUT cycle). This results in the timing diagram in the figure below. In the figure, the output clock is set to 90° phase, which is the default case. Figure 54: Low-Level Pixel Timing Control Channel Like all other data channels, the CTR_OUT channel transmits its data word-based. A word being transmitted on the CTR channel consists of a number of bits, each reflecting the status of a certain aspect of the sensor behavior. The table below lists the function of each bit. Figure 55: Control Word # Name Function [0] SYNC Always '1' [1] DVAL High when there is valid pixel data on DATAx_OUT. (Stays high for entire row of valid data) [2] FVAL Goes high together with first DVAL of frame. Goes low together with last DVAL of frame. (Frames valid frame) [3] LOBVAL High when there is valid OB pixel data on OBL_OUT [4] ROBVAL High when there is valid OB pixel data on OBR_OUT [5] EXP_L High when exposure group 'L' is integrating light [6] EXP_S High when exposure group 'S' is integrating light CLK_OUT CTR_OUT DATA0_OUT DATA1_OUT OBL_OUT OBR_OUT 1DVAL FVAL LOBVAL ROBVAL EXP_L EXP_S GLOB 0 0 00 1 0 [2][11] LOB[0] LOB[1] LOB[2] LOB[3] LOB[4] LOB[5] LOB[6] LOB[7] LOB[8] LOB[9] LOB[10] LOB[11] [2][11] ROB[0] ROB[1] ROB[2] ROB[3] ROB[4] ROB[5] ROB[6] ROB[7] ROB[8] ROB[9] ROB[10] ROB[11] [0] [0] [0] [0] [1] [1] [1] [1] DVAL FVAL

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 52

• Two DVAL periods are separated by an overhead time (OT). The length of this overhead time depends on the channel multiplexing and row time settings, but will be at least 1 word.
• The OB data of a row of pixels appears on OBx_OUT one row time before the valid pixel data of the same row appears on DATAx_OUT. This allows external grabbing and evaluation of the OB data before the pixels of the same row are being read. This way, corrections can be done without the need for an additional row buffer. Output Clock Phase Figure 57: Output Clock Phase Register Reg. Name B Addr Bits Def. Description CLKGEN_CFG. CLKGEN_PHASE 1 6 [2:1] 1 0: 0° 1: 90° 2: 180° 3: 270° The sensor has an output clock channel (CLK_P/N) that is running synchronous to the output data. This clock can be used to sample the data at the receiver side. The phase of this clock (with respect to the data) can be programmed with CLKGEN_CFG.CLKGEN_PHASE as shown in the figure below depending on the receiver needs. Figure 58: Output Clock: Phase Programmability

7.3.3 Packet-Based Readout Format

The data on DATAx_OUT, OBx_OUT and CTR_OUT can be re-formatted in byte-aligned packets. Three different packet types are used, as illustrated in Figure 59. CLK_P/N B0D*_P/N B1 B2 CLKGEN_PHASE = 0 B0 B1 B2 CLKGEN_PHASE = 1 90o B0 B1 B2 CLKGEN_PHASE = 2 180o B0 B1 B2 CLKGEN_PHASE = 3 270o LSB LSB LSB LSB

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 53 Figure 59: Packet Types Data packets generally consist of:

• SYNC: synchronization code
• HEADER: information on the data that will follow
• PAYLOAD: the actual pixel or meta data
• Optional padding bits to keep 16-bit alignment
• CRC: checksum on the payload to detect bit errors Every channel continuously sends packets. The CTR_OUT channel only sends meta-data packets. DATAx_OUT and OBx_OUT channels send pixel data packets during sensor READOUT state and empty packets during GLOB, EXPOSURE or IDLE states. The sensor may also insert empty packets in the middle of a frame readout, for example in multiplexing scenarios. The packet header of an empty packet is optional (controlled via register upload), since it doesn’t contain any information. The possible padding bits in the pixel data are random. Low-Level Packet Timing
• The data output interface operates in 8-bit mode.
• Data is transferred serially over each channel in packets.
• Every packet field is transferred LSB/lsb first.
• Channels are not necessarily word aligned (LSB of different channels may be sent during different CLK_OUT cycle).
• A fixed serial sequence synchronizes the start of a packet. Data is always sent in (even) byte multiples. The start of a new packet is given by a synchronization code, which forms a fixed known sequence on the serial output. SYNC HEADER PIXEL DATA CRC n*16 bit32 bit padding bits a) pixel data packet 32 bit (or 96 bit) 16 bit SYNC HEADER META CRC 16 bit32 bit 32 bit (or 96 bit) 16 bit SYNC HEADER 32 bit 32 bit (or 96 bit) b) meta data packet c) empty packet SYNC 32 bit or

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 56 Meta-Data Code Most of the validity information that is on CTR_OUT channel in CMV-like mode is included in the pixel data packet header. A few bits that do not directly relate to the pixel data validity can be signaled on CTR_OUT using meta-data packets. The meta-data transmitted (LSB-first) on the control channel is organized according to Figure 64. Figure 64: CTR_OUT Channel Meta-Data Bits # Name Function [0] EXP_L High when pixel of dual exposure group 'L' are integrating [1] EXP_S High when pixel of dual exposure group 'S' are integrating [2] GLOB High when global sampling period is active [3-15] - Always 0 CRC Code For all packets with a Payload, a CRC is calculated over the payload, including padding bits, using the CRC-16-CCITT polynomial (0x1021). The CRC register is initialized to all ones (65535) at the start of each packet. Header and sync code are not included in the CRC. The highest order coefficient is transmitted least significant bit first.

7.4 Configuring the Sensor

This section provides detailed recipes for configuring the sensor in a certain operation mode. Refer to sections 7.5 and 7.6 for details on sensor exposure control and reading out images.

7.4.1 Operation Modes

The sensor supports different operation modes, listed per category in the table below, allowing for a large number of possible combinations. Figure 65: Operation Modes Output Format Modes INT.1 Pixel-based Readout Format INT.2 Packet-based Readout Format

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 57 Data Multiplexing Modes MUX.1 Use all 22 output channels MUX.2 Multiplex image data to 11 output channels MUX.3 Multiplex image data to 8 output channels MUX.4 Multiplex image data to 6 output channels MUX.5 Multiplex image data to 5 output channels MUX.6 Multiplex image data to 4 output channels MUX.7 Multiplex image data to 3 output channels MUX.8 Multiplex image data to 2 output channels MUX.9 Multiplex image data to 1 output channel Sensor Control Modes SEN.1 Full External SEN.2 Programmed External SEN.3 Triggered Internal SEN.4 Streaming SEN.1 Full External SEN.2 Programmed External SEN.3 Triggered Internal SEN.4 Streaming Image Modes IMG.1 Full array readout IMG.2.1 Color; sub-sampling in X and Y IMG.2.2 Color; binning IMG.3.1 Mono; sub-sampling in X and Y IMG.3.2 Mono; binning Gain Modes GAIN.1 Analog gain: ×1 GAIN.2 Analog gain: ×2 GAIN.3 Analog gain: ×4 OB Clamping Modes OBC.1 Optical black clamping ON OBC.2 Optical black clamping OFF

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 58

7.4.2 Flow Chart

Using the flow chart below, all steps necessary to configure or reconfigure the sensor can be determined, as well as their correct and recommended order of execution. Each step is elaborated in the next sections as a small recipe or procedure to follow. Where applicable, a reference to additional background information will be provided. The configuration is split in a static and a dynamic part. The static part must be executed once after every power-up or upon a static mode change. The dynamic part must be executed once after every power-up and can then be executed (partially) when changing the operation mode on the fly. Subsequent steps cannot be skipped, e.g. GAIN mode can be changed without changing IMG mode, but not the other way around. Information Useful are the optional paths to return to either the soft reset state or the hard reset state, which can be taken to temporarily put the sensor in a lower consumption state without having to do a full power-down/power-up cycle. Attention Not following these recommendations can lead to the sensor being in an unknown state with unpredictable behavior.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 59 Figure 66: Flow Chart Static configuration done COMMON SPI UPLOAD SET DATA MULTIPLEXING (MUX) SET PLL SET INTERFACE FORMAT (INT) SET OB CORRECTION (OBC) SET GAIN MODE (GAIN) SET IMAGE MODE (IMG) RELEASE SOFT RESET WAIT FOR PLL LOCK SET ROW_LENGTH ENABLE REGULATORS ENABLE BIAS SET EXPOSURE TIME Dynamic configuration done POWER UP SEQUENCE Sensor in power down POWER DOWN SEQUENCE ADJUST SHUTTER TIMING SET CONTROL MODE (SEN) RST_N = ‘0’ Sensor in hard reset RST_N = ‘1’ ASSERT SOFT RESET Sensor in soft reset

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 60 Power-Up Sequence The power-up and reset release sequence is described in section 7.2.2. Power-Down Sequence The power-down and reset assert sequence is described in section 7.2.2. Common SPI Upload Independent of the sensor operation mode or use-case, these settings must be uploaded in the specified order. Each line is a single 8-bit SPI data write access. The bank selection uploads are not stated here but must be done when changing banks. Figure 67: Common SPI Upload Sequence # Bank Address Value (decimal) # Bank Address Value (decimal) 1 3 49 1 81 2 80 206 2 2 1 215 82 2 81 245 3 2 2 12 83 2 82 1 4 2 3 162 84 2 83 130 5 2 4 133 85 2 84 255 6 2 5 1 86 3 54 105 7 2 6 206 87 3 55 1 8 2 7 1 88 3 56 14 9 2 8 5 89 3 57 3 10 2 9 50 90 3 51 20 11 2 10 11 91 3 52 0 12 2 11 2 92 3 53 38 13 2 12 6 93 0 82 2 14 2 13 1 94 0 83 2 15 2 14 242 95 0 84 2 16 2 15 242 96 0 87 4 17 2 16 207 97 1 119 0 18 2 17 1 98 1 109 0 19 2 18 134 99 1 101 1 20 2 19 154 100 1 117 2 21 2 20 255 101 1 59 4 22 2 21 219 102 1 112 1 23 2 22 2 103 1 113 0 24 2 23 140 104 1 47 16

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 61 # Bank Address Value (decimal) # Bank Address Value (decimal) 25 2 24 231 105 1 48 0 26 2 25 32 106 1 26 2 27 2 26 245 107 1 41 36 28 2 27 12 108 1 61 23 29 2 28 145 109 1 62 2 30 2 29 208 110 1 63 2 31 2 30 123 111 1 66 150 32 2 31 206 112 1 68 85 33 2 32 141 113 1 69 95 34 2 33 221 114 1 72 75 35 2 34 245 115 1 77 13 36 2 35 13 116 1 78 13 37 2 36 129 117 1 79 10 38 2 37 3 118 1 80 13 39 2 38 255 119 1 81 13 40 2 39 154 120 1 82 13 41 2 40 100 121 1 83 13 42 2 41 90 122 1 84 13 43 2 42 160 123 1 85 13 44 2 43 192 124 1 86 13 45 2 44 24 125 1 87 13 46 2 45 49 126 1 88 13 47 2 46 122 127 1 89 13 48 2 47 199 128 1 90 13 49 2 48 26 129 1 91 13 50 2 49 91 130 1 92 13 51 2 50 190 131 1 93 13 52 2 51 149 132 1 94 13 53 2 52 206 133 1 95 13 54 2 53 6 134 1 96 13 55 2 54 127 135 3 8 5 56 2 55 125 136 3 10 2 57 2 56 90 137 3 12 7 58 2 57 65 138 3 15 6 59 2 58 255 139 3 16 6 60 2 59 204 140 3 17 6 61 2 60 130 141 3 18 6 62 2 61 242 142 3 19 8 63 2 62 205 143 3 47 1

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 62 # Bank Address Value (decimal) # Bank Address Value (decimal) 64 2 63 245 144 0 5 1 65 2 64 194 145 0 84 2 66 2 65 113 146 1 28 200 67 2 66 9 147 1 29 50 68 2 67 242 148 1 20 128 69 2 68 206 149 1 21 1 70 2 69 245 150 1 22 236 71 2 70 130 151 1 23 10 72 2 71 255 152 1 24 56 73 2 72 204 153 1 25 1 74 2 73 130 154 1 58 3 75 2 74 242 155 0 76 128 76 2 75 205 156 0 77 0 77 2 76 245 157 3 50 71 78 2 77 194 158 1 70 190 79 2 78 121 159 1 71 130 80 2 79 242 Set Output Format Next table lists the required register upload to set the sensor output format (see 7.3). Figure 68: Output Format Register Register Bank Address INT.1 INT.2 OUTP_FORMAT 0 6 0 1 Set PLL Starting from the input clock frequency and the targeted output data rate, 4 parameters must be calculated to correctly configure the PLL. Then the PLL must be configured using the upload sequence below.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 63 Figure 69: Set PLL Sequence # Bank Address Value 1 0 106 0 2 0 110 0 3 0 114 0 4 0 107 pll1_pre_div (see calculation below) 5 0 109 pll1_clkout_sel (see calculation below) 6 0 108 pll1_ndiv (see calculation below) 7 0 112 pll2_ndiv (see calculation below) 8 0 114 1 9 0 106 1 10 0 110 1 The parameter pll1_pre_div depends only on the frequency of the sensor input clock CLK_IN (between 6 MHz and 96 MHz). Figure 70: CLK_IN Divider Selection CLK_IN pll1_pre_div

6 MHz – 12 MHz 0

12 MHz – 24 MHz 1

24 MHz – 48 MHz 2

48 MHz – 96 MHz 3

The parameter pll1_clkout_sel depends only on the targeted output data rate. Figure 71: Data Rate Selection Target Output Data Rate pll1_clkout_sel 460 – 830 Mbit/s 0 230 – 460 Mbit/s 1 120 – 230 Mbit/s 2 The parameter pll1_ndiv depends on the frequency of the sensor input clock CLK_IN as well as the desired output data rate.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 64 Equation 1: 𝑝𝑙𝑙1_𝑛𝑑𝑖𝑣 = 𝑓𝑙𝑜𝑜𝑟 ⌊2𝑝𝑙𝑙1_𝑝𝑟𝑒_𝑑𝑖𝑣 ∗ 2𝑝𝑙𝑙1_𝑐𝑙𝑘𝑜𝑢𝑡_𝑠𝑒𝑙 ∗ 𝑓(𝐶𝐿𝐾_𝐴𝐷𝐶) 𝑓(𝐶𝐿𝐾_𝐼𝑁) ⌋ With f(CLK_ADC) (in MHz) corresponding to the target data rate (in Mbit/s), and the floor operation being a round down to an integer. The parameter pll2_ndiv depends only on the frequency of the sensor input clock CLK_IN. Equation 2: 𝑝𝑙𝑙2_𝑛𝑑𝑖𝑣 = 𝑓𝑙𝑜𝑜𝑟 ⌊2𝑝𝑙𝑙1_𝑝𝑟𝑒_𝑑𝑖𝑣 ∗ 640 𝑓(𝐶𝐿𝐾_𝐼𝑁) ⌋ The resulting effective data rate can be calculated with the equation: Equation 3: 𝑒𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 𝑑𝑎𝑡𝑎 𝑟𝑎𝑡𝑒 = 𝑝𝑙𝑙1_𝑛𝑑𝑖𝑣 ∗ ( 𝑓(𝐶𝐿𝐾_𝐼𝑁) 2𝑝𝑙𝑙1_𝑝𝑟𝑒_𝑑𝑖𝑣 ∗ 2𝑝𝑙𝑙1_𝑐𝑙𝑘𝑜𝑢𝑡_𝑠𝑒𝑙 ) Attention Due to the flooring operation in calculating the parameters, the targeted data cannot be reached exactly for every possible input clock frequency (see example 3 below). Figure 72: PLL Settings Examples Parameters Example 1 Example 2 Example 3 f(CLK_IN) 20 MHz 96 MHz 6 MHz Targeted data rate 830 Mbit/s 120 Mbit/s 415 Mbit/s pll1_pre_div 1 3 0 pll1_clkout_sel 0 2 1 pll1_ndiv 83 40 138 pll2_ndiv 64 53 107 Effective data rate 830 Mbit/s 120 Mbit/s 414 Mbit/s

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 69 Enable Regulators Next table lists the procedure to enable the on-chip regulators (see section 7.2.1). Both positive and negative regulators need to be enabled. Figure 82: Enable Regulators Sequence # Bank Address Value (decimal) 1 3 14 31 2 3 7 63 3 3 4 63 4 3 5 42

5 Wait ≥ 10ms (Settling)

7 Wait ≥ 10ms (Settling)

To enable the internal biases, the following upload sequence (8-bit register writes and settling times) has to be followed: Figure 83: Enable Biasing Sequence # Bank Address Value (decimal) 1 1 60 4

2 Wait ≥ 1ms (settling)

6 Wait ≥ 1ms (settling)

8 Wait ≥ 1ms (settling)

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 70 # Bank Address Value (decimal) 17 3 37 255 18 3 38 255 19 3 39 255 20 3 40 255 21 3 41 255 22 3 42 255 23 3 43 3 24 3 44 3 25 3 23 255 26 3 24 255 27 3 25 255 28 3 26 255 29 3 27 255 30 3 28 255 31 3 29 255 32 3 30 255 33 3 31 3 34 3 32 3

35 Wait ≥ 1ms (settling)

Depending on the selected image mode (see 7.4.1), the following SPI register settings must be Figure 84: Image Mode Registers Register Bank Address IMG.1 (full) IMG.2.1 (color subs) IMG2.2 (color bin) IMG3.1 (mono subs) IMG3.2 (mono bin) COLOR_MODE 0 4 0 1 1 0 0 XSUBS 0 24 0 1 0 1 0 BIN_MODE 0 25 0 0 1 0 1 YWIN0 0 32 116 186 116 186 116 0 33 215 203 215 203 215 0 34 2 2 2 2 2

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7.5 Configuring Readout and Exposure

7.5.1 Frame Time and Exposure Time

Figure 88: Frame and Exposure Time Registers Reg. Name Bank Addr Bits Description CTRL_MODE 0 9 [2:0] Sets the sensor control mode TIME_UNIT 0 10-11 [13:0] Unit for frame and exposure time FRAME_TIME 0 13-14 [15:0] Sets the frame time in TIME_UNITs EXP_TIME_L 0 16-17 [15:0] Sets the exposure time in TIME_UNITs The table below briefly recaps the exposure and frame time configurability in the various sensor control modes (see section 7.2.8). Figure 89: Sensor Control Modes CTRL_MODE Mode Frame Time Exposure Time

0 Full External Via external timing Via external timing

1 Programmed External Via external timing Via registers

2 Triggered Internal Via registers Via registers

3 Streaming Internal Via registers Via registers

Both Frame time and Exposure time are specified via registers in number of Time Units (TU). The length of a Time Unit (TU) is itself register-programmable in 'number of CLK_PIX cycles'. The period of CLK_PIX equals the length of one complete (pixel-based) word at the output interface. The nominal CLK_PIX frequency in 12-bit mode is 69.167 MHz (≈415MHz / 6). By setting the TIME_UNIT register to 69, the time unit becomes ~1µs. The frame and exposure time, as set with the FRAME_TIME and EXP_TIME_* registers now represent multiples of 1µs. A CLK_ADC of 828MHz, yields a time unit (TU) of exactly 1µs. As an example, the default settings for these registers give: Figure 90: Default Times Register Setting Equation Effective TIME_UNIT 69 69/ f(CLK_PIX) 1.0024 µs FRAME_TIME 50 000 50 000 TU 50 ms (=20 fps)

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 73 Register Setting Equation Effective EXP_TIME_L 10 000 10 000 TU 10 ms Frame and exposure time registers are both 16-bit wide, which means that the exposure time can be specified with a resolution of up to 1/65536 with respect to the frame time. A too short FRAME_TIME will lead to unpredictable behavior. Dual Exposure HDR Figure 91: HDR Registers Reg. Name Bank Addr Bits Description DUAL_EXPOSURE 0 15 [0] 0: Dual Exposure off 1: Dual exposure on DUAL_EXP_GROUPING 0 118 [0] 0: Default grouping (mono) 1: Paired grouping (color) EXP_TIME_L 0 16-17 [15:0] Exposure Time of group L EXP_TIME_S 0 18-19 [15:0] Exposure Time of group S In dual exposure mode, one image can have 2 different exposure times, divided in 2 column groups. In the camera system this image can then translated to an HDR image containing both details in dark and bright areas. In the effective pixel array, the pixels are split into two exposure groups. When DUAL_EXP_GROUPING is set low:

• Exposure group S: all pixels of columns 0+4i and 2+4i
• Exposure group L: all pixels of columns 1+4i and 3+4i When DUAL_EXP_GROUPING is set high, the exposure groups use adjacent column pairs:
• Exposure group S: all pixels of columns 0+4i and 1+4i
• Exposure group L: all pixels of columns 2+4i and 3+4i The latter should be used on color sensors, keeping the Bayer pattern complete.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 75 Component Description Equation Texp_S Exposure time, group S (when DUAL_EXPOSURE = 1) EXP_TIME_S × TU Trow Row length (= 1 / DVAL rate) ROW_LENGTH × TCLK_PIX Tfval Number of valid rows in frame sum(YWINenabled.SIZE) Tdummy Number of dummy rows in frame 5 + (2 × NR_DUMMIES) TU is time unit expressed in seconds, not to be confused with contents of register TIME_UNIT. The Tread component corresponds to the length of the READOUT state used in section 7.2.7. In the external control modes, the same frame time equation should be respected to not interrupt the readout of active frames. The Tdummy calculation is only valid in pipelined operation (starting a new exposure during read out). Five dummy rows are always inserted between GLOB and read out, the NR_DUMMIES dummy rows are inserted in the read out when a new exposure starts. The factor 2 is required for dual exposure mode. If the above equation is not respected, the sensor behavior is undefined and no warning or error message is generated. It's the responsibility of the external controller to apply compliant register settings. The equation above specifies a minimum frame time. On the upper side, the frame time may be set to any possible value within the limits of the relevant registers to fine-tune the frame rate. The sensor has an absolute minimal exposure time of 100µs! Maximum Frame Rate Calculation If the frame time is set at its minimum and the exposure time is smaller than the read out time, the frame rate will be maximum and can be calculated with the following equation: Equation 10: 𝐹𝑟𝑎𝑚𝑒 𝑟𝑎𝑡𝑒 = 1 𝐹𝑟𝑎𝑚𝑒 𝑡𝑖𝑚𝑒 = 1 Tglob + Tread With Tglob the overhead time between read outs, needed to close the global shutter and sample the pixel charges in the sampling capacitors. Equation 11: 𝑇𝑔𝑙𝑜𝑏 = 150 ∗ GRAN_GLOB ∗ 12 𝐶𝐿𝐾_𝐴𝐷𝐶

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 76 Data rate is the sub-LVDS output data rate. With the standard settings at the maximum data rate of 830Mbit/s, Tglob will be 149.64µs. The read out time Tread consists of the time actual data is read out (FVAL is high) and some dummy rows. 5 of these dummy rows are between the end of GLOB and start of FVAL and the other are injected when the exposure of the next frame starts (defined by 2 * NR_DUMMIES ). So the total read out time is: Equation 12: 𝑇(𝑟𝑒𝑎𝑑) = 𝑹𝑶𝑾_𝑳𝑬𝑵𝑮𝑻𝑯 ∗ ( sum[𝐘𝐖𝐈𝐍enabled. 𝑺𝐈𝐙𝐄] + #dummy_rows_total) ∗ 12 𝐶𝐿𝐾_𝐴𝐷𝐶 With ROW_LENGTH being the value of register as set in section 7.4.2, sum(YWINenabled.SIZE), the sum of the rows in all enabled windows and #dummy_rows_total the total amount of dummy rows. With the full array being read out, the total read out time is 370*(6004+15)*12/830 = 32.198ms. The total frame time then becomes 32.35ms which is a maximum frame rate of 30.9fps in pixel-based output interface mode. Sequence Length Figure 94: Number of Frames Register Register Name Bank Addr Bits Description NROF_FRAMES 0 12 [7:0] See below In triggered internal mode (CTRL_MODE = 2), every rising edge on REQ_EXP (through external pin or register) will initiate the capture of a sequence of frames. The value in the NROF_FRAMES register at the moment of the rising edge on REQ_EXP will determine the sequence length. NROF_FRAMES may be set to any value between 1 and 255. In all other control modes, the register is ignored. When a sequence is still active, a new rising edge on REQ_EXP will increment the remaining number of frames by the value set in NROF_FRAMES. The total number of remaining frames may not be higher than 255.

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7.5.2 Row Length

Figure 95: Row Length Register Register Name Bank Addr Bits Description ROW_LENGTH 0 22-23 [13:0] Use equations below The row length Trow defines the DVAL frequency during readout; it can be programmed in number of CLK_PIX cycles with the ROW_LENGTH register. The row length has a minimum value because a number of parallel processes in the sensor need to be completed within one row time. The minimal row length depends on the number of outputs used and the read out mode (see equations in section 7.4.2). The maximal row length value is only constrained by the 14 bits size of register. Fine frame rate adjustments are done through external timing or with the FRAME_TIME register. Changing the row length only influences the DVAL frequency within a readout sequence. This can be useful when smaller or slower row buffers are used in the FPGA.

7.5.3 Windowing

The sensor supports multiple windows in the vertical direction to create regions of interest (ROI). Row Addressing As introduced in section 7.1.1, the sensor has buffer pixels rows above and below the effective pixels. Every row in the array is paired with a physical row address. This row address is used to specify vertical ROI positions as described in next section. Row addresses are assigned in ascending order starting from 0 for the row closest to the package pin row 1. Figure 96: Valid Row Addresses Region Address Range Effective pixels 22 -> 6025 Bottom buffer rows 0 -> 21 Top buffer rows 6026 -> 6047

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 78 Vertical ROI Settings The sensor allows up to 10 vertical windows to be concatenated in one single frame readout. Each of these windows is enabled by setting their bit in YWIN_ENA to ‘1’ (bit [0] = YWIN0, [1] = YWIN1 …). Each of these windows is configured with an YWINi register that defines the position, size and sub- sampling of the window. The 29 bits of each YWINi register span 4 physical SPI addresses. In the table below, only the start address is given (the upper address being 35+4×j). Figure 97: Vertical Windows Registers Register Name Bank Addr Bits Description YWIN_ENA 0 28-29 [9:0] One bit per window 0: Disable 1: Enable YWIN_BLACK 0 30 [9:0] One bit per window to control the ‘Electrical Black’ mode 0: Disable 1: Enable YWINi.SIZE 0 32+4×i [12:0] Number of read out rows in window i YWINi.START 0 32+4×i [25:13] Physical address of first row in window i YWINi.SUBS 0 32+4×i [28:26] Row subsampling in window i Ratio = 1/(2SUBS) The START address of a window should comply with the values in Figure 96. Only windows for which the respective bit in YWIN_ENA is set high are actually read out. This way multiple relevant Y-window specifications can be stored in the register map at the same time, enabling only the relevant ones. All enabled windows are concatenated together (the first row of a new window is read immediately after the last row of the previous). The number of rows actually read in one frame (= # of DVAL within one FVAL) is the sum of the SIZE fields of all windows enabled by YWIN_ENA. The figure below shows an example of using multiple windows.

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7.5.4 Vertical Subsampling

Figure 100: Vertical Subsampling Registers Register Name Bank Addr Bits Description YWINi.SUBS 0 32+4×i [28:26] Row subsampling in window i COLOR_MODE 0 4 [0] 0: Monochrome 1: Color The sensor supports vertical subsampling (skipping rows), which can be set per window. The register YWINi.SUBS defines the ratio of the accessed rows in window i as 1 out of every 2SUBS rows. When COLOR_MODE register is set to 1, the rows are grouped per 2 to follow the Bayer pattern, as illustrated in Figure 101. It is recommended to only use even window sizes in color mode to keep the Bayer filter pattern intact. ROI0 in the example below demonstrates the effect of an odd window size. Figure 101: Vertical ROI Example (color mode) row 101 row 100 row 103 row 102 row 50 row 104 row 52 row 51 row 54 row 53 row 56 row 55 row 58 row 57 row 60 row 59 Read out row 62 row 61 row 64 row 63 row 66 row 65 row 67 row read out row skipped FVAL31001 YWIN0 201 YWIN1 0 0 0 0 0 0 1 0 0 1 YWIN_ENA 52000 YWIN2 6503 YWIN3 DVAL 100YADDR 101 104 58 59 66 6750 51 ROI 3 ROI 0

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7.5.5 Horizontal Subsampling

Figure 102: Horizontal Subsampling Registers Register Name Bank Addr Bits Description XSUBS 0 24 [1:0] Horizontal subsampling setting Ratio = 1/(2XSUBS) COLOR_MODE 0 4 [0] 0: Mono 1: Color The sensor supports horizontal subsampling, reducing the amount of pixels per line to 1:2XSUBS. This horizontal subsampling is applied to the whole array and not per ROI like vertical subsampling. Depending on COLOR_MODE, pixel grouping is done to preserve the Bayer pattern.

7.5.6 Subsampling Mode

Combining both horizontal and vertical subsampling will divide the resolution of the image by 2 in both dimensions as illustrated in Figure 103. Figure 103: XY-Subsampling for Color and Mono Sensors In color mode, only 4 out of 4x4 neighboring pixels are read out. The output data is still Bayer patterned. In monochrome mode, only 1 out of 2x2 neighboring pixels is read out. The amount of pixels per channel mentioned in Figure 111 scales accordingly when combining horizontal subsampling with the readout over a reduced number of data channels.

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7.5.7 Binning Mode

Figure 104: Binning Mode Registers Register Name Bank Addr Bits Description BIN_MODE 0 25 [0] 0: Binning disabled 1: Binning enabled COLOR_MODE 0 4 [0] 0: Mono 1: Color The sensor supports both color and mono-chrome binning modes. In this mode, the values of 4 pixels will be summed, before the ADC. This will reduce the read out resolution with x4, but increases full well charge, dynamic range and SNR. In color mode, the Bayer pattern is preserved. In binning mode, the summed value of 4 pixels is readout on the bottom-left position of each binning square. For every row N read at the output, two internal rows are accessed. As seen in Figure 105 in binning mode, the summed value of 4 pixels is readout on the bottom-left position of each binning square. This means only 1 out 2 columns will be read out. Figure 105: Color and Monochrome Binning Modes Setting YWINi.SUBS to 0 will output binned rows N, N+1, N+2 and N+3. YWINi.SIZE refers to the number of physical rows in the array. The number of binned rows at the output will be half of this number. Binning mode cannot be combined with horizontal subsampling. For correct operation of the sensor, XSUBS must be set to 0 when binning mode is enabled. Binning mode may be combined with vertical subsampling. E.g. setting YWINi.SUBS to 1 will readout binned rows N, N+1, N+4, N+5 … in color mode and binned rows N, N+2, N+4 … in mono-chrome mode. N N+1 N+2 N+3 N N+1 N+2 N+3 N N N+2 N+2 N+1 N+1 N+3 N+3

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 83 In binning mode, the start of a pipelined exposure must occur during an internal even row access. Depending on the control mode a distinction must be made on how to achieve this. In full external mode, the edges of REQ_EXP must be timed after the edge of REQ_FRAME in one of the discrete windows given by the equations below: Equation 13: 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐹𝑅𝐴𝑀𝐸 > 𝑇𝑃𝐼𝑋 × ((2 × 𝑛 × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) + 2) 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐹𝑅𝐴𝑀𝐸 < 𝑇𝑃𝐼𝑋 × ((2 × (𝑛 + 1) × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) − 2) For positive n and with TPIX = 1/fCLK_PIX Information In dual exposure mode, the equations must be satisfied for both edges of REQ_EXP. In programmed external mode, the time between two sequential REQ_EXP pulses must be timed according to the equations: Equation 14: 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃_𝑝𝑟𝑒𝑣 > 𝑇𝑃𝐼𝑋 × (𝑇𝐼𝑀𝐸_𝑈𝑁𝐼𝑇 × 𝐸𝑋𝑃_𝑇𝐼𝑀𝐸_𝑖 + (2 × 𝑛 × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) + 2) 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃 − 𝑡𝑅𝐸𝑄_𝐸𝑋𝑃_𝑝𝑟𝑒𝑣 < 𝑇𝑃𝐼𝑋 × (𝑇𝐼𝑀𝐸_𝑈𝑁𝐼𝑇 × 𝐸𝑋𝑃_𝑇𝐼𝑀𝐸_𝑖 + (2 × (𝑛 + 1) × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻) − 2) For both EXP_TIME_L and EXP_TIME_S register settings (in dual exposure mode) and with tREQ_EXP_prev = the time of the previous REQ_EXP. The EXP_TIME_i register settings are the ones at tREQ_EXP_prev in case they are updated between frames. In Triggered internal and streaming modes, the EXP_TIME_i registers must be programmed to satisfy the equations: Equation 15: 2 × 𝑛 × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻 < 𝑇𝐼𝑀𝐸_𝑈𝑁𝐼𝑇 × (𝐹𝑅𝐴𝑀𝐸_𝑇𝐼𝑀𝐸 − 𝐸𝑋𝑃_𝑇𝐼𝑀𝐸_𝑖) < 2 × (𝑛 + 1) × 𝑅𝑂𝑊_𝐿𝐸𝑁𝐺𝑇𝐻

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7.6 Configuring the Output Data Format

7.6.1 Main Output Format

Using the register OUTP_FORMAT one of the data readout formats introduced in section 7.3 can be selected. Figure 106: Output Format Register Reg. Name Bank Addr Bits Description OUTP_FORMAT 0 6 [1:0] 0: Pixel-based 1: Packet-based. A soft reset is required after changing OUTP_FORMAT. Refer to the flow chart in section 7.4.2.

7.6.2 Word Alignment

Depending on the selected output format, word alignment must be done in a different way. Pixel-Based Word Alignment Figure 107: Training Word Register Reg. Name Bank Addr Bits Description TRAINING_WORD 0 79-80 [13:0] See below. Default value is 85 Whenever a data channel is not sending valid data (*), a training word is being transmitted continuously. The content of the training word can be set with the TRAINING_WORD register. As the sensor operates in 12-bit mode, only the lowest 12 bits of the register are sent as training word. On all DATAx_OUT channels, the last word cycle before DVAL, the training word is inverted. If the overhead time between two DVAL cycles is only 1 word wide, only the inverted training word is sent. (*) Valid data is:

• DATAx_OUT: Valid pixel data (DVAL = '1')
• OBL_OUT: Valid OB pixel data (LOBVAL = '1')
• OBR_OUT: Valid OB pixel data (ROBVAL = '1') The figure below shows illustrates this timing (drawn in the parallel domain).

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 85 Figure 108: Training Pattern When the sensor is not transmitting valid data, the training word can be used by the external controller to do word alignment (in other words: finding the position of bit [0]). Detecting the inverted training word will alert the presence of valid pixel data 1 pixel cycle in advance. When the sensor is IDLE, all control word bits except the LSB (SYNC) are '0'. Detecting the SYNC bit allows for easy word alignment at the receiver side. Since all channels are bit and word aligned by default, finding the LSB of 1 channel means the LSB of all channels has been found. Packet-Based Word Alignment As detailed in section 7.3.3, word-alignment is done using the fixed SYNC code. The HEADER field will alert the presence of valid pixel data in advance.

7.6.3 Packet Formatting

Figure 109: Data Packet Formatting Registers Reg. Name Bank Addr Bits Description NOHDR_EMPTYPKT 0 79 [0] See below FEC_HEADER 0 79 [1] See below Depending on the requirements of the application, a trade-off can be made between data packet overhead (i.e. data throughput) and robustness. When register NOHDR_EMPTYPKT is set to 1, the empty packet type described in section 7.3.3, will consist only of a SYNC code, without header. When register NOHDR_EMPTYPKT is set to 0, the empty packet type will consist of SYNC+HEADER. When register FEC_HEADER is set to 1, the HEADER field will be sent as 96 bit using the 1/3 FEC described in section 7.6.3. This 1/3 FEC allows bit error corrections on the receiving side. When register FEC_HEADER is set to 0, the HEADER field will be sent in the short form (32 bit) and not be protected against bit-errors. DVAL

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 86 The register DATA_PKT_CTRL has no effect in pixel-based readout mode.

7.6.4 Outputs

As illustrated in Figure 52 the sensor has 22 output channels to transfer valid image data. This means that in the fastest configuration, the sensor can output 22 pixels at the same time. As the valid image width is 7920 columns, a complete row is transferred in 370 word cycles when utilizing all outputs. Reduced Number of Data Channels In many applications, it is not mandatory to use all data channels (for example when reading a limited horizontal ROI or when operating the sensor below its nominal frame rate). In these cases, it could be interesting to use less data channels to save power consumption. The number of DATAx_OUT channels used is programmable with the NR_OUTP register. Figure 110: Number of Outputs Registers Reg. Name Bank Addr Bits Description NR_OUTP 0 26 [4:0] See above. By default all channels are used NR_OUTP_SCHEME 0 27 [0] 0: The first N channels are used 1: Channels are distributed evenly When NR_OUTP_SCHEME is set to 1, the N channels are distributed evenly, starting at DATA0_OUT. The exact mapping details are given in the table below. Figure 111: Reduced Number of Output Settings (NR_OUTP_SCHEME=1) NR_OUTP Used DATAx_OUT Channels Nr. of Pixels per Channel Nr. of Padding Pixels 1 0 7920 0 2 0,11 3960 0 3 0,8,16 2880 720 4 0,6,12,18 2160 720 5 0,5,10,15,20 1800 1080 6 0,4,8,12,16,20 1440 720 8 0,3,6,9,12,15,18,21 1080 720

22 All (0 to 21) 360 0

When NR_OUTP_SCHEME is set to 0, the first N channels starting at DATA0_OUT are used.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 87 For example, when setting NR_OUTP to 5, DATA0_OUT to DATA4_OUT channels are used. DATA5_OUT to DATA21_OUT are disabled. All other values in table above are still applicable. It is not allowed to set NR_OUTP to any value not listed in Figure 111 (i.e. 0, 7, 9 to 10 or 12 to 21.) All unused DATAx_OUT channels are automatically disabled (powered down). The last (or rightmost) channel of the used DATAx_OUT channels pads dummy pixels after the valid pixels when needed. Every channel sends an equal amount of pixels. Pixel Order The selected ROI (or full image width) is divided over 1 or more output channels. On each output, pixels are presented in-order. The figure below shows the timing of the readout of a single row for NR_OUTP set to 4 (each box represents the physical column address of the pixel). Here pixels 7920 to 8639 are dummy padding pixels and must be discarded. Figure 112: Multiplexed Sub-LVDS Timing Example A similar example for packet-based readout format is given in Figure 113.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 88 Figure 113: Multiplexed Sub-LVDS Timing Example in Packet Mode Every used data output channel outputs 6 data packets per line, separated by a number of empty packets. DATA3_OUT transmits only 4 data packets per line, the last being #22 which contains pixels 7560 to 7919. After that, empty packets are sent on DATA3_OUT. In packet-base mode, the word alignment between subsequent data packets might vary (depending on subsampling …). In the example above, this may be the case if the data packet is not a multiple of 4 bytes. This translates into the need to redo word alignment between two packets on the same channel when reading out over a reduced number of data channels.

7.7 Configuring the On-Chip Data Processing

7.7.1 Optical Black Clamping

Figure 114: Optical Black Registers Reg. Name Bank Addr Bits Description EOB_TARGET 0 76-77 [13:0] Sets the target black level value in DN EOB_BYPASS 1 42 [0] 0: OBC on (recommended) 1: OBC off EOB_BYPASS_VALUE 1 43-44 [13:0] Sets the ideal black level at the ADC (when OBC off). DATA0_OUT SYNC HEADER PIXELS 0 to 359 CRC PIXELS 360 to 719 CRCSYNC HEADER Pixel data packet 1 Pixel data packet 2 SYNC SYNC PIXELS 1800 to 2159 CRCHEADER Pixel data packet 6 SYNC ... SYNC SYNC DATA1_OUT SYNC HEADER PIXELS 2160 to 2519 CRC PIXELS 2520 to 2879 CRCSYNC HEADERSYNC SYNC PIXELS 3960 to 4319 CRCHEADERSYNC ... SYNC SYNC Pixel data packet 7 Pixel data packet 8 Pixel data packet 12 DATA2_OUT SYNC HEADER PIXELS 4320 to 4679 CRC PIXELS 4680 to 4999 CRCSYNC HEADERSYNC SYNC PIXELS 6120 to 6479 CRCHEADERSYNC ... SYNC SYNC Pixel data packet 13 Pixel data packet 14 Pixel data packet 18 DATA3_OUT SYNC HEADER PIXELS 6480 to 6839 CRC PIXELS 6840 to 7159 CRCSYNC HEADERSYNC SYNC ... SYNC SYNC Pixel data packet 19 Pixel data packet 20 SYNC SYNCSYNC SYNC SYNC SYNC

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 89 This section explains how to set and correct the black levels. Black Level Mapping The black level at a certain point in the pixel data path on the sensor is the analog level or digital word that corresponds to the level of an ideal dark pixel (zero illumination). In practice, it is the average of all real dark pixels (optically shielded) at that point in the data path. The black level at the output of the ADC does not equal the desired black level in the output images for several reasons including the ADC architecture, fixed pattern and temporal noise (row noise, frame noise), dark current… As illustrated in the figure below, the black level at the ADC output needs to be mapped on the target black level at the sensor output. Figure 115: Black Level Mapping The mapping is done using the equation: Equation 16: 𝑃𝐼𝑋𝐷𝐴𝑇𝐴_𝑂𝑈𝑇 = 𝑐𝑙𝑖𝑝[𝑃𝐼𝑋𝐴𝐷𝐶_𝑂𝑈𝑇 − 𝐵𝐿𝐴𝐶𝐾_𝐿𝐸𝑉𝐸𝐿𝐴𝐷𝐶_𝑂𝑈𝑇 + 𝐵𝐿𝐴𝐶𝐾_𝐿𝐸𝑉𝐸𝐿𝐷𝐴𝑇𝐴_𝑂𝑈𝑇] BLACK_LEVELDATA_OUT is the target black level at the output of the sensor. It is specified with the register EOB_TARGET. The recommended minimal setting is 128 (lower settings may decrease the quality of the resulting image), which means the level at the output for black pixels will be around 128DN. BLACK_LEVELADC_OUT is the black level at the output of the ADC. Its value is set differently depending on how the black level correction is done. This is detailed in the next two sections. 2^15-1 BLACK LEVEL black white VALID RANGE row noise frame noise ADC_OUT target OUTPUT RANGE DATA_OUT

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 90 On-Chip OBC Setting EOB_BYPASS to 0 enables the automatic on-chip black level correction (clamping). In this mode, BLACK_LEVELADC_OUT is calculated on-chip, based on OB pixels, for every row allowing to correct for row and frame noise in the image. This is the recommended mode of operation. Off-Chip OBC Setting EOB_BYPASS to 1 disables the automatic OBC. BLACK_LEVELADC_OUT is now specified with register EOB_BYPASS_VALUE. This value is constant and cannot correct for row noise in the image. Equation 17: 𝑃𝐼𝑋𝐷𝐴𝑇𝐴_𝑂𝑈𝑇 = 𝑐𝑙𝑖𝑝[𝑃𝐼𝑋𝐴𝐷𝐶_𝑂𝑈𝑇 − 𝐸𝑂𝐵_𝐵𝑌𝑃𝐴𝑆𝑆_𝑉𝐴𝐿𝑈𝐸 + 𝐸𝑂𝐵_𝑇𝐴𝑅𝐺𝐸𝑇] Further external or off-chip OBC can be achieved by reading out the OB pixel data (refer to section 7.8.5).

7.7.2 Analog and Digital Gain

Register GANA is used to set the analog gain. When changing the analog gain, the OB black level also has to be fine-tuned to have optimal black level clamping. Figure 116: Analog Gain Registers Reg. Name Bank Addr Bits Description GANA 0 78 [7:0] See settings in 7.4.2 EOB_OFFSET_FINE 1 38-39 [15:0] See settings in 7.4.2 Digital gain can be specified for the 4 color channels individually (even/odd columns, even/odd rows). E.g. GDIG_RE_CO relates to Rows Even and Columns Odd. The digital gain for each channel is defined by a similar equation: Equation 18: 𝐷𝑖𝑔𝑖𝑡𝑎𝑙 𝑔𝑎𝑖𝑛 (𝑅𝑥_𝐶𝑦) = (𝐺𝐷𝐼𝐺_𝑅𝑥_𝐶𝑦 + 1)/16 Base (default) digital gain is set by uploading a value of 15 to GDIG_Rx_Cy. The maximum digital gain is 16x with GDIG_Rx_Cy at 256. The lowest digital gain is 1/16x with GDIG_Rx_Cy at 0.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 91 Figure 117: Digital Gain Registers Reg. Name Bank Addr Bits Description GDIG_RE_CE 0 72 [7:0] Even Rows & Even Columns See Equation 18 GDIG_RE_CO 0 73 [7:0] Even Rows & Odd Columns See Equation 18 GDIG_RO_CE 0 74 [7:0] Odd Rows & Even Columns See Equation 18 GDIG_RO_CO 0 75 [7:0] Odd Rows & Odd Columns See Equation 18 If possible, using analog gain is preferred to using digital gain because it will improve SNR. Analog gain is applied in the data path before the ADC and digital gain is applied after the black level correction. This means that changing the digital gain setting does not require any of the offset correction settings to be updated.

7.7.3 Color versus Monochrome Mode

Figure 118: Color Mode Register Register Name Bank Addr Bits Description COLOR_MODE 0 4 [0] 0: Mono 1: Color As introduced in sections 7.5.6 and 7.5.7, sub sampling and binning modes behave differently for color and monochrome sensors. Set COLOR_MODE 1 for color sensors and 0 for monochrome sensors.

7.8 Additional Features

7.8.1 Digital Test Output

Figure 119: Digital Test Output Register Reg. Name Bank Addr Bits Description DMUX1_SEL 1 99 [4:0] Sets pin TDIGO1 function

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 92 A number of digital signals of the chip can be monitored in real-time during normal sensor operation via the sensor output pin TDIGO1. This can be very helpful for testing and debugging the system without having to rely on the sub-LVDS implementation of the control channel, so a test pad or connection to the FPGA is recommended. Selecting which signal to be monitored is done with DMUX1_SEL.

7.8.2 OTP Memory

The anti-fuse memory cells are organized in 128 rows (addresses) of 16 bits each. It contains the Device Serial Number, which is the unique serial number that matches with the one printed on the package. This serial number is in ASCII, so every address contains two characters. The Device Serial Number has two retry registers in case it had to be rewritten. So, the last retry register which contains a value other than zero, contains the correct sensor serial number. Next to the serial number, the memory has the Temperature (wafer test 1) register. It contains the value of the TSENS1_OUTPUT SPI register during our wafer test with the device at 70°C. Below you can find the positions of the OTP registers which can be read out. Figure 120: OTP Registers OTP Register Name Description Addr Length Device serial nr Unique serial number of device 2 8 Device serial nr (retry 1) Retry 1 10 8 Device serial nr (retry 2) Retry 2 18 8 Temperature (wafer test 1) TSENS1_OUTPUT value at 70°C 38 1 Read Access via the SPI Interface The OTP addresses are read out via the SPI interface through a predefined protocol as indicated in the table below. Figure 121: Read Access (read from address Ai) Step Description Register Access

1 Int OTP_CONTROL = "001” wait

20µs

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 93 Step Description Register Access

2 Set up address OTP_A = Ai

3 Read

OTP_CONTROL = "101” wait 5µs OTP_CONTROL = "001” wait 10µs Read value from OTP_DOUT

4 Exit OTP_CONTROL = “000”

The address Ai needs to be replaced by the desired OTP register. For multiple reads, steps 2 and 3 can be repeated consecutively for every address Ai. In the table below the addresses of the registers used during the protocol are given. Figure 122: Registers Used During Read Access Register Name Bit Name Bank Addr Pos OTP_CONTROL OTP_PDN 0 97 [0] OTP_CONTROL OTP_READBPROG 0 97 [1] OTP_CONTROL OTP_SELECTWLBL 0 97 [2] OTP_A - 0 98 [6:0] OTP_DOUT - 0 101 [15:0]

7.8.3 Temperature Sensor

Figure 123: Temperature Sensor Registers Reg. Name Bank Addr Bits Description TSENS1_PDN 0 103 [0] Power down not TSENS1_RSTN 0 103 [1] Reset not TSENS1_DCORRECT 0 103 [7:2] Offset value TSENS1_OUTPUT 0 104-105 [9:0] Read-only code The sensor has a temperature sensor placed at the top side of the sensor. In the range of -40°C to 125°C, the temperature sensor has a maximum error of ±12°C without calibration. After a one-point calibration at 25°C, the maximum error is ±5°C, after a two-point calibration, the maximum error becomes ±3°C.

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 94 To disable the temperature sensor, both TSENS1_PDN and TSENS1_RSTN must be set to ‘0’. To enable the temperature sensor, both TSENS1_PDN and TSENS1_RSTN must be set to ‘1’ and a settling time of 0.5ms must be respected before reading TSENS1_OUTPUT. The bit [9] of TSENS1_OUTPUT is high when an overflow condition has occurred in the temperature sensor. If this condition occurs, the temperature is either out of range, or a wrong offset was programmed in the TSENS1_DCORRECT register. No Calibration In order to get the uncalibrated temperature of the die (±12°C), follow this procedure: 1. Write value 131 to TSENS1_CONTROL 2. Wait 0.5ms (settling time) 3. Read TSENS1_OUTPUT 4. Calculate the measured die temperature according to the equation: Tm = (TSENS1_OUTPUT[8:0] / 2) – 100 1-Point Calibration The procedure below describes how to calculate and set the calibration value for the temperature sensor to output the correct sensor temperature (±5°C) using one measurement. 1. Let the sensor reach a known temperature (Tj) around 25°C and let it settle so that the die temperature (which equals the package temperature) is stable. 2. Write value 131 to TSENS1_CONTROL 3. Wait 0.5ms (settling time) 4. Read TSENS1_OUTPUT 5. Calculate the uncalibrated die temperature according to the equation Tu = (TSENS1_OUTPUT[8:0] / 2) – 100 6. Calculate the calibration error: Te = Tj - Tu 7. Update TSENS1_DCORRECT to 32 + (2 × Te) From now on, to measure the die temperature within ±5°C accuracy in the range from -40°C to 125°C: 1. Read TSENS1_OUTPUT 2. Calculate the measured die temperatures according to the equation Tm = (TSENS1_OUTPUT[8:0] / 2) – 100 An example:

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 95

• We let the sensor settle unpowered to a known ambient temperature of 28°C. We power up the sensor and immediately read out TSENS1_OUTPUT[8:0]. This way the junction temperature will be very close to the ambient temperature. TSENS1_OUTPUT[8:0] contains 260.
• So now Tu = (260/2) – 100 = 30 and Te = 28 – 30 = -2.
• Upload TSENS1_DCORRECT with the value 32 + (2 × Te) = 28.
• Reading out TSENS1_OUTPUT[8:0] now gives a value of 256, which corresponds to the correct temperature Tm = (256/2) – 100 = 28.
• When during operation, you read out TSENS1_OUTPUT[8:0] as, for example, 338, you know that the junction temperature is equal to Tj = Tm = (338/2) – 100 = 69°C (±5°C) 2-Point Calibration A 2-point calibration will correct for the offset as well as the slope over temperature. The procedure below describes how to calculate and set the calibration value for the temperature sensor to output the correct sensor temperature (±3°C) using two measurements. 1. Let the sensor reach a known temperature (Tj1) and let it settle so that the die temperature (which equals the package temperature) is stable. 2. Write value 131 to TSENS1_CONTROL, which will 3. Wait 0.5ms (settling time) 4. Read TSENS1_OUTPUT[8:0] and save it as B1. 5. Change the temperature to Tj2 (preferably more than 30°C difference with Tj1) and let it settle. 6. Read out TSENS1_OUTPUT[8:0] and save it as B2. 7. Calculate the slope as: M = (Tj2 – Tj1)/(B2-B1). For an ideal and perfect temperature sensor the slope will be 0.5. 8. Calculate the offset as: C = Tj1 - M*B1 = Tj2 – M×B2 9. Store the values M and C, which define a straight line. From now on, to measure the die temperature within ±3°C accuracy in the range from -40°C to 125°C: 1. Read TSENS1_OUTPUT 2. Calculate the measured die temperatures according to the equation Tm = M ×TSENS1_OUTPUT[8:0] + C Information For 2-point calibration TSENS1_DCORRECT must be left at its default value (32).

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 96

7.8.4 Version ID

Figure 124: Version ID Register Reg. Name Bank Addr Bits Description VERSION_ID 0 116 [7:0] Read only The read-only register VERSION_ID contains the revision number of the sensor.

7.8.5 Enable Optical Black Outputs

By default, the OBx_OUT channels are disabled. To enable (or disabling again) the OB channels, use the following SPI sequence: Figure 125: Enable OB Outputs Sequence Upload # Bank Address Write Value 1 1 107 1 2 1 106 16 3 1 106 24 4 1 106 16 5 1 106 16 6 1 106 16 7 1 106 16 8 1 106 16 9 1 106 16 10 1 106 16 11 1 106 16 12 1 106 16 13 1 106 16 14 1 106 16 15 1 106 16 16 1 106 16 17 1 106 16 18 1 106 16 19 1 106 16

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 97 Upload # Bank Address Write Value 20 1 106 16 21 1 106 16 22 1 106 16 23 1 106 16 24 1 106 16 25 1 106 16 26 1 106 16 27 1 106 24 28 1 106 16 29 1 107 0 The OB data is read out 1 row before the image data row it refers to. See also section 7.3.2. OB channel enabling/disabling can only be done when the PLL’s are locked, enabled and reset is released.

7.8.6 Test Images

Right before the sub-LVDS output drivers, the data stream can be replaced with a number of test patterns. Selection of test mode is made with the TEST_LVDS register as indicated in the table below. Figure 126: Test Images Registers Reg. Name Bank Addr Bits Description TEST_LVDS 0 81 [2:0] See table below TRAINING_WORD 0 79-80 [13:0] Choose a value Figure 127: Sub-LVDS Test Modes TEST_LVDS DATAx_OUT OBx_OUT CTR_OUT CLK_OUT

0 Normal Normal Normal Normal

1 Force training word

2 Test image: gradient Drive constant 0 Normal Normal

3 Test image: LFSR Drive constant 0 Normal Normal

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 98 In test mode 1, the data and OB output channels are forced to output register TRAINING_WORD and the control channel outputs its own training word. In test modes 2 and 3, a fixed test image is created. The CLK_OUT and CTR_OUT channels drive their normal values, so only the actual pixel data is replaced. This is useful to debug the camera system before grabbing real images. In sub-LVDS test mode 2, the data of pixel N is replaced by the value: Equation 19: 𝐷𝑇𝐸𝑆𝑇 = 𝑁𝐶𝑂𝐿 + 𝑁𝑅𝑂𝑊 + 𝑁𝐾𝐸𝑅𝑁𝐸𝐿 + 1 With:

• NCOL is the running number of pixel N in the DVAL pulse (0 for first valid pixel on each output)
• NROW is the running number of the DVAL pulse within FVAL (0 for first valid row in each FVAL)
• NKERNEL is the number of the channel from which pixel N originates The result is a 2D gradient (per channel), with a starting offset depending on the kernel number. The figure below shows an example using NR_OUTP = 4 (NKERNEL is resp. 0, 6, 12, 18). Figure 128: Gradient Test Image Pixel Data DVAL DATA0_OUT TP DATA1_OUT DATA2_OUT DATA3_OUT FVAL (0 + 0 + 18 + 1) (1 + 0 + 18 +1) (0 + 0 + 12 + 1) (0 + 0 + 6 +1) (0 + 0 + 0 + 1) (1 + 0 + 12 + 1) (1 + 0 + 6 +1) (1 + 0 + 0 + 1) TP TP TP ... ... ... ... 2178 (2159 + 0 +18 +1) 2172 (2159 + 0 +12 +1) 2166 (2159 + 0 + 6 +1) 2160 (2159 + 0 + 0 + 1) TP TP TP TP 20 (0 + 1 + 18 +1) (0 + 1 + 12 +1) (0 + 1 + 6 + 1) (0 + 1 + 0 + 1)

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 99 Figure 129: Gradient Test Image Example In sub-LVDS test mode 3, the actual data of every pixel is replaced by the output of a pseudo-random generator. The value of the first valid pixel of a frame is 4095. All outputs drive the same output value (unlike test mode 2, where the NKERNEL generates an offset between outputs).

Document Feedback CMV50000 Functional Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 100 Figure 130: LSFR Test Image Example

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 101

8 Register Description

8.1 Register Overview

Figure 131: Register Overview Bank Select

0 BANK_SEL - - - - - - BANK_SEL [1:0]

Figure 132: Register Overview Bank 0

1 PARAM_HOLD - - - - - - - PARAM_

2 DISABLE_

• - - - - - - DISABLE_ FRAMESYNC

3 CMD_REGS - - - HALT_

HALT_ BLOCK REQ_ FRAME REQ_ EXP RST_ SOFT_N

4 COLOR_MODE - - - - - - - COLOR_

5 <RESERVED> - - - - - - - -

6 OUTP_FORMAT - - - - - - OUTP_FORMAT [1:0]

7 DATA_PKT_

• - - - - - NOHDR_ EMPTYPKT FEC_ HEADER 8 <RESERVED> - - - - - - - -

9 CTRL_MODE - - - - - CTRL_MODE [2:0]

10 TIME_UNIT TIME_UNIT [7:0]

11 TIME_UNIT - - TIME_UNIT [13:8]

12 NROF_FRAMES NROF_FRAMES [7:0]

13 FRAME_TIME FRAME_TIME [7:0]

14 FRAME_TIME FRAME_TIME [15:8]

15 DUAL_

16 EXP_TIME_L EXP_TIME_L [7:0]

17 EXP_TIME_L EXP_TIME_L [15:8]

18 EXP_TIME_S EXP_TIME_S [7:0]

19 EXP_TIME_S EXP_TIME_S [15:8]

20 <RESERVED> - - - - - - - - 21 <RESERVED> - - - - - - - -

22 ROW_LENGTH ROW_LENGTH [7:0]

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 102

23 ROW_LENGTH - - ROW_LENGTH [13:8]

24 XSUBS - - - - - - XSUBS [1:0]

25 BIN_MODE - - - - - - - BIN_MODE

26 NR_OUTP - - - NR_OUTP [4:0]

27 NR_OUTP_

• - - - - - - NR_OUTP_ SCHEME

28 YWIN_ENA YWIN_ENA [7:0]

29 YWIN_ENA - - - - - - YWIN_ENA [9:8]

30 YWIN_BLACK YWIN_BLACK [7:0]

31 YWIN_BLACK - - - - - - YWIN_BLACK [9:8]

32 YWIN0 SIZE [7:0]

33 YWIN0 START [2:0] SIZE [12:8]

34 YWIN0 START [10:3]

35 YWIN0 - - - SUBS [2:0] START [12:11]

36 YWIN1 SIZE [7:0]

37 YWIN1 START [2:0] SIZE [12:8]

38 YWIN1 START [10:3]

39 YWIN1 SIZE [7:0]

40 YWIN2 START [2:0] SIZE [12:8]

41 YWIN2 START [10:3]

42 YWIN2 - - - SUBS [2:0] START [12:11]

43 YWIN2 - - - SUBS [2:0] START [12:11]

44 YWIN3 SIZE [7:0]

45 YWIN3 START [2:0] SIZE [12:8]

46 YWIN3 START [10:3]

47 YWIN3 - - - SUBS [2:0] START [12:11]

48 YWIN4 SIZE [7:0]

49 YWIN4 START [2:0] SIZE [12:8]

50 YWIN4 START [10:3]

51 YWIN4 - - - SUBS [2:0] START [12:11]

52 YWIN5 SIZE [7:0]

53 YWIN5 START [2:0] SIZE [12:8]

54 YWIN5 START [10:3]

55 YWIN5 - - - SUBS [2:0] START [12:11]

56 YWIN6 SIZE [7:0]

57 YWIN6 START [2:0] SIZE [12:8]

58 YWIN6 START [10:3]

59 YWIN6 - - - SUBS [2:0] START [12:11]

60 YWIN7 SIZE [7:0]

61 YWIN7 START [2:0] SIZE [12:8]

62 YWIN7 START [10:3]

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 103

63 YWIN7 - - - SUBS [2:0] START [12:11]

64 YWIN8 SIZE [7:0]

65 YWIN8 START [2:0] SIZE [12:8]

66 YWIN8 START [10:3]

67 YWIN8 - - - SUBS [2:0] START [12:11]

68 YWIN9 SIZE [7:0]

69 YWIN9 START [2:0] SIZE [12:8]

70 YWIN9 START [10:3]

71 YWIN9 - - - SUBS [2:0] START [12:11]

72 GDIG_RE_CE GDIG_RE_CE [7:0]

73 GDIG_RE_CO GDIG_RE_CO [7:0]

74 GDIG_RO_CE GDIG_RO_CE [7:0]

75 GDIG_RO_CO GDIG_RO_CO [7:0]

76 EOB_TARGET EOB_TARGET [7:0]

77 EOB_TARGET - - EOB_TARGET [13:8]

78 GANA GANA [7:0]

79 TRAINING_

TRAINING_WORD [7:0]

80 TRAINING_

• - TRAINING_WORD [13:8]

81 TEST_LVDS - - - - - TEST_LVDS [2:0]

• 100 <RESERVED> - - - - - - - -

101 OTP_DOUT OTP_DOUT [7:0]

102 OTP_DOUT OTP_DOUT [15:8]

103 TSENS1_

DCORRECT [5:0] RSTN PDN

104 TSENS1_

TSENS1_OUTPUT [7:0]

105 TSENS1_

• - - - - - TSENS1_OUTPUT [9:8]

106 PLL1_ENABLE - - - - - - - PLL1_

107 PLL1_PRE_DIV - - - - - - PLL1_PRE_DIV [1:0]

108 PLL1_NDIV PLL1_NDIV [7:0]

109 PLL1_

CLKOUT_SEL - - - - - - PLL1_CLKOUT_SEL [1:0]

110 PLL2_ENABLE - - - - - - - PLL2_

111 <RESERVED> - - - - - - - -

112 PLL2_NDIV PLL2_NDIV [7:0]

113 <RESERVED> - - - - - - - -

114 PLL_CLKDIV_

• - - - - - - PLL_ CLKDIV_ RSTN

115 PLL_LOCK - - - - - - PLL2_LOCK PLL1_LOCK

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116 VERSION_ID VERSION_ID [7:0]

117 NO_

SHUTTER_LAG - - - - - - - NO_ SHUTTER_ LAG

118 DUAL_EXP_

• - - - - - - DUAL_EXP_ GROUPING Figure 133: Register Overview Bank 1 1 - 4 <RESERVED> - - - - - - - -

5 GRAN_GLOB GRAN_GLOB [7:0]

6 CLKGEN_CFG - <RESERVED> [2:0] <RE

SERVED> CLKGEN_PHASE [1:0] <RE SERVED>

99 TDIG <RESERVED> [2:0] DMUX1_SEL [4:0]

• 109 <RESERVED> - - - - - - - -

110 TG_LENGTH TG_LENGTH [7:0]

111 TG_LENGTH - - TG_LENGTH [13:8]

• 113 <RESERVED> - - - - - - - -

114 SHUTTER_LAG SHUTTER_LAG [7:0]

115 SHUTTER_LAG SHUTTER_LAG [13:8]

• 119 <RESERVED> - - - - - - - - Figure 134: Register Overview Bank 2 - 127 <RESERVED> - - - - - - - - Figure 135: Register Overview Bank 3 - 48 <RESERVED> - - - - - - - -

49 PLL1_DISABLE

_CLKOUT - - - - - - - PLL1_ DISABLE_ CLKOUT

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8.2 Detailed Register Description

8.2.1 BANK_SEL Register (Address 0)

Figure 136: BANK_SEL Register Addr: 0 BANK_SEL Bit Bit Name Default Access Bit Description [1:0] BANK_SEL 0 - 0: Bank 0 1: Bank 1 2: Bank 2 3: Bank 3

8.2.2 PARAM_HOLD Register (Bank 0, Address 1)

Figure 137: PARAM_HOLD Register Bank: 0 Addr: 1 PARAM_HOLD Bit Bit Name Default Access Bit Description

0 PARAM_HOLD 0 - 0: Frame sync

1: During SPI upload

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8.2.3 DISABLE_FRAMESYNC Register (Bank 0, Address 2)

Figure 138: DISABLE_FRAMESYNC Register Bank: 0 Addr: 2 DISABLE_FRAMESYNC Bit Bit Name Default Access Bit Description [0] DISABLE_FRAMESYNC 0 - 0: Enable frame sync 1: Disable frame sync

8.2.4 CMD_REGS Register (Bank 0, Address 3)

Figure 139: CMD_REGS Register Bank: 0 Addr: 3 CMD_REGS Bit Bit Name Default Access Bit Description [0] RST_SOFT_N 0 - 0: Assert soft reset 1: Release soft reset [1] REQ_EXP 0 - 0: - 1: Sensor in EXPOSURE state [2] REQ_FRAME 0 - 0: - 1: Sensor in GLOB state [3] HALT_BLOCK 0 - 0: - 1: Finish active READOUT state and go to IDLE state [4] HALT_NBLOCK 0 - 0: - 1: Immediately stop sensor and go to IDLE state

8.2.5 COLOR_MODE Register (Bank 0, Address 4)

Figure 140: COLOR_MODE Register Bank: 0 Addr: 4 COLOR_MODE Bit Bit Name Default Access Bit Description [0] COLOR_MODE 0 DC 0: Monochrome mode

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 107 Bank: 0 Addr: 4 COLOR_MODE Bit Bit Name Default Access Bit Description 1: Color mode

8.2.6 OUTP_FORMAT Register (Bank 0, Address 6)

Figure 141: OUTP_FORMAT Register Bank: 0 Addr: 6 OUTP_FORMAT Bit Bit Name Default Access Bit Description [1:0] OUTP_FORMAT 0 RST 0: Pixel based format 1: Packet based format

8.2.7 DATA_PKT_CTRL Register (Bank 0, Address 7)

Figure 142: DATA_PKT_CTRL Register Bank: 0 Addr: 7 DATA_PKT_CTRL Bit Bit Name Default Access Bit Description [0] NOHDR_EMPTYPKT 1 DC 0: SYNC + HEADER in empty packet. 1: Only SYNC in empty packet [1] FEC_HEADER 1 DC 0: 32b HEADER 1: 96b HEADER with 1/3 FEC

8.2.8 CTRL_MODE Register (Bank 0, Address 9)

Figure 143: CTRL_MODE Register Bank: 0 Addr: 9 CTRL_MODE Bit Bit Name Default Access Bit Description [2:0] CTRL_MODE 1 DC 0: Full External (FE)

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 108 Bank: 0 Addr: 9 CTRL_MODE Bit Bit Name Default Access Bit Description 1: Programmed External (PE) 2: Triggered Internal (TI) 3: Streaming (S)

8.2.9 TIME_UNIT Register (Bank 0, Address 10-11)

Figure 144: TIME_UNIT Register Bank: 0 Addr: 10-11 TIME_UNIT Bit Bit Name Default Access Bit Description [13:0] TIME_UNIT 69 FRAME Sets unit for frame and exposure time

8.2.10 NROF_FRAMES Register (Bank 0, Address 12)

Figure 145: NROF_FRAMES Register Bank: 0 Addr: 12 NROF_FRAMES Bit Bit Name Default Access Bit Description [7:0] NROF_FRAMES 1 - Sets sequence length for TI control mode

8.2.11 FRAME_TIME Register (Bank 0, Address 13-14)

Figure 146: FRAME_TIME Register Bank: 0 Addr: 13-14 FRAME_TIME Bit Bit Name Default Access Bit Description [15:0] FRAME_TIME 33000 DC Sets the frame time in time units

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8.2.12 DUAL_EXPOSURE Register (Bank 0, Address 15)

Figure 147: DUAL_EXPOSURE Register Bank: 0 Addr: 15 DUAL_EXPOSURE Bit Bit Name Default Access Bit Description [0] DUAL_EXPOSURE 0 DC 0: Disable dual exposure HDR 1: Enable dual exposure HDR

8.2.13 EXP_TIME_L Register (Bank 0, Address 16-17)

Figure 148: EXP_TIME_L Register Bank: 0 Addr: 16-17 EXP_TIME_L Bit Bit Name Default Access Bit Description [15:0] EXP_TIME_L 10000 FRAME Sets the exposure time of pixels in group L in time units

8.2.14 EXP_TIME_S Register (Bank 0, Address 18-19)

Figure 149: EXP_TIME_S Register Bank: 0 Addr: 18-19 EXP_TIME_S Bit Bit Name Default Access Bit Description [15:0] EXP_TIME_S 0 FRAME Sets the exposure time of pixels in group S in time units

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8.2.15 ROW_LENGTH Register (Bank 0, Address 22-23)

Figure 150: ROW_LENGTH Register Bank: 0 Addr: 22-23 ROW_LENGTH Bit Bit Name Default Access Bit Description [13:0] ROW_LENGTH 380 SYNC Sets the row time

8.2.16 XSUBS Register (Bank 0, Address 24)

Figure 151: XSUBS Register Bank: 0 Addr: 24 XSUBS Bit Bit Name Default Access Bit Description [1:0] XSUBS 0 SYNC Set horizontal subsampling ratio to 1/(2XSUBS)

8.2.17 BIN_MODE Register (Bank 0, Address 25)

Figure 152: BIN_MODE Register Bank: 0 Addr: 25 BIN_MODE Bit Bit Name Default Access Bit Description [0] BIN_MODE 0 SYNC 0: Disable binning 1: Enable binning

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8.2.18 NR_OUTP Register (Bank 0, Address 26)

Figure 153: NR_OUTP Register Bank: 0 Addr: 26 NR_OUTP Bit Bit Name Default Access Bit Description [4:0] NR_OUTP 22 DC Sets the number of data outputs used to 1, 2, 3, 4, 5, 6, 8, 11 or 22.

8.2.19 NR_OUTP_SCHEME Register (Bank 0, Address 27)

Figure 154: NR_OUTP_SCHEME Register Bank: 0 Addr: 27 NR_OUTP_SCHEME Bit Bit Name Default Access Bit Description [0] NR_OUTP_SCHEME 0 DC 0: Use the first NR_OUTP data outputs 1: Used channels are distributed evenly

8.2.20 YWIN_ENA Register (Bank 0, Address 28-29)

Figure 155: YWIN_ENA Register Bank: 0 Addr: 28-29 YWIN_ENA Bit Bit Name Default Access Bit Description [9:0] YWIN_ENA 1 SYNC Enables/disables one window per bit 0: Disable window N 1: Enable window N

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8.2.21 YWIN_BLACK Register (Bank 0, Address 30-31)

Figure 156: YWIN_BLACK Register Bank: 0 Addr: 30-31 YWIN_BLACK Bit Bit Name Default Access Bit Description [9:0] YWIN_BLACK 0 SYNC Enables/disables Electrical Black for one window per bit 0: Disable EB of window N 1: Enable EB of window N

8.2.22 YWIN0 Register (Bank 0, Address 32-35)

Figure 157: YWIN0 Register Bank: 0 Addr: 32-35 YWIN0 Bit Bit Name Default Access Bit Description [12:0] SIZE 6004 SYNC Number of rows in this window [25:13] START 22 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.23 YWIN1 Register (Bank 0, Address 36-39)

Figure 158: YWIN1 Register Bank: 0 Addr: 36-39 YWIN1 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

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8.2.24 YWIN2 Register (Bank 0, Address 40-43)

Figure 159: YWIN2 Register Bank: 0 Addr: 40-43 YWIN2 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.25 YWIN3 Register (Bank 0, Address 44-47)

Figure 160: YWIN3 Register Bank: 0 Addr: 44-47 YWIN3 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.26 YWIN4 Register (Bank 0, Address 48-51)

Figure 161: YWIN4 Register Bank: 0 Addr: 48-51 YWIN4 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 114 Bank: 0 Addr: 48-51 YWIN4 Bit Bit Name Default Access Bit Description [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.27 YWIN5 Register (Bank 0, Address 52-55)

Figure 162: YWIN5 Register Bank: 0 Addr: 52-55 YWIN5 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.28 YWIN6 Register (Bank 0, Address 56-59)

Figure 163: YWIN6 Register Bank: 0 Addr: 56-59 YWIN6 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

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8.2.29 YWIN7 Register (Bank 0, Address 60-63)

Figure 164: YWIN7 Register Bank: 0 Addr: 60-63 YWIN7 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.30 YWIN8 Register (Bank 0, Address 64-67)

Figure 165: YWIN8 Register Bank: 0 Addr: 64-67 YWIN8 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.31 YWIN9 Register (Bank 0, Address 68-71)

Figure 166: YWIN9 Register Bank: 0 Addr: 68-71 YWIN9 Bit Bit Name Default Access Bit Description [12:0] SIZE 0 SYNC Number of rows in this window [25:13] START 0 SYNC Physical start address of the first row of this window

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 116 Bank: 0 Addr: 68-71 YWIN9 Bit Bit Name Default Access Bit Description [28:26] SUBS 0 SYNC Set row subsampling in this window with ratio 1/(2SUBS)

8.2.32 GDIG_RE_CE Register (Bank 0, Address 72)

Figure 167: GDIG_RE_CE Register Bank: 0 Addr: 72 GDIG_RE_CE Bit Bit Name Default Access Bit Description [7:0] GDIG_RE_CE 15 SYNC Sets the digital gain for the pixels in the even rows and even columns

8.2.33 GDIG_RE_CO Register (Bank 0, Address 73)

Figure 168: GDIG_RE_CO Register Bank: 0 Addr: 73 GDIG_RE_CO Bit Bit Name Default Access Bit Description [7:0] GDIG_RE_CO 15 SYNC Sets the digital gain for the pixels in the even rows and odd columns

8.2.34 GDIG_RO_CE Register (Bank 0, Address 74)

Figure 169: GDIG_RO_CE Register Bank: 0 Addr: 74 GDIG_RO_CE Bit Bit Name Default Access Bit Description [7:0] GDIG_RO_CE 15 SYNC Sets the digital gain for the pixels in the odd rows and even columns

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8.2.35 GDIG_RO_CO Register (Bank 0, Address 75)

Figure 170: GDIG_RO_CO Register Bank: 0 Addr: 75 GDIG_RO_CO Bit Bit Name Default Access Bit Description [7:0] GDIG_RO_CO 15 SYNC Sets the digital gain for the pixels in the odd rows and odd columns

8.2.36 EOB_TARGET Register (Bank 0, Address 76-77)

Figure 171: EOB_TARGET Register Bank: 0 Addr: 76-77 EOB_TARGET Bit Bit Name Default Access Bit Description [13:0] EOB_TARGET 32 SYNC Sets the target black level value in DN 128: 128DN

8.2.37 GANA Register (Bank 0, Address 78)

Figure 172: GANA Register Bank: 0 Addr: 78 GANA Bit Bit Name Default Access Bit Description [7:0] GANA 0 SYNC Sets the analog gain. Non-binning / binning mode: 255 / 223: x1 243 / 211: x2 241 / 209: x4

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8.2.38 TRAINING_WORD Register (Bank 0, Address 79-80)

Figure 173: TRAINING_WORD Register Bank: 0 Addr: 79-80 TRAINING_WORD Bit Bit Name Default Access Bit Description [13:0] TRAINING_WORD 85 - The training word on the data outputs

8.2.39 TEST_LVDS Register (Bank 0, Address 81)

Figure 174: TEST_LVDS Register Bank: 0 Addr: 81 TEST_LVDS Bit Bit Name Default Access Bit Description [2:0] TEST_LVDS 0 - Sets the output test mode. 0: Normal data output 1: Continuous training word 2: Gradient test image 3: LFSR test image

8.2.40 OTP_CONTROL Register (Bank 0, Address 97)

Figure 175: OTP_CONTROL Register Bank: 0 Addr: 97 OTP_CONTROL Bit Bit Name Default Access Bit Description [3:0] OTP_CONTROL 0 - OTP control input

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8.2.41 OTP_A Register (Bank 0, Address 98)

Figure 176: OTP_A Register Bank: 0 Addr: 98 OTP_A Bit Bit Name Default Access Bit Description [6:0] OTP_A 0 - OTP address input

8.2.42 OTP_DOUT Register (Bank 0, Address 101-102)

Figure 177: OTP_DOUT Register Bank: 0 Addr: 101-102 OTP_DOUT Bit Bit Name Default Access Bit Description [15:0] OTP_DOUT 0 RO OTP data output

8.2.43 TSENS1_CONTROL Register (Bank 0, Address 103)

Figure 178: TSENS1_CONTROL Register Bank: 0 Addr: 103 TSENS1_CONTROL Bit Bit Name Default Access Bit Description [0] PDN 0 - Temperature sensor power state: 0: Down 1: Up [1] RSTN 0 - Temperature sensor reset state: 0: Assert reset 1: Release reset [7:2] DCORRECT 32 - Temperature sensor correction value

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8.2.44 TSENS1_OUTPUT Register (Bank 0, Address 104-105)

Figure 179: TSENS1_OUTPUT Register Bank: 0 Addr: 104-105 TSENS1_OUTPUT Bit Bit Name Default Access Bit Description [9:0] TSENS1_OUTPUT 0 RO Temperature sensor output

8.2.45 PLL1_ENABLE Register (Bank 0, Address 106)

Figure 180: PLL1_ENABLE Register Bank: 0 Addr: 106 PLL1_ENABLE Bit Bit Name Default Access Bit Description [0] PLL1_ENABLE 0 RST 0: Disable PLL1 1: Enable PLL1

8.2.46 PLL1_PRE_DIV Register (Bank 0, Address 107)

Figure 181: PLL1_PRE_DIV Register Bank: 0 Addr: 107 PLL1_PRE_DIV Bit Bit Name Default Access Bit Description [1:0] PLL1_PRE_DIV 0 RST Set by CLK_IN frequency: 0: 6MHz – 12MHz 1: 12MHz – 24MHz 2: 24MHz – 48MHz 3: 48MHz – 96MHz

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8.2.47 PLL1_NDIV Register (Bank 0, Address 108)

Figure 182: PLL1_NDIV Register Bank: 0 Addr: 108 PLL1_NDIV Bit Bit Name Default Access Bit Description [7:0] PLL1_NDIV 0 RST PLL1 divider parameter

8.2.48 PLL1_CLKOUT_SEL Register (Bank 0, Address 109)

Figure 183: PLL1_CLKOUT_SEL Register Bank: 0 Addr: 109 PLL1_CLKOUT_SEL Bit Bit Name Default Access Bit Description [1:0] PLL1_CLKOUT_SEL 0 RST Set by target output data rate: 0: 460 – 830Mbit/s 1: 230 – 460Mbit/s 2: 120 – 230Mbit/s

8.2.49 PLL2_ENABLE Register (Bank 0, Address 110)

Figure 184: PLL2_ENABLE Register Bank: 0 Addr: 110 PLL2_ENABLE Bit Bit Name Default Access Bit Description [0] PLL2_ENABLE 0 RST 0: Disable PLL1 1: Enable PLL1

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8.2.50 PLL2_NDIV Register (Bank 0, Address 112)

Figure 185: PLL2_NDIV Register Bank: 0 Addr: 112 PLL2_NDIV Bit Bit Name Default Access Bit Description [7:0] PLL2_NDIV 0 RST PLL2 divider parameter

8.2.51 PLL_CLKDIV_RSTN Register (Bank 0, Address 114)

Figure 186: PLL_CLKDIV_RSTN Register Bank: 0 Addr: 114 PLL_CLKDIV_RSTN Bit Bit Name Default Access Bit Description [0] PLL_CLKDIV_RSTN 0 - 0: Assert CLK_IN divider reset 1: Release CLK_IN divider reset

8.2.52 PLL_LOCK Register (Bank 0, Address 115)

Figure 187: PLL_LOCK Register Bank: 0 Addr: 115 PLL_LOCK Bit Bit Name Default Access Bit Description [0] PLL1_LOCK 0 RO 0: PLL1 out of lock 1: PLL1 in lock [1] PLL2_LOCK 0 RO 0: PLL2 out of lock 1: PLL2 in lock

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8.2.53 VERSION_ID Register (Bank 0, Address 116)

Figure 188: VERSION_ID Register Bank: 0 Addr: 116 VERSION_ID Bit Bit Name Default Access Bit Description [7:0] VERSION_ID 1 RO Sensor revision number

8.2.54 NO_SHUTTER_LAG Register (Bank 0, Address 117)

Figure 189: NO_SHUTTER_LAG Register Bank: 0 Addr: 117 NO_SHUTTER_LAG Bit Bit Name Default Access Bit Description [0] NO_SHUTTER_LAG 0 DC 0: Enable shutter lag 1: Disable shutter lag

8.2.55 DUAL_EXP_GROUPING Register (Bank 0, Address 118)

Figure 190: DUAL_EXP_GROUPING Register Bank: 0 Addr: 118 DUAL_EXP_GROUPING Bit Bit Name Default Access Bit Description [0] DUAL_EXP_GROUPING 0 DC Dual exposure column grouping: 0: Default (monochrome) 1: Paired (color)

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8.2.56 GRAN_GLOB Register (Bank 1, Address 5)

Figure 191: GRAN_GLOB Register Bank: 1 Addr: 5 GRAN_GLOB Bit Bit Name Default Access Bit Description [7:0] GRAN_GLOB 1 - Sets shutter timing granularity

8.2.57 CLKGEN_CFG Register (Bank 1, Address 6)

Figure 192: CLKGEN_CFG Register Bank: 1 Addr: 6 CLKGEN_CFG Bit Bit Name Default Access Bit Description [0] <RESERVED> 0 RST [2:1] PHASE 1 RST Sets the phase of the output clock to the data. 0: 0° 1: 90° 2: 180° 3: 270° [3] <RESERVED> 1 RST [6:4] <RESERVED> 0 RST

8.2.58 EOB_OFFSET_FINE Register (Bank 1, Address 38-39)

Figure 193: EOB_OFFSET_FINE Register Bank: 1 Addr: 38-39 EOB_OFFSET_FINE Bit Bit Name Default Access Bit Description [15:0] EOB_OFFSET_FINE 0 - Fine tunes the OB offset depending on gain: 32920: Analog gain x1 33083: Analog gain x2

Document Feedback CMV50000 Register Description Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 125 Bank: 1 Addr: 38-39 EOB_OFFSET_FINE Bit Bit Name Default Access Bit Description 33418: Analog gain x4

8.2.59 EOB_BYPASS Register (Bank 1, Address 42)

Figure 194: EOB_BYPASS Register Bank: 1 Addr: 42 EOB_BYPASS Bit Bit Name Default Access Bit Description [0] EOB_BYPASS 0 - Enables Optical Black Correction (OBC) 0: OBC on (recommended) 1: OBC off

8.2.60 EOB_BYPASS_VALUE Register (Bank 1, Address 43-44)

Figure 195: EOB_BYPASS_VALUE Register Bank: 1 Addr: 43-44 EOB_BYPASS_VALUE Bit Bit Name Default Access Bit Description [13:0] EOB_BYPASS_VALUE 0 - Sets the black level at the ADC (with OBC off)

8.2.61 NR_DUMMIES Register (Bank 1, Address 46)

Figure 196: NR_DUMMIES Register Bank: 1 Addr: 46 NR_DUMMIES Bit Bit Name Default Access Bit Description [3:0] NR_DUMMIES 0 - Sets the number of dummy rows in pipeline mode

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8.2.62 TDIG Register (Bank 1, Address 99)

Figure 197: TDIG Register Bank: 1 Addr: 99 TDIG Bit Bit Name Default Access Bit Description [4:0] DMUX1_SEL 0 - Sets pin TDIGO1 function: 0: None 1: PLL_1_LOCK 2: PLL_2_LOCK 5: CLK_PIX 6: INT_REQ_FRAME 7: INT_REQ_EXP(L) 12: GLOB start 14: CTR_EXP(L)

8.2.63 TG_LENGTH Register (Bank 1, Address 110-111)

Figure 198: TG_LENGTH Register Bank: 1 Addr: 110-111 TG_LENGTH Bit Bit Name Default Access Bit Description [13:0] TG_LENGTH 0 DC Sets shutter timing

8.2.64 SHUTTER_LAG Register (Bank 1, Address 114-115)

Figure 199: SHUTTER_LAG Register Bank: 1 Addr: 114-115 SHUTTER_LAG Bit Bit Name Default Access Bit Description [13:0] SHUTTER_LAG 0 DC Sets the shutter lag

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8.2.65 PLL1_DISABLE_CLKOUT Register (Bank 3, Address 49)

Figure 200: PLL1_DISABLE_CLKOUT Register Bank: 3 Addr: 49 PLL1_DISABLE_CLKOUT Bit Bit Name Default Access Bit Description [0] PLL1_DISABLE_CLKOUT 0 RST Disables the PLL1 clock output for soft-reset. 0: Enabled 1: Disabled

Document Feedback CMV50000

Application Information

Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 128

9 Application Information

9.1 Color Filter

A color version of the CMV50000 has the color filters are applied in a Bayer pattern. The first pixel read-out, pixel (0, 0), is the bottom left one and has a blue filter. Figure 201: Bayer Color Filter

9.2 Socket

To avoid putting the sensor through the soldering heat (stressing the color filters and micro-lenses), it is advised to use a socket and place the sensor after the solder stage. Sockets for this device are available from Andon Electronics (www.andonelect.com) in both SMD (p/n: 575-20-19A-141-93M- R27-L14) and TH (p/n: 575-20-19A-141-01M-R27-L14) configuration. Contact Andon Electronics directly for more information.

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9.3 Pin Layout

Figure 202: Pin Layout from Top View

Document Feedback CMV50000 Package Drawings & Markings Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 130 Figure 203: (1) All dimensions are in millimeters. Angles in degrees. (2) Au plate 0.75µm min. over 2.0µm min Ni (3) Unplated are on tip shall be less than Ø0.30 within 0.50 max from pin tip (4) Materials: 1. Package: Alumina ceramic; 2. Pin: Alloy42; 3: Standoff pin: Alloy42 (6) The package has a marking on top, in the left bottom corner, at pin A1 position (7) This package contains no lead (Pb). (8) This drawing is subject to change without notice.

Document Feedback CMV50000 Package Drawings & Markings Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 131 Figure 204: 141-PGA Assembly Outline Drawing (1) Die size: 39.4mm x 31.1mm, relative to the die SEAL ring edge, the dimensions after dicing will be typically larger. (2) Optical center to die and package center offset: in X = 0, in Y = 628µm (3) Die positioned in the middle of the package cavity (4) Die placement accuracy: ±100µm (5) Die rotation in package: max ±0.2° (6) Die tilt towards cavity bottom: max ±0.1° (7) Distance from the cavity bottom to the photosensitive pixel layer (top of the die): 0.86 ±0.06mm (8) Distance from the top of the glass to the photosensitive pixel layer (top of the die): 1.65 ±0.20mm (9) Glass lid positioned in the middle of the package; (10) Glass size tolerance: ±0.1mm (11) Glass thickness: 0.7 ±0.05mm (12) Glass lid placement accuracy: ±200µm (13) All dimensions are in millimeters. Angles in degrees. (14) This package contains no lead (Pb). (15) This drawing is subject to change without notice. (16) The devices come covered with a heat resistant protective tape. (17) The 4 notches are not to be mechanically stressed They can be used to measure the level and tilt of the cavity bottom (die attach surface).

Document Feedback CMV50000 Package Drawings & Markings Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 132 Figure 205:

Document Feedback CMV50000 Packing Information Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 133

11 Packing Information

The devices are shipped in JEDEC PGA matrix trays.

Document Feedback CMV50000 Soldering Information Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 134

12 Soldering Information

Image sensors with color filter arrays (CFA) and micro lenses are especially sensitive to high temperatures. Prolonged heating at elevated temperatures may result in deterioration of the optical performance of the sensor. A socket (see 9.2) is the safest way to avoid any thermal stress. When not using a socket, to avoid heating up the device we recommend to use manual hand soldering. Wave soldering can be used with precautions (see below). Reflow soldering is not recommended. Manual soldering: Use partial heating method and use a soldering iron with temperature control. The soldering iron tip temperature is not to exceed 350°C with a 270°C maximum pin temperature. Touch for a 2 seconds maximum duration per pin. Avoid touching and global heating of the ceramic package during soldering. Failure to do so may alter device performance and reliability. Wave soldering: Wave solder dipping can cause damage to the glass and harm the imaging capability of the device. Avoid the solder to come in contact with the glass or ceramic body.

Document Feedback CMV50000 Revision Information Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 135 Document Status Product Status Definition Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Datasheet Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams-OSRAM AG standard warranty as given in the General Terms of Trade Other Definitions Draft / Preliminary: The draft / preliminary status of a document indicates that the content is still under internal review and subject to change without notice. ams-OSRAM AG does not give any warranties as to the accuracy or completeness of information included in a draft / preliminary version of a document and shall have no liability for the consequences of use of such information. Short Datasheet: A short datasheet is intended for quick reference only, it is an extract from a full datasheet with the same product number(s ) and title. For detailed and full information always see the relevant full datasheet. In case of any inconsistency or conflict with the short datasheet, the full datasheet shall prevail. Changes from previous version to current revision v4-00 Page Removed part-number of removable glass variant 5

• Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
• Correction of typographical errors is not explicitly mentioned.

Document Feedback CMV50000 Legal Information Datasheet • PUBLIC DS000522 • v4-00 • 2023-Aug-03 136 │ 136

14 Legal Information

Copyright & Disclaimer Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior w ritten consent of the copyright owner. Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided by ams-OSRAM AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligat ion or liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services. Product and functional safety devices/applications or medical devices/applications: ams-OSRAM AG components are not developed, constructed or tested for the application as safety relevant component or for the application in medical devices. ams-OSRAM AG products are not qualified at module and system level for such application. In case buyer – or customer supplied by buyer – considers using ams-OSRAM AG components in product safety devices/applications or medical devices/applications, buyer and/or customer has to inform the local sales partner of ams - OSRAM AG immediately and ams-OSRAM AG and buyer and /or customer will analyze and coordinate the customer-specific request between ams-OSRAM AG and buyer and/or customer. ams OSRAM Semiconductor RoHS Compliance Statement RoHS Compliant: The term RoHS compliant means that ams-OSRAM AG semiconductor products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories (per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Headquarters ams-OSRAM AG Tobelbader Strasse 30

8141 Premstaetten

Austria, Europe Tel: +43 (0) 3136 500 0 Please visit our website at ams-osram.com For information about our products go to Products For technical support use our Technical Support Form For feedback about this document use Document Feedback For sales offices and branches go to Sales Offices / Branches For distributors and sales representatives go to Channel Partners