CMS32F035

CS32F035 CHIPSEA | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 51

Technical content

32-bitARM®M0-basedMCU REV1.4 CS32F035/F036 DATASHEET

聚点滴之芯．成浩瀚之海 RevisionHistory Reversion Description Date

1.0 Firstedition 2020-7-18

1.1 NewmodelCS32F035K6U6 2020-12-31

1.2 ChangeinCS32F036K6U7packagethickness 2021-3-5

1.3 Andpackageintroduction 2021-8-17

1.4 Addmodelcs32f035f6p7

Deletethetapepackingmodelintheorderinformation 2021-8-30

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 3/51 文件编号：CS-QR-YF-054A02 Tableofcontents

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 4/51 文件编号：CS-QR-YF-054A02

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 5/51 文件编号：CS-QR-YF-054A02

1 Introduction

TheCS32F035/F036isaseriesof32-bitARM®Cortex®-M0basedmicrocontrollerincludingCS32F035and CS32F036,rangingfrom20to32pinswith32KBFlashand 4KBofSRAM.Themaximumoperating frequencyis48MHz.TheCS32F035/F036offerstandardcommunicationinerfaces(SPI,USART,I2C),one 12-bitSARADC,five16-bittimersandoneadvanced-PWMtimer. TheCS32F035/F036canoperateinthetemperaturerangeof -40to85℃ or-40to105℃ and powersupply rangeof2.0to5.5V. TheCS32F035/F036offerasetoflow-powermodes,savingpowerfordifferentapplicaions. TheCS32F035/F036microcontrollersaresuitablefordifferentapplications,suchasSmartAppliance,mobile device,consumerelectronics,industrialapplications,andGPSdevice.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 6/51 文件编号：CS-QR-YF-054A02

2 Features

 Core — 32-bitARM® Cortex® -M0 — upto48MHz  Memories — 32KBprogramflash — 192Bdataflash — 4KBSRAMwithparitycheck  Clocks — 8MHzinternalRCoscillator(HRC),±1%@typ — 14MHzinternalRCoscillator(HRC14),±1%@typ — 40KHzinternalRCoscillator(LRC),±10%@typ — 4~32MHzexternalhighspeedcrystaloscillator(HXT) — Internalx2,x3,..,x16Phase-lockedloop(PLL),upto48MHz  Operationenvironment — VDDpowersupply:2.0to5.5V — VDDApowersupply:2.0to5.5V — Temperaturerange:-40to85℃ or-40to105℃  BOOTmode — Supportbootfromprogramflash — Supportbootfromsystemmemory — SupportbootfromSRAM  Powermanagement — Low-powermodes:sleep,deepsleep1,deepsleep2,powerdown — Power-on/power-downreset(POR/PDR) — Lowvoltagedetector(LVD)  I/Os — 27I/Osupto48MHz — AllI/Oscanbemappedtoexternalinterruptvectors  ADC — One12-bitADC — Conversiontimeisupto1uS — Upto10externalinputchannels — Operationvoltagerange:2.4to5.5V — Inputsignalrange:0~5.5V  Timers — Oneadvanced16-bittimerfor6channelsPWMoutput — Foregeneralpurpose16-bittimers — Onebasic16-bittimer — Onefreewatchdogtimer(FWDT):8-bitprescalerand12-bitdowncounter — Onewindowwatchdogtimer(WWDT):7-bitdowncounter

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 7/51 文件编号：CS-QR-YF-054A02 — OneSysTicktimer:24-bitdowncounter  DMA — Fivechannels — Supportperipherals:SPIx,I2Cx,USARTx,TIMx,ADC  Inerruptandevents — Upto32maskableinterruptchannels — Fourprioritylevels — Sixteenexternalinterruptlines  SPI — OnrSPI — 3-bitpredividersuppport8kindsof frequency — Framesizecanbeconfigedto4to16bits  USART — TwoUSARTs — Support:ISO7816,LIN,IrDAmode — Supportautobaudratedetection — Canwakeupfromdeepsleep1anddeepsleep2  I2C — OneI2Cwithmasterorslavemode — Support:standardmode(upto100kbit/s),Fastmode(upto400kbit/s), — Support:7-bitand10-bitaddressingmodes  CRCunit  Serialwiredebug(SWD)  Packages — TSSOP20 — QFN28 — QFN32 — LQFP32

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 8/51 文件编号：CS-QR-YF-054A02

3 Configuration

ThepackageofCS32F035/F036serialinclude:TSSOP20,QFN28,QFN32,LQFP32. CS32F035/F036serial Configureddevice CS32F035 CS32F036 K6Ux F6Px G6Ux K6Ux K6Tx Flash（Kbytes） 32 32 32 32 32 SRAM（Kbytes） 4 4 4 4 4 Timers 16-bit Advanced 16-bit General purpose FWDT 1 WWDT 1 SysTick 1 Communication interfaces SPI 1 1 1 1 1 I2C 1 1 1 1 1 USART 2 2 2 2 2 ADC Unit 1 Ext.channel 10 9 10 Int.channel 2 I/O 27 15 23 27 25 Operatingvoltage 2~5.5V Operatingtemperature Ambientoperationtemperature:-40~850C/-40~1050C Junctiontemperature:-40~1050C/-40~1250C PackingType QFN32 (4×4×0.75- e=0.40) TSSOP20 QFN28 (4×4×0.55- e=0.50) QFN32 (5×5×0.75- e=0.50) LQFP32

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 9/51 文件编号：CS-QR-YF-054A02 Figure1Blockdiagram

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 10/51 文件编号：CS-QR-YF-054A02

4 Pindescription

4.1 LQFP32

4.2 QFN32

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 11/51 文件编号：CS-QR-YF-054A02

4.3 QFN28

4.4 TSSOP20（CS32F036F6Px）

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 12/51 文件编号：CS-QR-YF-054A02

4.5 TSSOP20（CS32F035F6Px）

4.6 Pindescription

PinNo. Pinname Type

Description

Multiplexedfuncions Specialfunctions 2 2 2 2 PF0/HXT_IN (PF0) I/O - HXT_IN 3 3 3 3 PF1/HXT_OUT (PF1) I/O - HXT_OUT 4 4 4 4 NRST I/O Resetinput/internalresetoutput,withweakpull- upresistor（activelow） 5 5 5 5 VDDA S Analogpowersupply 6 6 6 6 PA0 I/O USART2_CTS ADC_IN0, WKUP1 7 7 7 7 PA1 I/O EVENTOUT, USART2_RTS ADC_IN1 8 8 8 8 PA2 I/O USART2_TX ADC_IN2 9 9 9 9 PA3 I/O USART2_RX ADC_IN3 10 10 10 10 PA4 I/O SPI1_NSS, TIM14_CH1, USART2_CK ADC_IN4 11 11 11 11 PA5 I/O SPI1_SCK ADC_IN5 12 12 12 12 PA6 I/O SPI1_MISO, ADC_IN6

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 13/51 文件编号：CS-QR-YF-054A02 TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT 13 13 13 13 PA7 I/O SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT ADC_IN7 14 14 14 PB0 I/O TIM3_CH3, TIM1_CH2N, EVENTOUT ADC_IN8 15 15 15 14 PB1 I/O TIM3_CH4, TIM14_CH1, TIM1_CH3N ADC_IN9

16 PB2 I/O - -

17 17 17 16 VDD S Digitalpowersupply 18 18 18 PA8 I/O USART1_CK, TIM1_CH1, EVENTOUT, CKO 19 19 19 17 PA9 I/O USART1_TX, TIM1_CH2, I2C1_SCL, CKO I2C.supportFast modePlus 20 20 20 18 PA10 I/O USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA I2C.supportFast modePlus 21 21 PA11 I/O USART1_CTS, TIM1_CH4, EVENTOUT 22 22 PA12 I/O USART1_RTS, TIM1_ETR, EVENTOUT 23 23 21 19 PA13 (SWDIO)(1) I/O IR_OUT, SWDIO - 24 24 22 20 PA14 (SWCLK)(1) I/O USART2_TX, SWCLK - 25 25 23 PA15 I/O SPI1_NSS, EVENTOUT, USART2_RX 26 26 24 PB3 I/O SPI1_SCK, EVENTOUT - 27 27 25 PB4 I/O SPI1_MISO, TIM3_CH1, EVENTOUT 28 28 26 PB5 I/O SPI1_MOSI, I2C1_SMBA, TIM16_BKIN, TIM3_CH2 29 29 27 PB6 I/O I2C1_SCL, USART1_TX, TIM16_CH1N I2C.supportFast modePlus

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 14/51 文件编号：CS-QR-YF-054A02 30 30 28 PB7 I/O I2C1_SDA, USART1_RX, TIM17_CH1N I2C.supportFast modePlus 31 31 1 1 BOOT0 I Bootmemoryselection

32 PB8 I/O I2C1_SCL,

TIM16_CH1 32 0 GND S Ground 1 1 VDD S Digitalpowersupply Note (1) Afterreset,thesepinswillbeconfiguredasSWDIOandSWCLK.Meanwhile,theinternalpull-upoftheSWDIOpinandtheinternalpull- downoftheSWCLKpinwillopen. Pindescriptionpart2 PinNO. Pinname Type 描述 QFN32 TSSOP20 Multiplexedfuncions Specialfunctions 2 3 PF0/HXT_IN (PF0) I/O - HXT_IN 3 4 PF1/HXT_OUT (PF1) I/O - HXT_OUT

4 NRST I/O Resetinput/internalresetoutput,withweakpull-

upresistor（activelow） 5 5 VDDA S Analogpowersupply 6 6 PA0 I/O USART2_CTS ADC_IN0, WKUP1 7 7 PA1 I/O EVENTOUT, USART2_RTS ADC_IN1 8 8 PA2 I/O USART2_TX ADC_IN2 9 9 PA3 I/O USART2_RX ADC_IN3 10 10 PA4 I/O SPI1_NSS, TIM14_CH1, USART2_CK ADC_IN4 11 11 PA5 I/O SPI1_SCK ADC_IN5 12 12 PA6 I/O SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, EVENTOUT ADC_IN6 13 13 PA7 I/O SPI1_MOSI, TIM3_CH2, TIM14_CH1, TIM1_CH1N, TIM17_CH1, EVENTOUT ADC_IN7

14 PB0 I/O

TIM3_CH3, TIM1_CH2N, EVENTOUT ADC_IN8 15 14 PB1 I/O TIM3_CH4, TIM14_CH1, TIM1_CH3N ADC_IN9

15 GND S Ground

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 15/51 文件编号：CS-QR-YF-054A02 17 16 VDD S Digitalpowersupply

18 PA8 I/O

USART1_CK, TIM1_CH1, EVENTOUT, CKO 19 17 PA9 I/O USART1_TX, TIM1_CH2, I2C1_SCL, CKO I2C.supportFast modePlus 20 18 PA10 I/O USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA I2C.supportFast modePlus

21 PA11 I/O

USART1_CTS, TIM1_CH4, EVENTOUT

22 PA12 I/O

USART1_RTS, TIM1_ETR, EVENTOUT 23 19 PA13 (SWDIO)(1) I/O IR_OUT, SWDIO - 24 20 PA14 (SWCLK)(1) I/O USART2_TX, SWCLK -

25 PA15 I/O

SPI1_NSS, EVENTOUT, USART2_RX

26 PB3 I/O SPI1_SCK,

27 PB4 I/O

SPI1_MISO, TIM3_CH1, EVENTOUT

28 PB5 I/O

SPI1_MOSI, I2C1_SMBA, TIM16_BKIN, TIM3_CH2 29 1 PB6 I/O I2C1_SCL, USART1_TX, TIM16_CH1N I2C.supportFast modePlus 30 2 PB7 I/O I2C1_SDA, USART1_RX, TIM17_CH1N I2C.supportFast modePlus

31 BOOT0 I Bootmemoryselection

TIM16_CH1

0 GND S Ground

1 VDD S Digitalpowersupply

(2) Afterreset,thesepinswillbeconfiguredasSWDIOandSWCLK.Meanwhile,theinternalpull-upoftheSWDIOpinandtheinternalpull- downoftheSWCLKpinwillopen.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 16/51 文件编号：CS-QR-YF-054A02

5 I/OMultiplexing

5.1 PORTAmultiplexedfunctions

PA0 USART2_CTS PA1 EVENTOUT USART2_RTS PA2 USART2_RX PA3 USART2_TX PA4 SPI1_NSS USART2_CK TIM14_CH1 PA5 SPI1_SCK, PA6 SPI1_MISO, TIM3_CH1 TIM1_BKIN TIM16_CH1 EVENTOUT PA7 SPI1_MOSI, TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_CH1 EVENTOUT PA8 CKO USART1_CK TIM1_CH1 EVENTOUT PA9 USART1_TX TIM1_CH2 I2C1_SCL CKO PA10 TIM17_BKIN USART1_RX TIM1_CH3 I2C1_SDA PA11 EVENTOUT USART1_CTS TIM1_CH4 PA12 EVENTOUT USART1_RTS TIM1_ETR PA13 SWDIO IR_OUT PA14 SWCLK USART2_TX PA15 SPI1_NSS, USART2_RX TIM2_CH1_ETR EVENTOUT

5.2 PORTBmultiplexedfunctions

PB0 EVENTOUT TIM3_CH3 TIM1_CH2N PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N PB2 PB3 SPI1_SCK, EVENTOUT PB4 SPI1_MISO TIM3_CH1 EVENTOUT PB5 SPI1_MOSI, TIM3_CH2 TIM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TIM16_CH1N PB7 USART1_RX I2C1_SDA TIM17_CH1N PB8 I2C1_SCL TIM16_CH1

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 17/51 文件编号：CS-QR-YF-054A02

6 Memory

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 18/51 文件编号：CS-QR-YF-054A02 Memorymappingtable Memory Startaddress Size Flash,systemmemoryorSRAM, congfiguredbyBOOT 0x00000000 32Kbytes Programflash 0x08000000 32Kbytes Systemmemory 0x1FFFEC00 3Kbytes OptionBytes 0x1FFFF800 64bytes Dataflase 0x1FFFF840 192bytes SRAM 0x20000000 4Kbytes APB Reserved 0x40000000 1Kbytes TIM3 0x40000400 1Kbytes Reserved 0x40000800 2Kbytes TIM6 0x40001000 1Kbytes TIM7 0x40001400 - Reserved 0x40001800 2Kbytes TIM14 0x40002000 1Kbytes Reserved 0x40002400 1Kbytes Reserved 0x40002800 1Kbytes WWDT 0x40002C00 1Kbytes FWDT 0x40003000 1Kbytes Reserved 0x40003400 1Kbytes SPI2 0x40003800 1Kbytes Reserved 0x40003C00 2Kbytes USART2 0x40004400 1Kbytes Reserved 0x40004800 - Reserved 0x40004C00 - Reserved 0x40005000 - I2C1 0x40005400 1Kbytes Reserved 0x40005800 1Kbytes Reserved 0x40005C00 5Kbytes PMU 0x40007000 1Kbytes Reserved 0x40007400 3Kbytes SYSCFG 0x40010000 1Kbytes EXTI 0x40010400 1Kbytes Reserved 0x40010800 3Kbytes Reserved 0x40011400 1Kbytes Reserved 0x40011800 1Kbytes Reserved 0x40011C00 1Kbytes

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 19/51 文件编号：CS-QR-YF-054A02 Reserved 0x40012000 1Kbytes ADC 0x40012400 1Kbytes Reserved 0x40012800 1Kbytes TIM1 0x40012C00 1Kbytes SPI1 0x40013000 1Kbytes Reserved 0x40013400 1Kbytes USART1 0x40013800 1Kbytes Reserved 0x40013C00 1Kbytes Reserved 0x40014000 1Kbytes TIM16 0x40014400 1Kbytes TIM17 0x40014800 1Kbytes Reserved 0x40014C00 3Kbytes DBGMCU 0x40015800 1Kbytes Reserved 0x40015C00 9Kbytes AHB1 Reserved 0x40000000 1Kbytes TIM3 0x40000400 1Kbytes Reserved 0x40000800 2Kbytes TIM6 0x40001000 1Kbytes TIM7 0x40001400 - Reserved 0x40001800 2Kbytes TIM14 0x40002000 1Kbytes Reserved 0x40002400 1Kbytes AHB2 Reserved 0x40002800 1Kbytes WWDT 0x40002C00 1Kbytes FWDT 0x40003000 1Kbytes Reserved 0x40003400 1Kbytes SPI2 0x40003800 1Kbytes Reserved 0x40003C00 2Kbytes Cortex-M0internalperipherals 0xE0000000 1Mbytes

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 20/51 文件编号：CS-QR-YF-054A02

7 Functiondescription

7.1 Core

TheARM®Cortex®-M0isagenerationofARM32-bitRISCprocessors. TheARM®Cortex®-M0supportslowpowerandefficientoperation,highperformanceinterruptresponse.It providesahighercodedensitythanother8-bitand16-bitmicrocontrollers,andcanbeappliedtoawiderrange ofembeddedsystems. Itprovidesexcellentperformance.ItiscompatiblewiththerestoftheCortex-Mprocessors.

7.2 Memories

CS32F035/F036supportsthefollowingfeatures:  Flashhasthreeblocks: — 32KbytesProgramflash. — 192bytesDataflase. — optionbytesandsystemmemory.  4KbytesofembeddedSRAMsupportsembeddedparitycheckingforexceptiongeneration. ProgramflashsupportsWriteprotectionwithsectorsize.Accordingtooptionbyte，Programflash supportsdifferentlevelsofprotection: — Level0:noprotection. — Level1:cannotwriteorreadindebugmodeorbootinSRAM/bootloader. — Level2:canreadandcannotwriteinusermode.DebugmodeorbootinSRAM/bootloaderisdisable.

7.3 Clocks

Theclocksystemconsistsof:  8MHzinternalhighspeedRCoscillator(HRC)  14MHzinternalhighspeedRCoscillator(HRC14)  40KHzinternallowspeedRCoscillator(LRC)  4~32MHzexternalhighspeedcrystaloscillator(HXT)  Internalx2,x3,..,x16Phase-lockedloop(PLL)

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 21/51 文件编号：CS-QR-YF-054A02 Figure7Clocktree

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 22/51 文件编号：CS-QR-YF-054A02

7.4 Operationenvironment

7.4.1 Powersupply

Thedevicehasthreedifferentpowersupplypins: VDD:PowersupplyforI/Olines,internalregulatorandHXT.Thevoltagerangeisfrom2.0Vto5.5V. VDDA:PowersupplyforADC,HRC,HRC14,PLL,POR/PDRandLVD.ThevoltagerangeisfromVDDto 5.5V.WhenADCisused,theminimumvoltageofVDDAis2.4V. VBAT:powersupplyforRTC,LXTandbackupregisters.Thevoltagerangeisfrom1.65Vto5.5V.

7.5 BOOTmode

CS32F035/F036XXXXsupportsthreedifferentstartuplocations: Differentstartuplocations BOOT0pin nBOOT1bit bootlocation

0 X Programflash

7.6 Powermanagement

7.6.1 Lowpowermodes

Thedevicehasfourlowpowermodes:  Sleepmode TheCPUisstoppedwhenthedeviceentersintosleepmode.Inthesleepmode,allperipheralscanoperate continuouslyandaninterrupt/eventcanwakeuptheCPU.  Deepsleep1mode Indeepsleep1mode,PLL,HRCandHXTaredisabled.Theregulatorison,thecontentof1.5Vdomaincan’t belost. AnyoneoftheEXTIlinescanwakeupthedeviceindeepsleep1mode.  Deepsleep2mode Indeepsleep2mode,thePLL,HRCandHXTaredisabled.Theregulatorison,thecontentof1.5Vdomain can’tbelost.Theinternalregulatorisinlowpowermode,sothewakeuptimeofdeepsleep2isbiggerthanthe wakeuptimeofdeepsleep1. AnyoneoftheEXTIlinescanwakeupthedeviceindeepsleep2mode.  Powerdownmode Inpowerdownmode,the1.5VregulatorisswitchedoffsothatthecontentsofSRAMandregistersarelost exceptforbackupregistersinVBATdomain.ThePLL,HRC,HRC14andHXTareswitchedoff. Anexternalreset,aFWDTreset,arisingedgeontheWKUPpinscanwakeupthedeviceinpowerdownmode.

7.6.2 POR/PDR

Thedevicehaspower-onresetandpower-downresetcircuits.ThePORcircuitmonitorsVDDsupplyvoltage. ThePDRcircuitmonitorsbothVDDandVDDAsupplyvoltage.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 23/51 文件编号：CS-QR-YF-054A02 Thesecircuitsarealwaysactivetomonitorifoperationvoltageisbiggerthan2V.Oncethecircuitsmonitorthe powersupplyvoltageislowerthan2V,thedevicewillkeepinresetstate.

7.6.3 LVD

Thedevicehasalowvoltagedetector(LVD),whichcanmonitortheVDDsupplyvoltageandcompareittothe thresholdvoltageofLVD.OnceVDDislowerthanthethresholdvoltageorhigherthanthethresholdvoltage, aninterruptwillbegenerated.Andthethresholdvoltagecanbeprogrammed.

7.7 I/Os

AllGPIOpinscanbeconfiguredasinput(withpull-uporpull-down),outputorallocatedtoperipherals.The outputfunctioncanbeconfiguredtobepush-pulloropen-drain. TheI/Oconfigurationcanbelockedtopreventfromaccidentaloperation.

7.8 ADC

TheCS32F035/F036XXXXcontainsa12-bitsuccessiveapproximationanalog-to-digitalconverter.TheADC canperformADconversionsonupto13channels,including10externalchannelsand3internalchannels.The threeinternalchannelsareusedformonitoringtheVBATvoltage,measuringtheinternalreferencevoltageand measuringthetemperatureofthechip.Withtheselectedconversiongroupandworkmode,conversionswere performedinasinglemode,continuousmode,ordiscontinuousmode.Vaiousconversionconfigurationsare supported,including samplingtime,dataresolution,dataformatalignmentandscansequencedirection. Theconversioncanbetriggeredbysoftwareorharewareeventsgeneratedbydifferenttimers.Adedicated HRC14clockisavailableforADC,aswellasdividedPCLK,whichcontainsnoclockuncertaintyinhardware triggerevent. AnanalogwatchdogisbuiltinsideADC,whichcanbeactivatedtomonitorthevoltageofasinglechannelora conversiongroup.Oncethevoltageisoutofthegivenwindow,aWDGEVTalarmisgenerated. TheoutputdatacanbemanagedbyDMA.DMAone-shotmodeisprovidedtoendADconversionwhena certainamountofdataistransfered,whileDMAcircleallowsoutputdatatobecontinuoustransferreduntilAD conversionisstoppedmanually.

7.8.1 Temperaturesensor

Temperaturesensor(TS)blockgeneratesavoltageTS_OUTwhichislinearwithtemperature.TS_OUTis snettoADCchannelADIN_16. ADCwillconvertthevoltageintoadigitalvalue.Inordertoprovidesgood linearity,TSshouldbecalibratedfirst.Thecalibrationdataarestoredinthesystemmemoryarea,whichisread only. TScalibrationvalues Calibrationvaluename Description Address TEMP30_CAL TSADCdataat300C(+/-50C), VDDA=3.3V(+/-10mV) 0x1FFFF7B8-0x1FFFF7B9 TEMP110_CAL TSADCdataat1100C(+/-50C), VDDA=3.3V(+/-10mV) 0x1FFFF7C2-0x1FFFF7C3

7.8.2 Internalrefenencevoltage

TheinternalreferencevoltageVrefintprovidesabandgapvoltageforADC.ItissenttochannelADIN_17. Vrefintismeasuredduringproductiontestandstoredinthesystemmemoryarea,whichisreadonly.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 24/51 文件编号：CS-QR-YF-054A02 Vrefintcalibrationvalues Calibrationvalue name Description Address VREFINT_CAL Vrefint ADCdataat300C(+/-50C), VDDA=3.3V(+/-10mV) 0x1FFFF7BA-0x1FFF F7BB

7.8.3 VBATmonitor

VBATvoltageismeasuredbyADCtomonitorifitisintheproperrange.ItissenttochannelADIN_18. ToavoidthecasethatVBATishigherthanVDDA,theVBATvoltageisdividedby2beforesenttoADC.

7.9 Timers

Thedevicesincludeoneadvancedcontroltimer,sixgeneral-purposetimersandonebasictimer. TIMxfeaturecomparison Type Timer Counter witdh Direction Pre-divider DMA requrest Channels Complementary channels Advanced Control TIM1 16-bit Up,down, upanddown From1to65536 Yes 4 3 TIM3 16-bit Up,down, upanddown From1to65536 Yes 4 0 TIM14 16-bit Up From1to65536 No 1 0 TIM16 16-bit Up From1to65536 Yes 1 1 TIM17 16-bit Up From1to65536 Yes 1 1

7.9.1 Advanced-controltimer(TIM1)

Theadvancedtimer(TIM1)isa16-bitcountertimerwitha16-bitpre-divider,whichcancountup,downorup anddown.Ithasfour-channelswhichsupportsinputcaptureandoutputcompare.TheycangeneratePWM signalstocontrolmotororbeusedforpowermanagementapplications.Itscomplementaryoutputchannelshas commonprogrammableinserteddeadtime. TIM1canbeinternalconnectedwithothertimersforsynchronizationoreventtrigger.TheregistersofTIM1 canbeaccessedbyDMAwhenDMArequestisenabled. Thecountercanbestoppedindebugmode.

7.9.2 General-purposetimer(TIM3,14,16,17)

Therearefourgeneral-purposetimers,whichcanbeusedassimpletimebaseoroutputPWM.  TIM3 TIM3isa16-bitcountertimerwitha16-bitpre-divider,whichcancountup,downorupanddown.Theyhave fourchannelsforindependentinputcapture,outputcompareandPWM. TIM3canworktogetherorwithotherTIMsthroughinternalconnectionforsynchronizationoreventtrigger. TheregistersofTIM3canbeaccessedwhenDMArequestisenabled. Thecountercanbestoppedindebugmode.  TIM14 TIM14isa16-bitupcountertimerwitha16-bitpre-divider,whichonlyhasonechannelforinputcapture, outputcompareandPWM.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 25/51 文件编号：CS-QR-YF-054A02 Thecountercanbestoppedindebugmode.  TIM16/TIM17 TIM16(onechannel)andTIM17(onechannel)arebasedona16-bitupcounteranda16-bitpre-divider.Their channelscanbeusedforinputcapture,outputcompareandPWM.Aprogrammabledeadtimegeneratorcanbe usedfortheircomplementaryoutputchannels. TheirregisterscanbeaccessedbyDMAwhenDMArequestisenabled.counterscanbestoppedindebug mode.

7.9.3 Freewatchdogtimer(FWDT)

Thefreewatchdogtimerisclockedbytheinternal40KHzLRC,whichisindependentofthemainclock.The maincomponentsofFWDTarean8-bitpre-divideranda12-bitdowncounterwithwindowoption,whichcan workindeepsleepandpowerdownmode.TheFWDTcangeneratearesetwhenthedowncounterreacheszero. Thecountercanbestoppedindebugmode.

7.9.4 Windowwatchdogtimer(WWDT)

Themaincomponentsofwindowwatchdogtimerareapre-dividerwithfouroptionsanda7-bitfreerunning downcounter.ItisclockedbyPCLK.Itcangenerateareminderinterruptflagwhenthedowncounterreaches 0x40andaresetwhenthedowncounterreaches0x3F. Thecountercanbestoppedindebugmode.

7.9.5 SysTick

TheSysTickcanbeusednotonlyforreal-timeoperatingsystems,butalsoasastandarddowncounter. Itisbasedona24-bitdowncounterwithautoreloadfunction,whichcanbeclockedbyHCLKorHCLK/8. Whenthecounterreacheszero,SysTickcangenerateamaskablesysteminterrupt.

7.10 DMA

Thedirectmemoryaccess(DMA)controllerprovidesahardwaremethodoftransferringdatabetween peripheralsandmemory. Thereare5channelsintheDMAcontroller.Eachchannelisconnectedtodedicatedperipheral(include SPIx,I2Sx,I2Cx,USARTxandTIMx)tomanagememoryaccessrequests.Anarbiterisimplementedinsideto handleDMArequests priority. TheDMAcontrolleralsosupportscircularbuffermodedatatransfer.Itcanremoveusercodeinterventionwhen thecontrollerreachestheendofthebuffer.

7.11 Inerruptandevents

Cortex-M0integratestheNestedVectoredInterruptController(NVIC)forefficientexceptionandinterrupts processing.YoucanreadtheTechnicalReferenceManualofCortex-M0formoredetails. TheExtendedinterrupt/eventcontroller(EXTI)containsupto24independentedgedetectorsandgenerates interruptrequestsoreventstotheCPU/InterruptController.TheEXTIhasthreetriggertypes:risingedge, fallingedgeandbothedges.Eachedgedetectorcanbeconfiguredandenabledindependently.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 26/51 文件编号：CS-QR-YF-054A02

7.12 SPI

TheSPImodulecancommunicatewithexternaldevicesusingtheSPIprotocolortheI2Saudioprotocol. TheSPIprovide aSPIprotocolofdatatransmissionandreceptionfunctioninmasterandslavemode.It supportsfull-duplexandsimplexmode,whichcommunicationspeedcanupto18Mbit/s.AhardwareCRC functionisalsoimplemented. DMAcanbeusedforsequentialtransmissionbothinSPImodeandI2Smode. SPIxfunctiontable SPIfeatures/modes SPI1 Rx/TxFIFO √ NSSpulsemode √ TImode √ HardwareCRCfunction √

7.13 USART

TheUniversalSynchronousAsynchronousreceivertransmitter(USART)providesauniversalinterfacefor serialcommunicationbetweentheMCUandexternaldevices.TheUSARTsupportssynchronous asynchronousfull-duplexcommunicationandsingle-wirehalf-duplexcommunication.Itusesaprogrammable baudrategeneratortoprovidedifferentcommunicationbaudrate,upto6Mbit/s. Inaddition,USARTalsosupportsDMAcontinuousdatatransmission,automaticbaudratedetection, multiprocessorcommunication,Modbuscommunication,smartcardmode,LINmode,IrDAmode,RS232 hardwareflowcontrolandRS485driveenable.USART1canwakeupMCUfromdeepsleep1ordeepsleep2 mode. USARTxfunctiontable USARTfeatures/modes USART1 USART2 Asynchronousfullduplexcommunication √ √ Synchronousmode √ √ Single-wirehalf-duplexcommunication √ √ DMA √ √ Autobaudratedetection √ X Multiprocessorcommunication √ √ Modbuscommunication √ X Smartcardmode √ X LINmode √ X IrDAmode √ X RS232hardwareflowcontrol √ √ RS485DriverEnable √ √ WakeupMCUfromdeepsleep1/2mode √ X

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 27/51 文件编号：CS-QR-YF-054A02

7.14 I2C

TheI2C(inter-integratedcircuit)moduleprovidesanindustrystandardI2Cinterface.Itcanworkinmaster modeandslavemode. TheI2CinterfaceimplementsstandardI2Cprotocolwithstandard-mode,fast-modeand fast-modeplusaswellasCRCcalculationandchecking,SMBus(systemmanagementbus)andPMBus(power managementbus).TheI2CinterfacesupportDMAmodeforhighspeeddatatransferbetweenmemoryand peripheralwithoutCPUinvolved. Itsmainfeaturesarethefollowing: ― SupportMastermodeandslavemode ― Multi-mastercapability ― Programmeddigitalfilterandoptionalanalogfilter ― Support7-bitaddressingmode10-bitaddressmode ― Supportstandard-mode(upto100KHz),fast-mode(upto400kHz) ― Wakeupfromdeepsleep1anddeepsleep2mode ― SupportDMAmode I2Cxfunctiontable I2Cfeatures/modes I2C1 7-bitaddressingmode √ 10-bitaddressingmode √ Standardmode(upto100Kbit/s) √ Fastmode(upto400Kbit/s) √ Independentclock √ Wakeupfromdeepsleep1/2 √

7.15 CRCunit

Inthefieldofdatastorageanddatacommunication,inordertoensurethecorretnessofdata,thecyclic redundancycheck(CRC)isusedcommonly. ThisCRCcalculationunitcanbeusedtocalculate32bitCRCcodewithfixedpolynomial.

7.16 Serialwiredebug(SWD)

AstheARMCortex-M0Coreisintergrated,thedebugfunctionalityisprovidedbyARMdebugcomponents withinM0core.TheARMserialwiredebugportisimplementedtoaccessthesedebugcomponent.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 28/51 文件编号：CS-QR-YF-054A02

8 Electricalcharacteristics

8.1 Disclaimer

Figure8isthepowersupplyschemeofCS32F035/F036. Unlessotherspecified,alltypicalvaluesarebasedonTrange=25℃ andVDD=3.3V. Unlessotherspecified,allvoltagesarereferencedtoGND. Unlessotherspecified,thevaluesarebasedondesignguidelines. Figure8Powersupplyscheme Theinputvoltageandloadingconditionsfor pinparametersareshowninFigure9. Figure9Pininputvoltageandloadingconditions

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 29/51 文件编号：CS-QR-YF-054A02

8.2 Absolutemaximumratings

Symbol Description Min Typ. Max. Units VDD ThevoltagebetweenVDDandGND -0.3 - 6 V VDDA ThevoltagebetweenVDDAandGND -0.3 - 6 V VBAT ThevoltagebetweenVBATandGND -0.3 - 6 V VDD-VDDA ThevoltagebetweenVDDandVDDA - - 0.4 V Vi/o ThevoltageontheI/Opins GND- 0.3 - 6 V Tstorage Storagetemperature -65 - 150 ℃ Tjunction Junctiontemperature - - 150 ℃ Itotal-pwr Totalcurrentinto alloftheVDDpowerlines - - 120 mA Itotal-GND Totalcurrentoutof alloftheGNDpowerlines -120 - - mA Ipwr-pin Currentintoeachpowerpin - - 100 mA IGND-pin CurrentoutofeachGNDpin -100 - mA Itotal-sunk TotalcurrentintoallofI/Opin - - 80 mA Itotal-source TotalcurrentoutofallofI/Opin -80 - mA Isunk-pin CurrentintoanyI/Opin - - 25 mA Isource-pin CurrentoutofanyI/Opin -25 - - mA

8.3 Operationenvironmentcharacteristics

Operationenvironmentcharateristics Symbol Description Min Typ. Max. Units VVDD-range TheoperatingvoltagerangeofpowersupplyVDD 2 - 5.5 V VVDDA-range TheoperatingvoltagerangeofpowersupplyVDDA 2 - 5.5 V Trange Theoperatingambienttemperaturerange(case1) -40 - 85 ℃ Theoperatingambienttemperaturerange(case2) -40 - 105 ℃ Tjunction-range Thejunctiontemperaturerange(case1) -40 - 105 ℃ Thejunctiontemperaturerange(case2) -40 - 125 ℃ fAHB-clock TheinternalAHBclockfrequencyrange 0 - 48 MHz fAPB-clock TheinternalAPBclockfrequencyrange 0 - 48 MHz VIO-range TheI/Osinputvoltagerange -0.3 - 5.5 V QFN32powerdissipationatTrange=85℃ orTrange=105℃ - - 484 mW QFN28powerdissipationatTrange=85℃ orTrange=105℃ - - - mW Tsupply-rise VDD/VDDAsupplyriserate 0 - - uS/V Tsupply-fall VDD/VDDAsupplyfallrate 20 - - uS/V TVDD-POR SupplyVDDpoweronresetthreshold 1.84 1.92 2 V TVDD-fall SupplyVDDpowerdownresetthreshold 1.80 1.88 1.96 V TVDDA-fall SupplyVDDApowerdownresetthreshold 1.80 1.88 1.96 V Treset-tempo Resettemporization,VVDD-range≤5.5V - 4.2 10 mS Resettemporization,VVDD-range≤3.6V - 4.2 7.5 mS VLVD Thestage-0risingthresholdvoltageof LVD 2.11 2.18 2.25 V Thestage-0fallingthresholdvoltageof LVD 2.01 2.08 2.15 V Thestage-1risingthresholdvoltageof LVD 2.20 2.28 2.36 V Thestage-1fallingthresholdvoltageof LVD 2.10 2.18 2.26 V Thestage-2risingthresholdvoltageof LVD 2.29 2.38 2.47 V Thestage-2fallingthresholdvoltageof LVD 2.19 2.28 2.37 V Thestage-3risingthresholdvoltageof LVD 2.39 2.48 2.57 V Thestage-3fallingthresholdvoltageof LVD 2.29 2.38 2.47 V Thestage-4risingthresholdvoltageof LVD 2.48 2.58 2.68 V Thestage-4fallingthresholdvoltageof LVD 2.38 2.48 2.58 V

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 30/51 文件编号：CS-QR-YF-054A02 Thestage-5risingthresholdvoltageof LVD 2.58 2.68 2.78 V Thestage-5fallingthresholdvoltageof LVD 2.48 2.58 2.68 V Thestage-6risingthresholdvoltageof LVD 2.67 2.78 2.89 V Thestage-6fallingthresholdvoltageof LVD 2.57 2.68 2.79 V Thestage-7risingthresholdvoltageof LVD 2.77 2.88 2.99 V Thestage-7fallingthresholdvoltageof LVD 2.67 2.78 2.89 V

8.4 I/OPincharacteristics

Symbol Description Min Typ. Max. Units VIH Inputhighlevelvoltage 0.7*VDD - - V VIL Inputlowlevelvoltage - - 0.3*VDD V VIL-BOOT0 InputlowlevelvoltageofBOOT0 - - 0.3*VDD -0.3 V VOH Outputhighlevelvoltage,|Isource-pin|=20mA,VDD≥2.7V VDD-1.5 - - V Outputhighlevelvoltage,|Isource-pin|=6mA VDD-0.4, VDD-0.45(3) - - V VOL Outputlowlevelvoltage,|Isunk-pin|=20mA,VDD≥2.7V - - 1.1 V Outputlowlevelvoltage,|Isunk-pin|=6mA - - 0.36 V VOL-FMP FastmodeplusforI2C,outputlowlevelvoltage, |Isunk-pin|=20mA,VDD≥2.7V - - 0.4 V FastmodeplusforI2C,outputlowlevelvoltage, |Isunk-pin|=10mA - - 0.3 V Rpull-up I/Opull-upresistance 17 40 140 Ω Rpull-down I/Opull-downresistance 15 40 154 Ω Ileakage(1) Inputleakageindigitalmode,GND<VIO-range <VDD - - ±0.5 uA Inputleakageindigitalmodel,VDD<VIO-range <VDDA - - ±0.5 uA Inputleakageinanalogmode,GND<VIO-range <VDDA - - ±0.5 uA Inputleakageinanalogmode,VDD<VIO-range <5V - - 5 uA Ileakage(2) Inputleakageindigitalmode,GND<VIO-range <VDD - - ±0.8 uA Inputleakageindigitalmodel,VDD<VIO-range <VDDA - - ±0.8 uA Inputleakageinanalogmode,GND<VIO-range <VDDA - - ±0.8 uA fIO GPIOx_OSj[1:0]=x0,IOoutputfrequency,CL=50pf - - 2 MHz GPIOx_OSj[1:0]=01,IOoutputfrequency,CL=50pf - - 10 MHz GPIOx_OSj[1:0]=11,IOoutputfrequency,CL=30pf, VDD≥2.7V - - 50 MHz GPIOx_OSj[1:0]=11,IOoutputfrequency,CL=50pf, VDD≥2.7V - - 30 MHz GPIOx_OSj[1:0]=11,IOoutputfrequency,CL=50pf, VDD＜2.7V - - 20 MHz FastmodeplusforI2C,outputfrequency,CL=50pf - - 2 MHz Tio-fall GPIOx_OSj[1:0]=x0,IOoutputfalltime,CL=50pf - - 12 nS GPIOx_OSj[1:0]=01,IOoutputfalltime,CL=50pf - - 11 nS GPIOx_OSj[1:0]=11,IOoutputfalltime,CL=30pf, VDD≥2.7V - - 6 nS GPIOx_OSj[1:0]=11,IOoutputfalltime,CL=50pf, VDD≥2.7V - - 8 nS GPIOx_OSj[1:0]=11,IOoutputfalltime,CL=50pf, VDD＜2.7V - - 11 nS FastmodeplusforI2C,outputfalltime,CL=50pf - - 11 nS Tio-rise IOoutputrisetime,CL=50pf - - 15 nS GPIOx_OSj[1:0]=11,IOoutputrisetime,CL=30pf, - - 7 nS

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 31/51 文件编号：CS-QR-YF-054A02 VDD≥2.7V GPIOx_OSj[1:0]=11,IOoutputrisetime,CL=50pf, VDD≥2.7V - - 10 nS GPIOx_OSj[1:0]=11,IOoutputrisetime,CL=50pf, VDD＜2.7V - - 14 nS Text-pw Theexternal-signalpulsewidthdetectedbyEXTI 10 - - nS Tnrst-fp Theexternal-signalpulsewidthfilteredbyNRST - - 60 nS Tnrst-nfp Theexternal-signalpulsewidthno-filteredbyNRST, 2.7V≤VVDD-range≤3.6V 300 - - nS Theexternal-signalpulsewidthno-filteredbyNRST, 2V≤VVDD-range≤3.6V 500 - - nS Theexternal-signalpulsewidthno-filteredbyNRST, 2V≤VVDD-range≤5.5V 390 - - nS (1) 2V≤VVDD-range≤3.6V,2V≤VVDDA-range≤3.6V (2) 2V≤VVDD-range≤5.5V,2V≤VVDDA-range≤5.5V (3) AppliedtoPF0

8.5 Lowpowermodewake-uptime

Symbol Description Min Typ. Max. Units Twk-sleep Thesleepmodewake-uptime - 5systemclk - uS Twk-deepsleep1 Thedeepsleep1modewake-uptime - 3 5.3 uS Twk-deepsleep2 Thedeepsleep2modewake-uptime - 4 7.2 uS Twk-powerdown Thepowerdownmodewake-uptime - 57 157 uS

8.6 RCoscillatorcharacteristics

Symbol Description Min Typ. Max. Units fHRC ThefrequencyofHRC - 8 - MHz TRIMHRC HRCusertrimmingstep - - 1 % DutyHRC ThedutycycleofHRC 48 - 52 % fvoltage-HRC VoltagecharacteristicsofHRCfrequency -0.5 - 0.5 % ftemp-HRC temperaturecharacteristicsofHRCfrequency -2 - 2 % faccuracy-HRC AccuracyofHRCfrequency -1 - 1 % Tsetup_HRC ThesetuptimeofHRC 0.14 - 1.2 uS Ipd-HRC ThepowerdissipationofHRC 44 66 102 uA HRC14characteristics Symbol Description Min Typ. Max. Units fHRC14 ThefrequencyofHRC14 - 14 - MHz TRIMHRC14 HRC14usertrimmingstep - - 1 % DutyHRC14 ThedutycycleofHRC14 47 - 53 % fvoltage-HRC14 VoltagecharacteristicsofHRC14frequency -0.5 - 0.5 % ftemp-HRC14 temperaturecharacteristicsofHRC14frequency -2 - 2 % faccuracy-HRC14 AccuracyofHRC14frequency -1 - 1 % Tsetup_HRC14 ThesetuptimeofHRC14 0.09 - 0.5 uS Ipd-HRC14 ThepowerdissipationofHRC14 64 96 152 uA

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 32/51 文件编号：CS-QR-YF-054A02 LRCcharacteristics Symbol Description Min Typ. Max. Units fLRC ThefrequencyofLRC 30 40 50 KHz Tsetup_LRC ThesetuptimeofLRC - - 84 uS Ipd-LRC ThepowerdissipationofLRC - 0.71 1.27(1), 2.47(2) uA (1) VDDA=3.3V,-40℃ ≤Trange ≤105℃ (2) VDDA=5.5V,-40℃ ≤Trange ≤105℃

8.7 Crystaloscillatorcharacteristics

Figure10showsthecrystalandtheloadingandparasiticcapacitancesofcrystaloscillator.BothCL1 andCL2 arethecapacitancedevicesonthePCBboard.BothCL1P andCL2P areparasiticcapacitanceonPCBboardand package. Figure10Theloadingandparasiticcapacitancesofcrystaloscillator CL(CLLXTorCLHXT)isthecrystalloadcapacitance.Thespecifiedcrystalhasstandardloadcapacitance. C’L1 =CL1 +CL1P C’L2 =CL2 +CL2P CL=C’L1 *C’L2 /(C’L1 +C’L2) HXTcharacteristics Symbol Description Min Typ. Max. Units fHXT-IN Cystaloscillatorfrequency 4 8 32 MHz Ipd-HXT Duringstartuptime - 1.8 6.5 mA VDD=3.3V,Rm=30Ω,CL=10pF@8MHz 0.12 0.22 0.45 mA VDD=3.3V,Rm=45Ω,CL=10pF@8MHz 0.13 0.24 0.46 mA VDD=3.3V,Rm=30Ω,CL=5pF@32MHz 0.21 0.34 0.6 mA VDD=3.3V,Rm=30Ω,CL=10pF@32MHz 0.33 0.46 0.7 mA VDD=3.3V,Rm=30Ω,CL=20pF@32MHz 0.58 0.72 0.87 mA gmHXT TheoscillatortransconductanceofHXT,HXTDRV[1:0]=00, lowdrive 0.7 - 16.4 mA/V TheoscillatortransconductanceofHXT,HXTDRV[1:0]=01, mediumlowdrive 5.0 - 27.3 mA/V TheoscillatortransconductanceofHXT,HXTDRV[1:0]=10, mediumhighdrive 6.2 - 32.6 mA/V TheoscillatortransconductanceofHXT,HXTDRV[1:0]=11, highdrive 13.1 - 43.4 mA/V CLHXT TheCrystalloadcapacitanceofHXT 5 10 20 pF Tsetup HXTsetuptime - 1 - mS

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 33/51 文件编号：CS-QR-YF-054A02

8.8 Externalclockcharacteristics

HXTexternalclockcharacteristics Symbol Description Min Typ. Max. Units FHXT-IN Externalclocksourcefrequency - 8 32 MHz VHXT-L InputpinlowlevelvoltageofHXTexternalsourceclock GND - 0.3*VDD V VHXT-H InputpinhighlevelvoltageofHXTexternalsourceclock 0.7*VDD - VDD V Twidth-HXT InputpinhighorlowtimeofHXTexternalsourceclock 15 - - nS Trise-HXT InputpinrisetimeofHXTexternalsourceclock - - 20 nS Tfall-HXT InputpinfalltimeofHXTexternalsourceclock - - 20 nS

8.9 PLLcharacteristics

Symbol Description Min Typ. Max. Units fPLL-IN FrequencyofPLLinputclock 1 8 24 MHz DutyPLL-IN DutycycleofPLLinputclock 40 - 60 % fPLL-OUT FrequencyofPLLoutputclock 16 - 48 MHz Tlock ThelocktimeofPLL - - 200 uS jitterPLL Cycletocyclejitter - - 300 pS

8.10 Powerconsumption

Powerconsumptioncharacteristicsofrunandsleepmode RunmodeCode execute conditions fHCLK (MHz) IVDD (peripheralson) (mA) IVDD (peripheralsoff) (mA) IVDDA (uA) Typ(1)Max(2)Max(3)Typ(1)Max(2)Max(3)Typ(1)Max(2)Max(3) run flash HXTbypass， PLLon 48 15.6 20.5 9.13 11.2 316 430 run flash HXTbypass， PLLon 32 10.41 12.6 6.82 8.4 240 run flash HXTbypass， PLLon 24 8.47 10 5.69 6.9 207 301 run flash HXTbypass， PLLoff 8 4 7.6 3.1 4 2.86 run flash HXTbypass， PLLoff 1 2.1 3 2 2.9 2.86 run flash HRC， PLLon 48 14.6 9.11 376 run flash HRC， PLLon 32 10.44 6.86 302 run flash HRC， PLLon 24 8.5 5.67 269 run flash HRC， PLLoff 8 4.06 3.08 61.5 104 run SRAM HXTbypass， PLLon 48 run SRAM HXTbypass， PLLon 32 run SRAM HXTbypass， PLLon 24 run SRAM HXTbypass， PLLoff 8 run SRAM HXTbypass， PLLoff 1

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 34/51 文件编号：CS-QR-YF-054A02 run SRAM HRC， PLLon 48 run SRAM HRC， PLLon 32 run SRAM HRC， PLLon 24 run SRAM HRC， PLLoff 8 sleep - HXTbypass， PLLon 48 9.43 3.45 316 sleep - HXTbypass， PLLon 32 7 2.92 240 sleep - HXTbypass， PLLon 24 5.74 2.67 207 sleep - HXTbypass， PLLoff 8 3.07 2.11 2.86 sleep - HXTbypass， PLLoff 1 2.02 1.91 2.86 sleep - HRC， PLLon 48 9.48 3.42 376 sleep - HRC， PLLon 32 7.05 2.89 302 sleep - HRC， PLLon 24 5.78 2.64 269 sleep - HRC， PLLoff 8 3.12 2.09 61.5 Powerconsumptioncharacteristicsofdeepsleepandpowerdownmode Runmode Code execute conditions fHCLK (MHz) IVDD (peripheralson) (uA) IVDD (peripheralsoff) (uA) IVDDA (uA) Typ(1)Max(2)Max(3)Typ(1)Max(2)Max(3)Typ(1)Max(2)Max(3) deepsleep1 - VDDAmonitoron - 21.3 42 - 2.73 15.8 deepsleep1 - VDDAmonitoroff - 21.3 42 - 1.24 deepsleep2 - VDDAmonitoron - 5.6 21 - 2.71 15.8 deepsleep2 - VDDAmonitoroff - 5.6 21 - 1.21 powerdown - LRCon,FWDTon VDDAmonitoron - 1.2 - - 3.6 powerdown - LRCoff,FWDToff VDDAmonitoron - 1.0 - - 2.3 powerdown - LRCon,FWDTon VDDAmonitoroff - 1.2 - - 2.5 powerdown - LRCoff,FWDToff VDDAmonitoroff - 1.0 - - 1.2 (1) VDD=VDDA=VBAT=3.3V,Trange=25℃ (2) VDD=VDDA=VBAT=3.6V,Trange=105℃ (3) VDD=VDDA=VBAT=5.5V,Trange=105℃

8.11 Internalreferencevoltage

Internalreferencevoltagecharacteristics Symbol Description Min Typ. Max. Units Vrefint Internalreferencevoltage 1.19 1.22 1.25 V deltVrefint Internalreferencevoltagevariationoverthetemperature range - - 11 mV Tc Temperaturecoefficient -60 - 60 ppm/0C

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 35/51 文件编号：CS-QR-YF-054A02

8.12 ADCcharacteristics

Symbol Description Min Typ. Max. Units VDDA VDDApowersupplyrangeforADC 2.4 - 5.5 V IVDDA-ADC VDDApowerconsumptionoftheADC,Autoff=0, VDDA=3.3V - 0.9 - mA fADC ADCclockfrequency 0.6 - 14 MHz Tsample SamplingtimeofADC 1.5 - 236.5 1/fADC Tconvert-time ConverttimeofADC 14 - 252 1/fADC Tswtich-on Switch-ontimeofADC - - 1 uS Tcalibration CalibrationtimeofADC - 83 - 1/fADC Vrange-input TheinputvoltagerangeofADC 0 - VDDA V Cinput-ADC TheinputcapacitorofADC - - 8 pF Rext-input Externalinputimpedance - - 50 kΩ B-3dB Inputsignal-3dBbandwidth 50 kHz Isoinput Inputsignalisolation - - -100 dB Resolution TheADCprogrammableresolution 6 - 12 Bit ERRabsolute ADCabsoluteerror - ±3.3 ±4 LSB INL ADCINL,fADC=14MHz,Rext-input<10kΩ,VDDA≥2.7V - ±1.2 ±2.3 LSB ADCINL,fADC=14MHz,Rext-input<10kΩ,VDDA=2.4V - ±1.5 ±3.5 LSB DNL ADCDNL,fADC=14MHz,Rext-input<10kΩ,VDDA≥2.7V - ±0.7 ±1.3 LSB ADCDNL,fADC=14MHz,Rext-input<10kΩ,VDDA=2.4V - ±2.8 ±3 LSB Offset ADCoffset,fADC=14MHz,Rext-input<10kΩ,VDDA≥2.7V - ±1.9 ±2.8 LSB ADCoffset,fADC=14MHz,Rext-input<10kΩ,VDDA=2.4V - ±2 ±3.5 LSB ERRGain ADCgainerror,fADC=14MHz,Rext-input<10kΩ, VDDA≥2.7V - ±2.8 ±3 LSB ADCgainerror,fADC=14MHz,Rext-input<10kΩ, VDDA=2.4V - ±2.8 ±3 LSB Rext-input maxforfADC=14MHz Tsample(1/fADC) Tsample(uS) Max.Rext-input(kΩ) 1.5 0.11 0.15 2.5 0.18 0.4 8.5 0.61 5.9 14.5 1.04 11.4 29.5 2.11 25.2 42.5 3.04 37.2 56.5 4.04 50 71.5 5.11 - 239.5 17.1 -

8.13 Temperaturesensorcharacteristics

Temperaturesensorcharacteristics Symbol Description Min Typ. Max. Units Ltemp Linearityoftemperaturesensor - ±1 ±2 ℃ Stemp Averageslopeoftemperaturesensorvoltage 4.35 4.47 4.60 mV/℃ Vtemp30 Temperaturesensorvoltageof30±5℃ 1.37 1.43 1.50 V Tstart-temp ThestartuptimeofTemperaturesensorblock - - 6 uS Tsample-temp TheADCsamplingtimeoftemperaturesensor 4 - - uS

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 36/51 文件编号：CS-QR-YF-054A02

8.14 Flashcharacteristics

Symbol Description Min Typ. Max. Units Tprog 16-bitprogramtime 33.6 35 36.4 uS 32-bitprogramtime 67.2 70 72.8 uS Terase Page(1kbytes)erasetime 17.6 18.3 19.1 mS Tmass-erase Masserasetime 29.1 30.3 31.6 mS Cycendurance Sectorendurance 20,000 - - Cycles Tretention Dataretention,Trange=25℃ 100 - - Year Dataretention,Trange=85℃ 20 - - Year Dataretention,Trange=105℃ 10 - - Year

8.15 Timerscharacteristics

Symbol Description Min Typ. Max. Units Tresolution Timerresolutiontime - TTIMxCLK - nS fext-clk TimerexternalclockfrequencyonCHx - TTIMxCLK/2 - MHz Tmax-count Maximumperiodof16-bittimer - 216*TTIMxCLK - nS Maximumperiodof32-bittimer - 232*TTIMxCLK - nS FWDTcharacteristics Pre-divider PDIV[2:0] MintimeoutUVAL[11:0]=0x000 MaxtimeoutUVAL[11:0]=0x000 Units /4 0 4*T40K 16384*T40K mS /8 1 8*T40K 32768*T40K mS /16 2 16*T40K 65536*T40K mS /32 3 32*T40K 131072*T40K mS /64 4 64*T40K 262144*T40K mS /128 5 128*T40K 524288*T40K mS /256 6or7 256*T40K 1048576*T40K mS WWDTcharacteristics Pre-divider PDIV[1:0] Mintimeoutvalue Maxtimeoutvalue Units /1 0 4096*TPLCK 262144*TPLCK mS /2 1 8192*TPLCK 524288*TPLCK mS /4 2 16384*TPLCK 1048576*TPLCK mS /8 3 32768*TPLCK 2097152*TPLCK mS

8.16 SPIcharacteristics

Symbol Description Min Typ. Max. Units fSCK SPIclockfrequencyinmastermode (VDD ≥3V,Trange≤85℃) - - 18 MHz SPIclockfrequencyinslavemode (VDD ≥3V,Trange≤85℃) - - 18 MHz SPIclockfrequencyinmastermode (VDD≥3V,85℃<Trange≤105℃) - - 15 MHz SPIclockfrequencyinslavemode - - 15 MHz

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 37/51 文件编号：CS-QR-YF-054A02 (VDD≥ 3V,85℃<Trange≤105℃) SPIclockfrequencyinmastermode (VDD≥2V,Trange≤105℃) - - 13 MHz SPIclockfrequencyinslavemode (VDD≥ 2V,Trange≤105℃) - - 13 MHz Trise-SCK TherisetimeofSPIclockwith15pfcapacitiveload - - 6 nS Tfall-SCK ThefalltimeofSPIclockwith15pfcapacitiveload - - 6 nS Tsetup-NSS NSSsetuptimeinslavemode 50 - - nS Thold-NSS NSSholdtimeinslavemode 2*Tpclk+10 - - nS Twidth-SCK HighorlowtimeofSPIclock,fPCLK=36MHz, PCLKPDIV=4 2*Tpclk-3 - 2*Tpclk+1 nS Tsetup-din Datainputsetuptimeinmastermode 4 - - nS Datainputsetuptimeinslavemode 5 - - nS Thold-din Datainputholdtimeinmastermode 4 - - nS Datainputholdtimeinslavemode 5 - - nS Taccess-dout Dataoutputaccesstimeinslavemode,fPCLK=20MHz 0 - 32 nS Tdisable-dout Dataoutputdisabletimeinslavemode 0 - 32 nS Tvalid-dout Dataoutputvalidtimeinslavemodeafterenableedge - - 35 nS Dataoutputvalidtimeinmastermodeafterenableedge - - 6 nS Thold-dout Dataoutputholdtimeinslavemodeafterenableedge 11.5 - - nS Dataoutputholdtimeinmastermodeafterenableedge 2 - - nS DutySCK SlaveinputclockdutycycleofSPI 25 - 75 nS Figure11SPItiming–slavemode(1) Figure12SPItiming–slavemode(2)

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 38/51 文件编号：CS-QR-YF-054A02 Figure13SPItiming–mastermode

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 39/51 文件编号：CS-QR-YF-054A02

8.17 I2Ccharacteristics

I2Canalogfiltercharacteristics Symbol Description Min Typ. Max. Units TI2C-fp Theexternal-signalpulsewidthfilteredbyI2Canalogfilter - 50 nS TI2C-nfp Theexternal-signalpulsewidthno-filteredbyI2Canalogfilter 160 - - nS

8.18 ESDcharacteristics

Symbol Description Class Value Units VESD-HBM Electrostaticdischargevoltageofhumanbodymodel, BasedonMIL-STD-883E, Trange=23±5℃ Relativehumidity:55%±10%(RH) 3A ≥4000 V VESD-MM Electrostaticdischargevoltageofmachinemodel, BasedonJEDECEIA/JESD22-A115, Trange=23±5℃ Relativehumidity:55%±10%(RH) C ≥400 V VESD-CDM Electrostaticdischargevoltageofchargedevicemodel, BasedonJEDECEIA/JESD22-C101F, Trange=23±5℃ Relativehumidity:55%±10%(RH) C2 ≥500 V Ilatchup Electrostaticdischargevoltageofmachinemodel, BasedonJEDECSTANDARDNO.78CSEPTMBER2010, Trange=105±5℃ Relativehumidity:55%±10%(RH) II ≥200 mA

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 40/51 文件编号：CS-QR-YF-054A02

9 Packaginginformation

9.1 LQFP32

Figure14LQFP32packageoutline LQFP32packagedimensions Symbol Millimeter Min Nom Max A - - 1.60 A1 0.05 - 0.15 A2 1.35 1.40 1.45 A3 0.59 0.64 0.69 b 0.33 - 0.41 b1 0.32 0.35 0.38 c 0.13 - 0.17 c1 0.12 0.13 0.14 D 8.80 9.00 9.20 D1 6.90 7.00 7.10 E 8.80 9.00 9.20 E1 6.90 7.00 7.10 eB 8.10 - 8.25 e 0.80BSC L 0.45 - 0.75 L1 1.00REF θ 0 - 7° LQFP32Packagethermalcharacteristics Name Value Unit ΘJA,by2S2P 54 ℃/W ΘJC 18.2 ℃/W LQFP32MoistureSensitivity Name Level MoisturesensitivityLevel MSL3

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 41/51 文件编号：CS-QR-YF-054A02 Figure15QFN32packageoutline QFN32Lpackagedimensions Symbol Millimeter Min Nom Max A 0.50 0.55 0.60 A1 0 0.02 0.05 b 0.19 0.24 0.29 b1 0.18REF c 0.152REF D 4.90 5.00 5.10 D2 3.40 3.50 3.60 e 0.50BSC Nd 3.50BSC E 4.90 5.00 5.10 E2 3.40 3.50 3.60 Ne 3.50BSC L 0.35 0.40 0.45 K 0.30 0.35 0.40 h 0.30 0.35 0.40 QFN32Packagethermalcharacteristics Name Value Unit ΘJA,by2S2P TBD ℃/W ΘJC TBD ℃/W QFN32MoistureSensitivity Name Level MoisturesensitivityLevel MSL3

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 42/51 文件编号：CS-QR-YF-054A02 Figure16QFN32packageoutline QFN32packagedimensions Symbol Millimeter Min Min A 0.70 0.75 0.80 A1 0 0.02 0.05 b 0.15 0.20 0.25 c 0.18 0.20 0.25 D 3.90 4.00 4.10 D2 2.60 2.65 2.70 e 0.40BSC Nd 2.80BSC E 3.90 4.00 4.10 E2 2.60 2.65 2.70 Ne 2.80BSC L 0.35 0.40 0.45 L1 0.30 0.35 0.40 L2 0.15 0.20 0.25 h 0.30 0.35 0.40 QFN32MoistureSensitivity Name Value Unit ΘJA,by2S2P TBD ℃/W ΘJC TBD ℃/W QFN32MoistureSensitivity Name Level MoisturesensitivityLevel MSL3

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 43/51 文件编号：CS-QR-YF-054A02

9.4 QFN28

Figure17QFN28packageoutline QFN28packagedimensions Symbol Millimeter Min Nom Max A 0.50 0.55 0.60 A1 0.00 0.02 0.05 A3 0.15REF b 0.20 0.25 0.30 D 3.90 4.00 4.10 E 3.90 4.00 4.10 D2 2.64 2.74 2.84 E2 2.64 2.74 2.84 e 0.40 0.50 0.60 H 0.35REF K 0.13 0.23 0.33 L 0.30 0.40 0.50 L1 0.20 0.30 0.40 R 0.10 - - c1 - 0.21 - c2 - 0.21 - QFN28Packagethermalcharacteristics Name Value Unit ΘJA,by2S2P 50.80 ℃/W ΘJC 19.7 ℃/W QFN28 MoistureSensitivity Name Level MoisturesensitivityLevel MSL3

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 44/51 文件编号：CS-QR-YF-054A02

9.5 TSSOP20

Figure18TSSOP20packageoutline TSSOP20packagedimensions Symbol Millimeter Min Nom Max A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 A3 0.39 0.44 0.49 b 0.20 - 0.28 b1 0.19 0.22 0.25 c 0.13 - 0.17 c1 0.12 0.13 0.14 D 6.40 6.50 6.60 E1 4.30 4.40 4.50 E 6.20 6.40 6.60 e 0.65BSC L 0.45 0.60 0.75 L1 1.00REF θ 0 - 8° TSSOP20Packagethermalcharacteristics Name Value Unit ΘJA,by2S2P 103 ℃/W ΘJC 35.7 ℃/W TSSOP20MoistureSensitivity Name Level MoisturesensitivityLevel MSL3

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 45/51 文件编号：CS-QR-YF-054A02

10 Productnamingrules

10.1 Productmodeldescription

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 46/51 文件编号：CS-QR-YF-054A02

10.2 Productprintingmark

Marking instructions:

1 Front pin Pin1 mark;

2 The first row on the front (Chipsea);

3 The second line on the front (product model);

The third line on the front (yywwxxx) is the main batch number. The two digits YY on the left are taken from the last two digits of the Gregorian calendar year, and the two digits WW in the middle are taken from the calendar weeks of the current year. If there are less than two digits, 0 is added on the left, and the three digits XXX on the right are variables, which shall be subject to the order specification;

5 Font is "Arial";

6 The printing method is laser positive printing

Forexample,themarkingofF035K6U6isasfollows:

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 47/51 文件编号：CS-QR-YF-054A02

11 Orderinginformation

Count Flash Package Pack Type Package Qty. Operating temperature CS32F035K6U6 32 32KB QFN32(4×4×0.75-e=0.40) Tray 4900 -40 C ~85 C CS32F035K6U6T 32 32KB QFN32(4×4×0.75-e=0.40) Tape & Reel 3000 -40 C ~85 C CS32F036F6P7 20 32KB TSSOP20 Tube 6000 -40 C ~105 C CS32F036G6U7 28 32KB QFN28(4×4×0.55-e=0.50) Tray 4900 -40 C ~105 C CS32F036K6U7 32 32KB QFN32(5×5×0.75-e=0.50) Tray 4900 -40 C ~105 C CS32F036K6U7T 32 32KB QFN32(5×5×0.75-e=0.50) Tape & Reel 3000 -40 C ~105 C CS32F036K6T7 32 32KB LQFP32 Tray 2500 -40 C ~105 C

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 48/51 文件编号：CS-QR-YF-054A02

12 Errata

Pleaserefertothedocument“ErrataofCS32F03X”.

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 49/51 文件编号：CS-QR-YF-054A02

13 Abbreviations

ADC AnalogtoDigitalConverter AHB AdvancedHigh-performanceBus APB AdvancedPeripheralBus ARM AdvancedRISCMachines Cortex EmbeddedMicrocontrollerProcessors CPU CentralProcessingUnit CRC Cyclicredundancycheck DMA DirectMemoryAccess ESD ElectrostaticDischarge ETR Externaltriggerinput EXTI Extendedinterrupt/eventcontroller FLASH Floatinggatetransistormemory FWDT Freewatchdogtimer GPIO GeneralPurposeInput/Output HXT Externalhighspeedcrystaloscillator HRC InternalhighspeedRCoscillator I2C Inter-integratedcircuit I2S Inter-ICsound IR Infraredradiation IrDA Infrareddataassociation ISO7816 InternationalOrganizationforStandardization（ISO）7816 LIN Localinterconnectnetwork LRC InternallowspeedRCoscillator LSB LastSignificantBit LVD Lowvoltagedetector LXT Externallowspeedcrystaloscillator MCU MicrocontrollerUnit MISO MasterIn/SlaveOut MOSI MasterOut/SlaveIn NRST Negativereset NSS SlaveSelect NVIC Nestedvectoredinterruptcontroller PCB PrintedCircuitBoard PDR Power-downreset PLL Phaselockedloop PMBus PowerManagementBus POR Power-onreset RAM RandomAccessMemory RTC Real-timeclock SCK SerialClock SD SerialData SMBus SystemManagementBus SPI Serialperipheralinterface SRAM StaticRandomAccessMemory SWD SerialWireDebug TIM TIMER

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 50/51 文件编号：CS-QR-YF-054A02 TS TemperatureSensor USART Universalsynchronous/asynchronousreceiver/transmitter WS WordSelect WWDT Windowwatchdogtimer

本资料为芯海科技专有财产，非经许可，不得复制、翻印或转变其他形式使用。 This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format without prior permission of CHIPSEA 聚点滴之芯．成浩瀚之海 51/51 文件编号：CS-QR-YF-054A02

14 Salesandservice

Chinaoffice: 9F,BlockA,GardenCityDigitalBuilding,No.1079NanhaiRoad,NanshanDistrict,Shenzhen Technicalsupport: Tel:+(86755)86155432 Fax:+(86755)86169057 Onlinesupport: Websiteaddress：www.chipsea.com Wechat:chipsea