CMF20120D CREE | Alldatasheet

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Subject to change without notice. www.cree.com/power CMF20120D-Silicon Carbide Power MOSFET 1200V 80 mΩ Z-FET™ MOSFET N-Channel Enhancement Mode CMF20120D Rev.

CMF20120D Rev. - CMF20120D-Silicon Carbide Power MOSFET Z-FET™ MOSFET N-Channel Enhancement Mode

Features

  • Industry Leading RDS(on)
  • High Speed Switching
  • Low Capacitances
  • Easy to Parallel
  • Simple to Drive
  • Pb-Free Lead Plating, ROHS Compliant, Halogen Free Benefits
  • Higher System Efficiency
  • Reduced Cooling Requirements
  • Avalanche Ruggedness
  • Increased System Switching Frequency

Applications

  • Solar Inverters
  • High Voltage DC/DC Converters
  • Motor Drives Package TO-247-3 Part Number Package CMF20120D TO-247-3 VDS = 1200 V RDS(on) = 80 mΩ ID(MAX)@TC=25°C = 33 A G D S S G D Maximum Ratings Symbol Parameter Value Unit Test Conditions Note ID Continuous Drain Current A VGS@20V, TC = 25˚C

17 VGS@20V, TC = 100˚C

IDpulse Pulsed Drain Current 78 A Pulse width tP limited by Tjmax TC = 25˚C EAS Single Pulse Avalanche Energy 2.2 J ID = 20A, VDD = 50 V, L = 9.5 mH EAR Repetitive Avalanche Energy 1.5 J tAR limited by Tjmax IAR Repetitive Avalanche Current 20 A ID = 20A, VDD = 50 V, L = 3 mH tAR limited by Tjmax VGS Gate Source Voltage -5/+25 V Ptot Power Dissipation 150 W TC=25˚C TJ , Tstg Operating Junction and Storage Temperature -55 to +125 ˚C TL Solder Temperature 260 ˚C 1.6mm (0.063”) from case for 10s Md Mounting Torque 1 8.8 Nm lbf-in M3 or 6-32 screw

CMF20120D Rev. - Table of Contents

CMF20120D Rev. - Applications Information 2.5V The Cree SiC MOSFET has removed the upper voltage limit of silicon MOSFETs. However, there are some differences in characteristics when compared to what is usually expected with high voltage silicon MOSFETs. These differences need to be carefully addressed to get maximum benefit from the SiC MOSFET. In general, although the SiC MOSFET is a superior switch compared to its silicon counterparts, it should not be considered as a direct drop-in replacement in existing applications. There are two key characteristics that need to be kept in mind when applying the SiC MOSFETs: modest transconductance requires that VGS needs to be 20 V to optimize performance. This can be see in the Output and Transfer Characteristics shown in Figures 1-3. The modest transconductance also affects the transition where the device behaves as a voltage controlled resistance to where it behaves as a voltage controlled current source as a funtion of VDS. The result is that the transition occurs over higher values of VDS than are usually experienced with Si MOSFETs and IGBTs. This might affect the operation anti-desaturation circuits, especially if the circuit takes advantage of the device entering the constant current region at low values of forward voltage. The modest transconductance needs to be carefully considered in the design of the gate drive circuit. The first obvious requirement is that the gate be capable of a >22 V (+20 V to -2V) swing. The recommended on state VGS is +20 V and the recommended off state VGS is between -2 V to -5 V. Please carefully note that although the gate voltage swing is higher than the typical silicon MOSFETs and IGBTs, the total gate charge of the SiC MOSFET is considerably lower. In fact, the product of gate voltage swing and gate charge for the SiC MOSFET is lower than comparable silicon devices. The gate voltage must have a fast dV/dt to achieve fast switching times which indicates that a very low impedance driver is necessary. Lastly, the fidelity of the gate drive pulse must be carefully controlled. The nominal threshold voltage is 2.5V and the device is not fully on (dVDS/dt≈0) until the VGS is above 16V. This is a noticeably wider range than what is typically experienced with silicon MOSFETs and IGBTs. The net result of this is that the SiC MOSFET has a somewhat lower ‘noise margin’. Any excessive ringing that is present on the gate drive signal could cause unintentional turn-on or partial turn-off of the device. The gate resistance should be carefully selected to ensure that the gate drive pulse is adequately dampened. To first order, the gate circuit can be approximated as a simple series RLC circuit driven by a voltage pulse as shown below.

CMF20120D Rev. - RLOOP LLOOP CGATEVPULSE C R LOOP GATELOOP ≥=ζζ ζζ GATE LOOP LOOP C L2R ≥∴   VCC SiC DMOSFET VEE GATE DRIVER T1GATE DRIVE INPUT IG SE NSE As shown, minimizing LLOOP minimizes the value of RLOOP needed for critical dampening. Minimizing LLOOP also minimizes the rise/fall time. Therefore, it is strongly recommended that the gate drive be located as close to the SiC MOSFET as possible to minimize LLOOP. The internal gate resistance of the SiC MOSFET is 5 Ω. An external resistance of 6.8 Ω was used to characterize this device. Lower values of external gate resistance can be used so long as the gate fidelity is maintained. In the event that no external gate resistance is used, it is suggested that the gate current be checked to indirectly verify that there is no ringing present in the gate circuit. This can be accomplished with a very small current transformer. A recommended setup is a two-stage current transformer as shown below:

CMF20120D Rev. - 100n -VEE ISO1 6N137 330 VGS MONITOR 390 LM2931T-5.0 IN1 OUT 3 GND2 10u C20 10u 10u IXDI414 VCC1 IN2 NC3 GND4 VCC 8 OUT 7 OUT 6 GND 5 100n THESE COMPONENTS ARE LOCATED ON THE -VEE PLANE 100n THESE COMPONENTS ARE LOCATED ON THE GND PLANE 100n C13 10n PIN 1 SOURCE -VEE +VCC -VEE -VEE -VEE +VCC GND C10 100n -VEE -VEE -VEE +VCC -VEE 10u 10u +VCC -VEE C14 100n C11 100u 6.3V -VEE PULSE GEN INP UT RB160M-60 120 120 TBD 1206 TBD 1206 TBD 1206 RB160M-60 C17 100n C18 100n -VEE -VEE 100n C12 100n -VEE -VEE C15 100n C16 100n -VEE -VEE BNC BNC C19 100n PIN 2 GATE -VEE Stray inductance on source lead causes load di/dt to be fed back into gate drive which causes the following:

  • Switch di/dt is limited
  • Could cause oscillation LOAD CURRENT LOAD CURRENT SiC DMOSR GATE L STRAY SiC DMOS R GATE L STRAY Kelvin gate connection with separate source return is highly recommended DRIVE DRIVE 20V 20V The gate driver is an IXYS IXDI414. This device has a 35 V ouput swing, output resistance of 0.6 Ω typical, and a peak current capability of 14 A. The external gate resistance used for characterization of the SiC MOSFET was 6.8 Ω. Careful consideration needs to be given to the selection of the gate driver. The typical application error is selection of a gate driver that has adequate swing, but output A schematic of the gate driver circuit used for characterization of the SiC MOSFET is shown below:

CMF20120D Rev. - resistance and current drive capability are not carefully considered. It is critical that the gate driver possess high peak current capability and low output resistance along with adequate voltage swing. A significant benefit of the SiC MOSFET is the elimination of the tail current observed in silicon IGBTs. However, it is very important to note that the current tail does provide a certain degree of parasitic dampening during turn-off. Additional ringing and overshoot is typically observed when silicon IGBTs are replaced with SiC MOSFETs. The additional voltage overshoot can be high enough to destroy the device. Therefore, it is critical to manage the output interconnection parasitics (and snubbers) to keep the ringing and overshoot from becoming problematic. ESD RATINGS ESD Test Total Devices Sampled Resulting Classification ESD-HBM All Devices Passed 1000V 2 (>2000V) ESD-MM All Devices Passed 400V C (>400V) ESD-CDM All Devices Passed 1000V IV (>1000V)

CMF20120D Rev. -

Electrical Characteristics

Symbol Parameter Min. Typ. Max. Unit Test Conditions Note V(BR)DSS Drain-Source Breakdown Voltage 1200 V VGS = 0V, ID = 100μA VGS(th) Gate Threshold Voltage 2.5 4 V VDS = VGS, ID = 1mA, TJ = 25ºC

1.8 VDS = VGS, ID = 1mA, TJ = 125ºC

IDSS Zero Gate Voltage Drain Current 1 100 μA VDS = 1200V, VGS = 0V, TJ = 25ºC 10 250 VDS = 1200V, VGS = 0V, TJ = 125ºC IGSS Gate-Source Leakage Current 250 nA VGS = 20V, VDS = 0V RDS(on) Drain-Source On-State Resistance 80 110 mΩ VGS = 20V, ID = 20A, TJ = 25ºC 95 130 VGS = 20V, ID = 20A, TJ = 125ºC gfs Transconductance 7.3 S VDS= 20V, IDS= 20A, TJ = 25ºC fig. 3

6.8 VDS= 20V, IDS= 20A, TJ = 125ºC

Ciss Input Capacitance 1915 pF VGS = 0V VDS = 800V f = 1MHz VAC = 25mV fig. 5 Coss Output Capacitance 120 Crss Reverse Transfer Capacitance 13 td(on)i Turn-On Delay Time 17.2 ns VDD = 800V VGS = -2/20V ID = 20A RG = 6.8Ω L = 856μH Per JEDEC24 Page 27 fig. 12 tr Rise Time 13.6 td(off)i Turn-Off Delay Time 62 tfi Fall Time 35.6 EON Turn-On Switching Loss (25ºC) (125ºC) 530 422 μJ EOff Turn-Off Switching Loss (25ºC) (125ºC) 320 329 μJ RG Internal Gate Resistance 5 Ω VGS = 0V, f = 1MHz, VAC = 25mV Reverse Diode Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note Vsd Diode Forward Voltage 3.5 V VGS = -5V, IF=10A, TJ = 25ºC

3.1 VGS = -2V, IF=10A, TJ = 25ºC

trr Reverse Recovery Time 220 ns VGS = -5V, IF=20A, TJ = 25ºC VR = 800V, diF/dt= 100A/μs fig. 13,14Qrr Reverse Recovery Charge 142 nC Irrm Peak Reverse Recovery Current 2.3 A Thermal Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note RθJC Thermal Resistance from Junction to Case 0.58 0.7 °C/W fig. 6RθCS Case to Sink, w/ Thermal Compound 0.25 RθJA Thermal Resistance From Junction to Ambient 40 Gate Charge Characteristics Symbol Parameter Typ. Max. Unit Test Conditions Note Qgs Gate to Source Charge 23.8 nC VDD = 800V ID =20A VGS = -2/20V Per JEDEC24-2 fig.9 Qgd Gate to Drain Charge 43.1 Qg Gate Charge Total 90.8 NOTES: 1. The recommended on-state VGS is +20V and the recommended off-state VGS is between -2V and -5V

Figure 3. Typical Transfer Characteristics

CMF20120D Rev. - 300 400 500 600 Switching Loss (µJ) Turn-on Loss 100 200 300 400 500 600 0 25 50 75 100 125 150 Switching Loss (µJ) Temp ( C) Turn-on Loss VGS (V) 0 20 40 60 80 100 VGS (V) Gate Charge (nC) Typical Performance Fig 6. Transient Thermal Impedence, Junction - Case Fig 9. Typical Gate Charge Characteristics @ 25°C Fig 7. Inductive Switching Energy(Turn-on) vs. T Fig 8. Inductive Switching Energy(Turn-off) vs. T ID=20A VDD=800V VGS= -2/20V RG= 11.8Ω Total VDD= 800V ID= 20A 300 400 500 600 Switching Loss (µJ) Turn-off Loss 100 200 300 400 500 600 0 25 50 75 100 125 150 Switching Loss (µJ) Temp ( C) Turn-off Loss VGS= -2/20V RG= 11.8Ω Total VDD= 800V ID= 20A 1.E-02 1.E-01 1.E+00 Zth (oC/W) 1.E-04 1.E-03 Time (s) 1000 1500 2000 2500 VDS (V) IDS (A) IDS VDS 500 Time (s) EAS = 2.20 J Fig 10. Typical Avalanche Waveform

CMF20120D Rev. - 10% Irr Vcc trr Irr Ic Vpk tx 10% Vcc Qrr=∫ trr id dt tx Diode Reverse Recovery Energy Diode Recovery Waveforms Erec=∫ id dt t1 t2 VGS(off) VGS(on) iD(off) iD(on) td(on)i td(off)itfi tri pulse duration tw Input (Vi) Output (iD) Input Pulse Rise Time Input Pulse Fall Time 90% 50% 10% 90% 50% 10% 10% 10% 90% 90% ton(i) toff(i) 800V - 42.3μf 856μH CMF20120D C2D10120D 10A, 1200V SiC Schottky Clamped Inductive Switch Testing Fixture Fig 11. Switching Waveform Test Circuit Fig 14. Body Diode Recovery Test 800V 42.3μf 856μH CMF20120D CMF20120D Fig 12. Switching Test Waveform Times Fig 13. Body Diode Recovery Waveform D.U.T. D.U.T.

CMF20120D Rev. - Package Dimensions Package TO-247-3 G D S S G D S G D Fig 16. Theoretical Avalanche WaveformFig 15. Avalanche Test Circuit EA = 1/2L x ID POS Inches Millimeters Min Max Min Max A .190 .205 4.83 5.21 A1 .090 .100 2.29 2.54 A2 .075 .085 1.91 2.16 b .042 .052 1.07 1.33 b1 .075 .095 1.91 2.41 b2 .075 .085 1.91 2.16 b3 .113 .133 2.87 3.38 b4 .113 .123 2.87 3.13 c .022 .027 0.55 0.68 D .819 .831 20.80 21.10 D1 .640 .695 16.25 17.65 D2 .037 .049 0.95 1.25 E .620 .635 15.75 16.13 E1 .516 .557 13.10 14.15 E2 .145 .201 3.68 5.10 E3 .039 .075 1.00 1.90 E4 .487 .529 12.38 13.43 e .214 BSC 5.44 BSC N 3 3 L .780 .800 19.81 20.32 L1 .161 .173 4.10 4.40 ØP .138 .144 3.51 3.65 Q .216 .236 5.49 6.00 S .238 .248 6.04 6.30

This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffic control systems, or weapons systems. Copyright © 2010-2011 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo, Z-REC and Z-FET are registered trademarks of Cree, Inc. 13 CMF20120D Rev. - Cree, Inc.

4600 Silicon Drive

Durham, NC 27703 USA Tel: +1.919.313.5300 Fax: +1.919.313.5451 www.cree.com/power Recommended Solder Pad Layout TO-247-3 Part Number Package CMF20120D TO-247-3 “The levels of environmentally sensitive, persistent biologically toxic (PBT), persistent organic pollutants (POP), or otherwise restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS), as amended through April 21, 2006.