R1275S-Y NISSHINBO | Alldatasheet

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Technical content

30 V, 2 A Synchronous PWM Step-down DC/DC Converter for Industrial Applications

NO.EY-371-201203 The R1275S is a 36-V synchronous step-down DC/DC converter with built-in drivers. It is designed for industrial equipment, OA equipment and home electronics that require a 24-V input. It operates at a 2-MHz switching frequency, which allows to use a small inductor to ensure a high transient response and to maintain a high efficiency at heavy load condition. Using a spread spectrum clock generator, the EMI noise can be reduced. This is a high-reliability semiconductor device for industrial application (-Y) that has pass ed both the screening at high temperature and the reliability test with extended hours.

  • Provides a high switching frequency at 2 MHz with an efficiency of 87%.
  • Maintains the output voltage constant by reducing a switching frequency to the minimum 1/4 when an input-output voltage difference is small.
  • Achieves the EMI noise reduction by using a spread spectrum clock generator. (Diffusion Rate: +8%).  Input Voltage Range (Max. Ratings): 3.6 V to 30 V (36 V)  Start-up Voltage: 4.5 V  Standby Current: Typ. 4 µA  Output Voltage Range: 3.3 V to 5.0 V  Feedback Voltage: 0.64 V ±1.0%  Adjustable Oscillator Frequency Using External Resistors: 2 MHz  External Synchronous Clock Frequency: 1.8 MHz to 2.2 MHz  Spread Spectrum Clock Generator (SSCG): Diffusion Rate: Typ. +8%  Minimum On Time: Typ. 70 ns  Minimum Off Time: Typ. 120 ns  Duty-over: Min. 1/4  Soft-start  Thermal Shutdown: Tj = 160°C  Undervoltage Lockout (UVLO): VCC = 3.3 V (Typ.)  Overvoltage Lockout (OVLO): VIN = 35 V (Typ.)  Overvoltage Detection (OVD): FB Pin Voltage (VFB) +10%  LX Current Limiting: Typ. 3 A  High-side Driver On Resistance: Typ. 0.145 Ω  Low-side Driver On Resistance: Typ. 0.095 Ω Efficiency (VOUT = 5 V) Choose the optional functions from below.  Overcurrent Protection SSCG A Hiccup-type Disable C Hiccup-type Enable  FA Equipment, Smart Meters  Surveillance Cameras and Vending Machines that are used outside or under high-temperature conditions  Motors and Lightings that are accompanied by self-heating 100 0 500 1000 1500 2000 Efficiency [%] Iout [mA] VIN=12V HSOP-18 5.2 mm x 6.2 mm x 1.45 mm OVERVIEW KEY BENEFITS KEY SPECIFICATIONS TYPICAL CHARACTERISTICS PACKAGE OPTIONAL FUNCTIONS

APPLICATIONS

NO.EY-371-201203 SELECTION GUIDE Selection Guide Product Name Package Quantity per Reel Pb Free Halogen Free R1275S003-E2-YE HSOP-18 1,000 pcs Yes Yes ：Choose the optional functions from below.  Overcurrent Protection SSCG A H iccup-type Disable C Hiccup-type Enable BLOCK DIAGRAM R1275S Block Diagram

NO.EY-371-201203 PIN DESCRIPTION Top View Bottom View HSOP-18 Pin Configuration  The tab on the bottom of the package is substrate level (GND). The tab must be connected to the ground plane on the board. HSOP-18 Pin Description Pin No. Pin Name Description 1, 2 VIN(1) Power Supply Pin

3 NC Not Connected

4 CE Chip Enable Pin, Active-high

5 CSS Soft-start Adjustment Pin

6 COMP Capacitor Connecting Pin for Error Amplifier’s Phase

7 FB Feedback Input Pin for Error Amplifier

8 PGOOD Power Good Output Pin

9 VOUT Output Voltage Feedback Input Pin

10 MODE(2) Mode Setting Input Pin

11 RT Oscillator Frequency Adjustment Pin

12 VCC VCC Output Pin

13 BST Bootstrap Pin

14, 15, 16 GND(1) GND Pin

17 NC Not Connected

18 LX Switching Pin

(1) The pins with the same name should be connected together. (2) This pin should be used with High or with external clock input.

NO.EY-371-201203 Equivalent Circuits for the Individual Terminals Equivalent Circuit for CE Pin E quivalent Circuit for CSS Pin Equivalent Circuit for COMP Pin Equivalent Circuit for FB Pin Equivalent Circuit for PGOOD Pin Equivalent Circuit for VOUT Pin

NO.EY-371-201203 Equivalent Circuit for MODE Pin Equivalent Circuit for RT Pin Equivalent Circuit for VCC Pin Equivalent Circuit for BST Pin Equivalent Circuit for LX Pin

NO.EY-371-201203 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings Symbol Parameter Rating U n i t VIN VIN Pin Input Volta ge −0.3 to 36 V VCE CE Pin Volta ge(1) −0.3 to VIN+0.3 ≤ 36 V VCSS CSS Pin Volta ge −0.3 to 3 V VOUT VOUT Pin Volta ge −0.3 to 16 V VRT RT Pin Volta ge −0.3 to 3 V VCOMP COMP Pin Volta ge(2) −0.3 to 6 V VFB FB Pin Volta ge −0.3 to 3 V VCC VCC Pin Voltage −0.3 to 6 V VCC Pin Output Current Internally Limited m A VBST BST Pin Volta ge LX−0.3 to LX+6 V VLX LX Pin Volta ge(1) −0.3 to VIN +0.3 ≤ 36 V VMODE MODE Pin Volta ge −0.3 to 6 V VPGOOD PGOOD Pin Volta ge −0.3 to 6 V PD Power Dissipation (3)(JEDEC STD.51-7 Test Land Pattern) 3100 mW Tj Junction Temperature Ran ge −40 to 125 °C Tstg S t o r a ge Temperature Range −55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the lifetime and safety for both device and system using the device in the field. The functional operation at or over t hese absolute maximum ratings is not assured. RECOMMENDED OPERATING CONDITIONS Recommended Operating Conditions Symbol Parameter Rating U n i t VIN Operatin g Input Voltage 3.6 to 30 V Ta Operatin g Temperature Range −40 to 105 °C RECOMMENDED OPERATING CONDITIONS All of electronic equipment shou ld be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if they are used over such condition s by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. (1) It should not exceed VIN + 0.3 V. (2) It should not exceed VCC + 0.3 V. (3) Refer to POWER DISSIPATION for detailed information.

NO.EY-371-201203

ELECTRICAL CHARACTERISTICS

VIN = 12 V, CE = VIN, unless otherwise specified. The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 105°C. Symbol Item Conditions Min. Typ. Max. Unit VSTART Start-up Voltage 4.5 V VCC VCC Pin Voltage (VCC-GND) VFB = 0.672 V 4.75 5 5.25 V ISTANDBY Standby Current VIN = 30 V, CE = 0 V 4 30 µA IVIN1 VIN Consumption Current 1 at PWM switching stop VFB = 0.672 V, MODE = 5 V, VOUT = LX = 5 V 1.0 1.35 mA VUVLO1 Undervoltage Lockout (UVLO) Threshold VCC Falling 3.2 3.3 3.4 V VUVLO2 VCC Rising 4.1 4.3 4.5 V VOVLO1 Overvoltage Lockout (OVLO) Threshold VIN Rising 33.6 35 36 V VOVLO2 VIN Falling 32 34 V fOSC0 Oscillator Frequency 0 RRT = 14 kΩ 1800 2000 2200 kHz fSYNC Synchronizing Frequency 1800 2200 kHz ΔfOSC_SSCG Oscillator Frequency Spreading Rate for SSCG VFB = 0.672 V (R1275S003C) +8 % tSS1 Soft-start Time 1 CSS = OPEN 0.36 0.75 ms tSS2 Soft-start Time 2 CSS = 4.7 nF 1.4 2 ms ITSS Soft-start Pin Charging Current CSS = 0 V 1.8 2 2.2 µA VSSEND CSS Pin Voltage at soft-start stop 0.635 0.64 0.705 V RDIS_CSS CSS Pin Discharge Resistance VIN = 4.5 V, CE = 0 V, CSS = 3 V 2 5 kΩ ILXLIMIT LX Current Limiting High-side Transistor, DC 2.55 3.0 3.45 A IREVLIMIT Reverse Current Limiting Low-side Transistor, DC 1.7 3.5 A VCEH CE ”High” Input Voltage 1.25 V VCEL CE ”Low” Input Voltage 1.1 V ICEH CE ”High” Input Current VIN = CE = 30 V 1.2 2.45 µA ICEL CE ”Low” Input Current 0 0.1 µA IFBH FB ”High” Input Current VFB = 0.672 V −0.1 0 0.1 µA IFBL FB ”Low” Input Current VFB = 0 V −0.1 0 0.1 µA All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C).

NO.EY-371-201203 ELECTRICAL CHARACTERISTICS (continued) VIN = 12 V, CE = VIN, unless otherwise specified. The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 105°C. Symbol Item Conditions Min. Typ. Max. Unit VMODEH MODE ”High” Input Voltage 1.33 V IMODEH MODE ”High” Input Current MODE = 5 V 6.25 14.0 µA TTSD Thermal Shutdown Temperature Threshold Rising 150 160 °C TTSR Falling 125 140 °C VPGOODOFF PGOOD ”Low” Output Voltage VIN = 3.6 V, PGOOD = 1 mA 0.25 V IPGOODOFF PGOOD Pin Leakage Current VIN = 30 V, PGOOD = 6 V 100 nA VFBOVD1 FB Pin Overvoltage Detection (OVD) Threshold VFB Rising VFB x1.10 0.730 V VFBOVD2 VFB Falling 0.650 VFB x 1.07 V VFBUVD1 FB Pin Undervoltage Detection (UVD) Threshold VFB Falling 0.556 VFB x 0.90 V VFBUVD2 VFB Rising VFB x 0.93 0.625 V All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C).

NO.EY-371-201203 THEORY OF OPERATION MODE Pin Function The R1275S switches the operation mode to either a forced PWM m ode or a PLL PWM mode by applying a voltage or a pulse to the MODE pin. By applying 1.33 V or more to the MODE pin, the operation mode goes into the forced PWM mode and oper ates at PWM regardless of a lo ad current. See Forced PWM Mode for more details. See Frequency Synchronization for the operation when an external clock is connected. Frequency Synchronization The R1275S can synchronize to t he external clock frequency sent to the MODE pin by using a PLL (Phase Locked Loop). The synchronizable frequency range is between 1.8 MHz to 2.2 MHz. During the synchronization, the operation mode is a forced PWM. The recommended pulse width of the external clock is 100 ns or more. When starting up the device while the external clock is sent to the MODE pin, the device synchronizes to the external c lock while starting up with soft-start. Be aware that if the voltage difference between input and output is reduced and the device goes into the maxduty or duty-over condition, the device starts operating at 1/4 of the synchronous frequency and goes into the asynchronous condition with the MODE pin. Duty-over When the input voltage is dropped at cranking, the R1275S linearly changes the operating frequency to 1/4 of the set oscillator frequency in order to maintain the output vo ltage. This can make the on duty more than the normal maxduty and it can also reduce the voltage difference between input and output. The duty-over starts operating when it detects the minimum off time in the set oscil lator frequency and the external synchronous oscillator frequency. UVLO (Undervoltage Lockout) If the VCC pin voltage drops below the UVLO detection threshold of 3.3 V (Typ.) due to the input voltage drop, the R1275S turns the switching off to prevent the malfunction of the device. Due to the switching stop, the output voltage drops according to the load and C OUT. If the VCC pin voltage rises above the UVLO threshold of 4.3 V (Typ.), the device restarts the operation with soft-start. For the R1275S, 4.5 V, the maximum UVLO release voltage, is a start-up voltage. OVLO (Overvoltage Lockout) If the input voltage rises above the OVLO detection threshold of 35 V (Typ.), the R1275S turns the switching off to prevent malfunctions of the device or damages on the driver due to overvoltage. Due to the switching stop, the output voltage drops according to the load and C OUT values. If the input voltage drops below the OVLO release threshold of 34 V (Typ.), the device restarts the operation with soft-start. Note that this function does not guarantee the operation above the absolute maximum ratings.

NO.EY-371-201203 PGOOD (Power Good) Output The power good function with using a NMOS open drain output pin can detect the following states of the R1275S. The NMOS turns on and the PGOOD pin becomes “Low” when detecting them. After the device returns to their original state, the NMOS turns off and the PGOOD pin outputs “High” (PGOOD Input Voltage: V UP). ・CE = “Low” (Shut down) ・UVLO ・OVLO ・Thermal Shutdown ・Soft-start ・UVD ・OVD ・Hiccup-type Protection The PGOOD pin is designed to become 0.25 V or less in “Low” level when the current floating to the PGOOD pin is 1 mA. The use of the PGOOD input voltage (V UP) of 5.5 V or less and the pull-up resistor (RPG) of 10 kΩ to 100 kΩ are recommended. If not using the PGOOD pin, connect it to “Open” or “GND”. Power Good Circuit

NO.EY-371-201203 Rising / Falling Sequence of Power Good Circuit

NO.EY-371-201203 Under Voltage Detection (UVD) The UVD function indirectly monitors the output voltage with using the FB pin. The PGOOD pin outputs “Low” when the UVD detector threshold is 90% (Typ.) of V FB and V FB is less than the UVD detector threshold for more than 15 µs (Typ.). When VFB is over 93% (Typ.) of 0.64 V, the PGOOD pin outputs “High” after delay time (Typ.120 µs.). And, the hiccup-type overcurrent protection works when detecting a current limiting during the UVD detection. Overvoltage Detection (OVD) The OVD function indirectly monitors the output voltage with us ing the FB pin. Switching stops even if the internal circuit is active state, when detecting the overvoltage of V FB. The PGOOD pin outputs “Low” when the OVD detector threshold is 110% (Typ.) of VFB and VFB is over the OVD detector threshold for more than 15 µs (Typ.). When VFB is under 107% (Typ.) of 0.64 V, which is the OVD released voltage, the PGOOD pin outputs “High” after delay time (Typ.120 µs.). Then, switching is controlled by normal operation. Hiccup-type Overcurrent Protection The hiccup-type overcurrent protection can work under the opera ting conditions that is the UVD can function during the current limiting. The hiccup type protection stops switching releases the circuit after the protection delay time (Typ. 7.5 ms). Since this protection is auto-release, the CE pin switching of “Low”/“High” is unnecessary. And, damage due to the overheating might not be caused because the term to release is long. When the output is shorted to GND, switching of “ON” / “OFF” is repeated until the shorting is released. Minimum On Time The minimum on time means the minimum time duration that the R1275S can turn the high-side transistor on during the oscillation period. The minimum on time of the devic e (Typ. 70 ns) is determined by the internal circuit. The device cannot generate a pulse width that is less than the pulse width of minimum on time. Therefore, when setting the output voltage and the oscillator frequency, be careful that the minimum step-down ratio [V OUT / VIN x (1 / fOSC)] is not less than the minimum on time. If they are set to less than the minimum step- down ratio, the pulse skipping occurs, which stabilizes the output voltage but increases the output ripple. Minimum Off Time By the adoption of bootstrap method, the high-side FET, which i s used as the R1275S internal circuit for the minimum off time, is used a NMOS. The voltage sufficient to dri ve the high-side FET must be charged. Therefore, the minimum off time is determined from the required time to charge the voltage. By the adoption of the frequency’s reduction method by one-quarter of a set value (Min.), if the input-output difference voltage becomes small or load transients are caused, the OFF period can be caused once in four-cycle period of normal cycle. As a result, the minimum off time becomes 120 ns (Typ.) substantially, and the maximum duty cycle can be improved.

NO.EY-371-201203 Current Limit The output current of the R1275S is limited by the current limit using a peak current method. The current limit is set to 3.0 A (Typ, DC valu e) and it is fixed inside the IC. The current limit circuit limits the current by monitoring the drain and source voltage of a high-side transistor. The transition al current limit of the inductor current is set to be higher than the DC value. The current limit of the device starts operating after the minimum on time, so it has to be careful especially when the device is used close to the minimum on time because the current limit will increase. The following diagram shows the relation between current limit and on time using our evaluation board. The longer the on-time is, the more the current approaches the current limit value of 3.0 A (Typ. DC value). R1275S Current Limit vs LX On Time 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 70 80 90 100 110 120 130 140 ILIM (A) On-Time (ns)

NO.EY-371-201203 Precautions for Operating in Low Input Voltage When using the R1275S with VIN = 5 V or less, the load current may be limited in following two cases. First Case: The device designed to reach current limit by monit oring the voltage difference between VIN and LX. During the low input voltage operation, the driving capability of high-side transistor decreases, so the voltage difference between VIN and LX becomes larger with smaller output current. Therefore, the load current may be limited during the low input voltage operation. Second Case: During the low input voltage operation, the duty-over function decreases the oscillator frequency. While the oscillator frequency is 1/4 of the set frequency, dra wing the load current can cause a voltage difference between the input and output. These make the device to exit from duty-over condition, and as a result, the output voltage drops. Both cases show that the current limit is depending on the input voltage and load current. Careful consideration is required when applying a heavy load while the input voltage is low. The following graph shows the relation between input voltage and load current. If the BST voltage between BST and LX drops extremely, the device forcibly turns off the switching to charge the BST voltage. This may occur when V IN is 4.5 V or less and it may affect the output voltage ripple. Also, if VIN is less than 4.5 V and UVD is detected as the output voltage d ecreases, the hiccup-type overcurrent protection may work due to the protection function inside the IC. VOUT = 3.3 V Setting R1275S Output Current vs Input Voltage 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 IOUT (A) VIN (V) Ta=25°C Ta=105°C Ta=125°C

NO.EY-371-201203 Output Voltage Setting The output voltage (V OUT) can be set by adjustable values of R TOP and R BOT. The value of V OUT can be calculated by Equation 1: VOUT = VFB × (RTOP + RBOT) / RBOT ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equation 1 For example, when setting VOUT = 3.3 V and setting RBOT = 39 kΩ, RTOP can be calculated by substituting them to Equation 1. As a result of the expanding Equation 2, RTOP can be set to 162 kΩ. To make 162 kΩ with using the E24 type resistors, the connecting use of 160 kΩ and 2 kΩ resistors in series is required. If the tolerance level of the set output voltage is wide, using a resistor of 160 kΩ to R TOP can reduce the number of components. RTOP = (3.3 V / 0.64 V - 1) × 39 kΩ = 162 kΩ ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ ꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏꞏ Equat ion 2 Oscillator Frequency Setting Connecting a 14-kΩ (Typ.) oscillation frequency setting resistor (R RT) between the RT pin and GND can control the oscillation frequency to 2 MHz. The following equation can calculate the variation in resistance of oscillator frequencies. To reduce the variation of oscillator frequencies, it is recommended that a ±1% or less R RT be used. For the SSCG type (R1275S003C), an up-spreading modulation is used (Typ. +8%). RRT [kΩ] = 37773 × fOSC [kHz] ^ (-1.04) R1275S Oscillator Frequency vs Oscillator Frequency Setting Resistance 1600 1700 1800 1900 2000 2100 2200 2300 2400 fOSC (kHz) RRT (kΩ)

NO.EY-371-201203 Soft-start Adjustment The soft-start time is a time between a rising edge (“High” level) of the CE pin and the timing when the output voltage reaches the set output voltage. Connecting a capacitor (CSS) to the CSS pin can adjust the soft-start time (tSS) – provided the internal soft-start time of 500 µs (Typ.) as a lower limit. The adjustable soft-start time and 0.64 V (Typ.). If not required to adjust the soft-start time, set the CSS pin to “Open” to enable the internal soft-start time (tSS1) of 500 µs (Typ.). When a large-capacitance output capacitor is connected, the overcurrent protection may work due to an inflow of large current at startup. Thus, set a longer soft start time to reduce the amount of current and prevent from operating the protections due to the rapid startup. Each of soft-start time (tss1/ tss2) is guaranteed under the co nditions described in the chapter of “Electrical Characteristics”. Soft-start Time Adjustment Capacitor vs Soft-start Time Soft-start Sequence CSS [nF] = (tSS – tVO_S) / 0.64 × 2.0 tSS: Soft-start time (ms) tVO_S: Time period from CE = “High” to VOUT’s rising (Typ. 0.160 ms)

NO.EY-371-201203 Reverse Current Limit The reverse current limit start operating when the reverse current flowing through the low-side transistor exceeds the set reverse current threshold. It turns off the low-side transistor to control the reverse current. The reverse current limit is 2 A (Typ.). This function operates whe n the output voltage is pulled up more than the set output voltage due to short-circuiting. SSCG (Spread Spectrum Clock Generator) The SSCG function works for EMI reduction at the PWM mode. This function is enabled in the R1275S003C. This function make EMI waveforms decrease in amplitude to generate a ramp waveform within approximately +8.0% (Typ.) of the oscillator frequency (fOSC). The modulation cycle is fOSC / 128. SSCG is enabled only when MODE = High. SSCG is not effective when a clock is externally a pplied. The oscillator frequencies are not modulated during the soft-start. Bad Frequency Protection (BADFREQ) If a current equivalent to 4 MHz (Typ.) or more or 125 kHz (Typ.) or less is applied to the RT pin when the oscillator frequency setting resistor (R RT) of the RT pin is in open / short, the R1275S will stop switching to protect the IC and will cause the internal state to transition to its state before the soft-start. The R1275S will restart under the normal control from the state of soft-start when recover after the abnormal condition. BADFREQ Detection/ Release Sequence

NO.EY-371-201203 Forced PWM Mode The R1275S goes into the forced PWM mode by setting the MODE pi n high or applying the external clock to the MODE pin. The forced PWM mode operates at fixed switching frequency even during the light load in order to reduce noise. Therefore, when the output current (I OUT) is less than ∆IL / 2, ILMIN becomes less than "0”. ILMAX ILMIN tON t OFF T=1/fOSC IL IOUT t ΔIL Forced PWM Mode

NO.EY-371-201203

APPLICATION INFORMATION

R1275S Typical Application Circuit1 Recommended Values VOUT CIN [μF] L [μH] COUT [μF] CBST [μF] CVCC [μF] CSPD [pF] RTOP [kΩ] RBOT [kΩ] RRT [kΩ] RC [kΩ] CC [nF] CC2 [pF]

3.3 V 21

(10×2+1) 2.2 48.7 (150+12) 39 14 8.2 4.7 -

5.0 V 21

(10×2+1) 2.2 48.7 (220+47) 39 14 12 4.7 - It is recommended to set 1 kΩ or higher for RCE and between 10 kΩ and 100 kΩ for RPG. Recommended Parts Symbol Capacitance Specification Parts Name CIN 1.0 µF 50 V, 125°C CGA4J3X7R1H105K (TDK) 10 µF 50 V, 125°C CGA6P3X7S1H106K (TDK) COUT 4.7 µF 25 V, 125°C CGA5L1X7R1E475K (TDK) 22 µF 16 V, 125°C CGA6P1X7R1C226M (TDK) CBST 0.1 µF 25 V, 125°C CGA3E2X7R1E104K (TDK) CVCC 1.0 µF 16 V, 125°C CGA3E1X7R1C105K (TDK) Symbol Inductance Specification Parts Name L 2.2 µH 5.5 A CLF7045NIT-2R2-D (TDK) (1) Connecting a Schottky barrier diode between LX and GND can reduce the LX noise and improve the efficiency.

NO.EY-371-201203 Precautions for Selecting External Components Inductor

  • Choose an inductor that has small DC resistance, has sufficie nt allowable current and is hard to cause magnetic saturation. The inductance value must be determined with consideration of load current under the actual condition. If the inductance value of an inductor is ext remely small, the peak current of LX may increase along with the load current. As a result, the current limit circuit may start to operate when the peak current of LX reaches to “LX limit current”. Capacitor
  • Choose a capacitor that has a sufficient margin to the drive voltage ratings with c onsideration of the DC bias characteristics and the temperature characteristics.
  • Ceramic capacitors are recommended for the input capacitor (C IN) and the output capacitor (COUT). The combined use of a ceramic capacitor and an electrolyte capacitor is recommended. Especially, choose the electrolyte capacitor with the lowest possible ESR with consideration of the allowable ripple current rating (I RMS). IRMS can be calculated by the following equation. IRMS ≒ I OUT/ VIN x √{ VOUT x (VIN – VOUT) } The electrolyte capacitor has a characteristic of increasing ESR when it is at a low temperature, so careful consideration is required on the phase characteristics in case of using an electrolyte capacitor for COUT.

NO.EY-371-201203 TECHNICAL NOTES The performance of a power source circuit using this device is highly dependent on a peripheral circuit. A peripheral component or the device mounted on PCB should not ex ceed its rated voltage, rated current or rated power. When designing a peripheral circuit, please be fully aware of the following points. Refer to PCB Layout below.

  • External components must be connected as close as possible to the ICs and make wiring as short as possible. Especially, the capacitor connected in between VIN pin and GND pin must be wiring the shortest. If their impedance is high, internal voltage of the IC may shift by the switching current, and the operating may be unstable. Make the power supply and GND lines sufficient.
  • Place a capacitor (C BST) as close as possible to the LX pin and the BST pin. If contro lling slew rate for EMI, a resistor (RBST) should be in series between the BST pin and the capacitor (CBST).
  • The tab on the bottom of the HSOP-18 package must be connecte d to GND when mounted on the board. To improve thermal dissipation on the multilayer board, set via to release the heat to the other layer in the connecting part of the tab on the bottom.
  • The NC pin must be set to “Open”.
  • The MODE pin requires the high voltages with the high stability when the forced PWM mode (MODE = “High”) is enabled. If the voltage with the high stability cann ot be applied, connection to the VCC pin as “High” level is recommended. Avoid the use of the MODE pin being “GND” or “Open”.
  • If V OUT is a minus potential, the setup cannot occur.
  • Shorten the wiring between the Lx pin and the inductor so that the parasitic capacitance is not provided.
  • It is recommended to place the input capacitor (C IN) on the same side as the IC. If it is placed on the different side as the IC by using via, the noise may be increased due to the parasitic inductance component of via.
  • Feedback the output voltage near the C OUT.
  • Place R TOP, RBOT, and CSPD near FB pin and mount them at a position apart from the inductor, Lx pin, and BST pin to prevent the effect of noise.

NO.EY-371-201203 PCB LAYOUT R1275S003x Layer 1 (Top) Layer 2 Layer 3 Layer 4 (Bottom)

NO.EY-371-201203 TYPICAL CHARACTERISTICS Note: Typical Characteristics are intended to be used as reference data; they are not guaranteed. 1) FB Voltage 2) Oscillator Frequency 0

2 MHz (RT = 14 kΩ)

3) Soft-start Time Internally Fixed Soft-start Time Externally Adjustable Soft-sta rt Time SS = Open) (CSS = 4.7 nF) 4) LX Limit Current 5) VIN Supply Current 1 VIN = 12 V, MODE = High

NO.EY-371-201203 6) UVLO 7) CE Input Voltage 8) Efficiency VOUT = 3.3 V, fOSC = 2 MHz, Ta = 25°C VOUT = 5.0 V, fOSC = 2 MHz, Ta = 25°C 9) Load Transient Response VIN = 12 V, VOUT = 3.3 V, fOSC = 2 MHz, MODE = High, Ta = 25°C

NO.EY-371-201203 10) Load Regulation VOUT = 3.3 V, fOSC = 2 MHz, Ta = 25°C VOUT =5 . 0V , fOSC = 2 MHz, Ta = 25°C 11) Input Voltage Transient Response 12) Line Regulation VIN = 8 V -> 16 V, tr = tf = 100 μs VOUT = 3.3 V, fOSC = 2 MHz, IOUT = 1 A, Ta = 25°C VOUT = 3.3 V, fOSC = 2 MHz IOUT =1 A, Ta = 25°C 13) Transient Voltage Surge V OUT = 3.3 V, fOSC = 2 MHz IOUT = 100 mA, Ta = 25°C

Ver. C i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51-7. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 0.8 mm Copper Ratio Outer Layer (First Layer): Less than 95% of 50 mm Square Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square Through-holes φ 0.3 mm × 21 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Item Measurement Result Power Dissipation 3100 mW Thermal Resistance (θja) θja = 32°C/W Thermal Characterization Parameter (ψjt) ψjt = 8°C/W θja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 500 1000 1500 2000 2500 3000 3500 0 25 50 75 100 125 Power Dissipation PD (mW) Ambient Temperature (°C) 105 3100

PACKAGE DIMENSIONS HSOP-18 i ∗ The tab on the bottom of the package is substrate level (GND). It must be connected to the ground plane on the board. Ver. B

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