HCPL-316J AVAGO | Alldatasheet

Document overview

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Technical content

Features

  • 2.5 A maximum peak output current
  • Drive IGBTs up to IC = 150 A, VCE = 1200 V
  • Optically isolated, FAULT status feedback
  • SO-16 package
  • CMOS/TTL compatible
  • 500 ns max. switching speeds Fault Protected IGBT Gate Drive HCPL-316J Gate Drive MICRO-CONTROLLER M HCPL - 316J –HV +HV ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY 3-PHASE INPUT FAULT Features (continued)
  • “Soft” IGBT turn-off
  • Integrated fail-safe IGBT protection – Desat (VCE) detection – Under Voltage Lock-Out protection (UVLO) with hysteresis
  • User configurable: inverting, noninverting, auto-reset, auto-shutdown
  • Wide operating VCC range: 15 to 30 Volts
  • -40°C to +100°C operating temperature range
  • 15 kV/µs min. Common Mode Rejection (CMR) at VCM = 1500 V
  • Regulatory approvals: UL, CSA, IEC/EN/DIN EN 60747- 5-2 (891 Vpeak Working Voltage) Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product

Figure 1. Typical desaturation protected gate drive circuit, noninverting. HCPL-316J will be the primary source of IGBT protection.

  • THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED.
  1. DESAT terminal monitors the IGBT VCE voltage through
  2. When the voltage on the DESAT terminal exceeds
  3. FAULT output goes low, notifying the microcontroller
  4. Microcontroller takes appropriate action.

Product Overview Description The HCPL-316J is a highly integrated power control de - vice that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit with fault pro- tection and feedback into one SO-16 package. TTL input logic levels allow direct interface with a microcontroller, and an optically isolated power output stage drives IGBTs with power ratings of up to 150 A and 1200 V. A high speed internal optical link minimizes the propaga - tion delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching ap - plications. An output IC provides local protection for the IGBT to prevent damage during overcurrents, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in “watch- dog” circuit monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. Two light emitting diodes and two integrated circuits housed in the same SO -16 package provide the input control circuitry, the output power stage, and two op - tical channels. The input Buffer IC is designed on a bi - polar process, while the output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return opti - cal signal path, as indicated by LED2, transmits the fault status feedback signal. Both optical channels are com - pletely controlled by the input and output ICs respec - tive-ly, making the internal isolation boundary transpar- ent to the microcontroller. Under normal operation, the input gate control signal di- rectly controls the IGBT gate through the isolated output detector IC. LED2 remains off and a fault latch in the in - put buffer IC is disabled. When an IGBT fault is detected, the output detector IC immediately begins a “soft” shut- down sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive overvoltages. Simultaneously, this fault status is transmitted back to the input buffer IC via LED2, where the fault latch disables the gate control input and the ac- tive low fault output alerts the microcontroller. During power-up, the Under Voltage Lockout (UVLO) fea- ture prevents the application of insufficient gate voltage to the IGBT, by forcing the HCPL-316J’s output low. Once the output is in the high state, the DESAT (V CE) detec - tion feature of the HCPL -316J provides IGBT protection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection. SHIELD HCPL-316J functional diagram DESAT FAULT UVLO OUTPUT IC SHIELD INPUT IC RESET 5 FAULT 6 VIN+ VIN- 2 VCC1 VCC2 VOUT VEE 9,10 VE DESAT14 VC VLED2+GND1 154 VLED1- 7 8 VLED1+ LED2 LED1 D R I V E R

Symbol Description Symbol Description VIN+ Noninverting gate drive voltage output (VOUT) VE Common (IGBT emitter) output supply voltage. control input. VIN- Inverting gate drive voltage output VLED2+ LED 2 anode. This pin must be left unconnected (VOUT) control input. for guaranteed data sheet performance. (For optical coupling testing only.) VCC1 Positive input supply voltage. (4.5 V to 5.5 V) DESAT Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 7 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 µs. See Note 25. GND1 Input Ground. VCC2 Positive output supply voltage. RESET FAULT reset input. A logic low input for at least VC Collector of output pull-up triple-darlington 0.1 µs, asynchronously resets FAULT output high transistor. It is connected to VCC2 directly or and enables VIN. Synchronous control of RESET through a resistor to limit output turn-on relative to VIN is required. RESET is not affected current. by UVLO. Asserting RESET while VOUT is high does not affect VOUT. FAULT Fault output. FAULT changes from a high VOUT Gate drive voltage output. impedance state to a logic low output within 5 µs of the voltage on the DESAT pin exceeding an internal reference voltage of 7 V. FAULT output remains low until RESET is brought low. FAULT output is an open collector which allows the FAULT outputs from all HCPL-316Js in a circuit to be connected together in a “wired OR” forming a single fault bus for interfacing directly to the micro-controller. VLED1+ LED 1 anode. This pin must be left unconnected VEE Output supply voltage. for guaranteed data sheet performance. (For optical coupling testing only.) VLED1- LED 1 cathode. This pin must be connected to ground.

Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the HCPL-316J’s white mold compound is normal and does note affect device performance or reliability. Floating Lead Protrusion is 0.25 mm (10 mils) max.

Ordering Information

HCPL-316J is UL Recognized with 3750 Vrms for 1 minute per UL1577. Part number Option Package Surface Mount Tape & Reel IEC/EN/DIN EN 60747-5-2 Quantity RoHS Compliant Non RoHS Compliant HCPL-316J -000E No option SO-16 X X 45 per tube -500E #500 X X X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-316J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-316J to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘ . 0.295 ± 0.010 (7.493 ± 0.254) 10111213141516 87654321 0.018 (0.457) 0.138 ± 0.005 (3.505 ± 0.127) 0.406 ± 0.10 (10.312 ± 0.254) 0.408 ± 0.010 (10.363 ± 0.254) 0.025 MIN. 0.008 ± 0.003 (0.203 ± 0.076) STANDOFF 0.345 ± 0.010 (8.763 ± 0.254) 0–8° 0.018 (0.457) 0.050 (1.270) ALL LEADS TO BE COPLANAR ± 0.002 A 316J YYWW TYPE NUMBER DATE CODE 0.458 (11.63) 0.085 (2.16) 0.025 (0.64) LAND PATTERN RECOMMENDATION

Solder Reflow Thermal Profile Recommended Pb-Free IR Profile Note: Non-halide flux should be used. Note: Non-halide flux should be used. Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, VCC2 - VEE = 30 V, VE - VEE = 0 V, and TA = +25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Note Input-Output Momentary VISO 3750 Vrms RH < 50%, t = 1 min., 1, 2, Withstand Voltage TA = 25°C 3 Resistance (Input-Output) RI-O >109 Ω VI-O = 500 Vdc 3 Capacitance (Input-Output) CI-O 1.3 pF f = 1 MHz Output IC-to-Pins 9 &10 qO9-10 30 °C/W TA = 100°C Thermal Resistance Input IC-to-Pin 4 Thermal Resistance qI4 60 TIME (SECONDS) TEMPERATURE ( °C) 200 100 50 150100 200 250 300 SEC. 50 SEC. SEC. 160 °C 140 °C 150 °C PEAK TEMP. 245 °C PEAK TEMP. 240 °C PEAK TEMP. 230 °C SOLDERING TIME 200 °C PREHEATING TIME 150 °C, 90 + 30 SEC. 2.5 °C ± 0.5 °C/SEC. TIGHT TYPICAL LOOSEROOM TEMPERATURE PREHEATING RATE 3 °C + 1 C/–0.5 °C/SEC. REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC. 217 °C RAMP-DOWN 6°C/SEC. MAX. RAMP-UP 3°C/SEC. MAX. 150 - 200°C 260 +0/-5 °C t 25°C to PEAK 60 to 150 SEC. 20-40 SEC. TIMEWITHIN 5°C of ACTUAL PEAKTEMPERATURE tp ts PREHEAT 60to180SEC. tL TL Tsmax Tsmin Tp TIME TEMPERATURE NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200°C, Tsmin = 150°C

Figure 2. Dependence of safety limiting values on temperature. face mount classification is class A in accordance with CECCOO802. EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.

Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap L(101) 8.3 mm Measured from input terminals to output terminals, (Clearance) shortest distance through air. Minimum External Tracking L(102) 8.3 mm Measured from input terminals to output terminals, (Creepage) shortest distance path along body. Minimum Internal Plastic Gap 0.5 mm Through insulation distance conductor to (Internal Clearance) conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance CTI >175 Volts DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature Ts -55 125 °C Operating Temperature TA -40 100 Output IC Junction Temperature TJ 125 4 Peak Output Current |Io(peak)| 2.5 A 5 Fault Output Current IFAULT 8.0 mA Positive Input Supply Voltage VCC1 -0.5 5.5 Volts Input Pin Voltages VIN+, VIN- and VRESET -0.5 VCC1 Total Output Supply Voltage (VCC2 - VEE) -0.5 35 Negative Output Supply Voltage (VE - VEE) -0.5 15 6 Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE) Gate Drive Output Voltage Vo(peak) -0.5 VCC2 Collector Voltage VC VEE + 5 V VCC2 DESAT Voltage VDESAT VE VE + 10 Output IC Power Dissipation PO 600 mW 4 Input IC Power Dissipation PI 150 Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Operating Temperature TA -40 +100 °C Input Supply Voltage VCC1 4.5 5.5 Volts 28 Total Output Supply Voltage (VCC2 - VEE) 15 30 9 Negative Output Supply Voltage (VE - VEE) 0 15 6 Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE) Collector Voltage VC VEE + 6 VCC2

Electrical Specifications (DC) Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Logic Low Input Voltages VIN+L, VIN-L, 0.8 V VRESETL Logic High Input Voltages VIN+H, VIN-H, 2.0 VRESETH Logic Low Input Currents IIN+L, IIN-L, -0.5 -0.4 mA VIN = 0.4 V IRESETL FAULT Logic Low Output IFAULTL 5.0 12 VFAULT = 0.4 V 30 Current FAULT Logic High Output IFAULTH -40 µA VFAULT = VCC1 31 Current High Level Output Current IOH -0.5 -1.5 A VOUT = VCC2 - 4 V 3, 8, 7 -2.0 VOUT = VCC2 - 15 V 32 5 Low Level Output Current IOL 0.5 2.3 VOUT = VEE + 2.5 V 4, 9, 7

2.0 VOUT = VEE + 15 V 33 5

Low Level Output Current IOLF 90 160 230 mA VOUT - VEE = 14 V 5, 34 8 During Fault Condition High Level Output Voltage VOH VC - 3.5 VC - 2.5 VC - 1.5 V IOUT = -100 mA 6, 8, 9, 10, 11 VC -2.9 VC - 2.0 VC - 1.2 IOUT = -650 µA 35 VC IOUT = 0 Low Level Output Voltage VOL 0.17 0.5 IOUT = 100 mA 7, 9, 26 High Level Input Supply ICC1H 17 22 mA VIN+ = VCC1 = 5.5 V, 10, 37 Current VIN- = 0 V 38 Low Level Input Supply ICCIL 6 11 VIN+ = VIN- = 0 V, Current VCC1 = 5.5 V Output Supply Current ICC2 2.5 5 VOUT open 11, 12, 11 39, 40 Low Level Collector Current ICL 0.3 1.0 IOUT = 0 15, 59 27 High Level Collector Current ICH 0.3 1.3 IOUT = 0 15, 58 27 1.8 3.0 IOUT = -650 µA 15, 57 VE Low Level Supply IEL -0.7 -0.4 0 14, 61 Current VE High Level Supply IEH -0.5 -0.14 0 14, 40 25 Current Blanking Capacitor ICHG -0.13 -0.25 -0.33 VDESAT = 0 - 6 V 13, 41 11, 12 Charging Current -0.18 -0.25 -0.33 VDESAT = 0 - 6 V, TA = 25°C - 100°C Blanking Capacitor IDSCHG 10 50 VDESAT = 7 V 42 Discharge Current UVLO Threshold VUVLO+ 11.6 12.3 13.5 V VOUT > 5 V 43 9, 11, 13 VUVLO- 11.1 12.4 VOUT < 5 V 9, 11, 14 UVLO Hysteresis (VUVLO+ - 0.4 1.2 VUVLO-) DESAT Threshold VDESAT 6.5 7.0 7.5 VCC2 - VE > VUVLO- 16, 44 11

Switching Specifications (AC) Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note VIN to High Level Output tPLH 0.10 0.30 0.50 µs Rg = 10 Ω 17,18,19, 15 Propagation Delay Time Cg = 10 nF, 20,21,22, VIN to Low Level Output tPHL 0.10 0.32 0.50 f = 10 kHz, 45,54,55 Propagation Delay Time Duty Cycle = 50% Pulse Width Distortion PWD -0.30 0.02 0.30 16,17 Propagation Delay Difference (tPHL - tPLH) -0.35 0.35 17,18 Between Any Two Parts PDD 10% to 90% Rise Time tr 0.1 45 90% to 10% Fall Time tf 0.1 DESAT Sense to 90% VOUT Delay tDESAT(90%) 0.3 0.5 Rg = 10 Ω, 23,56 19 Cg = 10 nF DESAT Sense to 10% VOUT Delay tDESAT(10%) 2.0 3.0 VCC2 - VEE = 30 V 24,28, 46,56 DESAT Sense to Low Level FAULT tDESAT(FAULT) 1.8 5 25,47, 20 Signal Delay 56 DESAT Sense to DESAT Low tDESAT(LOW) 0.25 56 21 Propagation Delay RESET to High Level FAULT Signal tRESET(FAULT) 3 7 20 26,27, 22 Delay 56 RESET Signal Pulse Width PWRESET 0.1 UVLO to VOUT High Delay tUVLO ON 4.0 VCC2 = 1.0 ms 49 13 UVLO to VOUT Low Delay tUVLO OFF 6.0 ramp 14 Output High Level Common Mode |CMH| 15 30 kV/µs TA = 25°C, 50,51, 23 Transient Immunity VCM = 1500 V, 52,53 VCC2 = 30 V Output Low Level Common Mode |CML| 15 30 TA = 25°C, 24 Transient Immunity VCM = 1500 V, VCC2 = 30 V

Notes: 1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detec- tion current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insu- lation Characteristic Table, if applicable. 2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table. 3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 4. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction tem- perature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating. 5. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO compensates for increased IOPEAK due to changes in VOL over temperature. 6. This supply is optional. Required only when negative gate drive is implemented. 7. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%. 8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details. 9. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VU- VLO+ threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero units. 10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 11. Once VOUT of the HCPL-316J is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the HCPL-316J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection. 12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details. 13. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE. 14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE. 15. This load condition approximates the gate load of a 1200 V/75A IGBT. 16. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit. 17. As measured from VIN+, VIN- to VOUT. 18. The difference between tPHL and tPLH between any two HCPL-316J parts under the same test conditions. 19. Supply Voltage Dependent. 20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. 21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. 22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 µs is the guaran- teed minimum FAULT signal pulse width when the HCPL-316J is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the end of this data sheet for further details. 23. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3K Ω pull-up resistor is needed in fault detection mode. 24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the 25. Does not include LED2 current during fault or blanking capacitor discharge current. 26. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull- down resistor is not used. 27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE. 28. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.

Figure 49. UVLO delay test circuit. Figure 50. CMR test circuit, LED2 off. Figure 51. CMR test circuit, LED2 on. Figure 52. CMR test circuit, LED1 off. Figure 53. CMR test circuit, LED1 on.

8 V+–

Figure 48. tRESET(FAULT) test circuit.

Figure 57. ICH test circuit. Figure 58. ICH test circuit. Figure 59. ICL test circuit. Figure 60. IEH test circuit. Figure 61. IEL test circuit.

30 V650 µA

Typical Application/Operation Introduction to Fault Detection and Protection The power stage of a typical three phase inverter is sus - ceptible to several types of failures, most of which are potentially destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply short circuits due to user misconnect or bad wiring, control signal failures due to noise or com- putational errors, overload conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions, the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become damaged when the current load approaches the saturation cur - rent of the device, and the collector to emitter voltage rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turn-off the overcurrents during a fault condition. A circuit providing fast local fault detection and shut - down is an ideal solution, but the number of required components, board space consumed, cost, and complex- ity have until now limited its use to high performance drives. The features which this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. Applications Information The HCPL -316J satisfies these cri - teria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and an optically isolated fault status feedback sig- nal into a single 16-pin surface mount package. The fault detection method, which is adopted in the HCPL-316J, is to monitor the saturation (collector) volt - age of the IGBT and to trigger a local fault shutdown se - quence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply dis - abled to prevent false ‘fault’ signals. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the HCPL -316J limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissi - pation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly- conser - vative overcurrent threshold is not needed to protect the IGBT. Recommended Application Circuit The HCPL -316J has both inverting and non-inverting gate control inputs, an active low reset input, and an open collector fault output suitable for wired ‘OR’ appli- cations. The recommended application circuit shown in Figure 62 illustrates a typical gate drive implementation using the HCPL-316J. The four supply bypass capacitors (0.1 µF) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charg - ing currents, a low current (5 mA) power supply suffices. The desat diode and 100 pF capacitor are the necessary external components for the fault detection circuitry. The gate resistor (10 Ω) serves to limit gate charge cur - rent and indirectly control the IGBT collector voltage rise and fall times. The open collector fault output has a passive 3.3 kΩ pull-up resistor and a 330 pF filtering capacitor. A 47 kΩ pulldown resistor on VOUT provides a more predictable high level output voltage (VOH). In this application, the IGBT gate driver will shut down when a fault is detected and will not resume switching until the microcontroller applies a reset signal.

Slow IGBT Gate Discharge During Fault Condition When a desaturation fault is detected, a weak pull-down device in the HCPL-316J output drive stage will turn on to ‘softly’ turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below VEE + 2 Volts, at which time the large pull down device clamps the IGBT gate to VEE. DESAT Fault Detection Blanking Time The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT ca- pacitor. The nominal blanking time is calculated in terms of external capacitance (C BLANK), FAULT threshold volt - age (V DESAT), and DESAT charge current (I CHG) as t BLANK = CBLANK x VDESAT / ICHG. The nominal blanking time with the recommended 100 pF capacitor is 100 pF * 7 V / 250 µA = 2.8 µsec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time also represents the longest time it will take for the HCPL- 316J to respond to a DESAT fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut- down sequence will begin after approximately 3 µsec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. The recommended 100 pF capaci - tor should provide adequate blanking as well as fault response times for most applications. Under Voltage Lockout The HCPL-316J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the HCPL-316J output low during power-up. IGBTs typically require gate voltages of 15 V to achieve their rated V CE(ON) voltage. At gate voltages below 13 V typically, their on-voltage increases dramatically, especially at higher currents. At very low gate voltages (below 10 V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever insufficient operating supply (V CC2) is applied. Once V CC2 exceeds VUVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. As VCC2 is increased from 0 V (at some level below VUVLO+), first the DESAT protection circuitry becomes active. As V CC2 is further increased (above VUVLO+), the UVLO clamp is released. Before the time the UVLO clamp is released, the DESAT protection is already active. Therefore, the UVLO and DESAT FAULT DETECTION features work together to provide seamless protection regardless of supply voltage (VCC2).

Figure 64. Behavioral circuit schematic. latched in the high state until the signal LED turns off.

static current of several 650 µA while the output is high. formula, Rpull-down = [VCC2-3 * (VBE)] / 650 µA. threshold or the DESAT blanking time. noise margins at the specified CMR value of 15 kV/µs. put delay when a desaturation condition is detected. requires a pull-up resistor to provide a high-level signal.

0.5 A, the value of R C can be estimated in the following

information on calculating value of RG. matically resets for every VIN- input). Figure 73c. Safe hardware reset for inverting input configuration. Figure 74. Use of RC to further limit ION,PEAK.

Figure 75. Current buffer for increased drive current. within the maximum allowable power rating.

  1. Calculate the minimum desired RG;

pair is appropriate for currents up to 15 A maximum. maximum reverse-voltage rating may be chosen.

15 V -5 V

  1. Calculate total power dissipation in the part referring
  2. Compare the input and output power dissipation

Figure 78. HCPL-316J thermal model. decrease by a factor of 2 depending on PCB layout and/or airflow. are considered negligible and not modeled here. and airflow, their exact number may not be available. on the pin at the HCPL-316J package edge. the thermal model shown in Figure 77 below. air flow where the estimated q4A and q9,10A are 100°C/W. more accurate estimate of the junction temperatures.

parasitic coupling that will degrade CMR performance. pate the majority of heat generated through these pins. timate junction temperature. Figure 79. Recommended layout(s).

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Figure 80. Minimum LED Skew for Zero Dead Time. Figure 81. Waveforms for Dead Time Calculation. side power transistors (Q1 and Q2 in Figure 62) are off. strophic condition that must be prevented. ing temperature range of -40°C to 100°C. and are switching identical IGBTs.