CH5101A

CH5101A ETC1

Document overview

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Technical content

Features

• 352 x 288 monochrome active pixel array, 1/3 inch lens format ¥
• Programmable formats CIF 352x288, QCIF 176x144, CCIR601 704x288
• Digital output CCIR601 4:2:2 (8-bit)
• Multidimensional automatic shutter control
• Below 1 LUX sensitivity
• Programmable I 2 C Serial bus control : - Frame rate: 30fps-1fps in eight steps - Gamma correction - Shutter speed - Analog gain - 16 backlight compensation zones - Black clamp level - Power down modes
• Stand-alone 25fps PAL and 30fps NTSC operation with all automatic features
• Single crystal operation: Video timing on-chip
• Single 5V power supply
• Less than 0.5 watt power dissipation

Description

The CH5101 is a single chip active pixel CMOS monochrome video camera with digital video output in several formats. Using sophisticated noise correction circuitry to minimize fixed pattern noise and dark current effects, the CH5101 provides a supurb quality picture in a low cost device. The CH5101 uses a proprietary autoshutter algorithm to dynamically control the shutter time, analog gain, and black clamp level, providing optimum picture and contrast under all lighting conditions. The CH5101 also incorporates extensive on-chip programmable digital signal processing to maximize the usefulness of the device in processor driven applications. This includes 16 programmable zones for backlight compensation, allowing the user to adjust the image to their unique lighting environment. Additionally, at power-up the backlight compensation zone, power-up condition, and direct A/D output modes are selectable without IIC control by using the PUD pins. Requiring a minimum of parts for operation, the CH5101 provides a low cost camera for the next generation videophone, toy, and surveillance products. ¥ Patent number x,xxx,xxx patents pending Figure 1: Block Diagram Shutter Control Gamma Correct 2-D LPFBlack Clamp Photocell Array352 Columns 288 Rows R O W T I M I N G Row Decode Gain TOUT/TOUTB OVR I C BUS 2 SD SC AS Output Format Y[7:0] A/D Timing Mode Control HREF PDP* HS* VS* CLKOUT Reset* XI/Fin XO PUD[6:0]

2 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A Figure 2: 52-Pin PQFP 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 DVDD SC SD DGND RESET* AS DVDD CMB2 AVDD TOUTB TOUT AGND VRS DGND PUD0* PUD1* PUD2* PUD3* PUD4* PUD5* PUD6 NC NC DVDD CLKOUT DVDD OVR HREF DGND VS* HS* AVDD ARF ARF2 AGND CRF VREF AVDD XI/FIN XO AGND DGND PDP* DVDD Image Array

201-0000-033 Rev 1.0, 6/2/99 3 Figure 3: 52 Contact Ceramic LCC (Top View) .600 in Sq Image Array 1mm VRS AGND TOUT TOUTB AVDD CMB2 DVDD AS RESET* DGND AGND DGND PDP* DVDD XO XI/FIN AVDD VREF CRF AGND ARF2 ARF AVDD PUD6 PUD4* DVDD CLKOUT DGND PUD0* PUD1* PUD2* PUD3* PUD5* NC NC SD SC DVDD OVR HREF DVDD HS* VS* DGND

4 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A Figure 4: CH5101 Array Image Offset Image Array 1301 um 60 um CMOS Die Package Centerline Package Centerline 3670.3 um 4906.7 um

Table 1. Pin Descriptions Note: Pin numbers in parenthesis ( ) are for 52 pin PQFP Provides the luminance data of the digital video output. These pins supply the 5V power to the digital section of CH5101. pins MUST be connected to the system ground. M0, ADDO, PD, ASW[3:0]. Attach 100K Ohms to DGND to pull low. Outputs a vertical sync pulse. Outputs a horizontal sync pulse. output from the device, and low otherwise. This pin selects the IIC address for the device. be HIGH during reset for proper initialization. connected to XI/FIN as an alternative.

Supplies the 5V power to the analog section of the CH5101. should be connected between VREF and AGND. For test purposes only. Should be NC. be connected between VRS and AGND.

201-0000-033 Rev 1.0, 6/2/99 7 Functional Description The CH5101 accepts a light input to a photosensitive array, and produces a digital video stream in response. The internal functions performed are:

• Scanning of the photodiode array into a serial data stream.
• Programmable gain sample and hold with programmable offset.
• Digitization of data stream.
• Programmable gamma correction.
• Interpolate/Decimate data to desired resolution
• Formatting of the data stream for the desired type of output.
• Automatic Shutter, Gain and Black Setting.
• Timing signal generation.
• Bus control.
• Power up control of key register bits Scanning of the photodiode array: The CH5101 serializes the data captured in the photo array, and outputs one pixel of data each clock period. The first row is output a programmable number of lines after the leading edge of the vertical sync output. After the entire row has been output, the next row will be addressed and output. Correlated double sampling techniques are used during readout to reduce fixed pattern noise. After this transfer is complete, pixel data is serially sent to the programmable gain amplifier and then to an A/D converter. Programmable gain sample and hold: The programmable gain is divided into two sections. The first gain block is controlled by PGSH[2:0] and the sec- ond by the ADFS control. ADFS can be treated as the MSB of the gain control, and a plot of gain versus control set- ting is shown below. The programmable gain section also provides a bias adjustment, under the control of the an chip DAC. When the ASBE bit is a one (default) this DAC value is determined automatically, via a feedback loop which monitors the A/D output signal. When the ASBE bit is a zero, the DAC can be controlled via BCLMP[7:0]. 0 2 4 6 8 10 12 14 160 GaindB n Gain n

8 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A A/D Conversion: The data out of the programmable sample and hold is input to an 8-bit A/D. The output of the A/D is sent to the datapath section, and can alternatively be sent directly to the Y[7:0] pins. The A/D has an over-range output which is available as an external pin. Programmable Gamma correction: The monochrome signals are next applied to a gamma correction block with selectable gamma settings of 1.0, 1.6 and 2.2, controlled via GAM[1:0]. Interpolate/Decimate data to desired resolution: The output resolution is determined by the mode register bits M[2:0]. When a CCIR601 mode is selected (M[2:0] = 4,5), a signal compatible with Chrontel's CH7202 input will be gener- ated. This entails interpolating the luminance signal by a factor of two, and selecting the 8-bit output mode (register 00h, bit 0). The value of 128 is substituted for chrominance data (no color). When a CIF output is selected (M[2:0] = 1), the value of 128 is substituted for chrominance data. When QCIF output is selected (M[2:0] = 3), the Y resolution will be decimated by a factor of two in both horizontal and vertical directions. This requires bandlimiting the Y data, decimating in the horizontal direction. The Y data is not decimated in the vertical direction.Automatic Shutter, Gain and Black Setting: Automatic Shutter, Gain and Black Setting: The CH5101 contains circuitry to automatically adjust the shutter (ESLE, ESLH and ESLL), programmable gain (PGSH[2:0]) and black level (BCLMP[7:0]. These feedback loops are independently controlled by the three control bits Auto-Shutter Shutter Enable (ASSE), Auto-Shutter Gain Enable (ASGE) and Auto-Shutter Black Enable (ASBE). When each of these loops is enabled (default), a read to the corresponding shutter, gain or black level register will result is a readout of the control signal the algorithm has determined to be correct. Data can continue to be written to the control registers, but will not have an effect until the automatic feedback control is disabled. The feedback loops will attempt to force a percentage of the image (controlled by ASBC[4:0] and ASBT[2:0]) to black, and a certain percentage of the image (controlled by ASWC[7:0]) inside the selectable window to white. This will create an output image which maximizes the dynamic range of the signal, without creating overflow or underflow problems within the A/D or the datapath. Timing signal generation: The CH5101 generates all required internal and external timing signals. The following timing signals are output by the CH5101:

• Clock out (CLKOUT) - This output is used to latch the outputs of the Y]7:0], HS*, VS* and HREF.
• Horizontal Sync (HS*) - The horizontal sync output is used to determine the start of a new line. Polarity is selectable via control bit HSP.
• Vertical Sync (VS*) - The vertical sync output is used to determine the start of a new frame. Polarity is selectable via control bit VSP.
• Horizontal Reference (HREF) - The horizontal reference is high when active data is output from the CH5101. The following timing parameters are programmable:
• Shutter - This control is divided among three registers, Electronic Shutter Length Extended (ESLE) , Electronic Shutter Length High (ESLH) and Electronic Shutter Length Low (ESLL). The control range is from ~1uS, to just under the frame duration.
• Frame rate - In non-CCIR601 modes, the frame rate is selectable via the FR register. The CH5101 has two methods for adjusting the frame rate of the device.

• Horizontal start - In non-CCIR601 modes, the delay between the HS* output and the output of active data from the CH5101 is programmable via the HS register. The polarity of this output is programmable.
• Vertical start - In non-CCIR601 modes, the delay between the VS* output and the output of active data from the CH5101 is programmable via the VS register. The polarity of this output is programmable.
• Frame rate adjustment method — The CH5101 has two methods for adjusting the frame rate of the device. The first method is to add additional black lines to each frame after reading out the active data. The second method is to have each frame remain a constant number of lines long, and have each line contain a variable number of blank pixels after reading out the active data. In this mode, all clock signals are 1/2 of the normal rate.
• Auto shutter speed — The auto-shutter loop speed can be controlled via ASSPD[2:0]. Bus control: The CH5101 is controlled via a 2 pin serial interface. The description of this interface, and all registers accessible via the interface is described later in the data sheet. Power up control: Seven bits within the CH5101 register map can have their default value determined at the time of power-up, or when the Reset pin is exercised. This is accomplished by using a high valued pull-down resistor on the PUD[6:0] pins. These pins are pulled high by an internal high impedance pull-up device. This pull-up can be overridden by con- necting a 100K ohm resistor externally to ground. After three frames, the level at the PUD[6:0] pins is latched, and seven register bits are set or cleared depending upon the corresponding pin's level. The PUD[6:0] pins functions are then returned to outputs of the chroma data. The power-up control affects the following register bits:

Table 2. Power Up Default Control The Mode[0] bit can be used to select between NTSC or PAL output at power up.

10 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A I2 C Port Operation The CH5101 contains a standard I 2 C control port, through which the control registers can be written and read. This port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to the SDB and SCB buses as shown in Figure5 . The Serial Clock line (SC) is input only and is driven by the output buffer of the master device. The CH5101 acts as a slave and generation of clock signals on the bus is always the responsibility of the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open- collector to perform the wired-AND function. Data on the bus can be transferred up to 400kbit/s according to I 2 C specifications. However, in direct connections to the bus master device, the CH5101 can operate at transfer rates up to 5 MHz. Figure 5: Connection of Devices to the Bus Electrical Characteristics for Bus Devices The electrical specifications of the bus devices ’ inputs and outputs and the characteristics of the bus lines connected to them are shown in Figure5 . A pullup resistor (R P ) must be connected to a 5V ± 10% supply. The CH5101 is a device with input levels related to V DD . Maximum and minimum values of pullup resistor (R P ) The value of R P depends on the following parameters:

• Supply voltage
• Bus capacitance
• Number of devices connected (input current + leakage current = I input ) The supply voltage limits the minimum value of resistor R P due to the specified minimum sink current of 3mA at VOL max = 0.4 V for the output stages: R P >= (V DD – 0.4) / 3 (R P in k Ω) The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum value of R P due to the specified rise time. The equation for RP is shown below: R P >= 10 3 /C (where: R P is in k Ω and C, the total capacitance, is in pF) The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 µA. Due to the desired noise margin of 0.2V DD for the HIGH level, this input current limits the maximum value of R P . SCLK IN2 DATA IN2 DATAN2 OUT SCB (Serial Clock Bus) SDB (Serial Data Bus) +VDD R P SLAVE SCLK IN1 DATA IN1 DATAN2 OUT SLAVE SCLK OUT FROM MASTER DATA IN MASTER DATAN2 OUT MASTER BUS MASTER SC SD

register address prior to each read or write from that location (i.e., transfers alternate between address and data). transfer protocol is shown in Figure6 and described below.

1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the

START condition. Transitions of address and data bits can only occur while SC is low.

1. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
2. Upon receiving the first START condition, the CH5101 expects a Device Address Byte (DAB) from the

determined by the state of the ADDR pin (see Table 1 for details).

1. After the DAB is received, the CH5101 expects a Register Address Byte (RAB) from the master. The

format of the RAB is shown in the RAB data format below (note that B7 is not used). R/W of registers 1: Auto-Increment enabled (auto-increment mode). Table 3. Device Address Byte (DAB)

be serially read), the address register will automatically be incremented by one. However, for the first read after an RAB, the address register will not be changed. 0: Auto-increment disabled (alternating mode). be serially read), the address register will remain unchanged. AR[5:0] Specifies the Address of the Register to be Accessed . follows, is directed to the register specified by the content stored in the address register. Table 4. Register Address Byte (RAB)

201-0000-033 Rev 1.0, 6/2/99 15 Table 5. Register Descriptions Mode/Output Format MOF 00 0000 1011 Selects the mode (CCIR601, CIF or QCIF) and output format. Frame Rate FR 01 0010 x000 Sets the frame rate of the output signal. The four MSBs contain the revision number. Horizontal Start HS 02 xx11 1101 Sets the horizontal start position of the active output pixel in relationship to the HSYNC signal. Vertical Start VS 03 x0x1 0101 Used to set the vertical start position of the active output pixel in relationship to the VSYNC signal. Electronic Shutter Length High Byte ESLH 04 1111 0000 Used in conjunction with ESLP register to specify the duration of the electronic shutter. Electronic Shutter Length Low Byte ESLL 05 0000 0000 Used in conjunction with ESLL register to specify the duration of the electronic shutter. RESERVED 06 - 16 Reserved Do not use PSH Gain Gamma PSHG 17 0001 1001 Selects the gain of the programmable sample and hold. 000 = 0dB gain, 111 = 14dB gain. Clamp Level BCLMP 18 1000 0000 Selects the level that the black level clamp adjust to during dark pixel. Miscellaneous MISC 19 1000 0000 7,6,5: Reserved 4: Power Down 3: V Sync. Polarity 2: H Sync. Polarity 1,0: Border Color Device ID DID 1A 0010 0000 The four MSBs hold the device ID. The four LSBs hold the version ID. Test Register TST 1B 0000 0000 Test Register Test Memory TM 1C 0000 0000 Test Register Auto-Shutter Enable ASE 1D 1110 0100 Enables and controls the following autoshutter algorithm parameters: 7: Enables the AS to control the shutter 6: Enables the AS to control black level 5: Enables the AS to control programmable gain. 4,3: Reserved 2-0: Determines the threshold of the shutter gain setting to enable black level changes.

16 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A Register Symbol Address (Hex) Default Value PUD[3:0] Used to select the autoshutter window, display window, and select input data to algorithm: 6: Autoshutter max input enable 5: Autoshutter A/D or CSC select 4: Window Display 3-0: Window Select Auto-Shutter Black Count Threshold Value ASBC 1F 1111 1001 Determines the threshold that compares the Black Sense value. Auto-Shutter White Count Threshold Value ASWC 20 1000 0000 Determines the threshold that compares the White Sense value. Extended Shutter Bits ESLE 21 xxx0 0000 ESLE (MSB) along with ESLH and ESLL form the overall Shutter Length Control Register. Miscellaneous 2 MISC2 22 0001 1001 Determines Master clock frequency, CLKOUT control, and A/D Direct Output mode Miscellaneous 3 MISC3 23 0011 1001 Determines internal clock delay and A/D full scale value Power Down Register PD 24 xxx1 0000 This register controls the following functions: 4: ResetB 3: High Light Intensity Enable 2-0: Reserved. Address Register AR 26 0000 0000 Holds the address of the IIC register being accessed Table 6. Register Map

00 CIF2 ELFA CVL CHL M2 M1 M0 OF

01 RNUM3 RNUM2 RNUM1 RNUM0 FR2 FR1 FR0

02 HS5 HS4 HS3 HS2 HS1 HS0

03 YDEL VS4 VS3 VS2 VS1 VS0

04 ESLH7 ESLH6 ESLH5 ESLH4 ESLH3 ESLH2 ESLH1 ESLH0

05 ESLL7 ESLL6 ESLL5 ESLL4 ESLL3 ESLL2 ESLL1 ESLL0

17 Reserved Reserved GAM1 GAM0 Reserved PSHG2 PSHG1 PSHG0

18 BCLMP7 BCLMP6 BCLMP5 BCLMP4 BCLMP3 BCLMP2 BCLMP1 BCLMP0

19 Reserved Reserved DVDD PD VSP HSP BDR1 BDR0

20 ASWC7 ASWC6 ASWC5 ASWC4 ASWC3 ASWC2 ASWC1 ASWC0

21 ESLE4 ESLE3 ESLE2 ESLE1 ESLE0

22 RENB ADD0 CLKOUTP DVC MCF

23 ADFSR CLKDLY3 CLKDLY2 CLKDLY1 CLKDLY0

24 ResetB Reserved PD2 PD1 PD0

201-0000-033 Rev 1.0, 6/2/99 17 Mode / Output Format Register Symbol: MOF Address: 00h Bits: 8 Register MOF determines the operating mode of the IC and the output data format. When bit 0 of register OF is low, data will be output in 16-bit mode. When OF is high, data will be time multiplexed and output on the 8-bit bus Y[7:0]. In the tables below, Y0 is the first pixel generated from the array on a given line, Y1 is the second pixel on that line, etc. In CCIR modes, Y0i, Y1i data are the pixels interpolated between the Y0 and Y1, and Y1 and Y2 samples. For each of the possible modes, the format of the output data is shown below. The total amount of time shown for each table is 24 cycles of MCLK when ELFA=0 and 48 cycles of MCLK when ELFA=1. The line number in each table refers to which active video line is being output. M[2:0] = 0 or 1, OF = 0, CIF2 = 0 (2 line pattern, CLKOUT = 6.75MHz (ELFA=0) or 3.375MHz (ELFA=1)) M[2:0] = 0 or 1, OF = 1, CIF2 = 0 (2 line pattern, CLKOUT = 13.5 MHz (ELFA=0) or 6.75MHz (ELFA=1)) M[2:0] = 0 or 1, OF = 0, CIF2 = 1 (1 line pattern, CLKOUT = 6.75MHz (ELFA=0) or 3.375MHz (ELFA=1)) M[2:0] = 0 or 1, OF = 1, CIF2 = 1 (1 line pattern, CLKOUT = 13.5 MHz (ELFA=0) or 6.75MHz (ELFA=1) ) M[2:0] 2 or 3, OF = 0 CIF2 = 0 (4 line pattern, CLKOUT = 6.75MHz (ELFA=0) or 3.375MHZ (ELFA=1)) BIT: 7 6 5 4 3 2 1 0 SYMBOL: CIF2 ELFA CVL CHL M2 M1 M0 OF TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 0 0 1 0 PUD6 1 Line CLKOUT 1 2 3 4 5 6

1 Y[7:0] Y0 Y1 Y2 Y3 Y4 Y5

2 Y[7:0] Y0 Y1 Y2 Y3 Y4 Y5

Line CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12

1 Y[7:0] 128 Y0 128 Y1 128 Y2 128 Y3 128 Y4 128 Y5

2 Y[7:0] 128 Y0 128 Y1 128 Y2 128 Y3 128 Y4 128 Y5

Line CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12

18 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A M[2:0] = 2 or 3, OF = 1 CIF2 = 0 (4 line pattern, CLKOUT = 13.5 MHz (ELFA=0) or 6.75MHZ (ELFA=1)) M[2:0] = 2 or 3, OF = 0 CIF2 = 1 (2 line pattern, CLKOUT = 6.75MHz (ELFA=0) or 3.375MHZ (ELFA=1)) M[2:0] = 2 or 3, OF = 1 CIF2 = 1 (2 line pattern, CLKOUT = 13.5 MHz (ELFA=0) or 6.75MHZ (ELFA=1)) M[2:0] = 4 or 5, OF = 0 (repeats pattern every line, CLKOUT =13.5 MHz) M[2:0] = 4 or 5, OF = 1 (repeats pattern every line, CLKOUT = 27MHz) Line CLKOUT 1 2 3 4 5 6

1 Y[7:0] Y0 Y0 Y2 Y2 Y4 Y4

2 Y[7:0] 16 16 16 16 16 16

3 Y[7:0] Y0 Y0 Y2 Y2 Y4 Y4

4 Y[7:0] 16 16 16 16 16 16

Line CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12

1 Y[7:0] 128 128 Y0 Y0 128 128 Y2 Y2 128 128 Y4 Y4

2 Y[7:0] 128 128 16 16 128 128 16 16 128 128 16 16

3 Y[7:0] 128 128 Y0 Y0 128 128 Y2 Y2 128 128 Y4 Y4

4 Y[7:0] 128 128 16 16 128 128 16 16 128 128 16 16

Line CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12 Line CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12

1 Y[7:0] Y0 Y0i Y1 Y1i Y2 Y2i Y3 Y3i Y4 Y4i Y5 Y5i

CIF2 bit is high, the CVL bit is ignored, and the chrominance signal is output on every line that has luminance.

1 Y[7:0] 1

Table 7. Operating Modes

can be selected in this mode, each one 289 lines. some of the key parameters are shown in Tables 8 & 9 . Table 8. Operating Modes For 27 MHz MCLK

Bits 7-4 (RNUM#) of the FR register contain the revision number of the CH5101 device. These bits are read only. (MCE=0) should be selected. All frame rates will be scaled by the value of 30/24. when ELFA=1. When M[2:0] = 4 or 5, this register is ignored and the timing below is followed assuming OF = 0. Table 9. Operating modes for 24 MHz MCLK

22 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A Vertical Start Register Symbol: VS Address: 03h Bits: 6 Register VS determines the number of lines between the leading edge of V Sync and the first active line to be output on the Y[7:0] and C[7:0] pins. The number is in units of lines; the range is 0 to 31 lines. When ELFA = 1, this register is ignored, and there is always a one line delay between the leading edge of vertical sync and the first line with active video. The YDEL (bit 6) controls the delay in the luma processing path. The value should match the setting of CHL. Electronic Shutter Length High Byte Symbol: ESLH Address: 04h Bits: 8 The ESLH register, combined with the ESLE and ESLL registers determine the length of the electronic shutter. Electronic Shutter Length Low Byte Symbol: ESLL Address: 05h Bits: 8 Registers ESLE, ESLH and ESLL specify the duration of the electronic shutter. These 21 bits are concatenated into a single 21-bit word ({ESLE,ESLH,ESLL}) whose value is multiplied by 8. The shutter is enabled for this number of MCLKs. The duration of the shutter can, therefore, be determined from the equation (8*(65536*ESLE + 256*ESLH + ESLL))/MCLK. The range is from 0mS to 699mS, but is limited to a lower value in some frame rates (see Frame Rate Register description). When the autoshutter algorithm is controlling the shutter value and this register is read out, the autoshutter generated value is read instead of the actual I 2 C register content. BIT: 7 6 5 4 3 2 1 0 SYMBOL: YDEL VS4 VS3 VS2 VS1 VS0 TYPE: R/W R/W R/W R/W R/W R/W DEFAULT: 0 1 0 1 0 1 BIT: 7 6 5 4 3 2 1 0 SYMBOL: ESLH7 ESLH6 ESLH5 ESLH4 ESLH3 ESLH2 ESLH1 ESLH0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 1 1 1 1 0 0 0 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: ESLL7 ESLL6 ESLL5 ESLL4 ESLL3 ESLL2 ESLL1 ESLL0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 0 0 0 0 0 0

Table 10. Gamma Correction

Bits 2 and 3 (HSP and VSP) of the MISC register control the polarity of the H and V sync signals. mode according to the user inputs. The default value of this bit is set using the PUD5 input. Bit 5 (DVDD) of the MISC register is a reserved bit for memory control. Register DID is a read only register which holds the device ID number of the CH5101. Table 11. Border Colors

201-0000-033 Rev 1.0, 6/2/99 25 Auto-Shutter Enable Symbol: ASE Address: 1Dh Bits: 8 Bits 0-2 of the ASE register control the speed of the autoshutter loop. Values 0 through 4 are valid. Bits 3 - 4 of the ASE register are reserved, and should be left at their default value. Bit 5 of the ASE register enables the autoshutter algorithm to adjust the gain of the programmable sample and hold. A 1 in this location allows the autoshutter algorithm to control this gain. A zero in this location disables the autoshutter algorithm from controlling this value, and allows bits 2-0 of register PSHG (17H) to control the gain. Bit 6 of the ASE register enables the autoshutter algorithm to adjust the black level (bias) of the readout signal prior to A/D conversion. A 1 in this location allows the autoshutter algorithm to control the black level. A 0 in this location disables the autoshutter algorithm from controlling this value and allows bits 7-0 of register BCLMP (18H) to control the black level. Bit 7 of the ASE register enables the autoshutter algorithm to adjust the shutter duration. A 1 in this location allows the autoshutter algorithm to control the shutter. A zero in this location disables the autoshutter algorithm from controlling this value and allows registers ESLE, ESLH and ESLL to control the shutter duration. Auto-Shutter Window / Input Control Symbol: ASW Address: 1Eh Bits: 7 Bits 0, 1, 2 and 3 of the ASW register determine the active window that is used to operate the autoshutter algorithm. There are 16 possible windows, which are shown in Figure 12. The default value of these bits can be set using the PUD [3:0] inputs. This allows the backlight compensation window to be set without using IIC control. Bit 4 of the ASW register enables the selected window to be highlighted in the image which is output from the CH5101. All image outside of the window will be reduced in amplitude. Bits 5 and 6 of the ASW register determine which data is input to the autoshutter algorithm, according to Table 12 . BIT: 7 6 5 4 3 2 1 0 SYMBOL: ASSE ASBE ASGE Reserved Reserved ASSPD2 ASSPD1 ASSPD0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 1 1 1 0 0 1 0 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: ASME ASCSC ASWD ASW3 ASW2 ASW1 ASW0 TYPE: R/W R/W R/W R/W R/W R/W R/W DEFAULT: 1 0 0 PUD3* PUD2* PUD1* PUD0*

pixels is greater than this value, the black level will be adjusted upwards. shutter value should be changed. Table 12. Autoshutter Algorithm Input

201-0000-033 Rev 1.0, 6/2/99 27 Electronic Shutter Length Extended Value Symbol: ESLE Address: 21h Bits: 5 The ESLE register, combined with the ESLH and ESLL registers, determine the length of the electronic shutter. Miscellaneous Register 2 Symbol:MISC2 Address: 22h Bits: 7 Bit 0 (Master Clock Frequency) of register MISC2 refers to the CH5101 the master clock (XO) frequency. A 0 should be written to this location when the master clock is 24MHz. A 1 should be written to this location when the master clock is 27MHz. When modes four or five are selected (M[2:0] = 4,5), the master clock must be 27MHz. Bit 1 (Data Valid Control) of register MISC2 selects whether or not the CLKOUT signal is gated. When this bit is a 0, the CLKOUT pin will produce a continuous clock output signal. When bit DVC is a 1, the CLKOUT will be gated, and will be active when active data is being output from the CH5101, and inactive when non-active data is present at the outputs. Bit 2 (CLKOUT Polarity) of register MISC2 selects the polarity of the CLKOUT signal. A 0 in this location means output data has been latched with the positive edge of the CLKOUT signal. A 1 in this location means output data has been latched with the negative edge of the CLKOUT signal. Bit 3 (A/D Direct Output) of register MISC2 selects whether the output signal is directly from the A/D converter or after the datapath postprocessing. In both cases, the relationship between the Hsync, Vsync and active video will remain the same. When a 0 is written to this location, the Y[7:0] will output luma data from the datapath circuitry. When a 1 is written to this location, the Y[7:0] pins will contain the A/D data directly with no postprocessing. If 8-bit output mode is selected, the A/D output will be multiplexed with the decimal value 128 to enable connection to an 8-bit video encoder resulting in a black and white image. Bit 7 (RENB) of register MISC2 enables the refresh circuitry of the DRAM. A zero in this location allows refresh of the memories to be performed. A 1 in this location prevents the refresh. BIT: 7 6 5 4 3 2 1 0 SYMBOL: ESLE4 ESLE3 ESLE2 ESLE1 ESLE0 TYPE: R/W R/W R/W R/W R/W DEFAULT: 0 0 0 0 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: RENB Reserved Reserved Reserved ADDO CLKOUTP DVC MCF TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 0 1 PUD5* 0 0 1

28 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A Miscellaneous Register 3 Symbol: MISC3 Address: 23h Bits: 6 Bits 0-3 (Clock Delay) of register MISC3 determine the clock delay between the analog and digital clocks. The recommended value is 9 Bit 7 (A/D Full Scale Range) of register MISC3 changes the full scale range of the AD converter. A 0 in this location sets the A/D full scale range at + 1 volt. A 1 in this location sets the A/D full scale range at + 0.25 volt. This bit can be combined with the PSHG[2:0] to form a 4-bit control. Power Down Register Symbol: PD Address: 24h Bits: 3 Bits 2-0 of register PD are used to power down portions of circuitry during test modes. These bits should always be set to zero during normal operation. Bit 4 of register PD is used to perform a software reset on the device. It is logically AND ’d with the power on reset signal. The output of this AND ’ing will be used to reset all circuitry in the CH5101, except for the ResetB bit itself and the IIC state machines. ResetB and the IIC state machines are reset by the power on reset signal only. Address Register Symbol: AR Address: 26h Bits: 8 Register AR is the CH5101 address register, which holds the address of the register currently being accessed. BIT: 7 6 5 4 3 2 1 0 SYMBOL: ADFSR Reserved Reserved Reserved CKDLY3 CKDLY2 CKDLY1 CKDLY0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 1 1 1 0 0 1 BIT: 7 6 5 4 3 2 1 0 SYMBOL: ResetB Reserved PD2 PD1 PD0 TYPE: R/W R/W R/W R/W R/W DEFAULT: 1 0 0 0 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 TYPE: R R R R R R R R DEFAULT: 0 0 0 0 0 0 0 0

1 Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. maximum rating conditions for extended periods may affect reliability. Table 13. Absolute Maximum Ratings Table 14. Recommended Operating Conditions Table 15. Digital Inputs/Outputs Table 16. Timing Characteristics

30 201-0000-033 Rev 1.0, 6/2/99 CHRONTEL CH5101A Figure 13: Timing Diagram (M[2:0] = 1, OF = 1, H Start = 0) Note: The output pixel Y0 will be delayed by 2 times the value of the HStart register +1 CLKOUT cycles, if HStart is non- zero. Figure 14: Timing Diagrams (M[2:0] = 1, OF = 0, HStart = 0) t VSWVS* t HSWHS* t P t Ph t PLt HD CLKOUT Y[7:0] t hP t SP

128 Y0 128 Y1 128

t VSWVS* t HSWHS* CLKOUT t HD Y0Y Y1 Y2 Y3 CRS

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ORDERING INFORMATION

Part number Package type Number of pins Voltage supply CH5101A-L LCC 52 5V CH5101A-Q PQFP 52 5V CHRONTEL CH5101A 32 201-0000-033 Rev 1.0, 6/2/99