CDX1250

CDX1250 SONY | Alldatasheet

Document overview

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Technical content

Features

4-channel vertical clock driver and 1 channel substrate driver are built-in. Application CCD camera Structure CMOS Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage V DD VL – 0.3 to VL + 35.0 V VM VL – 0.3 to VL + 35.0 V VH VL – 0.3 to VL + 35.0 V VHH VL – 0.3 to VL + 35.0 V
• Input volltage V I VL – 0.3 to VDD + 0.3 V
• Output voltage MV f (pins 13, 17) VL – 0.3 to VM + 0.3 V
• Output voltage HV f (pins 14, 16) VL – 0.3 to VH + 0.3 V
• Output voltage HHV f (pin 19) V L – 0.3 to VHH + 0.3 V
• Operating temperature Topr –25 to +85 °C
• Storage temperature Tstg –40 to +125 °C Recommended Operating Conditions
• Supply voltage V DD 5.0 ± 0.5 V VM VL + 10.0 V VH VL + 25.0 V VHH VL + 30.0 V VL –10.0 V
• Operating temperature Topr –20 to +75 °C – 1 – CXD1250M/N 80639C43-PK Vertical Clock Driver for CCD Image sensor Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD1250M 20 pin SOP (Plastic) CXD1250N 20 pin SSOP (Plastic)

– 2 – CXD1250M/N Block Diagram and Pin Configuration (Top View) Pin Description 11121314151617181920 21 3 4 5 6 7 8 9 10 GND Xsub XV2 XV1 XSG1 XV3 XSG2 XV4 V DD (5V) N.C V HH (20V) Vsub V L (–10V) Vφ2 Vφ1 V M (0V) Vφ3 Vφ4 V H (15V) N.C No. GND Xsub XV2 XV1 XSG1 XV3 XSG2 XV4 V DD NC NC V H Vf4 Vf3 VM Vf1 Vf2 VL Vsub V HH I I I I I I I O O O O O GND Output control (Vsub) Output control (Vf2) Output control (Vf1) Output control (Vf1) Output control (Vf3) Output control (Vf3) Output control (Vf4) Power supply (5V) Power supply (15V) Output (2 level : V M , VL) Output (3 level : VH , VM , VL) Power supply (0V) Output (3 level : V H , VM , VL) Output (2 level : VM , VL) Power supply (–10V) Output (2 level : V HH , VL) Power supply (20V) Symbol I/O Description

– 3 – CXD1250M/N Truth Table DC Characteristics (Ta = 25°C) Input XV1 · 3 L H X X X X L H H H X X X X L L X X L H X X X X X X X X L H X X V M VL X X X X V H Z X X VM VL X X X X X X X X V HH VL X X XSG1 · 2 XV2 · 4 Xsub Vf1 · 3 V f2 · 4 Vsub Output X : Don't care Z : High impedance Item "H" level input voltage "L" level input voltage "L" level output voltage "M" level output voltage "M" level output voltage "H" level output voltage "HH" level output voltage Input current Power supply current * Power supply current * Power supply current * Power supply current * V IH VIL VfL VfM VfM VfH VfHH Ii IM IDD IH IHH IfL = 20µA IfM = –20µA IfM = 20µA IfH = –20µA IfHH = –20µA 3.5 –0.1 14.9 19.9 –10 0.0 0.0 1.0 4.5 0.3 0.1 0.05 1.5 –9.9 0.1 5.0 0.5 0.2 0.1 V V V V V V V µA mA mA mA mA V DD = 5V VL = –10V VM = 0V VH = 15V VHH = 20V Symbol Min. Typ. Max. Unit Test condition Power supply * Suuply current at operation (See the Test Circuit)

– 4 – CXD1250M/N Switching Characteristics(See the Test Circuit Ta = 25°C, VHH = 20V, VH = 15V, VM = 0V, VL = –10V, VDD = 5V) Item Output current Output current Output current Output current Output current Output current Rise time V L fi VM Fall time VM fi VL Rise time VM fi VH Fall time VH fi VM Rise time VL fi VHH Fall time VHH fi VL Coupling amplitude (middle level) Coupling amplitude (low level) IL IM1 IM2 IH ISL ISH TTLM TTML TTMH TTHM TTLHH TTHHL VCOM VCOL Vf1 to 4 = –9.5V Vf1 to 4 = –0.5V Vf1, 3 = 0.5V Vf1, 3 = 14.5V Vsub = –9.5V Vsub = –19.5V Vf1 to 4 = –0.5V After input transient Vf1 to 4 = –9.5V After input transient Vf1, 3 = 14V After input transient Vf1, 3 = 1V After input transient Vsub = 17V After input transient Vsub = –7V After input transient Vf1 to 4 Vf1 to 4 –25 –12 1000 500 1000 1000 200 200 0.5 0.5 mA mA mA mA mA mA ns ns ns ns ns ns V V Symbol Conditions Max. Min. Unit Input Waveform (Repeat Cycle 15.7kHz) Output Waveform 600ns XV1 5 XV2 5 XV3 5 XV4 5 TTML TTLM VCOM VCOL Vφ1 –10 Vφ2 Vφ3 –10 –10 –10 Vφ4

– 5 – CXD1250M/N Switching Waveform Input Waveform Output Waveform 16.6ms XV1 XV3 XSG1 XSG2 Vφ1 0 –10 Vφ3 –10 Vφ2 –10 TTMH TTHM Xsub Vsub –10 TTLHH TTHHL 11121314151617181920 21 3 4 5 6 7 8 9 10 Timing generator (CXD1156Q) 20V –10V 500pF 15V C 1 C 2 C 2 C 1 R 1 R 1 C 2 R 2 C 1 C 2 C 1 R 1 R 1 R 1; 27Ω R 2; 5Ω C 1; 1500pF C 2; 3300pF Test Circuit

– 6 – CXD1250M/N Application Circuit +20V 3 4 1011 1 4 1µ/35 4.7µ/ 15k 47k 15k 39k 27k 0.1µ56k 0.1µ 270k –10V +15V ICX026/027 CXD1250M/N CXD1156Q Vφ4 Vφ3 Vφ1 Vφ2 sub NC VH Vφ4 Vφ3 VM Vφ1 Vφ2 VL Vsub V HH NC VDD XV4 XSG2 XV3 XSG1 XV1 XV2 Vsub GND XV4 VSG2 XV3 VSG1 XV1 XV2 Xsub +5V Refer to the Caution : Rise in power supply Note: The capacitor more than 0.1µF should be connected between the ground and each pin of V DD , VH , VHH and VL . Caution : Rise in Power Supply When the substrate driver is in use, be careful not to let the CCD imagesensors Sub (pin 4) turn into negative voltage. To this end, raise VL and VHH at the application circuit under the following conditions. 20% 20% VHH (20V) VL (–10V) t2 ≥ t1 ≥ 10msec

– 7 – CXD1250M/N Package Outline Unit: mm CXD1250M CXD1250N 20PIN SSOP (PLASTIC) SONY CODE EIAJ CODE JEDEC CODE PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM COPPER / 42 ALLOY 0.1g SSOP-20P-L01 SSOP020-P-0044 0.1 ± 0.1 0.5 ± 0.2 0° to 10° DETAIL A PLATING ∗6.5 ± 0.1 ∗4.4 ± 0.1 0.22 – 0.05 + 0.1 0.65 ± 0.12 20 11 101 A 0.1 + 0.05 1.25 – 0.1 + 0.2 0.15 – 0.02 6.4 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. SONY CODE EIAJ CODE JEDEC CODE SOP-20P-L01 ∗SOP020-P-0300-A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT COPPER ALLOY SOLDER PLATING EPOXY / PHENOL RESIN 0.3g 20PIN SOP (PLASTIC) 300mil 12.45 – 0.1 + 0.4 20 11 0.45 ± 0.1 1.27 101 5.3 – 0.1 + 0.3 7.9 ± 0.4 6.9 0.2 – 0.05 + 0.1 0.5 ± 0.2 0.1 – 0.05 + 0.2 1.85 – 0.15 + 0.4 0.15 ± 0.12M