CDP6805E2CE

IA6805E2_07 INNOVASIC | Alldatasheet

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As of Production Version 00 IA6805E2 Microprocessor Unit Data Sheet Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 1 of 33 1-888-824-4184

As of Production Version 00

FEATURES

Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 2 of 33 1-888-824-4184

• Form, Fit, and Function Compatible with the Harris© CDP6805E2CE and Motorola© MC146805E2 Internal 8-bit Timer with 7-Bit Programmable Prescaler On-chip Clock Memory Mapped I/O Versatile Interrupt Handling True Bit Manipulation Bit Test and Branch Instruction Vectored Interrupts Power-saving STOP and WAIT Modes Fully Static Operation

112 Bytes of RAM

Packaging options available: 40 Pin Plastic DIP or, 44 Pin Plastic Leaded Chip Carrier, Standard or RoHS packages available The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. Innovasic produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable timing. Package Pinout A12 NC (6)AS (1)RESET_N (2)IRQ_N (3)LI (4)DS (5)RW_N (7)PA7 (8) (9)PA5 (10) (11) (12)PA2 (13)PA1 (14)

40 Pin DIP

(20)VSS (15)A12 (16)A11 (17)A10 (18)A9 (19)A8 (21) (22) (23) (24) (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) PA0 PB2 PB3 PB0 PB1 OSC2 TIMER VDD OSC1 PA6 PA4 PA3 RW_N NC

44 Pin LCC

(12)PA3 (7)AS (8)PA7 (9)PA6 (10)PA5 (11)PA4 (13)PA2 (14)PA1 (15)PA0 (16)NC (17)NC PB1 PB7 PB6 PB5 PB3 PB2 A10 A11 (6) (5) (4) (3) (2) (1) (44) (43) (42) OSC2 (41) TIMER (40) PB0 (34) (39) (38) (37) (36) (35) (33) (32) (31) (30) (29) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) VDD OSC1 IRQ_N RESET_N DS LI VSS PB4

As of Production Version 00

Description

The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The following paragraphs will further describe this system block diagram and design in more detail. PROGRAM COUNTER LOW 112x8 RAM ADDRESS DRIVE MUX BUS DRIVE CPU PORT A REG OSCILLATOR DATA DIR REG PORT B REG DATA DIR REG CPU CONTROL ALU BUS CONTROL STACK POINTER CONDITION CODE REGISTER INDEX REGISTER ACCUMULATOR PROGRAM COUNTER HIGH TIMER CONTROL PRESCALER TIMER/ COUNTER PA0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PB0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PA0 OSC1 OSC2 TIMER RESET_N LI IRQ_N A12 A11 A10 RW_N DS AS X CC SP PCH PCL PORT A I/O LINES PORT B I/O LINES MULTIPLEXED ADDRESS DATA BUS ADDRESS BUS ADDRESS STROBE DATA STROBE READ/WRITE Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Figure 1. System Block Diagram

As of Production Version 00 I/O Signal Description The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. SIGNAL NAM E I/O DESCRIPTION V DD and V SS (Power and Ground) N/A Source: These two pins provide power to the chip. V DD provides +5 volts (±0.5) power and V SS is ground. RESET_n (Reset) I TTL: Input pin that can be used to reset the MPU's internal state by pulling the reset_n pin low. IRQ_n (Interrupt Request) I TTL: Input pin that is level and edge sensitive. Can be used to request an interrupt sequence. LI (Load Instruction) O TTL w ith slew rate control: Output pin used to indicate that a next opcode fetch is in progress. Used only for certain debugging and test systems. Not connected in normal operation. Overlaps Data Strobe (DS) signal. This output is capable of driving one standard TTL load and 50pF. DS (Data Strobe) O T T Lw i t hs l e wr a t ec o n t r o l :Output pin used to transfer data to or from a peripheral or memory. DS occurs anytime the MPU does a data read or write and during data transfer to or from internal memory. DS is available at f OSC ¸5 when the MPU is not in the W AIT or STOP mode. This output is capable of driving one standard TTL load and 130pF. RW _n (Read/Write) O TTL w ith slew rate control: Output pin used to indicate the direction of data transfer from internal memory, I/O registers, and external peripheral devices and memories. Indicates to a selected peripheral whether the MPU is to read (RW _n high) or write (RW _n low) data on the next data strobe. This output is capable of driving one standard TTL load and 130pF. AS (Address Strobe) O T T Lw i t hs l e wr a t ec o n t r o l : Output strobe used to indicate the presence of an address on the 8-bit multiplexed bus. The AS line is used to demultiplex the eight least significant address bits from the data bus. AS is available at f OSC ¸5w h e nt h e MPU is not in the W AIT or STOP modes. This output is capable of driving one standard TTL load and 130pF. PA0-PA7/PB0-PB7 (Input/Output Lines) I/O T T Lw i t hs l e wr a t ec o n t r o l : These 16 lines constitute Input/Output ports A and B. Each line is individually programmed to be either an input or output under software control of the Data Direction Register (DDR) as shown below in Table 1 and Figure 2 . The port I/O is programmed by writing the corresponding bit in the DDR to a "1" for output and a "0" for input. In the output mode the bits are latched and appear on the corresponding output pins. All the DDR's are initialized to a "0" on reset. The output port registers are not initialized on reset. Each output is capable of driving one standard TTL load and 50pF. A8-A12 (High Order Address Lines) O T T Lw i t hs l e wr a t ec o n t r o l : These five outputs constitute the higher order non- multiplexed address lines. Each output is capable of driving one standard TTL load and 130pF. B0-B7 (Address/Data Bus) I/O T T Lw i t hs l e wr a t ec o n t r o l : These bi-directional lines constitute the lower order addresses and data. These lines are multiplexed with address present at address strobe time and data present at data strobe time. W hen in the data mode, these lines are bi-directional, transferring data to and from memory and peripheral devices as indicated by the RW _n pin. As outputs, these lines are capable of driving one standard TTL load and 130 pF. Timer I TTL: Input used to control the internal timer/counter circuitry. OSC1, OSC2 (System Clock) TTL Oscillator input/output: These pins provide control input for the on-chip clock oscillator circuits. Either a crystal or external clock is connected to these pins to provide a system clock. The crystal connection is shown in Figure 3 .T h e O S C 1 t o bus transitions for system designs using oscillators slower than 5MHz is shown in Figure 4 . Crystal The circuit shown in Figure 3 is recommended when using a crystal. An external CMOS oscillator is recommended when using crystals outside the specified ranges. To minimize output distortion and start-up stabilization time, the crystal and components should be mounted as close to the input pins as possible. External Clock W hen an external clock is used, it should be applied to the OSC1 input with the OSC2 input not connected, as shown in Figure 3 . I/O Table 1 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 4 of 33 1-888-824-4184

written into the output data latch.

01 Data is written into the output data latch and

10 The state of the I/O pin is read. Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines)

are divided into internal memory space and external memory space as shown in Figure 5. being overwritten due to stacking from an interrupt or subroutine call. Figure 5. Memory Map

As of Production Version 00 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 9 of 33 1-888-824-4184 A(Accumulator): The accumulator is an 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. X(Index Register): The index register is an 8-bit register used duri ng the indexed addressing mode. It contains an 8-bit value used to create an effective address. The index register may also be used as a temporary storage area when not performing addressing operations. PC(Program Counter): The program counter is a 13-bit register that hol ds the address of the next instruction to be performed by the MPU. SP(Stack Pointer): The stack pointer is a 13-bit register that hol ds the address of the next free location on the stack. During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $007f. The seven most significant bits of the stack pointer are permanently set to 0000001. They are appended to the six least significant register bits to produce an address range down to location $0040. The stack pointer gets decremented as data is pushed onto the stack and incremented as data is removed from the stack. The stack area of RAM is used to store the return address on subroutine calls and the machine state during interrupts. The maximum number of locations for the stack pointer is 64 bytes. If the stack goes beyond this limit the stack pointer wraps around and points to its upper limit thereby losing the previously stored information. Subroutine calls use 2 bytes of RAM on the stack and interrupts use 5 bytes. CC(Condition code Register): The condition code register is a 5-bit register that indicates the results of the instruction just executed. The bit is set if it is high. A progra m can individually test these bits and specific actions can be taken as a result of their states. Following is an explanation of each bit. C(Carry Bit): The carry bit indicates that a carry or borro w out of the Arithmetic Logical Unit (ALU) occurred during the last arithmetic instruction. This bit is also modified during bit test, shift, rotate, and branch types of instructions. Z(Zero Bit): The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero. N(Negative Bit): The negative bit indicates the result to the last arithmetic, logical, or data manipulation was negative (bit 7 in the result is high).

As of Production Version 00 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 10 of 33 1-888-824-4184 I(Interrupt Mask Bit) The interrupt mask bit indicates that both the external interrupt and the timer interrupt are disabled (masked). If an interrupt occurs while th is bit is set, the interrupt is latched and is processed as soon as the interrupt bit is cleared. H(Half Carry Bit) The half carry bit indicates that a carry occu rred between bits 3 and 4 of the ALU during an ADD or ADC operation. Resets: The MPU can be reset by initial power up or by the external reset pin (reset_n). POR(Power On Reset) Power on reset occurs on initial power up. It is strictly for power initialization conditions and should not be used to detect drops in the power supply voltage. There is a 1920 t CYC time out delay from the time the oscillator is detected. If the reset_n pin is still low at the end of the delay, the MPU will remain in the reset state until the external pin goes high. Reset_n The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of t cyc to guarantee a reset. The reset_n pin is provided with a Schmitt Trigger to improve noise immunity capability. Interrupts: The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer interrupt request, or the software interrupt in struction. When any of these interrupts occur, normal processing is suspended at the end of the current instruction execution. The processor registers are saved on the stack (s tacking order shown in F i g u r e 7 ) a n d t h e interrupt mask (I) is set to prevent additiona l interrupts. Normal processing resumes after the RTI instruction causes the register conten ts to be recovered from the stack. When the current instruction is completed, the processor checks all pending hardware interrupts and if unmasked (I bit clear) proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. Masked interrupts are la tched for later interrupt service. External interrupts hold higher priority than timer interrupts. At the end of an instruction execution, if both an external interrupt and timer interru pt are pending, the external interrupt is serviced first. The SWI gets executed with th e same priority as any other instruction if the hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing flowchart.

Figure 8. Reset and Interrupt Processing Flowchart

to complete the service routine including the RTI instruction. Figure 9. Interrupt Functional Diagram

Figure 10. Interrupt Mode Diagram specify the address for this service routine. following paragraphs explain these modes of operation.

I bit in the condition code register. All othe r registers, memory, and I/O remain unaltered. shows a flowchart of the stop function. Figure 11. STOP Function Flowchart

no longer in the wait mode. Figure 12 shows a flowchart of the wait function. Figure 12. WAIT Function Flowchart

is fetched. Power-On-Reset causes the counter to set to $FF. clock (AS) or external input.

1. Counter is written to during Data St robe (DS) and counts down continuously.

Figure 13. Timer Block Diagram

As of Production Version 00 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 17 of 33 1-888-824-4184 The counter continues to count past zero, fa lling from $00 to $FF, and continues. The processor may read the counter at any time without disturbing the count by reading the timer data register (TDR). This allows a prog ram to determine the length of time since a timer interrupt has occurred. The timer interru pt request bit remains set until cleared by software. The interrupt is lost if this happens before the timer interrupt is serviced. The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits 0-2 are programmed to choose th e appropriate prescaler output, which is used as the count input. The prescaler is cleared by writing a “1” into TCR bit 3, which avoids truncation errors. The processor cannot write to or read from the prescaler. Timer Input Mode 1: When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the timer input is disabled. The internal clock mode can be used for periodic interrupt generation as well as a reference for frequency and event measurement. The internal clock is the instruction cycle clock and is coincident with Address Strobe (AS) except during the wait instruction where it goes low. During the wait instruction the internal clock to the timer continues to run at its normal rate Timer Input Mode 2: When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to form the timer input. This mode can be used to measure external pulse widths. The external pulse turns on the internal clock for the duration of the pulse. The count accuracy in this mode is ±1 clock. Accuracy improves with longer input pulse widths. Timer Input Mode 3: When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled. Timer Input Mode 4: When TCR4 = 1 and TCR5 = 1, the internal cloc k input to the timer is disabled and the timer input then comes from the external TI MER pin. The external clock can be used to count external events as well as to provide an external frequency for generating periodic interrupts.

As of Production Version 00 TCR (Timer Control Register ($0009)): An 8-bit register that controls functions such as configuring operation mode, setting ratio of the prescaler, and generating timer interrupt request signals. All bits except bit 3 are read/write. Bits TCR5 - TCR0 are unaffected by reset_n. 76543210 TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Reset: 01000000 TCR7 – Timer Interrupt Request Used to indicate the timer interrupt when it is logic one. 1 – Set when the counter decrements to zero or under program control. 0 – Cleared on external reset, POR, STOP instruction, or program control . TCR6 – Timer Interrupt Mask Used to inhibit the timer interrupt. 1 – Interrupt inhibited. Set on external res et, POR, STOP instruction, or program control. 0 – Interrupt enabled. TCR5 – External or Internal Selects input clock source. Unaffected by reset. 1 – External clock selected. 0 – Internal clock selected (AS) (f OSC/5). TCR4 – Timer External Enable Used to enable external timer pin or to enable the internal clock. Unaffected by reset. 1 – Enables external timer pin. 0 – Disables external timer pin. Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 18 of 33 1-888-824-4184

As of Production Version 00 TCR3 – Prescaler Clear Write only bit. Writing a “1” to this bit resets the prescaler to zero. A read of this location always indicates a zero. Unaffected by reset. TCR2, TCR1, TCR0 – Prescaler select bits Decoded to select one of eight outputs of the prescaler. Unaffected by reset. TRC2 TRC1 TRC0 RESET 000 ÷1 001 ÷2 010 ÷4 011 ÷8 100 ÷16 101 ÷32 110 ÷64 111 ÷128 Prescaler Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 19 of 33 1-888-824-4184

As of Production Version 00 Instruction Set Description The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, read- modify-write, branch, bit manipulation, and control. Register/Memory Instructions: Most of the following instructions use two operands. One is either the accumulator or the index register and the other is obtained from memory. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Function Mnemonic Load A from memory LDA Load X from memory LDX Store A in memory STA Store X in memory STX Add memory to A ADD Add memory and carry to A ADC Subtract memory SUB Subtract memory from A with Borrow SBC AND memory to A AND OR memory with A ORA Exclusive OR memory with A EOR Arithmetic compare A with memory CMP Arithmetic compare X with memory CPX Bit test memory with A (logical compare) BIT Jump Unconditional JMP Jump to subroutine JSR Read-Modify-Write Instructions: These instructions read a memory or register lo cation, modify or test its contents and then write the modified value back to memory or the register. Function Mnemonic Increment INC Decrement DEC Clear CLR Complement COM Negate (2's complement) NEG Rotate Left Thru Carry ROL Rotate Right Thru Carry ROR Logical shift left LSL Logical shift right LSR Arithmetic shift right ASR Test for negative or zero TST Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 20 of 33 1-888-824-4184

As of Production Version 00 Bit Manipulation Instructions: The MPU is capable of altering any bits residing in the first 256 bytes of memory. An additional feature allows the software to test an d branch on the state of any bit within these locations. For test and branch instructions the value of the bit tested is placed in the carry bit of the condition code register. Function Mnemonic n = 0…7 Branch if bit n set BRSET n Branch if bit n clear BRCLR n Set bit n BSET n Clear bit n BCLR n Branch Instructions: If a specific condition is met, the instruction branches. If not, no operation is performed. Function Mnemonic Branch always BRA Branch never BRN Branch if higher BHI Branch if lower or same BLS Branch if carry clear BCC Branch if higher or same BHS Branch if carry set BCS Branch if lower BLO Branch if not equal BNE Branch if equal BEQ Branch if half carry clear BHCC Branch if half carry set BHCS Branch if plus BPL Branch if minus BMI Branch if interrupt mask bit clear BMC Branch if interrupt mask bit set BMS Branch if interrupt line low BIL Branch if interrupt line high BIH Branch to subroutine BSR Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 21 of 33 1-888-824-4184

As of Production Version 00 Control Instructions: These are used to control processor operation during program execution. They are register reference instructions. Function Mnemonic Transfer A to X TAX Transfer X to A TXA Set carry bit SEC Clear carry bit CLC Set interrupt mask bit SEI Clear interrupt mask bit CLI Software interrupt SWI Return from subroutine RTS Return from interrupt RTI Reset stack pointer RSP No-Operation NOP Stop STOP Wait WAIT Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 22 of 33 1-888-824-4184

As of Production Version 00 Opcode Map Summary: The following table is an opcode map for the instructions used on the MPU. The legend following the table shows how to use the table. Hi Hi Low Low 5 5 3533659 234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

3B T B 2 B S C 2 R E L 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 5 353365 1 0 234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

3B T B 2 B S C 2 R E L 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 5 353365 234543

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX

Branch Read-Modify-Write Control Register/Memory INH IMM DIR EXT F 1111 BTB BSC REL DIR INH INH IX1 IX INH ROR LSR 1000 0111 CMP CMP AND LDA CMP SBC CPX AND CMP CMP CMP SBC SBC SBC SBC E 1110 F 1111 C 1100 D 11011010 AB 1011 1001 Bit Manipulation RTS 0101 0110 0000 BRSET0 NEGA 0010 0011 0100

0000 BSET0 BRA NEG NEGX NEG NEG RTI SUB SUB SUB SUB SUB SUB

2 0010BRSET1 BSET1 BHI SBC SWI 3 0011CPX CPX CPX CPX 4 0100 5 0101 COMA COMX COM COM CPX BIT BIT EOR BRCLR1 BCLR1 BLS COM BIT LDA LSRA AND AND ANDANDLSRBRSET2 BSET2 BCC LSR LSRX BITBRCLR2 BCLR2 BCS A 1010 9 1001 7 0111 6 0110 8 1000 BIT BIT EOR EOR RORA RORX ROR LDABRSET3 BSET3 BNE ROR D 1101 LDA LDA LDA STA STA STA EOR C 1100 B 1011 E 1110 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR TAX STA STA BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL CLC EOR EO R BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA ORA ORA ORA BRCLR5 BCLR5 BMI SEI ADD ADD ADD ADD ADD ADD BRSET6 BSET6 BMC INC INCA INCX INC INC RSP JMP JMP JMP JMP JMP BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR BRSET7 BSET7 BIL STOP LDX LDX LDX LDX LDX LDX BRCLR7 BCLR7 BIH CL R CLRA CLRX CL R CLR WAIT TXA STX STX STX STX STX 0110 0111 1000 0001 0010 0011 0100 D 1101 E 1110 F 1111 0001 1001 A 1010 B 1011 C 1100 0101 Abbreviations for Address Modes: Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: INH Inherent A Accumulator X Index Register IMM Immediate DIR Direct EXT Extended REL Relative BSC Bit set/clear SUB IX1 F 1111 0000 Opcode in Hexadecimal Opcode in Binary Address Mode Mnemonic Bytes # of Cycles BTB Bit test and branch IX Indexed, no offset IX1 Indexed, 1 byte offset IX2 Indexed, 2 byte offset Legend: Page 23 of 33 1-888-824-4184

As of Production Version 00 AC/DC Parameters Absolute maximum ratings: Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability of the device. DC Characteristics (VDD=4.5 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 24 of 33 1-888-824-4184 A A Symbol Parameter Min Max Unit VDD Supply Voltage 4.5 5.5 V VOL -0 . 4 V VOH 3.5 - V IOL -2 m IOH -- 2 m VIH High Level input Voltage 2 - V VIL Low Level input Voltage - 0.8 V IIH High Level input Current - 1 µA IIL Low Level input Current - -1 µA Vt- Schmitt Negative Threshold 1.1 - V Vt+ Schmitt Positive Threshold - 1.87 V Frequency of Operation fOSC Crystal - 5 MHz fOSC External Clock DC 5 MHz DC CHARACTERISTICS Output Current Output Voltage, I LOAD ≤ 2 mA

As of Production Version 00 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 25 of 33 1-888-824-4184 Control Timing VSS=0V, TA=TL to TH V = 5.0V ±10% DD fOSC = 5MHz Parameters Sym Min Typ Max Unit I/O Port Timing – Input Setup Time (Figure 14) tPVASL 196 - - ns Input Hold Time (Figure 14) tASLPX 0 - - ns Output Delay Time (Figure 14) tASLPV - - 0 ns Interrupt Setup Time (Figure 15) TILASL 0.4 - - μs Crystal Oscillator Startup Time (Figure 16) tOXOV - 5 100 ms Wait Recovery Startup Time (Figure 17) tIVASH - - 2 μs Stop Recovery Startup Time (Figure 18) tILASH - - 2 μs Required Interrupt Release (Figure 15) tDSLIH - - 1.0 μs Timer Pulse Width (Figure 17) tTH, tTL 0.5 - - tCYC Reset Pulse Width (Figure 16) tRL 1.05 - - μs Timer Period (Figure 17) tTLTL 1.0 - - tCYC Interrupt Pulse Width Low (Figure10) tILIH 1.0 - - tCYC Interrupt Pulse Period (Figure 10) tILIL * - - tCYC Oscillator Cycle Period (1/5 of tCYC) (Figure 3) tOLOL 200 - - ns OSC1 Pulse Width High (Figure 3) tOH 75 - - ns OSC1 Pulse Width Low (Figure 3) tOL 75 - - ns *The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the interrupt service routine plus 20 tCYC cycles.

1 TTL, 100pF Load

1 Cycle Time 1000 DC ns

2 Pulse Width, DS Low 587 - ns

3 Pulse Width, DS High 403 - ns

4 Clock Transition - 4 ns

8 RW_n 9 - ns

9 Non-Muxed Address Hold 97 - ns

11 RW_n Delay From DS Fall - 40 ns

16 Non-Muxed Address Delay From AS Rise - 11 ns

17 MPU Read Data Setup 18 - ns

18 Read Data Hold 0 ns

19 MPU Data Delay, Write - 0 ns

21 Write Data Hold 204 - ns

23 Muxed Address Delay From AS Rise - 26 ns

24 Muxed Address Valid to AS Fall 185 - ns

25 Muxed Address Hold 103 - ns

26 Delay DS Fall to AS Rise 190 - ns

27 Pulse Width, AS High 203 - ns

28 Delay, AS Fall to DS Rise 185 - ns

*Note: The address strobe of the first cycle of the next instruction. Figure 14. I/O Port Timing

Figure 19. Bus Timing

As of Production Version 00 Packaging Information PDIP Packaging LEAD 1 IDENTIFIER LEAD COUNT DIRECTION E1 E TOP eA eB C SIDE VIEW (WIDTH) Lead Count 40 (in Inches) Symbol MIN MAX A- . 200 A1 .015 - B .015 .020 B1 .040 .060 C .008 .012 D 1.980 2.065 E .580 .610 E1 .520 .560 e .100 TYP eA .580 - eB - .686 L .100 MIN D L A B e SIDE VIEW (LENGTH) Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 30 of 33 1-888-824-4184

As of Production Version 00 PLCC Packaging LEAD COUNT 44 (in Millimeters) Symbol MIN MAX A 4.20 4.57 A1 2.29 3.04 D1 16.51 16.66 D2 14.99 16.00 D3 12.70 BSC E1 16.51 16.66 E2 14.99 16.00 E3 12.70 BSC e1 .27 BSC D 17.40 17.67 E 17.40 17.65 .10 .51 MIN. R 1.14 / .64 SEATING PLANE e .81 / .66 A .53 / .33 D2 / E2 SIDE VIEW D E BOTTOM VIEW PIN 1 IDENTIFIER & ZONE 1.22/1.07

2 PLCS

Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 31 of 33 1-888-824-4184

As of Production Version 00 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 32 of 33 1-888-824-4184

Ordering Information

The IA6805E2 is available in two package styles, both standard and RoHS compliant, listed in the table below. Other packages and temperature grades may be available for additional cost and lead time. Order Number Temperature Grade Package Type IA6805E2-PDW40I-00 Industrial 40 Lead Plastic DIP, 600 mil wide IA6805E2-PDW40I-R-00 (RoHS compliant) Industrial 40 Lead Plastic DIP, 600 mil wide IA6805E2-PLC44I-00 Industrial 44 Lead Plastic Leaded Chip Carrier IA6805E2-PLC44I-R-00 (RoHS compliant) Industrial 44 Lead Plastic Leaded Chip Carrier Cross Reference to Original Manufacturers Innovasic Part Number Motorola® Part Number Harris® Part Number IA6805E2-PDW40I ‰ MC146805E2CP ‰ CDP6805E2CE ‰ MC146805E2P ‰ CDP6805E2E IA6805E2-PLC44I ‰ MC146805E2CFN ‰ CDP6805E2CQ ‰ MC146805E2FN ‰ CDP6805E2Q

As of Production Version 00 Copyright © 2007 IA211081401-03 www.Innovasic.com Customer Support: Page 33 of 33 1-888-824-4184 Errata Production Version 00 1. Functional differences between IA6805E2 and Harris and Motorola Versions: A. Stop mode on IA6805E2 will not halt oscillator. Recovery from stop will be quicker. B. There is a functional difference between the IA6805E2 and the original device instruction sets regarding instructions for BSET and BCLR. Analysis: The instructions, BSET and BCLR (bit set and bit clear), are not supposed to affect the carry flag in the condition code register but in the IA6805E2 they do. Any situations where the BSET or BCLR commands are executed between a decision type instruction (branches) based on the carry flag and the instruction that was to update the carry flag should be considered suspect. Workaround: The workaround selected by the particular user is code dependent. Software will need to be revised to address the instruction set issues noted above. C. There is a functional difference between the IA6805E2 and the original device regarding the external timer input. Analysis: The original device is edge sensitive on this input (negative edge). The IA6805E has a synchronizing register on this input. If the stimulus to this input is a negative pulse less than a clock cycle wide, it is possible that this event will be missed by the timer circuit. Workaround: The workaround selected by the particular user is situation dependent. The input pulse either needs to be a minimum of 1 clock cycle wide or the pulse needs to be centered on the falling edge of the input clock. 2. Observations: A. Original data sheets for Motorola and Harris are inconsistent when describing timer input mode 2. Original parts and Innovasic will AND together the timer input with the inverse of the internal clock (AS). B. Original Harris part would unpredictably “pre-increment” timer counter when writing to timer registers. IA6805E2 will not. C. Original Harris part displays incorrect address on external pins during intermediate cycles (not a functional problem) of multi-cycle instructions when accessing memory at page boundaries. IA6805E2 will not. D. Execution of illegal op-codes on the IA6805E2 will force a system reset. On the original Harris and Motorola parts, execution of illegal op-codes would produce unpredictable results.