CCD181

CCD181 SEME-LAB | Alldatasheet

Document overview

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Technical content

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500

FEATURES

• 2592 x 1 photosite array
• 10 µµµµµm x 10µµµµµm photosites on 10µµµµµm pitch
• Anti-blooming and integration control
• Voltage-selectable array lengths:

2592 Elements 2048 elements

1728 elements 1024 elements

• Enhanced spectral response (particularly in the blue region)
• Excellent low-light-level performance
• Low dark signal
• High responsivity
• High speed operation
• Dynamic range typical: 7500:1
• Over 1 V peak-to-peak outputs
• Dark references contained in sampled-and- held outputs
• Special selection available - consult factory CCD 181 Variable-Element High-Speed Linear Image Sensor

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181 GENERAL DESCRIPTION The CCD181 is a 2592-element line image sensor designed for industrial measurement, telecine, and document scanning applications which require high resolution, high sensitivity and high data rate. Incorporation of on-chip anti-blooming and integration controls allow the CCD181 to be extremely useful in an industrial measurement and control environment or in environments where lighting conditions are difficult to control. The CCD181 is equipped with special gates which allow the user to select 4 effective array lengths: 2592 elements: 300-lines/inch across 8.5 inch wide document 2048 elements: 240-lines/inch across 8.5 inch wide document 1728 elements: 200-lines/inch across 8.5 inch wide document 1024 elements: 120-lines/inch across 8.5 inch wide document The CCD181 is a third generation device having an overall improved performance compared with first and second generation devices, including enhanced blue response and excellent low light level per- formance, and high-speed operation up to 20 MHz. The photoelement size is 10 µm (0.39 mils) x 10 µm (0.39 mils) on 10µm (0.39 mils) centers. The device is manufactured using Fairchild Imaging’s advanced charge-coupled device n-channel isoplanar buried-channel technology. FUNCTIONAL DESCRIPTION The CCD191 consists of the following functional elements illustrated in the Block Diagram and Circuit Diagram (see Fig. 1A). Photosites — A row of 2592 image sensor elements separated by a diffused channel stop and covered by a silicon dioxide surface passivation layer. Image photons pass through the transparent sili- con creating hole-electron pairs. The photon generated electrons are accumulated in the photosites. The amount of charge accumu- lated in each photosite is a linear function of the incident illumination intensity and the integration period. The output signal will vary in an analog manner from a thermally generated background level at zero illumination to a maximum at saturation under bright illumination. Two Transfer Gate — Gate structures adjacent to the row of im- age sensor elements. The charge packets accumulated in the photosites are transferred in parallel via the transfer gates (φX) to the transport shift registers whenever the transfer gate voltages go high. Alternate charge packets are transferred to the A and B transport registers. Two Analog Shift Registers — The transport shift registers are used to move the light generated charge packets delivered by the transfer gates. (φ1A, φ1B, φ2A, φ2B) serially to the charge detector/am- plifier. The complementary phase relationship of the last elements of the two transport registers provides for alternate delivery of charge packets at the output amplifiers. A Gated Charge Detector/Amplifier — Charge packets are transported to a precharge capacitor whose potential changes lin- early in response to the quantity of the signal charge delivered. This potential is applied to the input gate of the two-stage NMOS amplifi- ers producing a signal at the output “V OUT” pin. Before each charge packet is sensed, a reset clock ( φRA, φRB) recharges the input node capacitor to a fixed voltage (VRDA, VRDB) Integration and Anti-Blooming Controls — In many applica- tions the dynamic range in parts of the image is larger than the dy- namic range of the CCD, which may cause more electrons to be generated in the photosite area than can be stored in the CCD shift register. This is particularly common in industrial inspection and sat- ellite applications. The excess electrons generated by bright illumi- nation tend to “bloom” or “spill over” to neighboring pixels along the shift register, thus “smearing” the information. This smearing can be eliminated using two methods: Anti-Blooming Operation: A DC voltage applied to the integration control gate (approximately 5 to 7 volts) will cause excess charge generated in the photosites to be diverted to the anti-blooming sink (V SINK) instead of to the shift regis- ters. This acts as a “clipping circuit” for the CCD output. (see Fig. 2)

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181 Fig. 2 MAXIMUM OUTPUT VOLTAGE vs. φφφφφIC Voltage

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181 Integration Control Operation: Variable integration times which are less than the CCD exposure time may be attained by supplying a clock to the integration control gate. Clocking φ IC reduces the integration time from t EXPOSURE to tINT (Fig. 3). This reduces the photosite signal in all photosites by the ratio EXPOSURE to t INT. Greater than 10:1 reduction in average photosite signal can be achieved with integration control. The integration-control and anti-blooming features can be imple- mented simultaneously. This is done by setting the φIC, clock-low level to approximately 5 to 7 volts. DEFINITION OF TERMS Charge-Coupled Device — A Charge-coupled device is a semi- conductor device in which finite isolated charge-packets are trans- ported from one position in the semiconductor to an adjacent posi- tion by sequential clocking of an array of gates. The charge-packets are minority carriers with respect to the semiconductor substrate. Sample -and Hold Clock φSHA, φSHB) — The voltage waveform applied to the sample-and-hold gates in the output amplifiers to cre- ate a continuous sampled video signal at the output. The sample- and-hold feature may be defeated by connecting φ SHA and φSHB to VDD. Dark Reference — Video output level generated from sensing elements covered with opaque metallization which provides a refer- ence voltage equivalent to device operation in the dark. This per- mits use of external DC restoration circuitry. Isolation Cell — This is a site on-chip producing an element in the video output that serves as a buffer between valid video data and dark reference signals. The output from an isolation cell contains no valid information and should be ignored. Dynamic Range — The saturation exposure divided by the RMS temporal noise equivalent exposure. Dynamic range is sometimes defined in terms of peak-to-peak noise. To compare the two defini- tions a factor of four to six is generally appropriate in that peak-to- peak noise is approximately equal to four to six times RMS noise. RMS Noise Equivalent Exposure — The exposure level that gives an output signal to the RMS noise level at the output in the dark. Saturation Exposure — The minimum exposure level that will provide a saturation output signal. Exposure is equal to the light intensity times the photosites integration time. Charge Transfer Efficiency — Percentage of valid charge in- formation that is transferred between each successive stage of the transport registers. Responsivity — The output signal voltage per unit exposure for a specified spectral type of radiation. Responsivity equals output volt- age divided by exposure. Total Photoresponse Non-uniformity — The difference of the response levels of the most and the least sensitive element under uniform illumination. Measurement of PRNU excludes first and last elements. Dark Signal — The output signal in the dark caused by thermally generated electrons that is a linear function of the integration time and highly sensitive to temperature. Saturation Output Voltage — The maximum usable signal out- put voltage. Charge transfer efficiency decreases sharply when the saturation output voltage is exceeded. Integration Time — The time interval between the falling edge of any two successive transfer pulses (φX). The integration is the time allowed for the photosites to collect charge. Exposure Time - The time interval between the falling edge of the two transfer pulses (φX) shown in the timing diagram. The exposure time is the time between transfers of signal charge from the photosites into the transport registers. Pixel - A picture element (photosite).

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181

Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500 CCD181 DEVICE CARE AND OPERATION Glass may be cleaned by saturating a cotton swab in alcohol and lightly wiping the surface. Rinse off the alcohol with deionized wa- ter. Allow the glass to dry, preferably by blowing with filtered dry N or air. It is important to note in design and applications considerations that the devices are very sensitive to thermal conditions. The dark sig- nal DC and low frequency components approximately double for every 5º C temperature increase and single-pixel dark signal non- uniformities approximately double for every 12º C temperature in- crease. The devices may be cooled to achieve very long integration times and very low light level capability. ORDER INFORMATION Order CCD181DC where “D” stands for a ceramic package and “C” for commercial temperature range.