CA16 AGERE | Alldatasheet
Document overview
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Technical content
Features
I 2.5 Gbits/s optical transmitter and receiver with 16-channel 155 Mbits/s multiplexer/demultiplexer. I Available with 1.55 µm cooled DFB laser transmit- ter and an APD receiver for long-reach applica- tions: — Offers 45 standard ITU wavelengths with 100 GHz spacing. — Each module is capable of two wavelengths under user control. I Pigtailed, low-profile package. I Differential L VPECL data interface. I Operating case temperature range: 0 °C to 65 °C. I Automatic transmitter optical power control. I Laser bias monitor output. I Transmitter laser disable input. I Line loopback and diagnostic loopback capability. I Multiple alarms: — Loss of signal. — Loss of reference clock. — Loss of framing. — Laser degrade alarm.
Applications
I Telecommunications: — Inter- and intraoffice SONET/SDH — Subscriber loop — Metropolitan area networks I High-speed data communications
Description
The CA16-type transponder performs the parallel-to- serial-to-optical transport and optical transport-to- serial-to-parallel function of the section and photonic layers of the SONET/SDH protocol. The CA16 trans- mitter section performs the bit serialization and opti- cal transmission of SONET/SDH OC-48/STM-16 data that has been formatted into standard SONET/ SDH compliant 16-bit parallel format. The CA16 receiver performs the optical-to-electrical conversion function and is then able to detect frame and byte boundaries and demultiplex the serial data into 16-bit parallel OC-48/STM-16 format. The CA16 transponder does not perform byte-level multiplexing or interleaving.
3Agere Systems Inc. Advance Data Sheet CA16-Type 2.5 Gbits/s DWDM Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demultiplexer Description (continued) Figure 1 shows a simplified block diagram of the CA16- T ype transponder. This device is a bidirectional module designed to provide a SONET or SDH compliant elec- tro-optical interface between the SONET/SDH photonic physical layer and the electrical section layer. The mod- ule contains a wavelength-tunable (two channels at 100 GHz) 2.5 Gbits/s optical transmitter and a
2.5 Gbits/s optical receiver in the same physical pack-
age along with the electronics necessary to multiplex and demultiplex sixteen 155 Mbits/s electrical channels. Clock synthesis, clock recovery, and SONET/SDH frame detection circuits are also included within the module. In the transmit direction, the transponder module multi- plexes sixteen 155 Mbits/s PECL electrical data signals into an optical signal at 2488.32 Mbits/s for launching into optical fiber. An internal 2.488 GHz reference oscil- lator is phase-locked to an external 155.52 MHz data timing reference. The optical transmitter is available at any ITU grid wavelength with a 1.55 µm cooled DFB laser for long- reach applications. The optical output signal is SONET and ITU compliant for OC-48/STM-16 applications as shown in Table 4, OC-48/STM-16 Transmitter Optical Characteristics. In the receive direction, the transponder module receives a 2488.32 Mbits/s optical signal and converts it to an electrical signal, and then extracts a clock sig- nal and demultiplexes the data into sixteen 155 Mbits/s differential LVPECL data signals. When enabled, the module can also detect SONET/SDH frame bound- aries. The optical receiver is available with an APD photodetector. The receiver operates over the wave- length range of 1.1 µm to 1.6 µm and is fully compliant to SONET/SDH OC-48/STM-16 physical layer specifi- cations as shown in Table 5, OC-48/STM-16 Receiver Optical Characteristics. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect reliability. 1. Human body model. Parameter Symbol Min Max Unit Operating Case Temperature Range T C 07 5 ° C Storage Case Temperature Range T S –40 85 °C Supply Voltage — –0.5 5.5 V Voltage on Any LVPECL Pin — 0 V CC — High-speed LVPECL Output Source Current — — 50 mA Static Discharge Voltage1 ESD — 500 V Relative Humidity (noncondensing) RH — 85 % Receiver Optical Input Power—Biased APD P IN —0 d B m Minimum Fiber Bend Radius — 1.25 (31.8) — in. (mm)
Figure 1. CA16-Type Transponder Block Diagram
Figure 2. CA16-Type Transponder Pinout
Table 1. CA16-Type Transponder Pinout
01 FGND I Supply Frame Ground 1
02 IPDMON O Analog Receiver Photodiode Current Monitor
03 TxDGND I Supply Transmitter Digital Ground
04 TxD15P I LVPECL Transmitter 155 Mbits/s MSB Data Input
05 TxD15N I LVPECL Transmitter 155 Mbits/s MSB Data Input
06 TxD13P I LVPECL T ransmitter 155 Mbits/s Data Input
07 TxD13N I LVPECL T ransmitter 155 Mbits/s Data Input
08 TxDGND I Supply Transmitter Digital Ground
09 TxD11P I LVPECL T ransmitter 155 Mbits/s Data Input
10 TxD11N I LVPECL T ransmitter 155 Mbits/s Data Input
11 TxD09P I LVPECL T ransmitter 155 Mbits/s Data Input
12 TxD09N I LVPECL T ransmitter 155 Mbits/s Data Input
13 TxDGND I SUPPL Y Transmitter Digital Ground
14 TxD07P I LVPECL T ransmitter 155 Mbits/s Data Input
15 TxD07N I LVPECL T ransmitter 155 Mbits/s Data Input
16 TxD05P I LVPECL T ransmitter 155 Mbits/s Data Input
17 TxD05N I LVPECL T ransmitter 155 Mbits/s Data Input
18 TxDGND I Supply Transmitter Digital Ground
19 TxD03P I LVPECL T ransmitter 155 Mbits/s Data Input
20 TxD03N I LVPECL T ransmitter 155 Mbits/s Data Input
21 TxD01P I LVPECL T ransmitter 155 Mbits/s Data Input
22 TxD01N I LVPECL T ransmitter 155 Mbits/s Data Input
23 TxDGND I Supply Transmitter Digital Ground
24 PIC
25 PIC LKN I LVPECL Byte-Aligned Parallel Input Clock at 155 MHz
26 LOCKDET O LVTTL Lock Detect
27 TxDGND I Supply Transmitter Digital Ground
30 TxAGND I Supply Transmitter Analog Ground
33 TxAGND I Supply Transmitter Analog Ground
34 LPM O Analog Laser Power Monitor
35 LSRALM O 5 V CMOS Laser Degrade Alarm
36 LSRBIAS O Analog Not Implemented on the CA16- Type Transponder
37 NC — — No User Connection Permitted
38 D LOOP I LVTTL Diagnostic Loopback
39 WDEA O 5 V CMOS Wavelength Deviation Error Alarm
40 FP O L VPECL Frame Pulse
41 FRAMEN I LVTTL Frame Enable
- Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
- Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC , Ground,
42 RxDGND I Supply Receiver Digital Ground
45 NC — — No User Connection Permitted
46 RxAGND I Supply Receiver Analog Ground
47 RxAGND I Supply Receiver Analog Ground
49 RxAGND I Supply Receiver Analog Ground
50 RxAGND I Supply Receiver Analog Ground
51 RxDGND I Supply Receiver Digital Ground
52 VTEC I Supply TEC Cooler 3 V Analog S upply Voltage
53 VTEC I Supply TEC Cooler 3 V Analog S upply Voltage
54 VTEC I Supply TEC Cooler 3 V Analog S upply Voltage
55 RxDGND I Supply Receiver Digital Ground
56 RxQ14P O LVPECL Receiver 155 Mbits/s Data Output
57 RxQ14N O LVPECL Receiver 155 Mbits/s Data Output
58 RxQ12P O LVPECL Receiver 155 Mbits/s Data Output
59 RxQ12N O LVPECL Receiver 155 Mbits/s Data Output
60 RxDGND I Supply Receiver Digital Ground
61 RxQ10P O LVPECL Receiver 155 Mbits/s Data Output
62 RxQ10N O LVPECL Receiver 155 Mbits/s Data Output
63 RxQ08P O LVPECL Receiver 155 Mbits/s Data Output
64 RxQ08N O LVPECL Receiver 155 Mbits/s Data Output
65 RxDGND I SUPPL Y Receiver Digital Ground
66 RxQ06P O LVPECL Receiver 155 Mbits/s Data Output
67 RxQ06N O LVPECL Receiver 155 Mbits/s Data Output
68 RxQ04P O LVPECL Receiver 155 Mbits/s Data Output
69 RxQ04N O LVPECL Receiver 155 Mbits/s Data Output
70 RxDGND I Supply Receiver Digital Ground
71 RxQ02P O LVPECL Receiver 155 Mbits/s Data Output
72 RxQ02N O LVPECL Receiver 155 Mbits/s Data Output
73 RxQ00P O LVPECL Receiver 155 Mbits/s LSB Data Output
74 RxQ00N O LVPECL Receiver 155 Mbits/s LSB Data Output
75 RxDGND I Supply Receiver Digital Ground
76 NC — — No User Connection Permitted
77 NC — — No User Connection Permitted 2
78 NC — — No User Connection Permitted 2
79 NC — — No User Connection Permitted 2
80 FGND I Supply Frame Ground 1
81 FGND I Supply Frame Ground 1
82 Reset I — Master Reset
Table 1. CA16-Type Transponder Pinout (continued)
- Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
- Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC , Ground,
83 TxDGND I Supply Transmitter Digital Ground
84 TxR EF C LKP I LVPECL Transmitter 155 Mbits/s Reference Clock Input
85 TxR EF C LKN I LVPECL T ransmitter 155 Mbits/s Reference Clock Input
86 TxD14P I LVPECL T ransmitter 155 Mbits/s Data Input
87 TxD14N I LVPECL T ransmitter 155 Mbits/s Data Input
88 TxDGND I Supply Transmitter Digital Ground
89 TxD12P I LVPECL T ransmitter 155 Mbits/s Data Input
90 TxD12N I LVPECL T ransmitter 155 Mbits/s Data Input
91 TxD10P I LVPECL T ransmitter 155 Mbits/s Data Input
92 TxD10N I LVPECL T ransmitter 155 Mbits/s Data Input
93 TxDGND I SUPPL Y Transmitter Digital Ground
94 TxD08P I LVPECL T ransmitter 155 Mbits/s Data Input
95 TxD08N I LVPECL T ransmitter 155 Mbits/s Data Input
96 TxD06P I LVPECL T ransmitter 155 Mbits/s Data Input
97 TxD06N I LVPECL T ransmitter 155 Mbits/s Data Input
98 TxDGND I Supply Transmitter Digital Ground
99 TxD04P I LVPECL T ransmitter 155 Mbits/s Data Input
100 TxD04N I LVPECL T ransmitter 155 Mbits/s Data Input
101 TxD02P I LVPECL T ransmitter 155 Mbits/s Data Input
102 TxD02N I LVPECL T ransmitter 155 Mbits/s Data Input
103 TxDGND I SUPPL Y Transmitter Digital Ground
104 TxD00P I LVPECL Transmitter 155 Mbits/s LSB Data Input
105 TxD00N I LVPECL Transmitter 155 Mbits/s LSB Data Input
106 TxDGND I Supply Transmitter Digital Ground
108 PC LKN I LVPECL Transmitter Parallel Reference Clock Output
109 TxDGND I Supply Transmitter Digital Ground
110 TxAGND I Supply Transmitter Analog Ground
113 NC — — Future Function (I
114 PHINIT I LVPECL Phase Initialization
115 T XDIS I TTL Transmitter Disable
116 NC — — Future Function (I 2C Data)
117 PHERR O LVPECL Phase Error
118 L LOOP I LVTTL Line Loopback (active-low)
119 LOS O LVTTL Loss of Signal
120 RxDGND I Supply Receiver Digital Ground
121 OOF I LVTTL Out of Frame (enable frame detection)
122 RxDGND I Supply Receiver Digital Ground
- Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
- Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC , Ground,
- Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
- Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC , Ground, or any signal
125 SEARCH O LVTTL Frame Search Output
126 RxAGND I Supply Receiver Analog Ground
127 RxAGND I Supply Receiver Analog Ground
129 POC
130 POC LKN O LVPECL Byte-Aligned Parallel Output Clock at 155 MHz
131 NC — — No User Connection Permitted 2
132 WS I LVTTL Binary Input to Select One of Two Grid Wavelengths
133 VTEC I Supply TEC Cooler 3 V Analog Supply Voltage
134 VTEC I Supply TEC Cooler 3 V Analog Supply Voltage
135 RxDGND I Supply Receiver Digital Ground
136 RxQ15P O LVPECL Receiver MSB 155 Mbits/s Data Output
137 RxQ15N O LVPECL Receiver MSB 155 Mbits/s Data Output
138 RxQ13P O LVPECL Receiver 155 Mbits/s Data Output
139 RxQ13N O LVPECL Receiver 155 Mbits/s Data Output
140 RxDGND I Supply Receiver Digital Ground
141 RxQ11P O LVPECL Receiver 155 Mbits/s Data Output
142 RxQ11N O LVPECL Receiver 155 Mbits/s Data Output
143 RxQ09P O LVPECL Receiver 155 Mbits/s Data Output
144 RxQ09N O LVPECL Receiver 155 Mbits/s Data Output
145 RxDGND I Supply Receiver Digital Ground
146 RxQ07P O LVPECL Receiver 155 Mbits/s Data Output
147 RxQ07N O LVPECL Receiver 155 Mbits/s Data Output
148 RxQ05P O LVPECL Receiver 155 Mbits/s Data Output
149 RxQ05N O LVPECL Receiver 155 Mbits/s Data Output
150 RxDGND I Supply Receiver Digital Ground
151 RxQ03P O LVPECL Receiver 155 Mbits/s Data Output
152 RxQ03N O LVPECL Receiver 155 Mbits/s Data Output
153 RxQ01P O LVPECL Receiver 155 Mbits/s Data Output
154 RxQ01N O LVPECL Receiver 155 Mbits/s Data Output
155 RxDGND I Supply Receiver Digital Ground
156 NC — — No User Connection Permitted
157 NC — — No User Connection Permitted 2
158 NC — — No User Connection Permitted 2
159 NC — — No User Connection Permitted 2
160 FGND I Supply Frame Ground 1
- Future versions of the cooled transponder will not support the frame-detect function.
Table 2. CA16-Type Transponder Input Pin Descriptions into the holding register of the parallel-to-serial converter. register. Input is internally terminated and biased. See discussion on timing interface, page 18. 0.8 nm (100 GHz frequency decrease). path from the optical receiver is disabled. serial data from the parallel-to-serial converter is ignored. disabled. Frame-detection process is initiated by rising edge of out-of-frame pulse.
- Future versions of the cooled transponder will not support the frame-detect function.
Table 3. CA16-Type Transponder Output Pin Descriptions word. RxQ15P/N is the most significant bit of the received word and is the first bit serialized. updated on the falling edge of POCLK. mum of one 155 MHz clock period beyond the third A2 byte before it will be set low. LSRBIAS Laser Bias Alarm (Analog). The analog bias alarm is not available on the CA16 transponders. degrades 2 dB below the nominal output power. should increase by 3 dB, this output will increase to 1000 mV. domain. PHERR is updated on the falling edge of the PCLK outputs. ~800 mV , depending on the optical input power. transmitter’s wavelength deviates from the nominal wavelength by more than ±100 pm. nal provided at the TXR EF C LK input pins. LOCKDET is an asychronous output.
1212 Agere Systems Inc. CA16-Type 2.5 Gbits/s DWDM Transponder with Advance Data Sheet 16-Channel 155 Mbits/s Multiplexer/Demultiplexer March 2001 Functional Description Receiver The optical receiver in the CA16-type transponder has an APD and is optimized for the particular SDH/SONET application segment in which it was designed to operate. The detected serial data output of the optical receiver is connected to a clock and data recovery circuit (CDR), which extracts a 2488.32 MHz clock signal. This recov- ered serial bit clock signal and a retimed serial data signal are presented to the 16-bit serial-to-parallel converter and to the frame and byte detection logic. The serial-to-parallel converter consists of three 16-bit registers. The first is a serial-in parallel-out shift register, which performs serial-to-parallel conversion. The second is an internal 16-bit holding register, which transfers data from the serial-to-parallel register on byte boundaries as determined by the frame and byte detection logic. On the falling edge of the free-running POC LK signal, the data in the holding register is transferred to the output holding register where it becomes available as RxQ[0:15]. Note: Future versions of the cooled transponder will not support the frame-detect function. The frame and byte boundary detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by an A2 byte. Framing pattern detection is enabled and disabled by the FRAMEN input. The frame detection process is started by a rising edge on OOF while FRAMEN is active (FRAMEN = high). It is disabled when a framing pattern is detected. When framing pattern detection is enabled (FRAMEN = high), the framing pat- tern is used to locate byte and frame boundaries in the incoming serial data stream from the CDR circuits. During this time, the parallel output data bus (RxQ[0:15]) will not contain valid data. The timing generator circuitry takes the located byte boundary and uses it to block the incoming serial data stream into bytes for output on the parallel out- put data bus (RxQ[0:15]). The frame boundary is reported on the framing pulse (FP) output when any 32-bit pattern matching the framing pattern is detected in the incoming serial data stream. When framing detection is disabled (FRAMEN = low), the byte boundary is fixed at the loca- tion found when frame detection was previously enabled. Transmitter The optical transmitter in the CA16-type transponder is optimized for the particular SDH/SONET segment in which it is destined to operate. The transmitter has a cooled DFB laser as the optical element and operates at a nominal 1550 nm (45 standard ITU wavelengths are avail- able for DWDM applications). Under user control, the transmitter can switch to either one of two adjacent ITU wavelengths (100 GHz spacing). The transmitter is driven by a serial data stream developed in the parallel-to-serial conversion logic and by a 2488.32 MHz serial bit clock sig- nal synthesized from the 155.52 MHz T XR EF C LK input. Note that the clock divider and phase-detect circuitry shown in Figure 1 generates internal reference clocks and timing functions for the transmitter. Therefore, it is impor- tant that the TxR EF C LK input is generated from a precise and stable source. To prevent internal timing signals from producing jitter in the transmitted serial data that exceeds the SDH/SONET jitter generation requirements of 0.01 UI, it is required that the TxR EF C LK input be generated from a crystal oscillator or other source having a frequency accu- racy better than 20 ppm. In order to meet the SDH/ SONET jitter generation requirement, the reference clock jitter must be guaranteed to be less than 1 ps rms over the 12 kHz to 20 MHz bandwidth. When used in SONET net- work applications, this input clock must be derived from a source that is synchronized to the primary reference clock. The timing generation circuitry provides two separate functions. It develops a byte rate clock that is synchro- nized to the 2488.32 MHz transmit serial clock, and it pro- vides a mechanism for aligning the phase between the incoming byte clock (PIC LK) and the clock that loads the parallel data from the input register into the parallel-to- serial shift register. The PC LK output is a byte rate (155 MHz) version of the serial transmit clock and is intended for use by upstream multiplexing and overhead processing circuits. Using PC LK for upstream circuits will ensure a stable frequency and phase relationship between the parallel data coming into the transmitter and the subsequent parallel-to-serial timing functions. In the parallel-to-serial conversion pro- cess, the incoming data is passed from the PIC LK byte clock timing domain to the internally generated byte clock timing domain that is phase aligned to the internal serial transmit clock. The timing generator also produces a feed- back reference clock to the phase detector. A counter divides the synthesized clock down to the same frequency as the reference clock TxR EF C LK. The parallel-to-serial converter shown in Figure 1 is com- prised of an FIFO and a parallel-to-serial register. The FIFO input latches the data from the TxD[0:15]P/N bus on the rising edge of PIC LK. The parallel-to-serial register is a loadable shift register that takes parallel input from the FIFO output. An internally generated divide-by-16 clock, which is phase aligned to the transmit serial clock, as described above, activates the parallel data transfer between registers. The serial data is shifted out of the par- allel-to-serial register at the transmit serial clock rate.
Minimum and maximum values specified over operating case temperature range at 50% duty cycle data signal. Typical values are measured at room temperature unless otherwise noted. Table 4. OC-48/STM-16 Transmitter Optical Characteristics (Tc = 0 °C to 65 °C)
- Output power definitions and measurements per ITU-T Recommendation G.957.
- Full spectral width measured 20 dB down from the central wavelength peak under fully modulated conditions.
- Ratio of the average output power in the dominant longitudinal mode to the power in the most significant side mode under fully modulated
- Ratio of logic 1 output power to logic 0 output power under fully modulated conditions.
- GR-253-CORE, Synchronous Optical Network (SONET) T ransport Systems: Common Generic Criteria.
- ITU-T Recommendation G.957, Optical Interfaces for Equipment and Systems Relating to the Synchronous Digital Hierarchy.
Table 5. OC-48/STM-16 Receiver Optical Characteristics (Tc = 0 °C to 65 °C)
- At 1310 nm, 1 x 10–10 BER, 223 – 1 pseudorandom data input.
16 Agere Systems Inc. CA16-Type 2.5 Gbits/s DWDM Transponder with Advance Data Sheet 16-Channel 155 Mbits/s Multiplexer/Demultiplexer March 2001
Electrical Characteristics
Table 6. Power Supply Characteristics (Tc = 0 °C to 65 °C) Table 7. Transmitter Electrical I/O Characteristics (TC = 0 °C to 65 °C, VCC = 3.3 V ± 5%)
- Internally biased and ac-coupled.
- The transmitter is normally enabled and only requires an external voltage to disable.
- The WDEA alarm becomes active when the optical wavelength deviates from the nominal center wavelength by more than 100 pm.
- Set at 500 mV at nominal optical output power. Provides linear P
- Terminated into 200 Ω to GND and 100 Ω line-to-line.
Parallel Input Clock PIC LKP/N Diff. Reference Clock Freq. T olerance TxR EF C LKP/N Diff.
- Internally biased and ac-coupled.
- The transmitter is normally enabled and only requires an external voltage to disable.
- The WDEA alarm becomes active when the optical wavelength deviates from the nominal center wavelength by more than 100 pm.
- Set at 500 mV at nominal optical output power. Provides linear PO tracking (–3 dB = 250 mV, +3 dB = 1000 V).
- T erminated into 200 Ω to GND and 100 Ω line-to-line.
Table 8. Receiver Electrical I/O Characteristics (Tc = 0 °C to 65 °C, Vcc = 3.3 V ± 5%)
- T erminated into 330 Ω to ground.
Table 7. Transmitter Electrical I/O Characteristics (TC = 0 °C to 65 °C, VCC = 3.3 V ± 5%) (continued)
1818 Agere Systems Inc. CA16-Type 2.5 Gbits/s DWDM Transponder with Advance Data Sheet 16-Channel 155 Mbits/s Multiplexer/Demultiplexer March 2001 Timing Characteristics Transmitter Data Input Timing The CA16 transponder utilizes a unique FIFO to decouple the internal and external (PICLK) clocks. The FIFO can be initialized, which allows the system designer to have an infinite PC LK-to-PICLK delay through this interfacing logic (ASIC or commercial chip set). The configuration of the FIFO is dependent upon the I/O pins, which comprise the synch timing loop. This loop is formed from PHERR to PHINIT and PC LK to PICLK. The FIFO can be thought of as a memory stack that can be initialized by PHINT or LOCKDET. The PHERR signal is a pointer that goes high when a potential tim- ing mismatch is detected between PIC LK and the inter- nally generated PCLK clock. When PHERR is fed back to PHINIT, it initializes the FIFO so that it does not over- flow or underflow. The internally generated divide-by-16 clock is used to clock-out data from the FIFO. PHINIT and LOCKDET signals will center the FIFO after the third PIC LK pulse. This is done to ensure that PICLK is stable. This scheme allows the user to have an infinite PCLK to PICLK delay through the ASIC. Once the FIFO is cen- tered, the PCLK and PICLK can have a maximum drift of ±5 ns. During normal operation, the incoming data is passed from the PICLK input timing domain to the internally generated divide-by-16 PCLK timing domain. Although the frequency of PICLK and PCLK is the same, their phase relationship is arbitrary. To prevent errors caused by short setup or hold times between the two domains, the timing generator circuitry monitors the phase rela- tionship between PIC LK and PCLK. When an FIFO timing violation is detected, the phase error (PHERR) signal pulses high. If the condition per- sists, PHERR will remain high. When PHERR is fed back into the PHINIT input (by shorting them on the printed-circuit board [PCB]), PHINIT will initialize the FIFO if PHINIT is held high for at least two byte clocks. The initialization of the FIFO prevents PC LK and PICLK from concurrently trying to read and write over the same FIFO bank. During realignment, one-to-three bytes (16 bits wide) will be lost. Alternatively, the customer logic can take in the PHERR signal, process it, and send an output to the PHINIT input in such a way that only idle bytes are lost during the initialization of the FIFO. Once the FIFO has been initialized, PHERR will go inactive.
ation on the same bank in the FIFO at the same time. Figure 5. Block Diagram Timing Mode 1
155.52 MHz ± 20 ppm
should continue until PHERR goes low. Figure 6. Block Diagram Timing Mode 2
a reference clock generated from the customer logic. Figure 7. Forward Clocking of the CA16 Transponder
tCH cannot be more than 5.2 ns. Figure 8. PCLK -to-PICLK Timing PICLK AFTER LOCKDET GOES ACTIVE.
goes active once the FIFI is initialized. Figure 9. PHERR/PHINIT Timing
2 BYTE
2 BYTE CLOCKS UPON DETECTING
Figure 14. FRAMEN Timing increase approximately 0.8 nm). during the wavelength change process.
27Agere Systems Inc. Advance Data Sheet CA16-Type 2.5 Gbits/s DWDM Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demultiplexer Qualification and Reliability To help ensure high product reliability and customer satisfaction, Agere Systems Inc. is committed to an intensive quality pro-gram that starts in the design phase and proceeds through the manufacturing process. Optoelectronics modules are qualified to Agere internal standards using MIL-STD-883 test methods and procedures and using sampling techniques consistent with T elcordia T echnologies * requirements. This qualification program fully meets the intent of Telcordia Technologies reliability practices TR-NWT -000468 and T A - T SY-000983. In addition, the Agere Optoelectronics design, development, and manufacturing facility has been certified to be in full compliance with the latest ISO † 9001 Quality System Standards. * T elcordia T echnologies is a trademark of T elcordia T echnologies, Inc. † ISO is a registered trademark of The International Organization for Standardization. Laser Safety Information Class I Laser Product All versions of the CA16-type transponders are classified as Class I laser products per FDA/CDRH, 21 CFR 1040 Laser Safety requirements. The transponders have been registered/certified with the FDA under accession number 8720009. All versions are classified as Class I laser products per IEC ‡ 825-1:1993. CAUTION: Use of controls, adjustments, and procedures other than those specified herein may result in hazardous laser radiation exposure. This product complies with 21 CFR 1040.10 and 1040.11. 8.8 µm single-mode pigtail with connector. Wavelength = 1.5 µm. Maximum power = 2.0 mW. Product is not shipped with power supply. Because of size constraints, laser safety labeling is not affixed to the module but is attached to the outside of the shipping carton. NOTICE Unterminated optical connectors can emit laser radiation. Do not view with optical instruments. Electromagnetic Emissions and Immunity The CA16 transponder will be tested against CENELEC E N50 081 part 1 and part 2, FCC 15, Class B limits for emissions. The CA16 transponder will be tested against CENELEC E N50 082 part 1 immunity requirements. ‡ IEC is a registered trademark of The International Electrotechnical Commission.
28 Agere Systems Inc. CA16-Type 2.5 Gbits/s DWDM Transponder with Advance Data Sheet 16-Channel 155 Mbits/s Multiplexer/Demultiplexer March 2001 Outline Diagram Dimensions are in inches and (millimeters) (for initial samples; production version will be slightly smaller). 1-1103(F) 4.00 (101.6) 3.50 (88.9) 1.02 (25.91) 0.76 (19.3) 0.25 (6.4) 1.65 (41.9) 0.015 (0.38) 0.20 (5.08) 0.29 (7.4) 0.17 (4.3) 0.45 (11.4) 1.84 (46.7) 0.83 (21.1) 1.70 (43.2) 1.80 (45.7) (3x) M2.5 x 0.45 MOUNTING HOLES 2 mm MAXIMUM LENGTH INTO PACKAGE
29Agere Systems Inc. Advance Data Sheet CA16-Type 2.5 Gbits/s DWDM Transponder with March 2001 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Ordering Information
- Other connectors may be made available.
Table 11. Ordering Information † For specific order codes for these products, please contact your local Agere account manager. Table 12. Related Product Information
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liabi lity is assumed as a result of their use or application. ST is a registered trademark of Agere Systems Inc. Copyright © 2001 Agere Systems Inc. All Rights Reserved Printed in U.S.A. March 2001 DS01-120OPTO (Replaces DS99-352LWP) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F , T ower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (T okyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, T AIWAN: (886) 2-2725-5858 (T aipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045