C541U

C541U SIEMENS | Alldatasheet

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Edition 05.99 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73,

81541 München

© Siemens AG 6/2/99. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Com- panies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please con- tact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! C541U Data Sheet Revision History : 05.99 Previous Releases : 10.97(Original Version) Page (10.97 version) Page (05.99 version) Subjects (changes since last revision) All sections All sections 6 to 9 39 to 40 All sections All sections 5 to 8 38 to 39 All references to C540U is removed. V CC is changed to VDD . Compliant to USB Specification “Rev 1.0”. Power supply voltage range changed to 4.25V to 5.5V. Line “* P-SDIP-52 package ...” is added. Table 1 is removed and replaced by “Ordering Information”. Figure 3; pin 2 is changed to ECAP. Figure 4 is removed. Table 1; column P-SDIP-52 is deleted and any references to P-SDIP-52 is also removed, the definition of pin 2 is changed to ECAP. Table 3; modified with addition of bit DRVI in GEPIR register. Table 4; modified with addition of bits DRVIE and XVREG in DPWDR register. First sentence; reference to P-SDIP-52 is removed. Figure 16 is modified to include DRVI and DRVIE. Figure 22 is removed. Table 8; column P-SDIP-52 is removed. “Absolute Maximum Ratings” is changed to tabular form. Fifth line; “During overload conditions ...” changed to “During absolute maximum rating conditons ...”. “Operating Conditions” is added. V DD is changed to 4.25V to 5.5V (5V +10%, -15%) “VCC = 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”. VIH min of EA is changed to 0.6 VDD . VOL max of Port 0 is changed to 0.6 V. IIL max is changed to -60 µA. Values for IDD (active and idle mode) and IPD Notes (6); modified. “VCC = 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”. “VCC = 5 V + 10% ... “ is replaced by “(Operating Conditions apply)”. Figure 37 is added. Figure 40 is removed.

8-Bit CMOS Microcontroller Advance Information C541U

• Enhanced 8-bit C500 CPU – Full software/toolset compatible to standard 80C51/80C52 microcontrollers
• 12 MHz external operating frequency – 500 ns instruction cycle
• Built-in PLL for USB synchronization
• On-chip OTP program memory – 8K byte – Alternatively up to 64K byte external program memory – Optional memory protection
• On-chip USB module – Compliant to USB specification Rev1.0 – Full speed or low speed operation – Five endpoints : one bidirectional control endpoint four versatile programmable endpoints – Registers are located in special function register area – On-chip USB transceiver Figure 1 C541U Functional Units SSC T0 CPU Port 0 Port 1 Port 2 Port 3 I/O I/O OTP Prog. Memory Watchdog I/O I/O On-Chip Emulation Support Module Module RAM 256 × 8Timer Oscillator Watchdog Power Saving Modes USB Transceiver D+ D- USB 8k× 8

Features (continued) :

• Up to 64K byte external data memory
• 256 byte on-chip RAM
• Four parallel I/O ports – P-LCC-44 package : three 8-bit ports and one 6-bit port – P-SDIP-52* package : four 8-bit ports – LED current drive capability for 3 pins (10 mA)
• Two 16-bit timer/counters (C501 compatible)
• SSC synchronous serial interface (SPI compatible) – Master and slave capable – Programmable clock polarity / clock-edge to data phase relation – LSB/MSB first selectable – 1.5 MBaud transfer rate at 12 MHz operating frequency
• 7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels
• Enhanced fail safe mechanisms – Programmable watchdog timer – Oscillator watchdog
• Power saving modes – idle mode – software power down mode with wake-up capability through INT0 pin or USB
• On-chip emulation support logic (Enhanced Hooks Technology TM)
• P-LCC-44 and P-SDIP-52* packages
• Power supply voltage range : 4.25V to 5.5V
• Temperature Range : TA = 0 to 70°C * P-SDIP-52 package is available on specific request from customer

Pin Configuration (Top View) P1.5/SLS P1.3/SRI 5 4 3 2 1 4 44 34 24 14 0 18 19 20 21 22 23 24 25 26 27 P1.1/LED1 P1.0/LED0 ECAP VDDU P1.2/SCLK VDD VSS P3.0/LED2 P3.1/DADD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VDD P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 RESET P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA P1.4/STO PSEN P2.7/A15 P2.6/A14 P2.5/A13 ALE C541U

Pin Definitions and Functions Symbol Pin Numbers I/O*) Function P-LCC-44 D+ 3 I/O USB D+ Data Line The pin D+ can be directly connected to USB cable (transceiver is integrated on-chip). D- 4 I/O USB D- Data Line The pin D- can be directly connected to USB cable (transceiver is integrated on-chip). P1.0 - P1.4 5 - 7, 12, 34, 44 I/O Port 1 is an 6-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 1 also contains two outputs with LED drive capability as well as the four pins of the SSC. The pins with LED drive capability are able to sink current up to 10 mA. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / LED0 LED0 output P1.1 / LED1 LED1 output P1.2 / SCLK SSC Master Clock Output / SSC Slave Clock Input P1.3 / SRI SSC Receive Input P1.4 / STO SSC Transmit Output P1.5 / SLS SSC Slave Select Inp. RESET 10 I RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the C541U. A small internal pulldown resistor permits power-on reset using only a capacitor connected to V DD . *) I = Input O = Output

P3.0 - P3.7 11, 13 - 19 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The pin with LED drive capability are able to sink current up to 10 mA. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / LED2 LED2 output P3.1 / DADD Device attached input P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory XTAL2 20 – XTAL2 is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator. XTAL1 21 – XTAL1 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Numbers I/O*) Function P-LCC-44

P2.0 - P2.7 24 - 31 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. PSEN

32 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. The signal remains high during internal program execution. ALE 33 O The Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every three oscillator periods except during an external data memory access. EA

35 I External Access Enable

When held high, the C541U executes instructions from the internal OTP program memory as long as the PC is less than 2000H for the C541U. When held low, the C541U fetches all instructions from external program memory. For the C541U-L this pin must be tied low. P0.0 - P0.7 43 - 36 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high- impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Numbers I/O*) Function P-LCC-44

ECAP 2 – External Capacitor This pin is required to be connected to an external capacitor which is connected to V SS . The recommended value for the capacitor is 6.8 nF. VDDU 1– Supply voltage for the on-chip USB transceiver circuitry VDD 8, 23 – Supply voltage for ports and internal logic circuitry during normal, idle, and power down mode. VSS 9, 22 – Ground (0V) during normal, idle, and power down mode. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Numbers I/O*) Function P-LCC-44

Block Diagram of the C541U Port 0 8-bit digit. I/O Port 2 8-bit digit. I/O Port 3 8-bit digit. I/O Port 0 Port 1 Port 2 Port 3 OSC & Timing CPU Timer 0 Interrupt Unit XTAL2 XTAL1 RESET ALE PSEN EA Port 1 6-bit digit. I/O 256 x 8 RAM Timer Progr. Watchdog Emulation Support Logic Oscillator Watchdog OTP Timer 1 SSC (SPI) Interface USB Module Memory C541U 8k x 8 PLL Transceiver

The C541U is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three- byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 500ns. Special Function Register PSW (Address D0H ) Reset Value : 00 H Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank Select Control Bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 PD0 H PSW D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VDD via a capacitor. Figure 6 shows the possible reset circuitries. Figure 6 Reset Circuitries RESET RESET RESET VDD VDDVDD C541U C541U C541U

The oscillator and clock generation circuitry of the C541U is shown in figure 5-7. The crystal oscillator generates the system clock for the microcontroller. The USB module can be provided with the following clocks : – Full speed operation : 48 MHz with a data rate of 12 Mbit/s – Low speed operation : 6 MHz with a data rate of 1.5 Mbit/s The low speed clock is generated by a dividing the system clock by 2. The full speed clock is generated by a PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general enable bit for the USB clock. Figure 7 Block Diagram of the Clock Generation Circuitry XTAL1 Crystal Oscillator XTAL2 Pin Pin System clock of the microcontroller

6 MHz

DCR.1 PLL x 4

48 MHz

DCR.7 to USB Module DCR.0 PCLKEnable

12 MHz

The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 8 shows the recommended oscillator circuits for crystal and external clock operation. Figure 8 Recommended Oscillator Circuitries XTAL1 XTAL2 C C MHz C = 20pF ± 10pF for crystal operation C541U External Clock Signal VDD N.C. XTAL2 XTAL1 C541U

Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens. MCS02647 SYSCON PCON TCON RESET EA PSEN ALE Port 0 Port 2 I/O Ports Optional Port 3 Port 1 C500 MCU Interface Circuit Enhanced Hooks RPort 0RPort 2 RTCON RPCON RSYSCON TEA TALE TPSEN EH-IC Target System Interface ICE-System Interface to Emulation Hardware

Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. One special function register of the C541U (PCON1) is located in the mapped special function register area. All other SFRs are located in the standard special function register area. For accessing PCON1 in the mapped special function register area, bit RMAP in special function register SYSCON must be set. Special Function Register SYSCON (Address B1H ) Reset Value : XX10XXXX B As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. The registers, except the program counter and the four general purpose register banks, reside in the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H , 88H , 90H , 98H , ..., F8H , FFH ) are bitaddressable. The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C541U are listed in table 2 to table 4. In table 2 they are organized in groups which refer to the functional blocks of the C541U. Table 4 and table 4 illustrate the contents of the SFRs in numeric order of their addresses. Bit Function RMAP Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area (PCON1) is enabled. 76543210 EALE RMAP –B1H SYSCON Bit No. MSB LSB The functions of the shaded bits are not described in this section.

Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL PSW SP VR0 VR1 VR2 SYSCON Accumulator B Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Version Register 0 Version Register 1 Version Register 2 System Control Register E0H F0H 83H 82H D0 H 81H FC H FD H FE H B1H 00H 00H 00H 00H 00H 07H C5 H C1 H YY H XX10XXXX B Interrupt System IEN0 IEN1 IP0 IP1 ITCON Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 External Interrupt Trigger Condition Register A8 H A9H B8 H B9H 9AH 0XXX0000 B XXXXX000 B XXXX0000 B XXXXX000 B XXXX1010 B Ports P0 Port 0 Port 1 Port 2 Port 3 80H 90H A0 H B0 H FFH FFH FFH FFH Timer 0 / Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H SSC Interface SSCCON STB SRB SCF SCIEN SSCMOD SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register 93H 94H 95H AB H AC H 96H 07H XX H XX H XXXXXX00 B XXXXXX00 B 00H Watchdog WDCON WDTREL Watchdog Timer Control Register Watchdog Timer Reload Register C0 H 86H XXXX0000 B 00H 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) The content of this SFR varies with the actual of the step C541U (eg. 01H for the first step) 4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Pow. Sav. Modes PCON PCON1 Power Control Register Power Control Register 1 87H 88H X00X0000 B 0XX0XXXX B USB Module EPSEL USBVAL ADROFF GEPIR DCR DPWDR DIER DIRR FNRL FNRH EPBCn EPBSn 1) EPIEn 1) EPIRn 1) EPBAn 1) EPLENn 1) USBPWD 4) USBDCR 4) USBDR0 4) USBDR1 4) USBDR2 4) USBDR3 4) USBDR4 4) USBDR5 4) USBDR6 4) USBDR7 4) USB Endpoint Select Register USB Data Register USB Address Offset Register USB Global Endpoint Interrupt Request Reg. USB Device Control Register USB Device Power Down Register USB Device Interrupt Control Register USB Device Interrupt Request Register USB Frame Number Register, Low Byte USB Frame Number Register, High Byte USB Endpoint n Buffer Control Register USB Endpoint n Buffer Status Register USB Endpoint n Interrupt Enable Register USB Endpoint n Interrupt Request Register USB Endpoint n Base Address Register USB Endpoint n Buffer Length Register USB Power Down Register USB Control Register USB Data Register 0 USB Data Register 1 USB Data Register 2 USB Data Register 3 USB Data Register 4 USB Data Register 5 USB Data Register 6 USB Data Register 7 D2 H D3 H D4 H D6 H C1 H C2 H C3 H C4 H C6 H C7 H C1 H C2 H C3 H C4 H C5 H C6 H E6H E7H E8H E9H EA H EB H EC H ED H EE H EF H 80H 00H 00H 00H 000X0000B 00H 00H 00H XX H 00000XXX B 00H 20H 00H 10H 00H 0XXXXXXX B 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 1) These register are multiple registers (n=0-4) with the same SFR address; selection of register “n“ is done by SFR EPSEL. 2) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset. 3) The reset value of EPIR0 is 11 H . 4) These registers are only used in USB low-speed operation. Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Reset Value1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 86H WDTREL 00 H WDT PSEL 87H PCON X00X- 0000B – PDS IDLS – GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 2) 3) PCON1 0XX0- XXXX B 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 2) P1 FFH .7 .6 SLS STO SRI SCLK LED1 LED0 93H SSCCON 07H SCEN TEN MSTR CPOL CPHA BRS2 BRS1 BRS0 94H 95H 96H SSCMOD 00H LOOPB T R I O 00000L S B S M 9AH ITCON XXXX- 1010B – – – – I1ETF I1ETR I0ETF I0ETR A0H A8H 2) IEN0 0XXX- 0000B EA – – – ET1 EX1 ET0 EX0 A9H IEN1 XXXX- X000B AB H SCF XXXX- XX00 B 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

2) P3 FFH RD WR T1 T0 INT1 INT0 DADD LED2 B1H SYSCON XX10- XXXX B B8H 2) IP0 XXXX- 0000B – – – – PT1 PX1 PT0 PX0 B9H IP1 XXXX- X000B C0 H 2) WDCON XXXX- 0000B – – – – OWDS WDTS WDT SWDT C1 H to C7H USB Device and Endpoint Register definition see table 3-3 D0 H PSW 00H CY AC F0 RS1 RS0 OV F1 P D2 H EPSEL 80 H EPS7 0 0 0 0 EPS2 EPS1 EPS0 D4 H ADROFF 00 H 6) 0 0 AO5 AO4 AO3 AO2 AO1 AO0 D6 H GEPIR 00 H DRVI 0 0 EPI4 EPI3 EPI2 EPI1 EPI0 E0H E6H 7) USBPWD 00 H 00 SUSPIE DADDIE SUSP DADD TPWD RPWD E7H 7) USBDCR 00 H TYPE3 TYPE2 TYPE1 TYPE0 LEN3 LEN2 LEN1 LEN0 E8H E9H EA H EB H EC H ED H EE H 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers 5) The content of this SFR varies with the actual step of the C541U (e.g. 01 H for the first step) 6) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset 7) These registers are only used in USB low-speed operation. Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Reset Value1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

3) 4) VR1 C1 H 11000001 FE H 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers 5) The content of this SFR varies with the actual step of the C541U (e.g. 01 H for the first step) 6) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset. 7) These registers are only used in USB low-speed operation. Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Reset Value1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H ) Addr Register Reset Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EPSEL = 1XXX.XXXX B Device Registers C1 H DCR 000X. 0000B SPEED DA SWR SUSP DINIT RSM UCLK PCLK C2 H DPWDR 00 H DRVIE XVREG 0 0 0 0 TPWD RPWD C3 H DIER 00 H SE0IE DAIE DDIE SBIE SEIE STIE SUIE SOFIE C4 H DIRR 00 H SE0I DAI DDI SBI SEI STI SUI SOFI C5 H reserved C6 H FNRL XX H FNR7 FNR6 FNR5 FNR4 FNR3 FNR2 FNR1 FNR0 C7 H FNRH 0000. 0XXX B 0 0 0 0 0 FNR10 FNR9 FNR8 EPSEL = 0XXX.X000 B Endpoint 0 Registers C1 H EPBC0 00 H STALL0 0 0 GEPIE0 SOFDE0 INCE0 0 DBM0 C2 H EPBS0 20 H UBF0 CBF0 DIR0 ESP0 SETRD0 SETWR0 CLREP0 DONE0 C3 H EPIE0 00 H AIE0 NAIE0 RLEIE0 – DNRIE0 NODIE0 EODIE0 SODIE0 C4 H EPIR0 11 H ACK0 NACK0 RLE0 – DNR0 NOD0 EOD0 SOD0 C5 H EPBA0 00 H PAGE0 0 0 0 A06 A05 A04 A03 C6 H EPLEN0 0XXX. XXXX B

0 L06 L05 L04 L03 L02 L01 L00

EPSEL = 0XXX.X001 B Endpoint 1 Registers C1 H EPBC1 00 H STALL1 0 0 GEPIE1 SOFDE1 INCE1 0 DBM1 C2 H EPBS1 20 H UBF1 CBF1 DIR1 ESP1 SETRD1 SETWR1 CLREP1 DONE1 C3 H EPIE1 00 H AIE1 NAIE1 RLEIE1 – DNRIE1 NODIE1 EODIE1 SODIE1 C4 H EPIR1 10 H ACK1 NACK1 RLE1 – DNR1 NOD1 EOD1 SOD1 C5 H EPBA1 00 H PAGE1 0 0 0 A16 A15 A14 A13 C6 H EPLEN1 0XXX. XXXX B

0 L16 L15 L14 L13 L12 L11 L10

EPSEL = 0XXX.X010 B Endpoint 2 Registers C1 H EPBC2 00 H STALL2 0 0 GEPIE2 SOFDE2 INCE2 0 DBM2 C2 H EPBS2 20 H UBF2 CBF2 DIR2 ESP2 SETRD2 SETWR2 CLREP2 DONE2 C3 H EPIE2 00 H AIE2 NAIE2 RLEIE2 – DNRIE2 NODIE2 EODIE2 SODIE2 C4 H EPIR2 10 H ACK2 NACK2 RLE2 – DNR2 NOD2 EOD2 SOD2 C5 H EPBA2 00 H PAGE2 0 0 0 A62 A52 A42 A32 C6 H EPLEN2 0XXX. XXXX B

0 L62 L52 L42 L32 L22 L12 L02

EPSEL = 0XXX.X011 B Endpoint 3 Registers C1 H EPBC3 00 H STALL3 0 0 GEPIE3 SOFDE3 INCE3 0 DBM3 C2 H EPBS3 20 H UBF3 CBF3 DIR3 ESP3 SETRD3 SETWR3 CLREP3 DONE3 C3 H EPIE3 00 H AIE3 NAIE3 RLEIE3 – DNRIE3 NODIE3 EODIE3 SODIE3 C4 H EPIR3 10 H ACK3 NACK3 RLE3 – DNR3 NOD3 EOD3 SOD3 C5 H EPBA3 00 H PAGE3 0 0 0 A63 A52 A43 A33 C6 H EPLEN3 0XXX. XXXX B

0 L63 L53 L43 L33 L23 L13 L03

EPSEL = 0XXX.X100 B Endpoint 4 Registers C1 H EPBC4 00 H STALL4 0 0 GEPIE4 SOFDE4 INCE4 0 DBM4 C2 H EPBS4 20 H UBF4 CBF4 DIR4 ESP4 SETRD4 SETWR4 CLREP4 DONE4 C3 H EPIE4 00 H AIE4 NAIE4 RLEIE4 – DNRIE4 NODIE4 EODIE4 SODIE4 C4 H EPIR4 10 H ACK4 NACK4 RLE4 –4 DNR4 NOD4 EOD4 SOD4 C5 H EPBA4 00 H PAGE4 0 0 0 A64 A54 A44 A34 C6 H EPLEN4 0XXX. XXXX B

0 L64 L54 L44 L34 L24 L14 L04

Contents of the USB Device and Endpoint Registers (Addr. C1H to C7H ) (cont’d) Addr Register Reset Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

The C541U three 8-bit I/O ports and one 6-bit I/O port (Port 1). Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Two port lines of port 1 (P1.0/LED0, P1.1/LED1) and one port line of port 3 (P3.0/LED2) have the capability of driving external LEDs in the output low state.

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 5 : In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is fOSC /6. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC /12. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the input clock logic. Figure 10 Timer/Counter 0 and 1 Input Clock Logic Table 5 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock M1 M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 fOSC /6x32 fOSC /12x32 1 16-bit timer/counter 1 1 fOSC /6 fOSC /12 2 8-bit timer/counter with 8-bit autoreload

3 Timer/counter 0 used as one

8-bit timer/counter and one 8-bit timer Timer 1 stops MCS03117 OSC C/T = 0 C/T = 1 Control TR1 P3.5/T1 (TMOD) P3.2/INT0 f Timer 0/1 Input Clock OSC /6 P3.4/T0 TR0 Gate P3.3/INT1

The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 11 shows the block diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input and the output of this shift register are each connected via a control logic to the pin P1.3 / SRI (SSC Receiver In) and P1.4 / STO (SSC Transmitter Out). This shift register can be written to (SFR STB) and can be read through the Receive Buffer Register SRB. Figure 11 SSC Block Diagram The SSC has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is P1.2/ SCLK. When operating in slave mode, a slave select input is provided which enables the SSC interface and also will control the transmitter output. The pin used for this is P1.5 / SLS. The SSC control block is responsible for controlling the different modes and operation of the SSC, checking the status, and generating the respective status and interrupt signals. Clock Divider Clock Selection Receive Buffer Register Int. Enable Reg. Control Register . . . fOSC Shift Register STB SRB Pin Control Logic Pin Pin Pin Pin P1.2 / SCLK P1.3 / SRI P1.4 / STO P1.5 / SLS SCIEN SSCCON SCF Status Register Control Logic Interrupt Internal Bus MCB03379

The USB module in the C541U handles all transactions between the serial USB bus and the internal (parallel) bus of the microcontroller. The USB module includes several units which are required to support data handling with the USB bus : the on-chip USB bus transceiver, the USB memory with two pages of 128 bytes each, the memory management unit (MMU) for USB and CPU memory access control, the UDC device core for USB protocol handling, the microcontroller interface with the USB specific special function registers and the interrupt control logic. A clock generation unit provides the clock signal for the USB module for full speed and low speed USB operation. Figure 12 shows the block diagram of the functional units of the USB module with their interfaces. Figure 12 USB Module Block Diagram MCB03380 Pin Pin PinPin XTAL1 XTAL2 D+ D- USB Bus Osc. (On-chip) Transceiver x 4 PLL 2

48 MHz 6 MHz

(128 x 8) F Data Data Control USB Memory Management MMU Interrupt Generation SFR Addr. 11Core Device USB MCU Interface Module USB Internal Bus Memory Page 1 (UDC) Control H H H 7 HF Address

Two different kinds of registers are implemented for full speed operation in the USB module. The global registers (GEPIR, EPSEL, ADROFF, USBVAL) describe the basic functionality of the complete USB module and can be accessed via unique SFR addresses. For reduction of the number of SFR addresses which are needed to control the USB module inside the C541U, device registers and endpoint registers are mapped into an SFR address block of seven SFR addresses (C1H to C7H ). The endpoint specific functionality of the USB module is controlled via the device registers DCR, DPWDR, DIER, DIRR and the frame number registers. An endpoint register set is available for each endpoint (n=0..4) and describes the functionality of the selected endpoint. Figure 13 explains the structure of the USB module registers. Figure 13 Register Structure of the USB Module D Global Registers EPSEL(D2 H ) Endpoint 0 Registers EPBC0 EPBS0 EPIE0 EPIR0 EPBA0 EPLEN0 C1 H C2 H C3 H C4 H C5 H C6 H C7 H reserved Endpoint 1 Registers EPBC1 EPBS1 EPIE1 EPIR1 EPBA1 EPLEN1 C1 H C2 H C3 H C4 H C5 H C6 H C7 H reserved Endpoint 2 Registers EPBC2 EPBS2 EPIE2 EPIR2 EPBA2 EPLEN2 C1 H C2 H C3 H C4 H C5 H C6 H C7 H reserved Endpoint 3 Registers EPBC3 EPBS3 EPIE3 EPIR3 EPBA3 EPLEN3 C1 H C2 H C3 H C4 H C5 H C6 H C7 H reserved Endpoint 4 Registers EPBC4 EPBS4 EPIE4 EPIR4 EPBA4 EPLEN4 C1 H C2 H C3 H C4 H C5 H C6 H C7 H reserved Device Registers DCR DIER DIRR FNRL C1 H C2 H C3 H C4 H C5 H C6 H C7 H reserved DPWDR FNRH .0.1.2.7 USBVAL(D3 H ) ADROFF(D4 H ) GEPIR(D6 H ) 0 0 0000 Decoder

Interrupt Request Sources (Part 2) Endpoint 4 Interrupts Endpoint 3 Interrupts Endpoint 2 Interrupts Low Priority High Priority 004BHEUEI IEN1.1 IP1.1 PUEI IEN0.7 EA Bit addressable Request flag is cleared by hardware after the corresponding register has been read. Endpoint 0 Interrupts ACK0 NACK0 RLE0 DNR0 NOD0 EOD0 AIE0 EPIE0.7 NAIE0 EPIE0.6 RLEIE0 EPIE0.5 DNRIE0 EPIE0.3 NODIE0 EPIE0.2 EODIE0 EPIE0.1 EPIR0.7 EPIR0.6 EPIR0.5 EPIR0.3 EPIR0.2 EPIR0.1 Endpoint 1 Interrupts Endpoint Interrupts 0043HESSC IEN1.0 SSC WCEN TCEN SCIEN.1 SCIEN.0 SCF.0 WCOL SCF.1 TC Interrupts PSSC IP1.0 GEPIE0 EPBC0.4 EPI0 GEPIR.0 SOD0 SODIE0 EPIE0.0EPIR0.0 Low Speed Interrupts SUSP SUSPIEUSBPWD.3 DADD DADDIEUSBPWD.2 USBPWD.5 USBPWD.4 SETUP packet OUT packet USB Reset

Interrupt Request Sources (Part 3) Table 6 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags (SFRs) External Interrupt 0 0003 H IE0 Timer 0 Overflow 000B H TF0 External Interrupt 1 0013 H IE1 Timer 1 Overflow 001B H TF1 SSC Interrupt 0043 H TC, WCOL USB Endpoint Interrupt 004B H in SFRs EPIR0-4 and GEPIR USB Device Interrupt 0053 H in SFRs DIRR and GEPIR Wake-up from power down 007B H – Low Priority High Priority IE0.7 EA 0053H IP1.2 PUDI SE0I DAI DDI SBI SEI STI SUI SE0IE DIER.7 DAIE DIER.6 DDIE DIER.5 SBIE DIER.4 SEIE DIER.3 STIE DIER.2 SUIE DIER.1 DIRR.7 DIRR.6 DIRR.5 DIRR.4 DIRR.3 DIRR.2 DIRR.1 EUDI IEN1.2 SOFI SOFIE DIER.0DIRR.0 Device Interrupts Bit addressable Request flag is cleared by hardware after the corresponding register has been read. DRVI DRVIE DPWDR.7GEPIR.7

The C541U offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 256 µs up to approx. 0.55 µs at 12 MHz. – an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. The watchdog timer in the C541U is a 15-bit timer, which is incremented by a count rate of fOSC /12 or fOSC /192. The system clock of the C541U is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler which are selected by bit WDTPSEL (WDTREL.7). For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 8-17 shows the block diagram of the watchdog timer unit. Figure 17 Block Diagram of the Watchdog Timer The watchdog timer can be started by software (bit SWDT) but it cannot be stopped during active mode of the C541U. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. MCB03384 WDCON (CO )H OSCf --- - OWDS WDTS WDT SWDT 2 16 WDTL WDTH / 6 External HW Reset Control Logic 670 WDT Reset-Request WDTPSEL WDTREL

The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on- chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. – Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. – Control of external wake-up from software power-down mode (description see chapter 9) When the power-down mode is left by a low level at the INT0 pin or by the USB, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power- down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.

Functional Block Diagram of the Oscillator Watchdog Int. Clock XTAL2 XTAL1 OWDS MCD03385 WDCON (C0 )H

3 MHz

2f 1f< Activity on Start / Stop Start / Stop Mode Activated Power - Down Power-Down Mode Wake - Up Interrupt Internal Reset P3.2 / INT0 Control WS (PCON1.4)(PCON1.7) EWPD >1Frequency Comparator RC On-Chip Oscillator Logic Oscillator Logic Control USB Bus

The C541U provides two basic power saving modes, the idle mode and the power down mode. – Idle mode In the idle mode the main oscillator of the C541U continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the SSC, the USB module, and the timers with the exception of the watchdog timer are further provided with the clock. The CPU status is preserved in its entirety : the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The idle mode can be terminated by activating any enabled interrupt. or by a hardware reset. – Power down mode In the power down mode, the RC osciillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The power down mode can be left either by an active reset signal or by a low signal at the P3.2/INT0 pin or any activity on the USB bus. Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state. Using the INT0 pin or USB bus for power down mode exit maintains the state of the SFRs, which has been frozen when power down mode is entered. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. Table 7 gives a general overview of the entry and exit procedures of the power saving modes. Table 7 Power Saving Modes Overview Mode Entering 2-Instruction Example Leaving by Remarks Idle mode ORL PCON, #01H ORL PCON, #20H Ocurrence of an interrupt from a peripheral unit CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Hardware Reset Power Down Mode ORL PCON, #02H ORL PCON, #40H Hardware Reset Oscillator is stopped; contents of on-chip RAM and SFR’s are maintained; Short low pulse at pin P3.2/INT0 or activity on the USB bus

The C541U contains a 8k byte one-time programmable (OTP) program memory. With the C541U fast programming cycles are achieved (1 byte in 100 µsec). Also several levels of OTP memory protection can be selected. For programming of the device, the C541U must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C541U operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5V programming voltage. Figure 19 shows the pins of the C541U-1E which are required for controlling of the OTP programming mode. Figure 19 Programming Mode Configuration Port 0 D0-D7 VDD VSS C541U PROG A0-A7 / Port 2 EA /VPP PMSEL0 PSEL RESET PSEN PMSEL1 PRD A8-A12 PALE XTAL1 XTAL2

Pin Configuration in Programming Mode Figure 20 Pin Configuration of the C541U in Programming Mode (Top View) 5 4 3 2 1 4 44 34 24 14 0 18 19 20 21 22 23 24 25 26 27 N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD VSS PMSEL0 N.C. PMSEL1 PSEL PRD PALE RESET N.C. EA /VPP N.C. PSEN PROG GND GND XTAL2 XTAL1 VSS VDD A0/A8 A1/A9 A2/A10 A3/A11 A4/A12 Programming Mode C541U GND

The following table 8 contains the functional description of all C541U-1E pins which are required for OTP memory programming. Table 8 Pin Definitions and Functions in Programming Mode Symbol Pin Num- bers I/O*) Function P-LCC-44 RESET 10 I Reset This input must be at static “1“ (active) level during the whole programming mode. PMSEL0 PMSEL1 I I Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PSEL

14 I Basic programming mode select

This input is used for the basic programming mode selection and must be switched according figure 10-21. PRD 15 I Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. PALE 16 I Programming mode address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level whenever the logic level of PMSEL1,0 is changed. XTAL2 20 O XTAL2 Output of the inverting oscillator amplifier. XTAL1 21 I XTAL1 Input to the oscillator amplifier. *) I = Input O = Output PMSEL PMSEL Access Mode

00 R e s e r v e d

1 0 Program/read lock bits 1 1 Program/read OTP memory byt e

P2.0-7 are used as multiplexed address input lines A0-A7 and A8- A12. A8-A12 must be latched with PALE. PSEN 32 I Program store enable This input must be at static “0“ level during the whole programming mode. PROG 33 I Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations During basic programming mode selection a low level must be applied to PROG EA /VPP 35 I External Access / Programming voltage This pin must be at 11.5 V (VPP ) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at high level (VIH). This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA /VPP . D0 - 7 43 - 36 I/O Data lines 0-7 During programming mode, data bytes are read or written from or to the C541U via the bidirectional D0-7 lines which are located at port 0. VSS 9, 22 – Circuit ground potential must be applied to these pins in programming mode. VDD 8, 23 – Power supply terminal must be applied to these pins in programming mode. N.C. 1 - 7, 12,, 34, 44 – Not Connected These pins should not be connected in programming mode. GND 17 - 19 I Ground pins In programming mode these pins must be connected to VIL level. *) I = Input O = Output Table 8 Pin Definitions and Functions in Programming Mode (cont’d) Symbol Pin Num- bers I/O*) Function P-LCC-44

Basic Programming Mode Selection The basic programming mode selection scheme is shown in figure 21. Figure 21 Basic Programming Mode Selection RESET PSEN PROG EA /VPP “1“ “0“ PSEL “0“ VDD Clock (XTAL1/XTAL2) stable PRD PALE “1“ “0“ Ready for access mode selectionDuring this period signals are not actively driven 0V VIH1 VPP PMSEL1,0 0,1

Lock Bits Programming / Read The C541U has two programmable lock bits which, when programmed according tabie 10, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Table 9 Access Modes Selection Access Mode EA / VPP PROG PRD PMSEL Address (Port 2) Data (Port 0)10 Program OTP memory byte V PP HH H A 0 - 7 A8-15 D0-7 Read OTP memory byte V IH H Program OTP lock bits V PP HH L –D 1 , D 0 s e e table 10Read OTP lock bits V IH H Read OTP version byte V IH H L H Byte addr. of sign. byte D0-7 Table 10 Lock Bit Protection Types Lock Bits at D1,D0 Protection Level Protection Type D1 D0 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C541U, the state of the EA pin is not latched on reset. 1 0 Level 1 During normal operation of the C541U, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible using the OTP verification mode for protection level 1. Further programming of the OTP memory is disabled (reprogramming security). 0 1 Level 2 Same as level 1, but also OTP memory read operation using OTP verification mode is disabled. 0 0 Level 3 Same as level 2; but additionally external code execution by setting EA =low during normal operation of the C541U is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible.

Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions V IN > V DD or V IN < V SS ) the voltage on V DD pins with respect to ground (V SS ) must not exceed the values defined by the absolute maximum ratings. Operating Conditions Parameter Symbol Limit Values Unit Notes min. max. Storage temperature TST – 65 150 °C – Voltage on VDD pins with respect to ground (VSS ) VDD –0.5 6.5 V– Voltage on any pin with respect to ground (VSS ) VIN –0.5 VDD + 0.5 V– Input current on any pin during overload condition –10 10 mA – Absolute sum of all input currents during overload condition – | 100 | mA – Power dissipation PDISS –T B D W – Parameter Symbol Limit Values Unit Notes min. max. Supply voltage VDD 4.25 5.5 V – Ground voltage VSS 0 V– Ambient temperature TA 07 0 ° C – CPU clock fCPU 21 2 M H z –

(Operating Conditions apply) Notes see next page Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (except EA, RESET) VIL – 0.5 0.2 VDD – 0.1 Input low voltage (EA) VIL1 – 0.5 0.2 VDD – 0.3 Input low voltage (RESET) VIL2 – 0.5 0.2 VDD + 0.1 Input high voltage (except XTAL1, RESET and EA ) VIH 0.2VDD + 0.9 VDD + 0.5 V – Input high voltage to XTAL1 VIH1 0.7VDD VDD + 0.5 V – Input high voltage to RESET and EA VIH2 0.6VDD VDD + 0.5 V – Output low voltage Ports 1, 2, 3 P1.0, P1.1, P3.0 VOL – 0.45 0.45 V V IOL = 1.6 mA 1) IOL =1 0 m A 1) Output low voltage (ALE, PSEN) VOL1 –0 . 4 5 V IOL = 3.2 mA 1) Output low voltage (Port 0) VOL2 –0 . 6 V IOL = 3.2 mA 1) Output high voltage (ports 1, 2, 3)VOH 2.4 0.9VDD V IOH =–8 0 µA, IOH =–1 0 µA Output high voltage (port 0 in external bus mode, ALE, PSEN) VOH2 2.4 0.9 VDD V IOH = – 800µA IOH =–8 0 µA 2) Logic 0 input current (ports 1, 2, 3)IIL –1 0 –6 0 µA VIN =0 . 4 5V Logical 1-to-0 transition current (ports 1, 2, 3) ITL –6 5 –6 5 0 µA VIN =2V Input leakage current (port 0, EA) ILI – ± 1 µA0 . 4 5 <VIN < VDD Pin capacitance C IO –1 0 p F fc =1M H z , TA =2 5°C 7) Overload current IOV – ± 5m A 6) 7) Programming voltage VPP 10.9 12.1 V 11.5 V ± 5%

Notes : 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA =P o r t 0=VDD ; XTAL2 = N.C.; XTAL1 =VSS ; RESET =VSS ; all other pins are disconnected. the USB transceiver is switched off; 4) IDD (active mode) is measured with: XTAL1 driven with tCLCH , tCHCL =5n s, VIL= VSS +0 . 5V , VIH = VDD – 0.5 V; XTAL2 = N.C.; EA = RESET = Port 0 = Port 1 =VDD ; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH , tCHCL =5n s , VIL= VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.; EA = RESET = Vss ; Port 0 =VDD ; all other pins are disconnected; 6) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits. 7) Not 100% tested, guaranteed by design characterization. 8) The typical IDD values are periodically measured at TA = +25 °C but not 100% tested. 9) The maximum IDD values are measured under worst case conditions (TA = 0 °C and VDD =5 . 5V ) Parameter Symbol Limit Values Unit Test Condition typ. 8) max. 9) Active mode 12 MHz IDD 25 30 mA 4) Idle mode 12 MHz IDD 15 20 mA 5) Power-down mode IPD 55 0 µA VDD =2 … 5.5 V 3)

(Operating Conditions apply) C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C541U to devices with float times up to 28 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. **) For correct function of the USB module the C541U must operate with 12 MHz external clock. The microcontroller (except the USB module) operates down to 2 MHz. Parameter Symbol Limit Values Unit 10-MHz clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP = 2 MHz to

12 MHz **)

min. max. min. max. ALE pulse width tLHLL 43 – CLP - 40 – ns Address setup to ALE tAVLL 13 – TCL Hmin -20 – ns Address hold after ALE tLLAX 13 – TCL Hmin -20 – ns ALE to valid instruction in tLLIV – 80 – 2 CLP - 87 ns ALE to PSEN tLLPL 13 – TCL Lmin -20 – ns PSEN pulse width tPLPH 86 – CLP+ TCL Hmin -30 –n s PSEN to valid instruction in tPLIV –5 1 – C L P + TCL Hmin- 65 ns Input instruction hold after PSENtPXIX 0 – 0–n s Input instruction float after PSENtPXIZ *) –2 3 – T C L Lmin -10 ns Address valid after PSEN tPXAV *) 28 – TCL Lmin - 5 – ns Address to valid instruction intAVIV – 140 – 2 CLP + TCL Hmin -60 ns Address float to PSEN tAZPL 0 0–n s

AC Characteristics (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 10-MHz clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP= 2 MHz to 12 MHz min. max. min. max. RD pulse width tRLRH 180 – 3 CLP - 70 – ns WR pulse width tWLWH 180 – 3 CLP - 70 – ns Address hold after ALE tLLAX2 56 – CLP - 27 – ns RD to valid data in tRLDV –1 1 0 – 2 C L P + TCL Hmin - 90 ns Data hold after RD tRHDX 00 – n s Data float after RD tRHDZ – 63 – CLP - 20 ns ALE to valid data in tLLDV – 200 – 4 CLP - 133 ns Address to valid data in tAVDV – 211 – 4 CLP + TCL Hmin -155 ns ALE to WR or RD tLLWL 66 166 CLP + TCL Lmin - 50 CLP+ TCL Lmin+ 50 ns Address valid to WR tAVWL 70 – 2 CLP - 97 – ns WR or RD high to ALE high tWHLH 85 8 T C L Hmin - 25 TCL Hmin + 25 ns Data valid to WR transition tQVWX 8–T C L Lmin - 25 – ns Data setup before WR tQVWH 163 – 3 CLP + TCL Lmin - 120 –n s Data hold after WR tWHQX 8–T C L Hmin - 25 – ns Address float after RD tRLAZ –0– 0 n s

AC Characteristics (cont’d) External Clock Drive Characteristics Parameter Symbol CPU Clock = 12 MHz Duty cycle 0.4 to 0.6 Variable CPU Clock 1/CLP = 2 to 12 MHz Unit min. max. min. max. Oscillator period CLP 83.3 83.3 83.3 500 ns High time TCL H 33 – 33 CLP-TCL L ns Low time TCL L 33 – 33 CLP-TCL H ns Rise time tR – 12 – 12 ns Fall time tF – 12 – 12 ns Oscillator duty cycle DC 0.4 0.6 33 / CLP 1 - 33 / CLP – Clock cycle TCL 33 50 CLP * DC min CLP * DCmax ns SSC Interface Characteristics Parameter Symbol Limit Values Unit min. max. Clock Cycle Time : Master Mode Slave Mode tSCLK tSCLK 667 667 ns ns Clock high time tSCH 300 – ns Clock low time tSCL 300 – ns Data output delay tD – 100 ns Data output hold tHO 0–n s Data input setup tS 100 – ns Data input hold tHI 50 – ns TC bit set delay tDTC –8 C L P n s SLS low to first SCLK clock edgetSC 2 tCLCL –n s Last SCLK clock edge to SLS high tCS tCLCL –n s SLS low to STO active tTS 0 100 ns SLS high to STO tristate tST – 100 ns Data output delay (already defined)tD – 100 ns

A0 - A7 Instr.IN A0 - A7Port 0 tAVLL PLPH t tLLPL tLLIV tPLIV tAZPL tLLAX tPXIZ tPXIX tAVIV tPXAV

A0 - A7 Instr. INData IN A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

External Clock Drive on XTAL1 MCT00098 ALE PSEN Port 2 WHLHt Port 0 WR tWLWHtLLWL tQVWX tAVLL tLLAX2 tQVWH tAVWL tWHQX A0 - A7 from Ri or DPL from PCL A0 - A7 Instr.INData OUT A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH TCL H TCL L CLP tR tF 0.2V CC

0.7 CCV

• 0.1 MCT03310 XTAL1 VDD VDD

Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and CPHA=0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA=0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.

SCLK (CPOL = 1) SCLK (CPOL = 0) SLS STO (CPHA = 0) STO (CPHA = 1) tTS tDtD tD DttD tST CStSCt DOUT 7 DOUT 0 DOUT 7 DOUT 1 DOUT 0 MCT03390

AC Characteristics of Programming Mode VDD = 5 V ± 10 %; VPP = 11.5 V ± 5% ; TA = 25 °C ± 10 °C Parameter Symbol Limit Values Unit min. max. ALE pulse width tPAW 35 – ns PMSEL setup to ALE rising edge tPMS 10 – Address setup to ALE, PROG, or PRD falling edge tPAS 10 – ns Address hold after ALE, PROG, or PRD falling edge tPAH 10 – ns Address, data setup to PROG or PRD tPCS 100 – ns Address, data hold after PROG or PRD tPCH 0–n s PMSEL setup to PROG or PRD tPMS 10 – ns PMSEL hold after PROG or PRD tPMH 10 – ns PROG pulse width tPWW 100 – µs PRD pulse width tPRW 100 – ns Address to valid data out tPAD –7 5 n s PRD to valid data out tPRD –2 0 n s Data hold after PRD tPDH 0–n s Data float after PRD tPDF –2 0 n s PROG high between two consecutive PROG low pulses tPWH1 1– µs PRD high between two consecutive PRD low pulses tPWH2 100 ns XTAL clock period tCLKP 83.3 500 ns

Programming Code Byte - Write Cycle Timing tPAW tPMS PAHtPASt A8-A13 A0-A7 D0-D7 PCSt PWWt PCHt tPWH MCT03369 H, H PALE PMSEL1,0 Port 2 Port 0 PROG

Verify Code Byte - Read Cycle Timing tPAW tPMS PAHtPASt A8-13 A0-7 PADt D0-7 tPDH tPDFPRDt PCSt PRWt PCHt tPWH MCT03392 H, H PALE PMSEL1,0 Port 2 Port 0 PRD Notes: PROG must be high during a programming read cycle.

OTP Verification Characteristics OTP Verification Mode for Protection Level 1 Figure 32 OTP Verification Mode for Protection Level 1 Parameter Symbol Limit Values Unit min. typ max. ALE pulse width tAWD –2 tCLCL –n s ALE period tACY – 12 tCLCL –n s Data valid after ALE tDVA ––4 tCLCL ns Data stable after ALE tDSA 8 tCLCL ––n s P3.5 setup to ALE low tAS – tCLCL –n s Oscillator frequency 1/tCLCL 4–6M H z MCT02613 tACY tAWD tDSA DVAt tAS Data Valid ALE Port 0 P3.5

USB Transceiver Characteristics (Operating Conditions apply) Notes : 1) This value includes an external resistor of 30Ω ± 1% (see “Load for D+/D-“ diagram for testing details) 2) The crossover point is in the range of 1.3V to 2.0V for the high speed mode with a 50pF capacitance. In the low-speed mode with a 100pF or greater capacitance, the crossover point is in the range of 1.3V to 2.0V. Parameter Symbol Limit Values Unit Test Condition min. max. Output impedance (high state)RDH 28 43 Ω 1) Output impedance (low state) RDL 28 51 Ω Input leakage current I I –± 5 µA VIN = VSS or VDD Tristate output off-state currentI OZ –± 1 0 µA VOUT = VSS or VDD Crossover point VCR 1.3 2.0 V 2) Parameter Symbol Limit Values Unit min. max. High speed mode rise time tFR 42 0 n s High speed mode fall time tFF 42 0 n s Low speed mode rise time tLR 75 300 ns Low speed mode fall time tLF 75 300 ns

Plastic Package, P-LCC-44-1 (SMD) (Plastic Leaded Chip Carrier Package) GPL05102 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device