C517

C517A INFINEON | Alldatasheet

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8-Bit CMOS Microcontroller Advance Information C517A

• Full upward compatibility with SAB 80C517A/83C517A-5
• Up to 24 MHz external operating frequency – 500 ns instruction cycle at 24 MHz operation
• Superset of the 8051 architecture with 8 datapointers
• On-chip emulation support logic (Enhanced Hooks Technology TM)
• 32K byte on-chip ROM (with optional ROM protection) – alternatively up to 64K byte external program memory
• Up to 64K byte external data memory
• 256 byte on-chip RAM
• Additional 2K byte on-chip RAM (XRAM)
• Seven 8-bit parallel I/O ports
• Two input ports for analog/digital input (further features are on next page) Figure 1 C517A Functional Units MCA03317 Port 0 Port 1 Port 2 XRAM RAM MDU ROM I/O (8 Datapointer) I/OAnalog/ Digital Input Port 332k x 8 CPU Port 8 Input Digital Analog/ 256 x 82K x 8 Port 7 Port 6 Port 5 Port 4 Watchdog Timer Oscillator Watchdog 10-Bit A/D Converter

8 Bit

ModesOn-Chip Emulation Support Module I/O I/O I/O I/O I/O

Features (continued) :

• Two full duplex serial interfaces (USART) – 4 operating modes, fixed or variabie baud rates – programmable baud rate generators
• Four 16-bit timer/counters – Timer 0 / 1 (C501 compatible) – Timer 2 for 16-bit reload, compare, or capture functions – Compare timer for compare/capture functions
• Powerful 16-bit compare/capture unt (CCU) with up to 21 high-speed or PWM output channels and 5 capture inputs
• 10-bit A/D converter – 12 multiplexed analog inputs – Built-in self calibration
• Extended watchdog facilities – 15-bit programmable watchdog timer – Oscillator watchdog
• Power saving modes – Slow down mode – Idle mode (can be combined with slow down mode) – Software power-down mode – Hardware power-down mode
• 17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels
• P-MQFP-100 and P-LCC-84 packages
• Temperature Ranges : SAB-C517A TA = 0 to 70°C SAF-C517A TA = -40 to 85°C SAH-C517A TA = -40 to 110°C

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery. For the available ordering codes for the C517A please refer to the „Product Information Microcontrollers“, which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code.

Pin Configuration P-MQFP-100 Package (Top View) C517A HWPD MCP03319 P2.6/A14 P0.3/AD3 P1.5/T2EX P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 CC1/INT4/P1.1 CC2/INT5/P1.2 N.C. N.C. N.C. N.C. CC4/INT2/P1.4 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 CCM7/P5.7 CCM6/P5.6 CCM5/P5.5 CCM1/P5.1 CCM0/P5.0 OWE ADST/P6.0 RxD1/P6.1 TxD1/P6.2 P6.3 P6.4 P4.0/CM0 P4.1/CM1 P4.2/CM2 PE/SWD P4.3/CM3 P4.4/CM4 P4.5/CM5 P4.6/CM6 N.C. N.C. N.C. N.C. P1.6/CLKOUT P1.7/T2 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD0 P3.0/RxD0 N.C. N.C. P7.0/AIN0 P7.1/AIN1 P7.2/AIN2 P7.3/AIN3 P7.4/AIN4 P7.5/AIN5 P7.6/AIN6 10031 801 RO P8.3/AIN11 P8.2/AIN10 P8.1/AIN9 P8.0/AIN8 P6.7 P6.6 P6.5 P2.7/A15 PSEN ALE EA N.C. P0.0/AD0 P0.1/AD1 N.C. VSS CCV V AGND AREF V SSV VCC CCM2/P5.2 CCM3/P5.3 CCM4/P5.4 P0.2/AD2 N.C. CC0/INT3/P1.0 CC3/INT6/P1.3 P7.7/AIN7 RESET P4.7/CM7 N.C. N.C. N.C. 792 783 774 765 756 747 738 729 7110 7011 6912 6813 6714 6615 6516 6417 6318 6219 6120 6021 5922 5823 5724 5625 5526 5427 5328 5229 5130 9932 9833 9734 9635 9536 9437 9338 9239 9140 9041 8942 8843 8744 8645 8546 8447 8348 8249 8150 VDD VDD

Pin Configuration P-LCC-84 Package (Top View) 75P6.4 P6.3 P6.2/TxD1 P6.1/RxD1 P6.0/ADST OWE P5.0/CCM0 P5.1/CCM1 P5.2/CCM2 P5.3/CCM3 P5.4/CCM4 P5.5/CCM5 P5.6/CCM6 P5.7/CCM7 HWPD P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 V AGND P7.7/AIN7 P7.6/AIN6 P7.5/AIN5 P7.4/AIN4 P7.3/AIN3 P7.2/AIN2 P7.1/AIN1 P7.0/AIN0 P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD P1.7/T2 P1.6/CLKOUT P1.5/T2EX P1.4/INT2/CC4 VAREF RESET P4.7/CM7 P4.6/CM6 P4.5/CM5 P4.4/CM4 P4.3/CM3 PE /SWD P4.2/CM2 P4.1/CM1 P4.0/CM0 VDD VSS RO P8.3/AIN11 P8.2/AIN10 P8.1/AIN9 P8.0/AIN8 P6.7 P6.6 P6.5 P1.3/INT6/CC3 P1.2/INT5/CC2 P1.1/INT4/CC1 P1.0/INT3/CC0 VSS VDD XTAL2 XTAL1 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.0/AD0 P0.1/AD1

Pin Definitions and Functions 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&& 100 - 98 100 36 - 29 I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / INT3 / CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 / INT4 / CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 / INT5 / CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 / INT6 / CC3 Interrupt 6 input / compare 3 output / capture 3 input P1.4 / INT2 / CC4 Interrupt 2 input / compare 4 output / capture 4 input P1.5 / T2EX Timer 2 external reload / trigger input P1.6 / CLKOUT System clock output P1.7 / T2 Counter 2 input *) I = Input, O = Output

VSS 10, 62 37, 83 – Ground (0V) during normal, idle, and power down operation. V DD 11, 63 38, 84 – Supply voltage during normal, idle, and power down mode. X T A L 2 1 23 9– XTAL2 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed. X T A L 1 1 34 0– XTAL1 is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator. P2.0 - P2.7 14 - 21 41 - 48 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&&

PSEN 22 49 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. The signal remains high during internal program execution. A L E 2 35 0O T h e Address Latch enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. EA 24 51 I External Access Enable When held high, the C517A executes instructions from the internal ROM as long as the PC is less than 8000H . When held low, the C517A fetches all instructions from external program memory. For the C517A-L this pin must be tied low. For the C517A-4R, if the device is protected (see section 4.6 in the User Manual) then this pin is only latched during reset. 30 - 35 52 - 59 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high- impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C517A- 4R. External pullup resistors are required during program verification. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&&

HWPD 36 60 I Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C517A. A low level for a longer period will force the part into hardware power down mode with the pins floating. There is no internal pullup resistor connected to this pin. P5.0 - P5.7 44 - 37 68 - 61 I/O Port 5 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 5 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. This port also serves the alternate function "Concurrent Compare" and "Set/Reset Compare". The secondary functions are assigned to the port 5 pins as follows: CCM0 to CCM7 P5.0 to P5.7 : concurrent compare or Set/Reset lines O W E 4 56 9I Oscillator Watchdog Enable A high level on this pin enables the oscillator watchdog. When left unconnected this pin is pulled high by a weak internal pull-up resisitor. The logic level at OWE should not be changed during normal operation. When held at low level the oscillator watchdog function is turned off. During hardware power down the pullup resistor is switched off. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&&

P6.0 - P6.7 46 - 50, 54 - 56 70 - 77 I/O Port 6 is a quasi-bidirectional I/O port with internal pull-up resistors. Port 6 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 6 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port 6 also contains the external A/D converter start control pin and the transmit and receive pins for the serial interface 1. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 6, as follows : P6.0 ADST external A/D converter start pin P6.1 RxD1 receiver data input of serial interface 1 P6.2 TxD1 transmitter data input of serial interface 1 P8.0 - P8.3 57 - 60 78 - 81 I Port 8 is a 4-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the higher 4-bit of the multiplexed analog inputs of the A/D converter, simultaneously. P8.0 - P8.3 AIN8 - AIN11 analog input 8 - 11 RO 61 82 O Reset Output This pin outputs the internally synchronized reset request signal. This signal may be generated by an external hardware reset, a watchdog timer reset or an oscillator watchdog reset. The RO output signal is active low. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&&

P4.0 - P4.7 64 - 66, 68 - 72 1 - 3, 5 - 9 I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. Port 4 also serves as alternate compare functions. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 4 as follows : P4.0 - P4.7 CM0 - CM7 Compare channel 0 - 7 PE /SWD 67 4 I Power saving mode enable / Start watchdog timer A low level at this pin allows the software to enter the power saving modes (idle mode, slow down mode, and power down mode). In case the low level is also seen during reset, the watchdog timer function is off on default. Usage of the software controlled power saving modes is blocked, when this pin is held at high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. During hardware power down the pullup resisitor is switched off. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&&

P3.0 - P3.7 90 - 97 21 - 28 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / RxD0 Receiver data input (asynch.) or data input/output (synch.)of serial interface 0 P3.1 / TxD0 Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&&

A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C517A. A small internal pullup resistor permits power-on reset using only a capacitor connected to V SS . VAREF 78 11 – Reference voltage for the A/D converter VAGND 79 12 – Reference ground for the A/D converter P7.0 - P7.7 87 - 80 20-13 I Port 7 is an 8-bit unidirectional input port. Port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the lower 8-bit of the multiplexed analog inputs of the A/D converter, simultaneously. P7.0 - P7.7 AIN0 - AIN7 analog input0 - 7 N.C. 2 - 5, 25, 28, 29, 51 - 53, 74 - 77 88, 89 –– Not connected These pins of the P-MQFP-100 package must not be connected. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) 6\\PERO 3LQ1XPEHU ,2/G13 )XQFWLRQ 304)3 3/&&

Block Diagram of the C517A Port 8 Port 8 Port 7 Port 7 Port 6Port 6 Port 5Port 5 Port 4Port 4 Port 3Port 3 Port 2Port 2 Port 1Port 1 8-Bit Digital I/O Port 0Port 0 Programmable Watchdog Timer OSC & Timing Oscillator Watchdog Serial Channel 1 Baud Rate Generator Programmable Serial Channel 0 Timer 1 Timer 0 Timer 2 Compare Timer Capture Compare Unit S & H Analog RESET RO ALE EA PE/SWD AREFV VAGND MCB03320 XTAL1 XTAL2 Interrupt Unit A/D Converter

10 Bit

8 Datapointer

The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three- byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1µs (24 MHz : 500 ns). Special Function Register PSW (Address D0H ) Reset Value : 00 H Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 PD0 H PSW D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VDD to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VSS via a capacitor. Figure 7 shows the possible reset circuitries. Figure 7 Reset Circuitries MCS03323 RESET C517A b)a) RESET RESET C517A C517A

Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens. SYSCON PCON TCON RESET EA ALE PSEN Port 0 Port 2 Port 1Port 3 opt. I/O Ports C500 MCU RPCON RTCON Enhanced Hooks Interface Circuit RSYSCON RPORT RPORT TEA TALE TPSEN EH-IC ICE-System interface to emulation hardware Target System Interface MCS03254

Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C517A. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.

Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer E0H F0H 83H 82H 92H D0 H 81H 00H 00H 00H 00H XXXX X000 B 00H 07H A/D- Converter ADCON0 2) ADCON1 ADDATH ADDATL A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register, High Byte A/D Converter Data Register, Low Byte D8 H DC H D9 H DA H 00H 0XXX 0000B 00H 00XX XXXX B Interrupt System IEN0 2) IEN1 2) IEN2 IP0 2) IP1 IRCON0 IRCON1 TCON 2) T2CON 2) S0CON 2) CTCON 2) Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register 0 Interrupt Request Control Register 1 Timer 0/1 Control Register Timer 2 Control Register Serial Channel 0 Control Register Compare Timer Control Register A8 H B8 H 9AH A9H B9H C0 H D1 H 88H C8 H 98H E1H 00H 00H XX00 00X0B 00H XX00 0000B 00H 00H 00H 00H 00H 0X00 0000B MUL/DIV Unit ARCON MD0 MD1 MD2 MD3 MD4 MD5 Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 EF H E9H EA H EB H EC H ED H EE H 0XXXXXXX B XX H XX H XX H XX H XX H XX H Timer 0 / Timer 1 TCON 2) TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved

(CCU) Timer 2 CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL COMSETL COMSETH COMCLRL COMCLRH SETMSK CLRMSK CTCON CTRELH CTRELL TH2 TL2 T2CON IRCON0 2) Compare/Capture Enable Register Compare/Capture 4 Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 4, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Compare/Capture Register 4, Low Byte Compare Enable Register Compare Register 0, High Byte Compare Register 1, High Byte Compare Register 2, High Byte Compare Register 3, High Byte Compare Register 4, High Byte Compare Register 5, High Byte Compare Register 6, High Byte Compare Register 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Comp./Rel./Capt. Register High Byte Comp./Rel./Capt. Register Low Byte Compare Set Register Low Byte Compare Set Register, High Byte Compare Clear Register, Low Byte Compare Clear Register, High Byte Compare Set Mask Register Compare Clear Mask Register Compare Timer Control Register Compare Timer Rel. Register, High Byte Compare Timer Rel. Register, Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Request Control Register 0 C1 H C9 H C3 H C5 H C7 H CF H C2 H C4 H C6 H CE H F6H D3 H D5 H D7 H E3H E5H E7H F3H F5H D2 H D4 H D6 H E2H E4H E6H F2H F4H F7H CB H CA H A1H A2H A3H A4H A5H A6H E1H DF H DE H CD H CC H C8 H C0 H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0X00 0000B 00H 00H 00H 00H 00H 00H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4-bit 80H 90H A0 H B0 H E8H F8H FA H DB H DD H FFH FFH FFH FFH FFH FFH FFH XRAM XPAGE SYSCON 2) Page Address Register for Extended On-Chip RAM System/XRAM Control Register 91H B1H 00H XXXX XX01 B Serial Channels ADCON0 2) PCON 2) S0BUF S0CON S0RELL S0RELH S1BUF S1CON S1RELL S1RELH A/D Converter Control Register Power Control Register Serial Channel 0 Buffer Register Serial Channel 0 Control Register Serial Channel 0 Reload Reg., Low Byte Serial Channel 0 Reload Reg., High Byte Serial Channel 1 Buffer Register Serial Channel 1 Control Register Serial Channel 1 Reload Reg., Low Byte Serial Channel 1 Reload Reg., High Byte D8 H 87H 99H 98H 1) AA H BA H 9C H 9BH 9D H BB H 00H 00H XX H 00H D9 H XXXX XX11 B 3) XX H 0X00 0000B 3) 00H XXXX XX11 B Watchdog IEN0 2) IEN1 2) IP0 2) WDTREL Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Watchdog Timer Reload Register A8 H B8 H A9H 86H 00H 00H 00H 00H Pow. Sav. Modes PCON 2) Power Control Register 87 H 00H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved. Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 83H WDTREL 00 H WDT- PSEL 87H PCON 00 H SMOD PDS IDLS SD GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 2) P1 FFH T2 CLK- OUT T2EX INT2 INT6 INT5 INT4 INT3 92H DPSEL XXXX- X000B 98H 2) S0CON 00H SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0 9AH IEN2 XX00- 00X0B – – ECR ECS ECT ECMP – ES1 9BH S1CON 0X00- 0000B SM – SM21 REN1 TB81 RB81 TI1 RI1 A0H 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers

2) IEN0 00H EAL WDT ET2 ES0 ET1 EX1 ET0 EX0 B0H 2) P3 FFH RD WR T1 T0 INT1 INT0 TxD0 RxD0 B1H SYSCON XXXX- XX01 B B8H 2) IEN1 00H EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC B9H IP1 XX00- 0000B BA H S0RELH XXXX- XX11 B BB H S1RELH XXXX- XX11 B C0 H IRCON0 00H EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC C1 H CCEN 00 H COCA COCA COCA COCA COCA COCA COCA COCA C8 H T2CON 00H T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 C9 H CC4EN 00 H COCO EN1 COCO COCO COCO COCO EN0 COCA COCA COMO 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PSW 00H CY AC F0 RS1 RS0 OV F1 P D1 H IRCON1 00 H ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0 D8 H ADCON0 00H BD CLK ADEX BSY ADM MX2 MX1 MX0 DA H ADDATL 00XX- XXXX B DC H ADCON1 0XXX- 0000B ADCL – – – MX3 MX2 MX1 MX0 E0H E1H CTCON 0X00. 0000B T2PS1 – ICR ICS CTF CLK2 CLK1 CLK0 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2) P4 FFH CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 EF H ARCON 0XXX. XXXX B F0H F8H 2) P5 FFH CCM7 CCM6 CCM5 CCM4 CCM3 CCM2 CCM1 CCM0 1) X means that the value is undefined and the location is reserved 2) Shaded registers are bit-addressable special function registers Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

The C517A allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P6 are performed via their corresponding special function registers P0 to P6. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time- multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. Analog Input Ports Ports 7 (8-bit) and 8 (4-bit) are input ports only and provide two functions. When used as digital inputs, the corresponding SFR P7 and P8 contains the digital value applied to the port 7/8 lines. When used for analog inputs the desired analog channel is selected by a four-bit field in SFR ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P7 or P8. This will have no effect. lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications VIL/VIH). Since P7 and P8 are not bit-addressable, all input lines of P7 and P8 are read at the same time by byte instructions. Nevertheless, it is possible to use port 7 and 8 simultaneously for analog and digital input. However, care must be taken that all bits of P7 and P8 that have an undetermined value caused by their analog function are masked.

Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4 : In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is fOSC /12. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC /24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the input clock logic. Figure 10 Timer/Counter 0 and 1 Input Clock Logic Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock M1 M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 fOSC /12x32 fOSC /24x32 1 16-bit timer/counter 1 1 fOSC /12 fOSC /24 2 8-bit timer/counter with 8-bit autoreload

3 Timer/counter 0 used as one

8-bit timer/counter and one 8-bit timer Timer 1 stops 12 fOSC /12 MCS01768 OSCf C/T TMOD Control Timer 0/1 Input Clock TCON TR 0/1 Gate TMOD P3.4/T0 P3.5/T1 max P3.2/INT0 P3.3/INT1 OSC /24f 1

Cpmpare / Capture Unit (CCU) The compare/capture unit is one of the C517A’s most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. The CCU consists of two 16-bit timer/counters with automatic reload feature and an array of 13 compare or compare/capture registers. A set of six control registers is used for flexible adapting of the CCU to a wide variety of user’s applications. The block diagram in figure 11 shows the general configuration of the CCU. All CC1 to CC4 registers and the CRC register are exclusively assigned to timer 2. Each of the eight compare registers CM0 through CM7 can either be assigned to timer 2 or to the faster compare timer, e.g. to provide up to 8 PWM output channels. The assignment of the CMx registers - which can be done individually for every single register - is combined with an automatic selection of one of the two possible compare modes. Figure 11 Timer 2 Block Diagram Capt./Comp. MCB01577 Max.Clock =fOSC Timer 2 (CM7) 16-bit Compare (CM0) Compare Timer Prescaler (CTREL) 16-bit Reload Comp. 4 (CC4) Capt./Comp. 3 (CC3) Capt./Comp. 2 (CC2) Capt./Comp.1 (CC1) 16-bit Rel.Capt. (CRC) "Internal Bus" Shadow Latch CC4EN Logik Control Port Latch P1- I/O- I/O- P5- Latch /12 Max.Clock = /2OSCf Prescaler Latch I/O- P4- Logik Port Control

The main functional blocks of the CCU are : – Timer 2 with fOSC /12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and overflow interrupt request. – Compare timer with fOSC /2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt request. – Compare/(reload/)capture register array consisting of four different kinds of registers: one 16-bit compare/reload/capture register, three 16-bit compare/capture registers, one 16-bit compare/capture register with additional "concurrent compare" feature, eight 16-bit compare registers with timer-overflow controlled loading. Table 5 shows the possible configurations of the CCU and the corresponding compare modes which can be selected. The following sections describe the function of these configurations. Table 5 CCU Configurations Assigned Timer Compare Register Compare Output at Possible Modes Timer 2 CRCH/CRCL CCH1/CCL1 CCH2/CCL2 CCH3/CCL3 CCH4/CCL4 P1.0/INT3 /CC0 P1.1/INT4/CC1 P1.2/INT5/CC2 P1.3/INT6/CC3 P1.4/INT2 /CC4 Compare mode 0, 1 + Reload Compare mode 0, 1 / capture Compare mode 0, 1 / capture Compare mode 0, 1 / capture Compare mode 0, 1 / capture CCH4/CCL4 P1.4/INT2 /CC4 P5.0/CCM0 to P5.7/CCM7 Compare mode 1 “Concurrent compare“ CMH0/CML0 to CMH7/CML7 P4.0/CM0 to P4.7/CM7 Compare mode 0 COMSET COMCLR P5.0/CCM0 to P5.7/CCM7 Compare mode 2 Compare Timer CMH0/CML0 to CMH7/CML7 P4.0/CM0 to P4.7/CM7 Compare mode 1

Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. Gated Timer Mode : In gated timer function, the external input pin P1.7/T2 operates as a gate to the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. The external gate signal is sampled once every machine cycle. Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1- to-0 transition at its corresponding external input pin P1.7/T2. In this function, the external input is sampled every machine cycle. The maximum count rate is 1/24 of the oscillator frequency.Reload of Timer 2 : Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon- ding input pin P1.5/T2EX. Figure 12 Block Diagram of Timer 2 MCB03328 Programmable OSC T2PS T2PS1 No input selected Timer stop00 Counter function via ext. input P1.7/T2 Timer function Gated timer function by ext. input P1.7/T2 T2I1 T2I0 SFR T2CON P1.7/T2 TL2 TH2 TF2 EXF2 Interrupt EXEN2 SyncP1.5/T2EX Reload Timer 2 Input Clock (8 Bits) (8 Bits) Prescaler

The compare timer receives its input clock from a programmable prescaler which provides input frequencies, ranging from fOSC /2 up to fOSC /256. The compare timer is, once started, a free-running 16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register. The compare timer has - as any other timer in the C517A - their own interrupt request flags CTF. These flags are set when the timer count rolls over from all ones to the reload value. Figure 13 shows the block diagram of compare timer and compare timer 1. Figure 13 Compare Timer Block Diagram 16-Bit Reload (CTREL) 16-Bit Compare Timer Control (CTCON) CTF Overflow To Interrupt Circuitry To Compare Circuitry 3-Bit Prescaler Compare Timer fOSC /2 MCB00783

The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 14 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. Figure 14 Port Latch in Compare Mode 0 Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. In compare mode 1 (see figure 15) the port circuit consists of two separate latches. One latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. MCS02661 Latch Port Q QCLK D Port Pin Read Pin CCV Read Latch Port Circuit Internal Bus Latch Write to Compare Reg. Compare Register Circuit Comparator Timer Register Timer Circuit Compare Match S R Overflow Timer

16 Bit

Compare Function in Compare Mode 1 Compare Mode 2 In the compare mode 2 the port 5 pins are under control of compare/capture register CC4, but under control of the compare registers COMSET and COMCLR. When a compare match occurs with register COMSET, a high level appears at the pins of port 5 when the corresponding bits in the mask register SETMSK are set. When a compare match occurs with register COMCLR, a low level appears at the pins of port 5 when the corresponding bits in the mask register CLRMSK are set. Figure 16 Compare Function of Compare Mode 2 MCS02662 Latch Port Q QCLK D Read Pin CCV D CLK Q Shadow Latch Read Latch Port Circuit Internal Bus Latch Write to Compare Reg. Compare Register Circuit Comparator Timer Register Timer Circuit Compare Match Pin Port16 Bit Q QCLK D Read Pin CCV Read Latch Port Circuit Internal Bus Latch Write to Comparator Compare Signal S R SETMSK Bits COMSET TH2 Comparator COMCLR Timer 2 TL2 Bits CLRMSKSignal Compare Pin Port

Multiplication / Division Unit (MDU) This on-chip arithmetic unit of the C517A provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are unsigned integer operations. Table 6 describes the five general operations the MDU is able to perform. 1) 1 tCY = 12 tCLCL = 1 machine cycle = 500 ns at 24 MHz oscillator frequency 2) The maximal shift speed is 6 shifts per machine cycle The MDU consists of seven special function registers (MD0-MD5, ARCON) which are used as operand, result, and control registers. The three operation phases are shown in figure 17. Figure 17 Operating Phases of the MDU Table 6 MDU Operation Characteristics Operation Result Remainder Execution Time 32bit/16bit 16bit/16bit 16bit x 16bit 32-bit normalize 32-bit shift L/R 32bit 16bit 32bit 16bit 16bit tCY 4 tCY 4 tCY 6 tCY 6 tCY

For starting an operation, registers MD0 to MD5 and ARCON must be written to in a certain sequence according table 7 and 8. The order the registers are accessed determines the type of the operation. A shift operation is started by a final write operation to SFR ARCON. Abbrevations : D'end : Dividend, 1st operand of division D'or : Divisor, 2nd operand of division M'and : Multiplicand, 1st operand of multiplication M'or : Multiplicator, 2nd operand of multiplication Pr : Product, result of multiplication Rem : Remainder Quo : Quotient, result of division ...L : means, that this byte is the least significant of the 16-bit or 32-bit operand ...H : means, that this byte is the most significant of the 16-bit or 32-bit operand Table 7 Programming the MDU for Multiplication and Division Operation 32Bit/16Bit 16Bit/16Bit 16Bit x 16Bit First Write Last Write MD0 D’endL MD1 D’end MD2 D’end MD3 D’endH MD4 D’orL MD5 D’orH MD0 D’endL MD1 D’endH MD4 D’orL MD5 D’orH MD0 M’andL MD4 M’orL MD1 M’andH MD5 M’orH First Read Last Read MD0 QuoL MD1 Quo MD2 Quo MD3 QuoH MD4 RemL MD5 RemH MD0 QuoL MD1 QuoH MD4 RemL MD5 RemH MD0 PrL MD1 MD2 MD3 PrH Table 8 Programming athe MDU for a Shift or Normalize Operation Operation Normalize, Shift Left, Shift Right First write Last write MD0 least significant byte MD1 . MD2 . MD3 most significant byte ARCON start of conversion First read Last read MD0 least significant byte MD1 . MD2 . MD3 most significant byte

The C517A has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation. The two channels are full-duplex, meaning they can transmit and receive simultaneously. The serial channel 0 is completely compatible with the serial channel of the C501 (one synchronous mode, three asynchronous modes). Serial channel 1 has the same functionality in its asynchronous modes, but the synchronous mode and the fixed baud rate UART mode is missing. The operating modes of the serial interfaces is illustrated in table 9. The possible baudrates can be calculated using the formulas given in table 10. Table 9 Operating Modes of Serial Interface 0 and 1 Serial Interface Mode S0CON S1CON Description SM0 SM1 SM 000 0 – Shift register mode Serial data enters and exits through R×D0; T×D0 outputs the shift clock; 8-bit are transmitted/received (LSB first); fixed baud rate 1 0 1 – 8-bit UART, variable baud rate 10 bits are transmitted (through T×D0) or received (at R×D0) 2 1 0 – 9-bit UART, fixed baud rate 11 bits are transmitted (through T×D0) or received (at R×D0) 3 1 1 – 9-bit UART, variable baud rate Like mode 2

1 A – – 0 9-bit UART; variable baud rate

11 bits are transmitted (through T×D1) or received (at R×D1) B – – 1 8-bit UART; variable baud rate 10 bits are transmitted (through T×D1) or received (at R×D1)

Table 10 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with its dependencies of the control bits BD and SMOD. Table 10 Serial Interfaces - Baud Rate Dependencies Serial Interface Operating Modes Active Control Bits Baud Rates SMOD BD Mode 0 (Shift Register)– – Fixed baud rate clock fosc/12 Mode 1 (8-bit UART) Mode 3 (9-bit UART) X 0 Timer 1 overflow is used for baud rate generation; SMOD controls a divide-by-2 option. Baud rate = 2SMOD x timer 1 overflow rate / 32

1 Baud rate generator is used for baud rate

generation; SMOD controls a divide-by-2 option Baud rate = 2 SMOD x oscillator frequency / 64 x (baud rate gen. overflow rate) Mode 2 (9-bit UART) X – Fixed baud rate clock fosc/32 (SMOD=1) or fosc/ 64 (SMOD=0) Mode A (9-bit UART) Mode B (8-bit UART) – – Baud rate generator is used for baud rate generation; SMOD controls a divide-by-2 option Baud rate = oscillator frequency / 32 x (baud rate gen. overflow rate)

The C517A provides an A/D converter with the following features: – 12 multiplexed input channels (port 7, 8), which can also be used as digital inputs – 10-bit resolution – Single or continuous conversion mode – Internal or external start-of-conversion trigger capability – Interrupt request generation after each conversion – Using successive approximation conversion technique via a capacitor array – Built-in hidden calibration of offset and linearity errors The A/D converter operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The externally applied reference voltage range has to be held on a fixed value within the specifications. The main functional blocks of the A/D converter are shown in figure 20.

ADCON0 (D8 ) internal MUX Port 7 S&H fADC OSCf VAREF VAGND P6.0/ADST Shaded bit locations are not used in ADC-functions MCB03332 Single/ Continuous Mode )(D9 (DA ) H Clock Prescaler ÷8, ÷4 ADCON1 (DC )H P7 (DB )H P8 (DD )H IRCON0 (C0 )H IEN1 (B8 )H Port 8 Bus Write to ADDATL Conversion Clock Input Clock INf Start of Conversion internal Bus IEX5 BSY EX5 CLK ADCL BD ADEX TF2 EXF2 IEX6 SWDTEXEN2 EX6 MX3 ADM _ MX2 MX1 MX2 MX1 IEX3 P8.3_ IEX4 P8.2 P8.1 IEX2 MX0 MX0 P8.0 IADC EADCEX4 EX3 EX2 MSB LSB HH Figure 20 A/D Converter Block Diagram

The C517A provides 17 interrupt sources with four priority levels. Ten interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, A/D converter, and serial interface 0 and 1) and seven interrupts may be triggered externally (P3.2/INT0, This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers. Figure 21 to 23 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections.

Interrupt Structure, Overview (Part 1) MCS03333 Bit addressable Request Flag is cleared by hardware IP1.0 H0003TCON.1 IEN0.0 IE0 EX0 P3.2/ IT0 TCON.0 IP0.0 Highest Priority Level ES1 RI1 IEN2.0 S1CON.0 0083 H UART 1 Timer 0 H000BTCON.5 IEN0.1 TF0 ET0Overflow INT0 INT2/ T2CON.5 I2FR P1.4/ EX2 IEX2 IEN1.1 IRCON0.1 Lowest Priority Level EAL IEN0.7 Polling Sequence 004B H IP0.1IP1.1 1_< TI1 S1CON.1 CC4 A/D Converter 0043IRCON0.0 IEN1.0 EADC IADC H

Interrupt Structure, Overview (Part 2) MCS03334 Bit addressable Request Flag is cleared by hardware IP1.2 H0013TCON.3 IEN0.2 IE1 EX1 P3.3/ IT1 TCON.2 IP0.2 Highest Priority Level ECMP IEN2.2 0093 H Match in CM0-CM7 Timer 1 H001BTCON.7 IEN0.3 TF1 ET1Overflow INT1 ECT CTF IEN2.3 CTCON.3 Lowest Priority Level EAL IEN0.7 Polling Sequence 009B H IP0.3IP1.3 0053 H IRCON1.0-7 ICMP0-7 I3FR T2CON.5 CC0 P1.0/ INT3/ IRCON0.2 IEN1.2 IEX3 EX3 Overflow Compare Timer IRCON0.3 IEX4 005B IEN1.3 EX4 HCC1 INT4/ P1.1/

Interrupt Structure, Overview (Part 3) MCS03335 Bit addressable Request Flag is cleared by hardware IP1.4 H0023 IP0.4 Highest Priority Level ES0 RI0 IEN0.4 S0CON.0 00A3 H USART 0 Timer 2 H002B IEN0.5 ET2 Overflow INT6/ P1.3/ EX6 IEX6 IEN1.5 IRCON0.5 Lowest Priority Level EAL IEN0.7 Polling Sequence 006B H IP0.5IP1.5 1_< TI0 S0CON.1 CC3 0063IRCON0.4 IEN1.4 EX5 IEX5 H CTCON.4 ECS IEN2.4 ICS TF2 IRCON0.6 _< 1 00ABCTCON.5 IEN2.5 ICR ECR H IRCON0.7 EXF2 IEN1.7 EXEN2 P1.2/ INT5/ CC2 P1.5/ T2EX Match in COMSET Match in COMCLR

Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003 H IE0 Timer 0 Overflow 000B H TF0 External Interrupt 1 0013 H IE1 Timer 1 Overflow 001B H TF1 Serial Channel 0 0023 H RI0 / TI0 Timer 2 Overflow / Ext. Reload 002BH TF2 / EXF2 A/D Converter 0043 H IADC External Interrupt 2 004B H IEX2 External Interrupt 3 0053 H IEX3 External Interrupt 4 005B H IEX4 External Interrupt 5 0063 H IEX5 External Interrupt 6 006B H IEX6 Serial Channel 1 0083 H RI1 / TI1 Compare Match Interupt of Compare Registers CM0-CM7 assigned to Timer 2 0093H ICMP0 - ICMP7 Compare Timer Overflow 009B H CTF Compare Match Interupt of Compare Register COMSET 00A3H ICS Compare Match Interupt of Compare Register COMCLR 00AB H ICR

The C517A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 512 µs up to – an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. The watchdog timer in the C517A is a 15-bit timer, which is incremented by a count rate of fOSC /24 up to fOSC /384. The system clock of the C517A is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit. Figure 24 Block Diagram of the Watchdog Timer The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD, but it cannot be stopped during active mode of the C517A. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. MCB03250 IP0 (A9 )H OSCf 2 16 WDTL WDTH /12 External HW Reset External HW Power-Down PE/SWD Control Logic IEN0 (A8 )H IEN1 (B8 )H 670 WDT Reset-Request WDTPSEL WDTREL (86 )H - WDT -- - - -- - SWDT -- - - --

The oscillator watchdog unit serves for four functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on- chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. – Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. – Restart from the hardware power down mode. If the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function. Figure 25 Block Diagram of the Oscillator Watchdog OWDS IP0 (A9 ) Frequency Comparator Delayf2 < 1f Internal Clock On-Chip Oscillator Oscillator RC XTAL1 XTAL2 RCf 3MHz MCB03337 H ÷ 5 ÷ 2 _< Internal Reset

The C517A provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. – Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset. – Slow down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals, to 1/8th of their normal operating frequency and also reduces power consumption. – Software power down mode The operation of the C517A is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. This power down mode is entered by software and can be left by reset. – Hardware Power down mode If pin HWPD gets active (low level) the part enters the hardware power down mode and starts a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and the port pins and several control lines enter a floating state. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. Table 12 gives a general overview of the entry and exit procedures of the power saving modes.

Power Saving Modes Overview Mode Entering 2-Instruction Example Leaving by Remarks Idle mode ORL PCON, #01H ORL PCON, #20H Ocurrence of an interrupt from a peripheral unit CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Hardware Reset Slow Down Mode In normal mode : ORL PCON,#10H ANL PCON,#0EFH or Hardware Reset Internal clock rate is reduced to 1/8 of its nominal frequency With idle mode : ORL PCON,#01H ORL PCON, #30H Ocurrence of an interrupt from a peripheral unit CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with 1/8 of its nominal frequency Hardware reset Software Power Down Mode ORL PCON, #02H ORL PCON, #40H Hardware Reset Oscillator is stopped; contents of on-chip RAM and SFR’s are maintained; Rising edge at PE /SWD Hardware Power Down Mode HWPD = 0 HWPD = 1 Oscillator is stopped; internal reset is executed;

Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions V IN > V DD or V IN < V SS ) the voltage on V DD pins with respect to ground (V SS ) must not exceed the values defined by the absolute maximum ratings. Operating Conditions Parameter Symbol Limit Values Unit Notes min. max. Storage temperature TST – 65 150 °C – Voltage on VDD pins with respect to ground (VSS ) VDD –0.5 6.5 V– Voltage on any pin with respect to ground (VSS ) VIN –0.5 VDD + 0.5 V– Input current on any pin during overload condition –10 10 mA – Absolute sum of all input currents during overload condition – | 100 | mA – Power dissipation PDISS –T B D W – Parameter Symbol Limit Values Unit Notes min. max. Supply voltage VDD 4.25 5.5 V – Ground voltage VSS 0 V– Ambient temperature SAB-C517A SAF-C517A SAH-C517A TA TA TA –40 –40 110 18 and 24 MHz 18 and 24 MHz

18 MHz

Analog reference voltage VAREF 4 VDD + 0.1 V – Analog ground voltage VAGND VSS - 0.1 VSS + 0.2 V – Analog input voltage VAIN VAGND VAREF V– CPU clock fCPU 3.5 24 MHz –

(Operating Conditions apply) Notes see next page Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage Pins except EA,RESET ,HWPD EA pin HWPD and RESET pins VIL VIL1 VIL2 –0 . 5 –0 . 5 –0 . 5 0.2 VDD – 0.1 0.2 VDD – 0.3 0.2 VDD + 0.1 V V V Input high voltage pins except RESET , XTAL2 and HWPD XTAL2 pin RESET and HWPD pin VIH VIH1 VIH2 0.2VDD + 0.9 0.7VDD 0.6VDD VDD + 0.5 VDD + 0.5 VDD + 0.5 V V V Output low voltage Ports 1, 2, 3, 4, 5, 6 Port 0, ALE, PSEN , RO VOL VOL1 0.45 0.45 V V I OL = 1.6 mA 1) I OL = 3.2 mA 1) Output high voltage Ports 1, 2, 3, 4, 5, 6 Port 0 in external bus mode, ALE, PSEN , RO VOH VOH1 2.4 0.9 VDD 2.4 0.9VDD V V V V I OH = – 80 µA I OH = – 10 µA I OH = – 800 µA2) I OH = – 80 µA 2) Logic 0 input current Ports 1, 2, 3, 4, 5, 6 I LI – 10 – 70 µA V I N = 2 V Logical 0-to-1 transition current, Ports 1, 2, 3, 4, 5, 6 I TL – 65 – 650 µA V I N = 2 V Input leakage current Port 0, 7 and 8, EA, HWPD I LI – ± 1 µA 0.45 < V I N < VDD Input low current to RESET for reset XTAL2 PE /SWD, OWE I IL2 I IL3 I IL4 – 10 – 100 – 15 – 20 µA µA µA V IN = 0.45 V V I N = 0.45 V V I N = 0.45 V Pin capacitance C IO – 10 pF fC = 1 MHz, T A = 25°C Overload current IOV – ± 5m A 7) 8)

Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = RESET = Port 0 = Port 7 = Port 8 =V DD ; XTAL1 = N.C.; XTAL2 =V SS ; PE/SWD = OWE = V SS ; HWPD = VDD for software power-down mode; VAGND = VSS ; VAREF = VDD ; all other pins are disconnected. IPD (hardware power-down mode) is independent of any particular pin connection. 4) IDD (active mode) is measured with: XTAL2 driven with tCLCH , tCHCL =5n s, VIL= VSS +0 . 5V , VIH = VDD – 0.5 V; XTAL1 = N.C.; EA =P E/SWD == V SS ; Port 0 = Port 7 = Port 8 =V DD ; HWPD = V DD ; RESET = V DD ; all other pins are disconnected. 5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL =5n s , VIL= VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL1 = N.C.; RESET = VDD ; HWPD = Port 0 = Port 7 = Port 8 =VDD ;E A=P E/SWD = VSS ; all other pins are disconnected; 6) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL =5n s, VIL= VSS +0 . 5V , VIH = VDD – 0.5 V; XTAL1 = N.C.; HWPD = VDD ; RESET = VDD ; Port 7 = Port 8 =VDD ;; EA=P E/SWD == VSS ; all other pins are disconnected. 7) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits. 8) Not 100% tested, guaranteed by design characterization 9) The typical IDD values are periodically measured at TA = +25 °C and VDD = 5 V but not 100% tested. 10)The maximum IDD values are measured under worst case conditions (TA = 0 °C or -40 °C and VDD =5 . 5V ) Parameter Symbol Limit Values Unit Test Condition typ. 9) max. 10) Active mode 18 MHz

24 MHz

21.3 27.3 29.2 37.6 mA mA Idle mode 18 MHz 11.6 14.6 16.2 20.4 mA mA Active mode with slow-down enabled 9.5 10.7 13.1 14.9 mA mA Power-down mode IPD 15 50 µA VDD =2 … 5.5 V 3)

Note : fosc is the oscillator frequency in MHz. IDD values are given in mA. Table 13 Power Supply Current Calculation Formulas Parameter Symbol Formula Active mode IDD typ IDD max 1 * fOSC + 3.3 1.4 * fOSC + 4.0 Idle mode IDD typ IDD max 0.5 * fOSC + 2.6 0.7 * fOSC + 3.6 Active mode with slow-down enabled IDD typ IDD max 0.25 * fOSC + 4.95 0.3 * fOSC + 7.7 MCD03338 fOSC CCΙ 3.5 8 12 16 20 24 MHz mA CC typΙ ΙCC max Active Mode Idle Mode Idle Mode Active Mode Active + Slow Down Mode IDD IDD IDD

A/D Converter Characteristics (Operating Conditions apply) Notes see next page. Clock calculation table : Further timing conditions : tADC min = 500 ns tIN = 2 / fOSC = 2 tCLCL Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage VAIN VAGND VAREF V 1) Sample time tS – 16 x tIN 8 x tIN ns Prescaler ÷ 8 Prescaler ÷ 4 2) Conversion cycle time tADCC – 96 x tIN 48 x tIN ns Prescaler ÷ 8 Prescaler ÷ 4 3) Total unadjusted error TUE – ± 2 LSB V SS +0.5V ≤ VIN ≤ VDD -0.5V 4) Internal resistance of reference voltage source RAREF – tADC / 250 - 0.25 kΩ tADC in [ns] 5) 6) Internal resistance of analog source RASRC – tS / 500 - 0.25 kΩ tS in [ns] 2) 6) ADC input capacitance C AIN –5 0p F 6) Clock Prescaler Ratio ADCL t ADC t S t ADCC ÷ 81 8 x t IN 16 x t IN 96 x t IN ÷ 40 4 x t IN 8 x t IN 48 x t IN

Notes: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH , respectively. 2) During the sample time the input capacitance C AIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization.

AC Characteristics (18 MHz) (Operating Conditions apply) (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C517A to devices with float times up to 45 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. CLKOUT Characteristics Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 18 MHz min. max. min. max. ALE pulse width tLHLL 71 –2 tCLCL – 40 – ns Address setup to ALE tAVLL 26 – tCLCL – 30 – ns Address hold after ALE tLLAX 26 – tCLCL – 30 – ns ALE low to valid instruction intLLIV – 122 – 4 tCLCL – 100 ns ALE to PSEN tLLPL 31 – tCLCL – 25 – ns PSEN pulse width tPLPH 132 – 3 tCLCL – 35 – ns PSEN to valid instruction intPLIV –9 2 – 3 tCLCL – 75 ns Input instruction hold after PSENtPXIX 0 – 0–n s Input instruction float after PSEN tPXIZ *) –4 6 – tCLCL – 10 ns Address valid after PSEN tPXAV *) 48 – tCLCL – 8 – ns Address to valid instr in tAVIV – 180 – 5 tCLCL – 98 ns Address float to PSEN tAZPL 0 – 0–n s Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 18 MHz min. max. min. max. ALE to CLKOUT tLLSH 349 – 7 tCLCL – 40 – ns CLKOUT high time tSHSL 71 – 2 tCLCL – 40 – ns CLKOUT low time tSLSH 516 – 10 tCLCL – 40 – ns CLKOUT low to ALE high tSLLH 16 96 tCLCL – 40 tCLCL + 40 ns

AC Characteristics (18 MHz, cont’d) External Data Memory Characteristics External Clock Drive Characteristics Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 18 MHz min. max. min. max. RD pulse width tRLRH 233 –6 tCLCL – 100 – ns WR pulse width tWLWH 233 – 6 tCLCL – 100 – ns Address hold after ALE tLLAX2 81 – 2 tCLCL – 30 – ns RD to valid data in tRLDV – 128 – 5 tCLCL – 150 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ –5 1 – 2 tCLCL – 60 ns ALE to valid data in tLLDV – 294 – 8 tCLCL – 150 ns Address to valid data in tAVDV – 335 – 9 tCLCL – 165 ns ALE to WR or RD tLLWL 117 217 3 tCLCL – 50 3 tCLCL + 50 ns Address valid to WR or RD tAVWL 92 – 4 tCLCL – 130 – ns WR or RD high to ALE high tWHLH 16 96 tCLCL – 40 tCLCL + 40 ns Data valid to WR transition tQVWX 11 – tCLCL – 45 – ns Data setup before WR tQVWH 239 – 7 tCLCL – 150 – ns Data hold after WR tWHQX 16 – tCLCL – 40 – ns Address float after RD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 18 MHz min. max. Oscillator period tCLCL 55.6 285.7 ns High time tCHCX 15 tCLCL – tCLCX ns Low time tCLCX 15 tCLCL – tCHCX ns Rise time tCLCH –1 5 n s Fall time tCHCL –1 5 n s

AC Characteristics (24 MHz) (Operating Conditions apply) (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C517A to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. CLKOUT Characteristics Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max. ALE pulse width tLHLL 43 –2 tCLCL – 40 – ns Address setup to ALE tAVLL 17 – tCLCL – 25 – ns Address hold after ALE tLLAX 17 – tCLCL – 25 – ns ALE low to valid instruction intLLIV –8 0 – 4 tCLCL – 87 ns ALE to PSEN tLLPL 22 – tCLCL – 20 – ns PSEN pulse width tPLPH 95 – 3 tCLCL – 30 – ns PSEN to valid instruction intPLIV –6 0 – 3 tCLCL – 65 ns Input instruction hold after PSENtPXIX 0 – 0–n s Input instruction float after PSEN tPXIZ *) –3 2 – tCLCL – 10 ns Address valid after PSEN tPXAV *) 37 – tCLCL – 5 – ns Address to valid instr in tAVIV – 148 – 5 tCLCL – 60 ns Address float to PSEN tAZPL 0 – 0–n s Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max. ALE to CLKOUT tLLSH 252 – 7 tCLCL – 40 – ns CLKOUT high time tSHSL 43 – 2 tCLCL – 40 – ns CLKOUT low time tSLSH 377 – 10 tCLCL – 40 – ns CLKOUT low to ALE high tSLLH 28 2 tCLCL – 40 tCLCL + 40 ns

AC Characteristics (24 MHz, cont’d) External Data Memory Characteristics External Clock Drive Characteristics Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 24 MHz min. max. min. max. RD pulse width tRLRH 180 –6 tCLCL – 70 – ns WR pulse width tWLWH 180 – 6 tCLCL – 70 – ns Address hold after ALE tLLAX2 53 – 2 tCLCL – 30 – ns RD to valid data in tRLDV – 118 – 5 tCLCL – 90 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ –6 3 – 2 tCLCL – 20 ns ALE to valid data in tLLDV – 200 – 8 tCLCL – 133 ns Address to valid data in tAVDV – 220 – 9 tCLCL – 155 ns ALE to WR or RD tLLWL 75 175 3 tCLCL – 50 3 tCLCL + 50 ns Address valid to WR or RD tAVWL 67 – 4 tCLCL – 97 – ns WR or RD high to ALE high tWHLH 17 67 tCLCL – 25 tCLCL + 25 ns Data valid to WR transition tQVWX 5– tCLCL – 37 – ns Data setup before WR tQVWH 170 – 7 tCLCL – 122 – ns Data hold after WR tWHQX 15 – tCLCL – 27 – ns Address float after RD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 24 MHz min. max. Oscillator period tCLCL 41.7 285.7 ns High time tCHCX 12 tCLCL – tCLCX ns Low time tCLCX 12 tCLCL – tCHCX ns Rise time tCLCH –1 2 n s Fall time tCHCL –1 2 n s

A0 - A7 Instr.IN A0 - A7Port 0 tAVLL PLPH t tLLPL tLLIV tPLIV tAZPL tLLAX tPXIZ tPXIX tAVIV tPXAV

ROM Verification Characteristics for the C517A-4RM/4RN ROM Verification Mode 1 Figure 32 ROM Verification Mode 1 Parameter Symbol Limit Values Unit min. max. Address to valid data tAVQV – 10 tCLCL ns P1.0-P1.7 P2.0-P2.6 Port 0 MCS03253 Address New Address New Data OutData Out t AVQV Data: Addresses: P0.0-P0.7 P1.0-P1.7 P2.0-P2.6 D0-D7 A0-A7 A8-A14 VRESET = IL2 PSENInputs: ALE, EA SS V V IH

Parameter Symbol Limit Values Unit min. typ max. ALE pulse width tAWD –2 tCLCL –n s ALE period tACY – 12 tCLCL –n s Data valid after ALE tDVA ––4 tCLCL ns Data stable after ALE tDSA 8 tCLCL ––n s P3.5 setup to ALE low tAS – tCLCL –n s Oscillator frequency 1/ tCLCL 3.5 – 24 MHz MCT02613 tACY tAWD tDSA DVAt tAS Data Valid ALE Port 0 P3.5

Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package) GPR05365

Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device Plastic Package, P-LCC-84-2 (SMD) (Plastic Leaded Chip-Carrier) ±0.10.43 1.27 0.5 min. 3.81 0.1 4.58 max. ±0.5 25.4 28.2 2) 84 1 29.31±0.0761) 1.14 x 45˚ Index Marking ±0.1330.23 ±0.5 1.27 x 45˚ 0.2 1) Does not include plastic or metal protrusions of 0.25 max. per side 0.18 84xM 30.23±0.13 29.31±0.076 2) Dimension from center to center