C515C-8RM

C515C INFINEON | Alldatasheet

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Data Sheet, Feb. 2003 Microcontrollers Never stop thinking. C515C 8-Bit Single-Chip Microcontroller

Published by Infineon Technologies AG, St.-Martin-Strasse 53,

81669 München, Germany

© Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, Feb. 2003 C515C 8-Bit Single-Chip Microcontroller Microcontrollers Never stop thinking.

Enhanced Hooks Technology™ is a trademark of Infineon Technologies. C515C Data Sheet Revision History: 2003-02 Previous Version: 2000-08 Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

C515C8-Bit Single-Chip Microcontroller

Features

 Full upward compatibility with SAB 80C515A  On-chip program memory (with optional memory protection) – C515C-8R 64 Kbytes on-chip ROM – C515C-8E 64 Kbytes on-chip OTP – alternatively up to 64 Kbytes external program memory  256 bytes on-chip RAM  2 Kbytes of on-chip XRAM  Up to 64 Kbytes external data memory  Superset of the 8051 architecture with 8 datapointers  Up to 10 MHz external operating frequency (1 µs instruction cycle time at 6 MHz external clock)  On-chip emulation support logic (Enhanced Hooks Technology)  Current optimized oscillator circuit and EMI optimized design (further features are on next page) Figure 1 C515C Functional Units MCA03646 On-Chip Emulation Support Module Port 0 Port 1 Port 2 Port 3 RAM 256 x 8 XRAM CPU USART I/O I/O I/O I/O

8 Datapointer

Port 7 Port 6 Port 5 Port 4 Capture/Compare Unit Timer 2 Full-CAN Controller

10 Bit ADC

(8 inputs) Oscillator Watchdog Save Modes Idle/ Power down Slow down SSC (SPI) Interface I/O I/O I/OAnalog/ Digital Input Power Bit8 2k x 8 C515C-8R : 64k x 8 ROM Program Memory C515C-8E : 64k x 8 OTP

 Eight ports: 48 + 1 digital I/O lines, 8 analog inputs – Quasi-bidirectional port structure (8051 compatible) – Port 5 selectable for bidirectional port structure (CMOS voltage levels)  Full-CAN controller on-chip – 256 register/data bytes are located in external data memory area – max. 1 MBaud at 8 - 10 MHz operating frequency  Three 16-bit timer/counters – Timer 2 can be used for compare/capture functions  10-bit A/D converter with multiplexed inputs and built-in self calibration  Full duplex serial interface with programmable baudrate generator (USART)  SSC synchronous serial interface (SPI compatible) – Master and slave capable – Programmable clock polarity/clock-edge to data phase relation – LSB/MSB first selectable – 2.5 MHz transfer rate at 10 MHz operating frequency  Seventeen interrupt vectors, at four priority levels selectable  Extended watchdog facilities – 15-bit programmable watchdog timer – Oscillator watchdog  Power saving modes –S l o w - d o w n m o d e – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake-up capability through INT0 or RXDC pin – Hardware power-down mode  CPU running condition output pin  ALE can be switched off  Multiple separate VDD/VSS pin pairs  P-MQFP-80-1 package  Temperature Ranges: SAB-C515C versions: TA = 0 to 70 °C SAF-C515C versions: TA = -40 to 85 °C SAH-C515C versions: TA = -40 to 110 °C Note: Versions for extended temperature range -40 °C to 110 °C (SAH-C515C) are available on request. The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time (1 µs at 6 MHz).

The C515C-8R contains a non-volatile 64 Kbytes read-only program memory. The C515C-L is identical to the C515C-8R, except that it lacks the on-chip program memory. The C515C-8E is the OTP version in the C515C microcontroller with an on-chip 64 Kbytes one-time programmable (OTP) program memory. The C515C is mounted in a P-MQFP-80-1 package. If compared to the C515C-8R and C515C-L, the C515C-8E OTP version additionally provides two features:  The wake-up from software power down mode can, additionally to the external pin P3.2/INT0 wake-up capability, also be triggered alternatively by a second pin P4.7/RXDC.  For power consumption reasons the on-chip CAN controller can be switched off. Note: The term C515C refers to all versions described within this document unless otherwise noted.

Ordering Information

The ordering code for Infineon Technologies’ microcontrollers provides an exact reference to the required product. This ordering code identifies:  The derivative itself, i.e. its function set  The specified temperature rage  The package and the type of delivery For the available ordering codes for the C515C please refer to the “Product information Microcontrollers”, which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Table 1 Differences in Internal Program Memory of the C505 MCUs Device Internal Program Memory ROM OTP C515C-LM –– C515C-8RM 64 Kbytes – C515C-8EM – 64 Kbytes

8 Bit Digital I/O

1 Bit Digital I/O

8 Bit Analog/

Figure 3 C515C Pin Configuration P-MQFP-80-1 (top view) MCP02715 N.C. 345 P6.7/AIN7 6P6.6/AIN6 7P6.5/AIN5 8P6.4/AIN4 9P6.3/AIN3 10P6.2/AIN2 11P6.1/AIN1 12P6.0/AIN0 13 14 15 P3.0/RXD 16P3.1/TXD 17P3.2/INT0 18P3.3/INT1 19P3.4/T0 20P3.5/T1VAGND 4142434445464748495051525354555657585960 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 EA ALE PSEN CPUR P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P4.7/RXDC P4.6/TXDC P4.5/INT8 P4.4/SLS P4.3/STO PE/SWD P4.2/SRI P4.1/SCLK P4.0/ADST N.C. HWPD P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 VSSE1 P3.6/WR P3.7/RD P1.7/T2 P1.6/CLKOUT P1.5/T2EX P1.4/INT2 P1.3/INT6/CC3 P1.2/INT5/CC2 P1.1/INT4/CC1 P1.0/INT3/CC0 XTAL2 XTAL1 P2.0/A8 P2.1/A9 4061 P5.6 P5.7 SS1V VDDE1 DD1V P2.2/A10 AREFV RESET C515C VSSCLK DDCLKV P7.0/INT7 VDDEXT SSEXTV VDDE2 SSE2V

Table 2 Pin Definitions and Functions Symbol Pin Number I/O 1) Function P-MQFP-80-1 RESET 1I RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515C. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS . VAREF 3– Reference voltage for the A/D converter VAGND 4– Reference ground for the A/D converter P6.0-P6.7 12-5 I Port 6 is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages and for the eight multiplexed analog inputs. P7.0 / INT7

23 I/O Port 7

is an 1-bit quasi-bidirectional I/O port with internal pull-up resistor. When a 1 is written to P7.0 it is pulled high by an internal pull-up resistor, and in that state can be used as input. As input, P7.0 being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pull-up resistor. If P7.0 is used as interrupt input, its output latch must be programmed to a one (1). The secondary function is assigned to the port 7 pin as follows: P7.0 INT7 , Interrupt 7 input

P3.0-P3.7 15-22 I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RXD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 TXD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 INT0 External interrupt 0 input / timer 0 gate control input P3.3 INT1 External interrupt 1 input / timer 1 gate control input P3.4 T0 Timer 0 counter input P3.5 T1 Timer 1 counter input P3.6 WR WR control output; latches the data byte from port 0 into the external data memory P3.7 RD RD control output; enables the external data memory Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-80-1

P1.0 - P1.7 31-24 I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 INT3 CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 INT4 CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 INT5 CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 INT6 CC3 Interrupt 6 input / compare 3 output / capture 3 input P1.4 INT2 Interrupt 2 input P1.5 T2EX Timer 2 external reload / trigger input P1.6 CLKOUT System clock output P1.7 T2 Counter 2 input XTAL2 36 I XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-80-1

Output of the inverting oscillator amplifier. P2.0-P2.7 38-45 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. CPUR

46 O CPU Running Condition

This output pin is at low level when the CPU is running and program fetches or data accesses in the external data memory area are executed. In idle mode, hardware and software power down mode, and with an active RESET signal CPUR is set to high level. CPUR can be typically used for switching external memory devices into power saving modes. PSEN 47 O The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-80-1

ALE 48 O The Address Latch Enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally. EA

49 I External Access Enable

When held high, the C515C executes instructions always from the internal ROM. When held low, the C515C fetches all instructions from external program memory. Note: For the ROM protection version EA pin is latched during reset. P0.0-P0.7 52-59 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515C. External pullup resistors are required during program verification. P5.0-P5.7 67-60 I/O Port 5 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup resistors. Port 5 can also be switched into a bidirectional mode, in which CMOS levels are provided. In this bidirectional mode, each port 5 pin can be programmed individually as input or output. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-80-1

HWPD 69 I Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515C. A low level for a longer period will force the part to power down mode with the pins floating. I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pull-up resistors. P4 also contains the external A/D converter control pin, the SSC pins, the CAN controller input/output lines, and the external interrupt 8 input. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The alternate functions are assigned to port 4 as follows: P4.0 ADST External A/D converter start pin P4.1 SCLK SSC Master Clock Output / SSC Slave Clock Input P4.2 SRI SSC Receive Input P4.3 STO SSC Transmit Output P4.4 SLS Slave Select Input P4.5 INT8 External interrupt 8 input P4.6 TXDC Transmitter output of the CAN controller P4.7 RXDC Receiver input of the CAN controller Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-80-1

PE/SWD 75 I Power saving mode enable / Start watchdog timer A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. VSSCLK 13 – Ground (0 V) for on-chip oscillator This pin is used for ground connection of the on-chip oscillator circuit. VDDCLK 14 – Supply voltage for on-chip oscillator This pin is used for power supply of the on-chip oscillator circuit. VDDE1 VDDE2 – Supply voltage for I/O ports These pins are used for power supply of the I/O ports during normal, idle, and power down mode. VSSE1 VSSE2 – Ground (0 V) for I/O ports These pins are used for ground connections of the I/O ports during normal, idle, and power down mode. VDD1 33 – Supply voltage for internal logic This pins is used for the power supply of the internal logic circuits during normal, idle, and power down mode. VSS1 34 – Ground (0 V) for internal logic This pin is used for the ground connection of the internal logic circuits during normal, idle, and power down mode. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-80-1

VDDEXT 50 – Supply voltage for external access pins This pin is used for power supply of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN , P3.6/WR, and P3.7/RD). VSSEXT 51 – Ground (0 V) for external access pins This pin is used for the ground connection of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN, P3.6/WR, and P3.7/RD). N.C. 2, 71 – Not connected These pins should not be connected. 1) I = Input; O = Output Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-80-1

Figure 4 Block Diagram of the C515C MCB03647 Oscillator Watchdog OSC & Timing CPU Timer 1 Timer 2 A/D Converter Timer 0 S & H MUX XRAM 2k x 8 256 x 8 RAM ROM/OTP Port 0 Port 1 Port 2 Port 3 Port 0 Port 1 Port 2 XTAL2 XTAL1 RESET ALE EA VAGND AREFV Support Emulation Logic

8 Datapointers

V C515C /DD SSV 64k x 8 CPUR SSC (SPI) Interface Digital Inputs Port 5 Port 4 Port 3 Port 6 Port 7 Reg./Data

256 Byte

10 Bit

The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1 µs (10 MHz: 600 ns). PSW Special Function Register (D0 H) Reset Value: 00 H Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag PP a r i t y F l a g Set/cleared by hardware after each instruction to indicate an odd/even number of “one” bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 PD0H PSW D7H D6H D5H D4H D3H D2H D1H D0H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H-07H 0 1 Bank 1 selected, data address 08 H-0FH 1 0 Bank 2 selected, data address 10 H-17H 1 1 Bank 3 selected, data address 18 H-1FH

Control of XRAM/CAN Controller Access The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller. SYSCON Special Function Register (B1 H) C515C-8R Reset Value: X010XX01 B C515C-8E Reset Value: X010X001B Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. Bit Function XMAP1 XRAM/CAN controller visible access control Control bit for RD/WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0: The signals RD and WR are not activated during accesses to the XRAM/CAN Controller XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally. XMAP0 Global XRAM/CAN controller access enable/disable control XMAP0 = 0: The access to XRAM and CAN controller is enabled. XMAP0 = 1: The access to XRAM and CAN controller is disabled (default after reset). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. 76543210 Bit No. MSB LSB EALE RMAP –B1H SYSCONCSWO XMAP1–P M O D XMAP0 The function of the shaded bits is not described in this section.

The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN controller, the effective address stored in DPTR must be in the range of F700H to FFFFH. The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which use only an 8-bit address (indir ect addressing with registers R0 or R1). Therefore, a special page register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the state of pin EA. Table 3 lists the various operating conditions.

modes compatible to 8051/C501 family Table 3 Behaviour of P0/P2 and RD /WR During MOVX Accesses XMAP1, XMAP0 00 10 X1 EA = 0 MOVX @DPTR DPTR XRAM/CAN address range a) P0/P2→Bus b) RD/WR active c) ext.memory is used a) P0/P2→Bus b) RD/WR active c) ext.memory is used a) P0/P2→Bus b) RD/WR active c) ext.memory is used DPTR XRAMCAN address range a) P0/P2→Bus (RD/WR-Data) b) RD/WR inactive c) XRAM is used a) P0/P2→Bus (RD/WR-Data) b) RD/WR active c) XRAM is used a) P0/P2→Bus b) RD/WR active c) ext.memory is used MOVX @ Ri XPAGE XRAMCAN addr. page range a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used XPAGE XRAMCAN addr. page range a) P0→Bus (RD/WR-Data) P2→I/O b) RD/WR inactive c) XRAM is used a) P0→Bus (RD/WR-Data only) P2→I/O b) RD/WR active c) XRAM is used a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used EA = 1 MOVX @DPTR DPTR XRAM/CAN address range a) P0/P2→Bus b) RD/WR active c) ext.memory is used a) P0/P2→Bus b) RD/WR active c) ext.memory is used a) P0/P2→Bus b) RD/WR active c) ext.memory is used DPTR XRAMCAN address range a) P0/P2→Ι/0 b) RD/WR inactive c) XRAM is used a) P0/P2→Bus (RD/WR-Data) b) RD/WR active c) XRAM is used a) P0/P2→Bus b) RD/WR active c) ext.memory is used MOVX @ Ri XPAGE XRAMCAN addr. page range a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used XPAGE XRAMCAN addr. page range a) P2→I/O P0/P2→I/O b) RD/WR inactive c) XRAM is used a) P0→Bus (RD/WR-Data) P2→I/O b) RD/WR active c) XRAM is used a) P0→Bus P2→I/O b) RD/WR active c) ext.memory is used

Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. MCS03280 SYSCON PCON TCON RESET EA PSEN ALE Port Port I/O Ports Optional Port 3 Port 1 C500 MCU Interface Circuit Enhanced Hooks RPort 0RPort 2 RTCON RPCON RSYSCON TEA TALE TPSEN EH-IC Target System Interface ICE-System Interface to Emulation Hardware

Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Two special function regi sters of the C515C (PCON1 and DIR5) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0”). As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each. SYSCON Special Function Register (B1 H) C515C-8R Reset Value: X010XX01 B C515C-8E Reset Value: X010X001 B The 59 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C515C are listed in Table 4 and Table 5. In Table 4 they are organized in groups which refer to the functional blocks of the C515C. The CAN- SFRs are also included in Table 4. Table 5 illustrates the contents of the SFRs in numeric order of their addresses. Table 6 list the CAN-SFRs in numeric order of their addresses. Bit Function RMAP Special function register map bit RMAP = 0: The access to the non-mapped (standard) special function register area is enabled (reset value). RMAP = 1: The access to the mapped special function register area is enabled. 76543210 Bit No. MSB LSB EALE RMAP –B1H SYSCONCSWO XMAP1–P M O D XMAP0 The function of the shaded bits is not described in this section.

Table 4 Special Function Registers - Functional Block Block Symbol Name Addr Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP SYSCON Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register C515C-8R C515C-8E H F0H 83H 82H 92H D0H 81H B1H B1H 00H 00H 00H 00H XXXXX000B 00H 07H X010XX01B X010X001B A/D- Converter ADCON01) ADCON1 ADDATH ADDATL A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte H DCH D9H DAH 00H 0XXXX000B 00H 00XXXXXXB Interrupt System IEN01) IEN11) IEN2 IP01) IP1 TCON T2CON1) SCON1) IRCON Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register H B8H 9AH A9H B9H 88H C8H 98H C0H 00H 00H XX00X00XB 00H 0X000000B 00H 00H 00H 00H XRAM XPAGE SYSCON1) Page Address Register for Extended on-chip XRAM and CAN Controller System Control Register C515C-8R C515C-8E 91H B1H B1H 00H X010XX01B X010X001B Ports P0 DIR5 SYSCON Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 5 Direction Register Port 6, Analog/Digital Input Port 7 System Control Register C515C-8R C515C-8E H 90H A0H B0H E8H F8H F8H 2)4) DBH FAH B1H FFH FFH FFH FFH FFH FFH FFH XXXXXXX1B X010XX01B X010X001B Watchdog WDTREL IEN01) IEN11) IP01) Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 H A8H B8H A9H 00H 00H 00H 00H

ADCON01) PCON1) SBUF SCON SRELL SRELH A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte H 87H 99H 98H AAH BAH 00H 00H XXH 00H D9H XXXXXX11B CAN Controller CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0n DB1n DB2n DB3n DB4n DB5n DB6n DB7n Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers: Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7 F700 H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH F70CH F70DH F70EH F70FH F7n0H F7n1H F7n2H F7n3H F7n4H F7n5H F7n6H F7n7H F7n8H F7n9H F7nAH F7nBH F7nCH F7nDH F7nEH 101H XXH XXH UUH 0UUUUUUUB UUH UUU11111B UUH UUH UUH UUUUU000B UUH UUH UUH UUUUU000B UUH UUH UUH UUH UUH UUUUU000B UUUUUU00B XXH XXH XXH XXH XXH XXH XXH XXH Table 4 Special Function Registers - Functional Block (cont’d) Block Symbol Name Addr Contents after Reset

SSC Interrupt Enable Register SSC Mode Test Register H 94H 95H ABH ACH 96H 07H XXH XXH XXXXXX00B XXXXXX00B 00H Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register H 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Compare/ Capture Unit/ Timer 2 CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Power Save Modes PCON1) PCON1 Power Control Register Power Control Register 1 C515C-8R C515C-8E H 88H 88H 00H 0XXXXXXXB 0XX0XXXXB 1) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 2) Bit-addressable special function registers 3) “X” means that the value is undefined and the location is reserved. 4) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. 5) The notation “n” in the message object address definition defines the number of the related message object. 6) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation. 7) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Table 4 Special Function Registers - Functional Block (cont’d) Block Symbol Name Addr Contents after Reset

Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 86H WDTREL 00 H WDT PSEL 87H PCON 00 H SMOD PDS IDLS SD GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 3) PCON14) 0XXX- XXXXB 88H 3) PCON15) 0XX0- XXXXB 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 2) P1 FFH T2 CLK- OUT T2EX INT2 INT6 INT5 INT4 INT3 92H DPSEL XXXX- X000B 93H SSCCON 07 H SCEN TEN MSTR CPOL CPHA BRS2 BRS1 BRS0 96H SSCMOD 00 H LOOPB TRIO 0 0 0 0 0 LSBSM 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI 9AH IEN2 X00X- X00XB – – EX8 EX7 – ESSC ECAN – A0H A8H 2) IEN0 00H EAL WDT ET2 ES ET1 EX1 ET0 EX0

2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B1H SYSCON4) X010- XX01B – PMOD EALE RMAP – – XMAP1 XMAP0 B1H SYSCON5) X010- X001B – PMOD EALE RMAP – CSWO XMAP1 XMAP0 B8H 2) IEN1 00H EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC B9H IP1 0X00- 0000B BAH SRELH XXXX- XX11B C0H 2) IRCON 00H EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC C1H CCEN 00 H COCA COCA COCA COCA COCA COCA COCA COCA C8H 2) T2CON 00H T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2) PSW 00H CY AC F0 RS1 RS0 OV F1 P D8H 2) ADCON0 00H BD CLK ADEX BSY ADM MX2 MX1 MX0 DAH ADDATL 00XX- XXXXB DCH ADCON1 0XXX- X000B ADCL – – – 0 MX2 MX1 MX0 E0H E8H 2) P4 FFH RXDC TXDC INT8 SLS STO SRI SCLK ADST F0H F8H F8H FAH P7 XXXX- XXX1B FCH VR07)8) C5H 1 1 0001 0 1 FDH VR17)8) 95H 1 0 0101 0 1 FEH VR27)8) 02H 9) 0 0 0000 1 0 1) “X” means that the value is undefined and the location is reserved. 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) This SFR is available in the C515C-8R and C515C-L. 5) This SFR is available in the C515C-8E. 6) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. 7) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 8) These SFRs are read-only registers (C515C-8E only). 9) The content of this SFR varies with the actual step of the C515C-8E (e.g. 01 H for the first step). Table 5 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Table 6 Contents of the CAN Registers in Numeric Order of their Addresses Addr. n = 1 to FH Regis- ter Content after Reset2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F700H CR 01 H TEST CCE 0 0 EIE SIE IE INIT F701H SR XX H BOFF EWRN – RXOK TXOK LEC2 LEC1 LEC0 F702H IR XX H INTID F704H BTR0 UU H SJW BRP F705H BTR1 0UUU. UUUUB 0T S E G 2 T S E G 1 F706H GMS0 UU H ID28-21 F707H GMS1 UUU1. 1111B I D 2 0 - 1 8 11111 F708H UGML0 UU H ID28-21 F709H UGML1 UU H ID20-13 F70AH LGML0 UU H ID12-5 F70BH LGML1 UUUU. U000B I D 4 - 0 000 F70CH UMLM0 UU H ID28-21 F70DH UMLM1 UU H ID20-18 ID17-13 F70EH LMLM0 UU H ID12-5 F70FH LMLM1 UUUU. U000B I D 4 - 0 000 F7n0H MCR0 UU H MSGVAL TXIE RXIE INTPND F7n1H MCR1 UU H RMTPND TXRQ MSGLST CPUUPD NEWDAT F7n2H UAR0 UU H ID28-21 F7n3H UAR1 UU H ID20-18 ID17-13 F7n4H LAR0 UU H ID12-5 F7n5H LAR1 UUUU. U000B I D 4 - 0 000 F7n6H MCFG UUUU. UU00B DLC DIR XTD 0 0

1) The notation “n” in the address definition defines the number of the related message object. 2) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation. Table 6 Contents of the CAN Registers in Numeric Order of their Addresses (cont’d) Addr. n = 1 to FH Regis- ter Content after Reset2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P7 are performed via their corresponding special function registers P0 to P7. The port structure of port 5 of the C515C is especially designed to operate either as a quasi-bidirectional port structure, compatible to the standard 8051-Family, or as a genuine bidirectional port structure. This port operating mode can be selected by software (setting or clearing the bit PMOD in the SFR SYSCON). The output drivers of port 0 and 2 and the in put buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. Analog Input Ports Ports 6 is available as input port only and provides two functions. When used as digital inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or SFR ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have no effect. If a digital value is to be read, the voltage levels are to be held within the input voltage specifications ( VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte instructions. Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked.

Port Structure Selection of Port 5 After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as an input or an output, additionally, after the selection of the bidirectional mode the direction register DIR5 of port 5 must be written. This direction register is mapped to the port 5 register. This means, the port register address is equal to its direction register address. Figure 10 illustrates the port and direction register configuration. Figure 10 Port Register, Direction Register MCS02649 D RQ QInt. Bus, Bit 7 Write to IP 1 Delay:

2.5 Machine Cycles

Instruction sequence for the programming of the direction registers: ORL IP1, #80H ; Set bit PDIR Write port x direction register with value YYH;#OYYHDIRx,MOV

Timer / Counter 0 and 1 can be used in four operating modes as listed in Table 7: In the “timer” function (C/ T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is fOSC/6. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the input clock logic. Figure 11 Timer/Counter 0 and 1 Input Clock Logic Table 7 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Timer/Counter Input Clock M1 M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 fOSC/6 × 32 fOSC/12 × 32 1 16-bit timer/counter 0 1 fOSC/6 fOSC/12 2 8-bit timer/counter with 8-bit autoreload

3 Timer/counter 0 used as

one 8-bit timer/counter and one 8-bit timer / Timer 1 stops MCS03117 OSC C/T = 0 C/T = 1 Control TR1 P3.5/T1 (TMOD) P3.2/INT0 f Timer 0/1 Input Clock OSC/6 P3.4/T0 TR0 Gate P3.3/INT1

Timer / Counter 2 with Compare/Capture/Reload The timer 2 of the C515C provides additional compare/capture/reload features, which allow the selection of the following operating modes:  Compare: up to 4 PWM signals with 16-bit/600 ns resolution  Capture: up to 4 high speed capture inputs with 600 ns resolution  Reload: modulation of timer 2 cycle time The block diagram in Figure 12 shows the general configuration of timer 2 with the additional compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as multifunctional port functions at port 1. Figure 12 Timer 2 Block Diagram MCB02730 Comparator CCL3/CCH3 Capture Input/ Output Control P1.0/ INT3/ CC0 CC1 INT4/ P1.1/CC2 INT5/ P1.2/ CC3 INT6/ P1.2/ CCL2/CCH2 Comparator CCL1/CCH1 Comparator CRCL/CRCH Comparator Bit16 16 Bit 16 Bit 16 Bit OSC ÷12 f OSC T2PS Sync.P1.7/ T2EX P1.5/ Sync. T2I1 T2I0 Timer 2 TH2TL2 TF2 Reload EXEN2 Reload 1EXF2 Interrupt Request Compare

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation. Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. If T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The external gate signal is sampled once every machine cycle. Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. Reload of Timer 2: Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been set.

The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. Figure 13 Port Latch in Compare Mode 0 MCS02661 Latch Port Q QCLK D Port Pin Read Pin DDV Read Latch Port Circuit Internal Bus Latch Write to Compare Reg. Compare Register Circuit Comparator Timer Register Timer Circuit Compare Match S R Overflow Timer

16 Bit

If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. In compare mode 1 (see Figure 14) the port circuit consists of two separate latches. One latch (which acts as a “shadow latch”) can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. Figure 14 Compare Function in Compare Mode 1 MCS02662 Latch Port Q QCLK D Read Pin DDV D CLK Q Shadow Latch Read Latch Port Circuit Internal Bus Latch Write to Compare Reg. Compare Register Circuit Comparator Timer Register Timer Circuit Compare Match Pin Port16 Bit

Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 8. For clarification some terms regarding the difference between “baud rate clock” and “baud rate” should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have to provide a “baud rate clock” (output signal in Figure 15 to the serial interface which - there divided by 16 - results in the actual “baud rate”. Further, the abbreviation fOSC refers to the oscillator frequency (crystal or external clock operation). The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1 or from a dedicated baud rate generator (see Figure 15). Table 8 USART Operating Modes Mode SCON Description SM0 SM1 00 0 Shift register mode, fixed baud rate Serial data enters and exits through R×D; T×D outputs the shift clock; 8-bit are transmitted/received (LSB first) 10 1 8-bit UART, variable baud rate 10 bits are transmitted (through T×D) or received (at R×D) 21 0 9-bit UART, fixed baud rate 11 bits are transmitted (through T×D) or received (at R×D) 31 1 9-bit UART, variable baud rate Like mode 2

Figure 15 Block Diagram of Baud Rate Generation for the Serial Interface Table 9 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD. Table 9 Serial Interface - Baud Rate Dependencies Serial Interface Operating Modes Active Control Bits Baud Rate Calculation BD SMOD Mode 0 (Shift Register) –– fOSC / 6 Mode 1 (8-bit UART) Mode 3 (9-bit UART)

0 X Controlled by timer 1 overflow:

(2SMOD × timer 1 overflow rate) / 32

1 X Controlled by baud rate generator

(2SMOD × fOSC) / (32 × baud rate generator overflow rate) Mode 2 (9-bit UART) – 0 fOSC / 32 fOSC / 16 MCS02733 Rate f OSC (SMOD) Baud Clock PCON.7 (SM0/ SM1) SCON.7 SCON.6 Only one mode can be selected ADCON0.7 (BD) Baud Rate Generator (SRELH SRELL) Timer 1 Mode 2 Mode 0 Note: The switch configuration shows the reset state. Mode 3 Mode 1 Overflow

The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 16 shows the block diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input and the output of this shift register are each connected via a control logic to the pin P4.2 / SRI (SSC Receiver In) and P4.3 / STO (SSC Transmitter Out). This shift register can be written to (SFR STB) and can be read through the Receive Buffer Register SRB. Figure 16 SSC Block Diagram The SSC has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is P4.1 / SCLK. When operating in slave mode, a slave select input is provided which enables the SSC interface and also will control the transmitter output. The pin used for this is P4.4 / SLS The SSC control block is responsible for controlling the different modes and operation of the SSC, checking the status, and generating the respective status and interrupt signals. MCB02735 P4.1/SCLK P4.2/SRI P4.3/STO P4.4/SLS Pin Control Logic Shift Register Receive Buffer Register STB Clock Selection Clock Divider SRB f OSC Control Register Status Register Int. Enable Reg. SCIEN SSCCON SCF Control Logic Internal Bus Interrupt

The on-chip CAN controller is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15). This includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc. In order to implement the physical layer, external components have to be connected to the C515C. The internal bus interface connects the on-chip CAN controller to the internal bus of the microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256 bytes wide address range of the external data memory area (F700 H to F7FFH) and can be accessed using MOVX instructions. Figure 17 shows a block diagram of the on-chip CAN controller.

Figure 17 CAN Controller Block Diagram The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory. The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the processes of reception, arbitration, transmission, and error signalling are performed according to the CAN protocol. Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP. MCB02736 Bit Timing Logic Timing Generator BTL-Configuration CRC Gen./Check TX/RX Shift Register TXDC RXDC Intelligent Interrupt Register Memory Processor Register Status Stream Bit Error Logic Management Messages Handlers Control Status + to internal Bus Clocks Control Messages (to all)

The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages. This is done by dividing the data stream by the code generator polynomial. The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit Stream Processor. According to the values of the error counters, the CAN controller is set into the states error active, error passive and busoff. The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant busline transition at Start of Frame (hard synchronization) and on any further recessive to dominant busline transition, if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time. The programming of the BTL depends on the baudrate and on external physical delay times. The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of control and status bits. After the initial configuration, the Intelligent Memory can handle the reception and transmission of data without further CPU actions. Switch-off Capability of the CAN Controller (C515C-8E only) For power consumption reasons, the on-chip CAN controller in the C515C-8E can be switched off by setting bit CSWO (bit 2) in SFR SYSCON. When the CAN controller is switched off its clock signal is turned off and the operation of the CAN controller is stopped. This switch-off state of the CAN controller is equal to its state in software power down mode. After clearing bit CSWO again the CAN controller has to be reconfigured.

The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features:  8 multiplexed input channels (port 6), which can also be used as digital inputs  10-bit resolution  Single or continuous conversion mode  Internal or external start-of-conversion trigger capability  Interrupt request generation after each conversion  Using successive approximation conversion technique via a capacitor array  Built-in hidden calibration of offset and linearity errors The main functional blocks of the A/D converter are shown in Figure 19. The A/D converter uses basically two clock signals for operation: the input clock fIN (= 1/tIN) and the conversion clock fADC (= 1/tADC). These clock signals are derived from the C515C system clock fOSC which is applied at the XTAL pins. The input clock fIN is equal to fOSC. The conversion clock is limited to a maximum frequency of 2 MHz and therefore must be adapted to fOSC by programming the conversion clock prescaler. The table in Figure 18 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates.

Figure 18 A/D Converter Clock Selection MCU System Clock Rate (fOSC) ADCL Conversion Clock fADC [MHz] 2 MHz 0 .5

4 MHz 0 1

6 MHz 0 1.5

8 MHz 0 2

10 MHz 1 1.25 MCS02748 MUX ADCL OSCf Clock Prescaler Conversion Clock f ADC Input Clock INf A/D Converter Conditions: f ADC max 2 MHz f IN = f OSC = 1 CLP

Figure 19 A/D Converter Block Diagram Input Clock Clock Conversion S & H Conversion Start of Shaded bit locations are not used in ADC-functions. Write to ADDATL P4.0/ADST AGND OSC AREF V V f Port 6 MUX Conversion Clock Prescaler IRCON (C0 ) ADCON0 (D8 ) ADCON1 (DC ) ADCL BD HP6 (DB ) P6.7 EXF2 ADEXCLK H BSY P6.5 IEX6 H P6.6 TF2 H P6.4 IEX5 SWDT IEN1 (B8 )H EXEN2 EX6 EX5 Single/ HH Converter Continuous A/D f IN ADCf Mode MSB LSB MCB02747 Bus Internal ADDATL (DA ) MX2 MX2ADM MX1 MX1 IEX3 P6.2P6.3 IEX4 P6.1 IEX2 ADDATH (D9 ) MX0 MX0 P6.0 IADC EX3EX4 EX2 EADC Bus Internal

The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC interface, CAN controller), and ten interrupts may be triggered interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at pin P3.2/INT0. In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt sources. Each interrupt group can be programmed to one of the four interrupt priority levels. Figure 20 to Figure 22 give a general overview of the interrupt sources and illustrate the interrupt request and control flags.

Figure 20 Interrupt Request Sources (Part 1) Polling Sequence HECANIEErrorCAN Controller Interrupt Sources Note: Each of the 15 CAN controller message objects provides the bits/flags in the shaded area. IEN0.7 cleared by hardware Request Flag is Receive INT2 P1.4/ T2CON.5 Bit addressable I2FR RXIE MCR0.5/4 Message Transmit Message TXIE MCR0.3/2 CR.3 EIE IEN1.1 IEX2 IRCON.1 EX2 EAL H004B IEN2.1 INTPND MCR0.0/1 1<_ CR.1 see Note MCS02752 IP1.1 IP0.1 0003INT0 Overflow Status Timer 0 CR.2 SIE A/D Converter TCON.0 IT0 IEN0.1 _<1 TCON.5 TF0 008B ET0 H000B IEN0.0 EADC IEN1.0 IADC IRCON.0 TCON.1 H0043 EX0 H P3.2/ IE0 Priority Level IP1.0 IP0.0 Lowest Highest Priority Level

Figure 21 Interrupt Request Sources (Part 2) MCS02753 Bit addressable Request Flag is cleared by hardware IP1.2 H0013TCON.3 IEN0.2 IE1 EX1 P3.3/ IT1 TCON.2 ESSC IEN2.2 0093 H SCF.1 WCOL TC SCF.0 SSC IP0.2 Highest Priority Level 0053 H IP1.3 IP0.3 Timer 1 H001BTCON.7 IEN0.3 TF1 ET1 Overflow INT1 INT4/ P1.1/ EX4 IEX4 IEN1.3 IRCON.3 005B HCC1 Lowest Priority Level EAL IEN0.7 Polling Sequence T2CON.6 I3FR EX3 IEX3 IEN1.2 IRCON.2CC0 P1.0/ INT3/ Inerface SCIEN.1 WCEN TCEN SCIEN.0

Figure 22 Interrupt Request Sources (Part 3) MCS02754 Bit addressable Request Flag is cleared by hardware IP1.4 H0023 ES IEN0.4 00A3 H SCON.0 RI TI SCON.1 USART IP0.4 Highest Priority Level EX5 IEX5 IEN1.4 IRCON.4 0063 H IP1.5 IP0.5 Timer 2 H00AB Overflow 006B H Lowest Priority Level EAL IEN0.7 Polling Sequence IEN2.4 EX7 CC2 P1.2/ INT5/ IRCON.7 EXF2 TF2 IRCON.6 IEN0.5 ET2 002B H EXEN2 IEN1.7 P1.5/ T2EX INT6/ P1.3/ CC3 EX8 IEN2.5 IRCON.5 IEN1.5 IEX6 EX6 INT7 P7.0/ P4.5/ INT8

Table 10 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003 H IE0 Timer 0 Overflow 000B H TF0 External Interrupt 1 0013 H IE1 Timer 1 Overflow 001B H TF1 Serial Channel 0023 H RI / TI Timer 2 Overflow / Ext. Reload 002B H TF2 / EXF2 A/D Converter 0043 H IADC External Interrupt 2 004B H IEX2 External Interrupt 3 0053 H IEX3 External Interrupt 4 005B H IEX4 External Interrupt 5 0063 H IEX5 External Interrupt 6 006B H IEX6 Wake-up from power-down mode 007BH – CAN controller 008B H – External Interrupt 7 00A3 H – External Interrupt 8 00AB H – SSC interface 0093 H TC / WCOL

The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic “fail-safe” reaction for cases where the controller’s hardware fails or the software hangs up:  A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds up to approx. 1.1 seconds at 6 MHz.  An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. Programmable Watchdog Timer The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate of fOSC/12 up to fOSC/192. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 23 shows the block diagram of the watchdog timer unit. Figure 23 Block Diagram of the Programmable Watchdog Timer The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD, but it cannot be stopped during active mode of the C515C. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of MCB02755 Control Logic PE/SWD External HW Power-Down WDT Reset Request 14 8 WDTH WDTREL (86 ) 07 6 IEN1 (B8 ) IEN0 (A8 ) H H WDTL IP0 (A9 )H WDT SWDT - - H External HW Reset -- -----WDTS WDTPSEL ÷16/6OSCf ÷2

two consecutive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. Oscillator Watchdog The oscillator watchdog unit serves for four functions:  Monitoring of the on-chip oscillator’s function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again.  Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function.  Restart from the hardware power down mode If the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function.  Control of external wake-up from software power-down mode When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.

Figure 24 Block Diagram of the Oscillator Watchdog OWDS IP0 (A9 ) Frequency Comparator Delay f 2 < 1f f 1 Internal Clock On-Chip Oscillator Oscillator RC RCf

3 MHz

H Start/ Stop Stop Start/ Control Logic XTAL1 XTAL2 P3.2/ INT0 Logic Control EWPD (PCON1.7) Mode Activated Power-Down Power-Down Mode Wake-Up Interrupt Reset Internal ÷5÷2

The C515C provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode.  Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset.  Power down mode The operation of the C515C is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. Software power down mode: Software power down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/INT0 (or P4.7/RXDC , C515C-8E only). Hardware power down mode: Hardware power down mode is entered when the pin HWPD is put to low level.  Slow-down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32 th of their normal operating frequency. Slowing down the frequency significantly reduces power consumption. The slow down mode can be combined with the idle mode. Table 11 gives a general overview of the entry and exit conditions of the power saving modes. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is disturbed and replaced by the reset state of the C515C. If WS (bit 4) is SFR PCON1 is set (C515C-8E only), pin P4.7/RXDC is alternatively selected as wake-up pin for the software power down mode. If WS (bit 4) is SFR PCON1 is cleared (C515C-8E only), pin P3.2/INT0 is selected as wake-up pin for the software power down mode. For the C515C-8R, P3.2/INT0 is always selected as wake-up pin.

Table 11 Power Saving Modes Overview Mode Entering (2-Instruction Example) Leaving by Remarks Idle mode ORL PCON, #01 H ORL PCON, #20H Occurrence of an interrupt from a peripheral unit CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Hardware Reset Software Power-Down Mode ORL PCON, #02 H ORL PCON, #40H Hardware Reset Oscillator is stopped; contents of on-chip RAM and SFR’s are maintained; Short low pulse at pin P3.2/INT0 (or P4.7/RXDC, C515C-8E only) Hardware Power-Down Mode HWPD = low HWPD = high C515C is put into its reset state and the oscillator is stopped; ports become floating outputs Slow Down Mode ORL PCON, #10 H ANL PCON, #0EFH or Hardware Reset Oscillator frequency is reduced to 1/32 of its nominal frequency

OTP Memory Operation (C515C-8E only) The C515C-8E contains a 64 Kbytes one-time programmable (OTP) program memory. With the C515C-8E fast programming cycles are achieved (1 byte in 100 µs). Also several levels of OTP memory protection can be selected. For programming of the device, the C515C-8E must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C515C-8E operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. Figure 25 shows the pins of the C515C-8E which are required for controlling of the OTP programming mode. Figure 25 Programming Mode Configuration of the C515C-8E MCP03651 VSSDDV A0-7 A8-A15 PALE PMSEL0 PMSEL1 XTAL1 XTAL2 P0-7 EA/ PROG PRD RESET PSEN PSEL PPV Port 2 Port 0 C515C-8E

C515C-8E Pin Configuration in Programming Mode Figure 26 P-MQFP-80-1 Pin Configuratio n of the C515C-8E in Programming Mode (top view) MCP03652 123456789 1 0 1 1 N.C. 12 13 14 15 16 17 18 19 20 4142434445464748495051525354555657585960 A2/A10 SSV SSV N.C. PALE PRD PSEL PMSEL1 PMSEL0 N.C. RESET VSS A3/A11 A4/A12 A5/A13 A6/A14 A7/A15 N.C. PSEN PROG EA/ 4061 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SSV DDV DDV N.C. VPP A1/A9 A0/A8 XTAL1 XTAL2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD DDV N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. C515C-8E N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS VDD N.C. N.C.

The following Table 12 contains the functional description of all C515C-8E pins which are required for OTP memory programming. Table 12 Pin Definitions and Functions in Programming Mode Symbol Pin Number I/O 1) Function RESET 1I Reset This input must be at static “0” (active) level during the whole programming mode. PMSEL0 PMSEL1 I I Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PSEL

17 I Basic programming mode select

This input is used for the basic programming mode selection and must be switched according Figure 27. PRD 18 I Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. PALE 19 I Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level whenever the logic level of PMSEL1,0 is changed. XTAL2 36 I XTAL2 Input to the oscillator amplifier. XTAL1 37 O XTAL1 Output of the inverting oscillator amplifier. PMSEL1 PMSEL0 Access Mode

00 R e s e r v e d

1 0 Program/read lock bits 1 1 Program/read OTP memory byte

P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A15. A8-A15 must be latched with PALE. PSEN 47 I Program store enable This input must be at static “0” level during the whole programming mode. PROG 48 I Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection a low level must be applied to PROG EA/VPP 49 I External Access / Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at high level ( VIH). This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA /VPP. D0 - 7 52 - 58 I/O Data lines 0-7 During programming mode, data bytes are read or written from or to the C515C-8E via the bidirectional D0-7 which are located at port 0. VSS 13, 34, 35, 51, 70 – Circuit ground potential must be applied to these pins in programming mode. VDD 14, 32, 33, 50, 69 – Power supply terminal must be applied to these pins in programming mode. N.C. 2-12, 20-31, 46, 60-67, 69, 71-80 – Not Connected These pins should not be connected in programming mode. 1) I = Input; O = Output Table 12 Pin Definitions and Functions in Programming Mode (cont’d) Symbol Pin Number I/O 1) Function

C515C-8E Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 27. Figure 27 C515C-8E Basic Programming Mode Selection MCT03653 "0" (XTAL1/XTAL2) Clock VDD RESET "0"PSEN 0.1PMSEL1, 0 "0"PROG "1"PRD PSEL "0"PALE EA/VPP PPV IHV are not actively driven During this period signals Ready for access mode selection 5 V 0 V Stable

C515C-8E Lock Bits Programming / Read The C515C-8E has two programmable lock bits which, when programmed according Table 14, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Table 13 Access Modes Selection Access Mode EA / VPP PROG PRD PMSEL Address (Port 2) Data (Port 0)10 Program OTP memory byte VPP H HHA 0 - 7 A8-15 D0-7 Read OTP memory byte VIH H Program OTP lock bits VPP HH L – D 1 , D 0 see Table 14 Read OTP lock bits VIH H Read OTP version byte VIH H L H Byte addr. of version byte D0-7

Table 14 Lock Bit Protection Types Lock Bits at D1, D0 Protection Level Protection Type D1 D0 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C515C-8E, the state of the EA pin is not latched on reset. 1 0 Level 1 During normal operation of the C515C-8E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to ROM verification mode 2, as it is defined for a protected ROM version of the C515C-8R. Further programming of the OTP memory is disabled (reprogramming security). 0 1 Level 2 Same as level 1, but also OTP memory read operation using ROM verification mode 2 is disabled. 0 0 Level 3 Same as level 2; but additionally external code execution by setting EA = low during normal operation of the C515C-8E is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible.

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions ( VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Parameter Symbol Limit Values Unit Notes min. max. Storage temperature TST -65 150 °C– Voltage on VDD pins with respect to ground (VSS) VDD -0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 VDD + 0.5 V – Input current on any pin during overload condition – -10 10 mA – Absolute sum of all input currents during overload condition Power dissipation PDISS –1W –

Parameter Symbol Limit Values Unit Notes min. max. Supply voltage VDD 4.25 5.5 V Active mode, fOSCmax = 10 MHz 2 5.5 V Power Down mode Ground voltage VSS 0 V Reference voltage Ambient temperature: °C– SAB-C515C TA 07 0 SAF-C505 TA -40 85 SAH-C505 TA -40 110 Analog reference voltage VAREF 4 VDD + 0.1 V – Analog ground voltage VAGND VSS - 0.1 VSS + 0.2 V – Analog input voltage VAIN VAGND VAREF V– XTAL clock fOSC 21 0 M H z –

DC Characteristics (Operating Conditions apply) Parameter Sym- bol Limit Values Unit Test Conditionmin. max. Input low voltages all except EA, RESET, HWPD EA pin RESET and HWPD pins Port 5 in CMOS mode VIL VIL1 VIL2 VILC -0.5 -0.5 -0.5 -0.5 0.2 VDD - 0.1 0.2 VDD - 0.3 0.2 VDD + 0.1

0.3 VDD

all except XTAL2, RESET, and HWPD) XTAL2 pin RESET and HWPD pins Port 5 in CMOS mode VIH VIH1 VIH2 VIHC 0.2 VDD + 0.9

0.7 VDD

0.6 VDD

VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 Output low voltages Ports 1, 2, 3, 4, 5, 7 (incl. CMOS) Port 0, ALE, PSEN , CPUR P4.1, P4.3 in push-pull mode VOL VOL1 VOL3 0.45 0.45 0.45 V IOL = 1.6 mA1) IOL = 3.2 mA1) IOL = 3.75 mA1) Output high voltages Ports 1, 2, 3, 4, 5, 7 Port 0 in external bus mode, ALE, PSEN, CPUR Port 5 in CMOS mode P4.1, P4.3 in push-pull mode VOH VOH2 VOHC VOH3 2.4 0.9 VDD 2.4

0.9 VDD

V IOH = -80 µA IOH = -10 µA IOH = -800 µA IOH = -80 µA2) IOH = -800 µA IOH = -833 µA Logic 0 input current Ports 1, 2, 3, 4, 5, 7 IIL -10 -70 µA VIN = 0.45 V Logical 0-to-1 transition current Ports 1, 2, 3, 4, 5, 7 ITL -65 -650 µA VIN = 2 V Input leakage current Port 0, EA, P6, HWPD, AIN0-7 ILI – ±1 µA0 . 4 5 < VIN < VDD Input low current To RESET for reset XTAL2 PE /SWD ILI2 ILI3 ILI4 -100 -15 -20 µA VIN = 0.45 V VIN = 0.45 V VIN = 0.45 V Pin capacitance CIO –1 0 p F fc = 1 MHz, TA = 25 °C Overload current IOV – ±5m A 3)4) Programming voltage VPP 10.9 12.1 V 11.5 V ± 5%

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing. 3) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits. 4) Not 100% tested, guaranteed by design characterization.

Limit Values Unit Test Condition typ.1) 1) The typical IDD values are periodically measured at TA = +25 °C and VDD = 5 V but not 100% tested. max.2) 2) The maximum IDD values are measured under worst case conditions ( TA = 0 °C or -40 °C and VDD = 5.5 V) Active mode C515C-8R/ C515C-LM

6 MHz

10 MHz

IDD 11.97 18.81 13.74 21.10 mA 3) IDD (active mode) is measured with: XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; EA = PE/SWD = Port 0 = Port 6 = VDD; HWPD = VDD; RESET = VSS; all other pins are disconnected. C515C-8E 6 MHz IDD 11.3 17.66 12.94 20.10 mA Idle mode C515C-8R/ C515C-LM IDD 6.9 10.46 7.87 11.87 mA 4) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; RESET = VDD; EA = VSS; Port0 = VDD; all other pins are disconnected; C515C-8E 6 MHz IDD 3.95 4.71 4.70 5.50 mA Active mode with slow-down enabled C515C-8R/ C515C-LM IDD 4.06 4.62 5.03 5.75 mA 5) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; RESET = VDD; all other pins are disconnected; the microcontroller is put into slow-down mode by software. C515C-8E 6 MHz IDD 4.01 4.65 4.77 5.53 mA Idle mode with slow-down enabled C515C-8R/ C515C-LM IDD 3.54 3.86 4.46 4.90 mA C515C-8E 6 MHz IDD 3.62 4.14 4.21 4.77 mA Power-down mode C515C-8R/ C515C-LM IPD 26 42.9 µA VDD = 2 … 5.5 V C515C-8E IPD 11.14 30 µA At EA/VPP in programming mode C515C-8E IDDP –3 0 m A –

6) IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH, tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL1 = N.C.; RESET = VDD; EA = VSS; Port0 = VDD; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software. 7) IPD (power-down mode) is measured under following conditions: EA = RESET = Port 0 = Port 6 = VDD; XTAL1 = N.C.; XTAL2 = VSS; PE /SWD = VSS; HWPD = VDD; VAGND = VSS; VAREF = VDD; all other pins are disconnected. IPD (hardware power-down mode) is independent of any particular pin connection.

Power Supply Current Calculation Formulas Note: fOSC is the oscillator frequency in MHz. IDD values are given in mA. Parameter Symbol Formula Active mode C515C-8R/ C515C-LM IDD typ IDD max 1.71 × fOSC + 1.71 1.84 × fOSC + 2.7 C515C-8E IDD typ IDD max 1.59 × fOSC + 1.76 1.79 × fOSC + 2.2 Idle mode C515C-8R/ C515C-LM IDD typ IDD max 0.89 × fOSC + 1.56 1.00 × fOSC + 1.87 C515C-8E IDD typ IDD max 0.19 × fOSC + 2.81 0.20 × fOSC + 3.5 Active mode with slow-down enabled C515C-8R/ C515C-LM IDD typ IDD max 0.14 × fOSC + 3.22 0.18 × fOSC + 3.95 C515C-8E IDD typ IDD max 0.16 × fOSC + 3.05 0.19 × fOSC + 3.63 Idle mode with slow-down enabled C515C-8R/ C515C-LM IDD typ IDD max 0.08 × fOSC + 3.06 0.11 × fOSC + 3.8 C515C-8E IDD typ IDD max 0.13 × fOSC + 2.84 0.14 × fOSC + 3.37

Figure 28 IDD Diagrams of C515C-8R/C515C-LM fOSC [MHz]642 10 [mA] Idle Mode Active Mode Active Mode Idle Mode Idle+Slow-down Slow-down Mode IDD max IDD typ C515C-8E C515C-LM

Figure 29 IDD Diagrams of C515C-8E C515C-8E fOSC [MHz]642 10 [mA] Idle Mode+Slow-down Active Mode Idle Mode Active Mode+Slow-down IDD max IDD typ

A/D Converter Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage VAIN VAGND VAREF V 1) 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. Sample time tS –1 6 × tIN 8 × tIN ns Prescaler ÷ 8 Prescaler ÷ 42) 2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Conversion cycle time tADCC –9 6 × tIN 48 × tIN ns Prescaler ÷ 8 Prescaler ÷ 43) 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. Total unadjusted error T UE – ±2L S B 4) 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. Internal resistance of reference voltage source RAREF – tADC / 250 - 0.25 kΩ tADC in [ns]5)6) 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Internal resistance of analog source RASRC – tS / 500 - 0.25 kΩ tS in [ns]2)6) ADC input capacitance CAIN –5 0 p F 6)

Further timing conditions: tADC min = 500 ns tIN = 1 / fOSC = tCLP Clock Prescaler Ratio ADCL tADC tS tADCC ÷81 8 × tIN 16 × tIN 96 × tIN ÷40 4 × tIN 8 × tIN 48 × tIN

AC Characteristics (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values Unit 10-MHz Clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP = 2 MHz to 10 MHz min. max. min. max. ALE pulse width tLHLL 60 – CLP - 40 – ns Address setup to ALE tAVLL 15 – TCL Hmin - 25 – ns Address hold after ALE tLLAX 15 – TCL Hmin - 25 – ns ALE to valid instruction in tLLIV – 113 – 2 CLP - 87 ns ALE to PSEN tLLPL 20 – TCL Lmin - 20 – ns PSEN pulse width tPLPH 115 – CLP + TCLHmin - 30 –n s PSEN to valid instruction in tPLIV –7 5 – C L P + TCLHmin - 65 ns Input instruction hold after PSEN tPXIX 0–0 – n s Input instruction float after PSEN tPXIZ 1) Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. –3 0 – T C L Lmin - 10 ns Address valid after PSEN tPXAV 1) 35 – TCL Lmin - 5 – ns Address to valid instruction in tAVIV – 180 – 2 CLP + TCLHmin - 60 ns Address float to PSEN tAZPL 00 – n s

External Data Memory Characteristics Parameter Symbol Limit Values Unit 10-MHz Clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP= 2 MHz to 10 MHz min. max. min. max. RD pulse width tRLRH 230 – 3 CLP - 70 – ns WR pulse width tWLWH 230 – 3 CLP - 70 – ns Address hold after ALE tLLAX2 48 – CLP - 15 – ns RD to valid data in tRLDV –1 5 0 – 2 C L P + TCLHmin - 90 ns Data hold after RD tRHDX 0–0 – n s Data float after RD tRHDZ – 80 – CLP - 20 ns ALE to valid data in tLLDV – 267 – 4 CLP - 133 ns Address to valid data in tAVDV –2 8 5 – 4 C L P + TCLHmin - 155 ns ALE to WR or RD tLLWL 90 190 CLP + TCLLmin - 50 CLP + TCLLmin + 50 ns Address valid to WR tAVWL 103 – 2 CLP - 97 – ns WR or RD high to ALE high tWHLH 15 65 TCL Hmin - 25 TCL Hmin + 25 ns Data valid to WR transition tQVWX 5–T C L Lmin - 35 – ns Data setup before WR tQVWH 218 – 3 CLP + TCLLmin - 122 –n s Data hold after WR tWHQX 13 – TCL Hmin - 27 – ns Address float after RD tRLAZ –0– 0 n s

Note: The 10 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. SSC Interface Characteristics Parameter Symbol Limit Values Unit min. max. Clock Cycle Time: Master Mode Slave Mode tSCLK tSCLK 0.4 1.0 µs µs Clock high time tSCH 360 – ns Clock low time tSCL 360 – ns Data output delay tD – 100 ns Data output hold tHO 0–n s Data input setup tS 100 – ns Data input hold tHI 100 – ns TC bit set delay tDTC –8 C L P n s External Clock Drive at XTAL2 Parameter Symbol CPU Clock = 10 MHz Duty cycle 0.4 to 0.6 Variable CPU Clock 1/CLP = 2 to 10 MHz Unit min. max. min. max. Oscillator period CLP 100 100 100 500 ns High time TCL H 40 – 40 CLP - TCL L ns Low time TCL L 40 – 40 CLP - TCL H ns Rise time tR –1 2 – 1 2 n s Fall time tF –1 2 – 1 2 n s Oscillator duty cycle DC 0.4 0.6 40 / CLP 1 - 40 / CLP – Clock cycle TCL 40 60 CLP × DCmin CLP × DCmax ns

Figure 30 Program Memory Read Cycle MCT00096 ALE PSEN Port 2 LHLLt A8 - A15 A8 - A15 A0 - A7 Instr.IN A0 - A7Port 0 tAVLL PLPHt t LLPL t LLIV t PLIV t AZPL t LLAX t PXIZ t PXIX t AVIV t PXAV

Figure 31 Data Memory Read Cycle MCT00097 ALE PSEN Port 2 WHLHt Port 0 RD t LLDV t RLRHt LLWL t RLDV t AVLL t LLAX2 t RLAZ t AVWL t AVDV tRHDX t RHDZ A0 - A7 from Ri or DPL from PCL A0 - A7 Instr. INData IN A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

Notes: 1. Shown is the data/clock relationship for CPOL = CPHA = 1. The timing diagram is valid for the other cases accordingly. 2. In the case of slave mode and CPHA = 0, the output delay for the MSB applies to the falling edge of SLS (if transmitter is enabled). 3. In the case of master mode and CPHA = 0, the MSB becomes valid after the data has been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition. MCT02417 SCLK STO SRI TC t SCL MSB LSB MSB LSB SCHt t SCLK St HIt Dtt HD DTCt

OTP Memory Programming Mode Characteristics VDD = 5 V ± 10%; VPP = 11.5 V ± 5%; TA = 25 °C ± 10 °C Parameter Symbol Limit Values Unit min. max. ALE pulse width tPAW 35 – ns PMSEL setup to ALE rising edge tPMS 10 – ns Address setup to ALE, PROG, or PRD falling edge tPAS 10 – ns Address hold after ALE, PROG, or PRD falling edge tPAH 10 – ns Address, data setup to PROG or PRD tPCS 100 – ns Address, data hold after PROG or PRD tPCH 0–n s PMSEL setup to PROG or PRD tPMS 10 – ns PMSEL hold after PROG or PRD tPMH 10 – ns PROG pulse width tPWW 100 – µs PRD pulse width tPRW 100 – ns Address to valid data out tPAD –7 5 n s PRD to valid data out tPRD –2 0 n s Data hold after PRD tPDH 0–n s Data float after PRD tPDF –2 0 n s PROG high between two consecutive PROG low pulses tPWH1 1– µs PRD high between two consecutive PRD low pulses tPWH2 100 – ns XTAL clock period tCLKP 21 0 M H z

Figure 35 Programming Code Byte - Write Cycle Timing t PAW t PMS PAHtPASt A8-15 A0-7 D0-7 PCSt PWWt PCHt t PWH MCT03690 H, H PALE PMSEL1,0 Port 2 Port 0 PROG PRD must be high during a programming write cycle.Notes:

Figure 36 Verify Code Byte - Read Cycle Timing t PAW t PMS PAHtPASt A8-15 A0-7 PADt D0-7 t PDH t PDFPRDt PCSt PRWt PCHt t PWH MCT03689 H, H PALE PMSEL1,0 Port 2 Port 0 PRD Notes: PROG must be high during a programming read cycle.

Figure 37 Lock Bit Access Timing H, L H, L D0, D1 D0, D1 t PCS PMSt PMHt t PCH PWWt PMSt PRDt t PDH PDFt PMHt PRWt MCT03393 PMSEL1,0 Port 0 PROG PRD PALE should be low during a lock bit read / write cycle.Note:

Figure 38 Version Byte - Read Timing e. g. FD D0-7 t PCS PMSt t PDH PDFt PMHt MCT03394 Port 2 Port 0 PRD PMSEL1,0 L, H H PRWt PRDt PCHt PROG must be high during a programming read cycle.Note:

ROM/OTP Verification Characteristics for C515C-8R / C515C-8E Figure 39 ROM Verification Mode 1 ROM Verification Mode 1 (C515C-8R) Parameter Symbol Limit Values Unit min. max. Address to valid data tAVQV –5 C L P n s MCT02764 Inputs: PSEN = SSV ALE, EA = VIH RESET = VIL2 Address Port 0 New Address Data Out New Data Out t AVQV Data: Addresses: P2.0 - P2.7 P1.0 - P1.7 P1.0 - P1.7 = A0 - A7 P2.0 - P2.7 = A8 - A15 P0.0 - P0.7 = D0 - D7

Figure 40 ROM/OTP Verification Mode 2 ROM/OTP Verification Mode 2 Parameter Symbol Limit Values Unit min. typ. max. ALE pulse width tAWD –C L P –n s ALE period tACY –6 C L P –n s Data valid after ALE tDVA ––2 C L P n s Data stable after ALE tDSA 4 C L P ––n s P3.5 setup to ALE low tAS – tCL –n s O s c i l l a t o r f r e q u e n c y 1 / C L P 4–6M H z MCT02613 t ACY t AWD t DSA DVAt t AS Data Valid ALE Port 0 P3.5

0.65 0.3 12.35 0.1 2 2.45 max Index Marking 17.2 0.25 min +0.1 0.88 0.6x45˚ 1) Does not include plastic or metal protrusions of 0.25 max per side A-B0.2 HD 4x A-B0.2 D 80x A B D C0.12 80xDA-BM C 1)14 17.2 -0.05 H 7˚max -0.02 +0.080.15 ±0.08 P-MQFP-80-1 (Plastic Metric Quad Flat Package) GPM05249 Y ou can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mmSMD = Surface Mounted Device

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