C513AO

C513AO INFINEON | Alldatasheet

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8-bit CMOS Microcontroller C513AO Data Sheet 02.00 DS 1 http://www. infine on.com/ c513ao_ds_0200.frm Page -1 Wednesday, August 30, 2000 12:45 PM

Edition 02.00 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. C513AO Data Sheet Revision History : Current Version: 02.00 Previous Releases: (Original Version) c513ao_ds_0200.frm Page 0 Wednesday, August 30, 2000 12:45 PM

Data Sheet 1 02.00 8-Bit CMOS Microcontroller Advance Information C513AO

Full upward compatibility with standard 8051 microcontroller
Up to 16 MHz external operating frequency – 750 ns instruction cycle at 16 MHz operation
On-chip program memory – C513AO-2R: 16 Kbytes ROM (with optional ROM protection) – C513AO-2E: 16 Kbytes OTP – C513AO-L: version without on-chip program memory (ROMless)
Up to 64K byte external data memory
2 5 6 × 8 RAM
2 5 6 × 8 XRAM
Four 8-bit digital I/O ports
Three 16-bit timers/counters (Timer 2 with Up/Down and 16-bit auto-reload features)
Full duplex serial interface (USART)
Synchronous Serial Channel (SSC)
Seven interrupt sources with two priority levels
On-chip emulation support logic (Enhanced Hooks Emulation Technology ™ ) (further features are on next page) Figure 1 C513AO Functional Units MCB04006 I/O I/O I/O I/O On-Chip Emulation Support Module Watchdog Timer SSC Interface Timer 2 Oscillator Watchdog XRAM 256 x 8 XRAM 256 x 8 ROM/OTP

16 K x 8 Port 3

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Data Sheet 2 02.00 Features (continued):

Programmable 15-bit Watchdog Timer
Oscillator Watchdog
Fast Power On Reset
Power Saving Modes – Slow-down mode – Idle mode – Software power-down mode with optional wake up capability through pin P3.2/INT0
Available in P-DIP40-2, P-LCC-44-1 and P-MQFP-44-2 packages
Fully pin-compatible with C501, C504, C505C, C505CA and C511/C513-devices.
Temperature ranges: SAB-C513AO TA: 0 to 70°C SAF-C513AO TA: – 40 to 85°C

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies:

the derivative itself, i.e. its function set
the specified temperature range
the package and the type of delivery For the available ordering codes for the C513AO please refer to the “Product Information Microcontrollers”, which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after the verification of the respective ROM code. c513ao_ds_0200.frm Page 2 Wednesday, August 30, 2000 12:45 PM

Data Sheet 3 02.00 Figure 2 Logic Symbol MCL04007 C513AO Port 0 8-Bit Digital I/O Port 1 8-Bit Digital I/O Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O XTAL1 XTAL2 RESET EA ALE PSEN V DD V SS c513ao_ds_0200.frm Page 3 Wednesday, August 30, 2000 12:45 PM

Data Sheet 4 02.00 Figure 3 C513AO V DD40 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 EA31 ALE30 PSEN29 P2.7/A15 P2.6/A14 26 P2.5/A13 P2.4/A1225 P2.3/A1124 P2.2/A1023 P2.1/A922 P2.0/A82120 V SS 19XTAL1 18XTAL2 17P3.7/RD 16P3.6/WR 15P3.5/T1 14P3.4/T0 13P3.3/INT1 11P3.1/TxD 10P3.0/RxD 9RESET 8P1.7 7P1.6 6P1.5/SLS 5P1.4/STO 4P1.3/SRI 3P1.2/SCLK 2P1.1/T2EX 1P1.0/T2 P3.2/INT0 MCP04008 c513ao_ds_0200.frm Page 4 Wednesday, August 30, 2000 12:45 PM

Data Sheet 5 02.00 Figure 4 C513AO P2.4/A12 27 26 25 24 23 22 21 20 19 18 P2.3/A11P2.2/A10 P2.1/A9 P2.0/A8V DD V SS XTAL1 XTAL2 P3.7/RDP3.6/WR P3.5/T117 P3.4/T016 P3.3/INT115 P3.2/INT014 P3.1/TxD13 N.C.12 P3.0/RxD11 RESET10 P1.79 P1.68 P1.5/SLS7 4 0 4 1 4 2 4 3 4 4 123456 P0.3/AD3P0.2/AD2 P0.1/AD1 P0.0/AD0 V DD V SS P1.0/T2 P1.1/T2EXP1.2/SCLK P1.3/SRIP1.4/STO P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA N.C. ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 29 MCP04009 c513ao_ds_0200.frm Page 5 Wednesday, August 30, 2000 12:45 PM

Data Sheet 6 02.00 Figure 5 C513AO 34 22 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 V DD V SS XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/T1P3.4/T0 P3.3/INT1P3.2/INT0P3.1/TxD N.C. P3.0/RxD RESET P1.7P1.6 P1.5/SLS P1.4/STO P1.3/SRI P1.2/SCLK P1.1/T2EX P1.0/T2 V SS V DD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 32 31 30 29 28 27 26 25 24 23 23456789 1 0 1 1 MCP04010 c513ao_ds_0200.frm Page 6 Wednesday, August 30, 2000 12:45 PM

Data Sheet 7 02.00 Table 1 Pin Definitions and Functions Symbol Pin Number I/O Function P- DIP -40 P-LCC- P-MQFP- P1.7- P1.0 8-1 9-2 3-1, 44-40 I/O Port 1 Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins that have “1s” written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up transistors. The output latch corresponding to a secondary function must be programmed to 1 for that function to operate. For the outputs of the Synchronous Serial Channel (SSC), SCLK and STO, special circuitry is implemented providing true push-pull capability. The STO output, in addition, will have true tristate capability. When used for SSC inputs, the pull-up transistors will be switched off and the inputs float (high ohm inputs). The secondary functions are assigned to the pins of Port 1 as follows: P1.0 / T2 Input to Counter 2 P1.1 / T2EX Capture/reload trigger of Timer 2 Up-Down count P1.2 / SCLK SSC Master Clock Output SSC Slave Clock Input P1.3 / SRI SSC Receive Input P1.4 / STO SSC Transmit Output P1.5 / SLS Slave Select Input *) I = Input O = Output c513ao_ds_0200.frm Page 7 Wednesday, August 30, 2000 12:45 PM

Data Sheet 8 02.00 P3.0- P.3.7 10-17 11, 13-19 7-13 I/O Port 3 Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have “1”s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up transistors. The output latch corresponding to a secondary function must be programmed to a “1” for that function to operate (except for TxD and WR The secondary functions are assigned to the pins of Port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External Interrupt 0 input / Timer 0 gate control input P3.3 / INT1 External Interrupt 1 input / Timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from Port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory to Port 0 RESET 9 10 4 I RESET A high level on this pin for the duration of two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD . *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O Function P- DIP -40 P-LCC- P-MQFP- c513ao_ds_0200.frm Page 8 Wednesday, August 30, 2000 12:45 PM

Data Sheet 9 02.00 XTAL2 18 20 14 O XTAL2 Output of the inverting oscillator amplifier. XTAL1 19 21 15 I XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. P2.0- P2.7 21-28 24-31 18-25 I/O Port 2 Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pull-up arrangement. Port 2 pins that have “1s” written to them are pulled high by the internal pull-up transistors, and in that state can be used as inputs. As inputs, Port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup transistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing “1”s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), Port 2 issues the contents of the P2 Special Function Register and uses only the internal pull-up transistors. PSEN 29 32 26 O Program Store Enable This is a control signal that enables output of the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. It remains high during internal program execution. This pin should not be driven during reset operation. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O Function P- DIP -40 P-LCC- P-MQFP- c513ao_ds_0200.frm Page 9 Wednesday, August 30, 2000 12:45 PM

Data Sheet 10 02.00 ALE 30 33 27 O Address Latch Enable This output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. When instructions are executed from internal program memory (EA = 1) the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. EA 31 35 29 I External Access Enable When held at high level, instructions are fetched from the internal program memory when the PC is less than 4000 H . When held at low level, the C513AO fetches all instructions from external program memory. This pin should not be driven during reset operation. Note: For the C513AO-L this pin must be tied low. P0.0- P0.7 32-39 43-36 37-30 I/O Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have “1s” written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-up transistors when issuing 1s. External pull-up resistors are required during program verification. VSS 20 22, 1 16, 39 – Ground (0 V) VDD 40 44, 23 38, 17 – Power Supply (+ 5 V) N.C. – 12, 34 6, 28 – No Connection. These pins should not be connected. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number I/O Function P- DIP -40 P-LCC- P-MQFP- c513ao_ds_0200.frm Page 10 Wednesday, August 30, 2000 12:45 PM

Data Sheet 11 02.00 Figure 6 Block Diagram of the C513AO MCB04011 Oscillator Watchdog OSC & Timing CPU Timer 0 Timer 1 Timer 2 Interrupt Unit USART SSC XRAM 256 byte RAM 256 byte ROM/OTP

16 K x 8

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Data Sheet 12 02.00 CPU The C513AO is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 16-MHz crystal, 58% of the instructions execute in 750 ns. Special Function Register PSW (Address D0 H ) Reset Value: 00 H Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag 0 RS1 RS0 Register bank Select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag 1 P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of “one” bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 PD0 H PSW D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH c513ao_ds_0200.frm Page 12 Wednesday, August 30, 2000 12:45 PM

Data Sheet 14 02.00 Reset and System Clock The reset input is an active high input. An internal Schmitt-trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running, the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. Figure 8 shows the possible reset circuitries. Figure 8 Reset Circuitries C513AO RESET V DD + C513AO RESET C513AO RESET& V DD a) b) c) MCS03291 c513ao_ds_0200.frm Page 14 Wednesday, August 30, 2000 12:45 PM

Data Sheet 17 02.00 Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology TM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. Figure 12 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. SYSCON PCON TCON RESET EA ALE PSEN Port 0 Port 2 Port 1Port 3 opt. I/O Ports C500 MCU RPCON RTCON Enhanced Hooks Interface Circuit RSYSCON RPORT RPORT TEA TALE TPSEN EH-IC ICE-System interface to emulation hardware Target System Interface MCS03254 c513ao_ds_0200.frm Page 17 Wednesday, August 30, 2000 12:45 PM

Data Sheet 18 02.00 Special Function Registers The registers reside in the special function register area, with the exception of the Program Counter and the four General Purpose Register banks. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. Four special function registers of the C513AO (PCON1, VR0, VR1 & VR2) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers of the C513AO are located in the standard special function register area. Special Function Register SYSCON (Address B1 H ) Reset Value: XX10XXX0 B If bit RMAP is set, mapped special function registers can be accessed. This bit is not cleared by hardware automatically. The forty Special Function Registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C513AO are listed in Table 2 and Table 3. In Table 2, they are organized in groups which refer to the functional blocks of the C513AO. Table 3 illustrates the contents of the SFRs in numeric order of their addresses. Bit Function RMAP Special function Register MAP bit RMAP = 0: The access to the non-mapped (standard) special function register area is enabled. RMAP = 1: The access to the mapped special function register area is enabled. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP –B1H SYSCON Bit No. MSB LSB ––– XMAP The functions of the shaded bits are not described in this section. c513ao_ds_0200.frm Page 18 Wednesday, August 30, 2000 12:45 PM

Data Sheet 19 02.00 Table 2 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL PSW SP SYSCON 2) VR0 4) 5) VR1 4) 5) VR2 4) 5) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 27) E0H F0H 83H 82H D0 H 81H B1H FC H FD H FE H 00H 00H 00H 00H 00H 07H XX10XXX0 B C5 H Interrupt System IE IP Interrupt Enable Register Interrupt Priority Register A8 H B8 H 00H X0000000 B Ports P0 Port 0 Port 1 Port 2 Port 3 80H 90H A0 H B0 H FFH FFH FFH FFH Serial Channel (USART) PCON SBUF SCON Power Control Register Serial Channel Buffer Register Serial Channel Control Register H 99H 98H 000X0000 B XX H 00H SSC Interface SSCCON STB SRB SCF SCIEN SSCMOD SSC Control Register SSC Transmit Register SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register H E9H EA H F8H F9H EB H 07H XX H XX H XXXXXX00 B XXXXXX00 B 00H Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) This SFR is read-only. 6) C513AO-L/2R: 13H C513AO-2E: 83H 7) This SFR varies with the step of the microcontroller: for example, 01H for the first step 8) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. c513ao_ds_0200.frm Page 19 Wednesday, August 30, 2000 12:45 PM

Data Sheet 20 02.00 Timer 2 T2CON T2MOD RC2H RC2L TH2 TL2 Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture Register, High Byte Timer 2 Reload/Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte H C9 H CB H CA H CD H CC H 00H XXXXXXX0 B 00H 00H 00H 00H Watchdog WDCON WDTREL Watchdog Timer Control Register Watchdog Timer Reload Register C0 H 86H XXXX0000 B 00H Power Save Mode PCON PCON1 4) Power Control Register Power Control Register 1 87H 88H 000X0000 B 0XXXXXXX B 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) This SFR is read-only. 6) C513AO-L/2R: 13 H C513AO-2E: 83H 7) This SFR varies with the step of the microcontroller: for example, 01H for the first step 8) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset c513ao_ds_0200.frm Page 20 Wednesday, August 30, 2000 12:45 PM

Data Sheet 21 02.00 Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 86H WDTREL 00 H WDT PSEL 87H PCON 0XX0- 0000B SMOD – – SD GF1 GF0 PDE IDLE 88H 2) 3) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 3) PCON1 0XX0- XXXX B 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 2) P1 FFH – – .SLS STO SRI SCLK T2EX T2 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI A0H A8H 2) IE 00H EA ESSC ET2 ES ET1 EX1 ET0 EX0 B0H 2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B1H SYSCON XX10- XXX0 B B8H 2) IP X000- 0000B – PSSC PT2 PS PT1 PX1 PT0 PX0 C0 H 2) WDCON XXXX- 0000B – – – – OWDS WDTS WDT SWDT 1) “X” means that the value is undefined and the location is reserved. 2) Bit-addressable special function registers. 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual step of the C513A0: for example, 01 H for the first step). 6) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. c513ao_ds_0200.frm Page 21 Wednesday, August 30, 2000 12:45 PM

Data Sheet 22 02.00 C8 H 2) T2CON 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/ RL2 C9 H T2MOD XXXX- XXX0 B D0 H 2) PSW 00H CY AC F0 RS1 RS0 OV F1 P E0H E8H 2) SSCCON 07H SCEN TEN MSTR CPOL CPHA BRS2 BRS1 BRS0 EB H SSCMOD 00 H 6) L O O P B T R I O 0 000 0L S B S M F0H F8H 2) SCF XXXX- XX00 B F9H SCIEN XXXX- XX00 B FC H FD H FE H 1) “X” means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These SFRs are read-only registers. 5) The content of this SFR varies with the actual step of the C513A0: for example, 01 H for the first step) 6) This register is only used for test purposes and must not be written during normal operation. Unpredictable results may occur upon a write operation. 7) C513AO-L/2R: 13H C513AO-2E: 83H Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 c513ao_ds_0200.frm Page 22 Wednesday, August 30, 2000 12:45 PM

Data Sheet 23 02.00 Parallel I/O Port The C513AO has four 8-bit I/O ports. Port 0 is an open-drain bidirectional I/O port, while Ports 1, 2, and 3 are quasi-bidirectional I/O ports with internal pull-up resistors. Thus, when configured as inputs, Ports 1 to 3 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of Port 0 and Port 2 and the input buffers of Port 0 are also used for accessing external memory. In this application, Port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue to emit the P2 SFR contents. In this case, Port 0 is not an open-drain port, but uses a strong internal pull-up Field Effect Transistors (FETs). Port 1 pins used for Synchronous Serial Channel (SSC) outputs are true push-pull outputs. When used as SSC inputs, they float (no pull-up). c513ao_ds_0200.frm Page 23 Wednesday, August 30, 2000 12:45 PM

Data Sheet 24 02.00 Timer/Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4: In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Since a machine cycle consists of twelve oscillator periods, the count rate is 1/12th of the oscillator frequency. In “counter” function, the register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0 or T1 (alternate functions of P3.4 and P3.5, respectively). Since it takes two machine cycles to detect a falling edge; therefore, the maximum count rate is 1/ 24th of the oscillator frequency. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 13 illustrates the input clock logic. Figure 13 Timer/Counter 0 and 1 Input Clock Logic Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock M1 M0 Internal External (max.) 0 8-bit timer/counter with a divide-by-32 prescaler 00 fOSC /(12× 32) fOSC /(24× 32) 1 16-bit timer/counter 1 1 fOSC /12 fOSC /24 2 8-bit timer/counter with 8-bit autoreload

3 Timer/counter 0 used as one

8-bit timer/counter and one 8-bit timer Timer 1 stops ÷12 12 fOSC /12 MCS01768 OSCf C/T TMOD Control Timer 0/1 Input Clock TCON TR 0/1 Gate TMOD P3.4/T0 P3.5/T1 max P3.2/INT0 P3.3/INT1 OSC /24f 1 c513ao_ds_0200.frm Page 24 Wednesday, August 30, 2000 12:45 PM

Data Sheet 25 02.00 Timer/Counter 2 with Compare/Capture/Reload Timer 2 is a 16-bit timer/counter with an up/down count feature. It has three operating modes:

16-bit auto-reload mode (up or down counting)
16-bit capture mode
Baudrate generator Note: ↓ denotes a falling edge Table 5 Timer / Counter 2 Operating Modes Mode T2CON T2MOD T2CON P1.1/ T2EX Remarks Input Clock RCLK or TCLK CP/ RL2 TR2 DCEN EXEN2 Internal External (P1.0/ T2) 16-bit Auto- reload X X X reload upon overflow reload trigger (falling edge) down counting up counting fOSC /12 max fOSC /24 16-bit Capture X X X 16-bit Timer/ Counter (only up-counting) capture TH2, TL2 → RC2H, RC2L fOSC /12 max fOSC /24 Baudrate Generator X X X X X no overflow interrupt request (TF2) extra external interrupt (“Timer 2”) fOSC /12 max fOSC /24 off X X 0 X X X Timer 2 stops – – c513ao_ds_0200.frm Page 25 Wednesday, August 30, 2000 12:45 PM

Data Sheet 26 02.00 Serial Interface (USART) The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive register. The serial port can operate in 4 modes (one synchronous and three asynchronous) as illustrated in Table 6. For clarification, some terms regarding the difference between “baudrate clock” and “baudrate” should be mentioned. The serial interface requires a clock rate which is 16 times the baudrate for internal synchronization. Therefore, the baudrate generators must provide a “baudrate clock” to the serial interface which divides it by 16, thereby resulting in the actual “baudrate”. The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These baudrates can be determined by Timer 1 or by Timer 2 or both (one for transmit, the other for receive). Table 6 USART Operating Modes Mode SCON Description SM0 SM1 0 0 0 Shift register mode Serial data enters and exits through R×D. T×D outputs the shift clock. 8-bit data are transmitted/received (LSB first) at a fixed baudrate of 1/12th of the oscillator frequency. 1 0 1 8-bit USART, variable baudrate 10 bits are transmitted (through T×D) or received (at R×D). 2 1 0 9-bit USART, fixed baudrate 11 bits are transmitted (through T×D) or received (at R×D). 3 1 1 9-bit USART, variable baudrate Similar to mode 2, except for the variable baudrate. c513ao_ds_0200.frm Page 26 Wednesday, August 30, 2000 12:45 PM

Data Sheet 27 02.00 Figure 14 Block Diagram of Baudrate Generation for the Serial Interface Table 7 lists the values/formulas for the baudrate calculation of the serial interface with its dependencies on the control bits SMOD (in SFR PCON), TCLK and RCLK (both in SFR T2CON). Table 7 Serial Interface - Baudrate Dependencies Serial Interface Operating Modes Control Bits Baudrate Calculation SMOD TCLK/RCLK Mode 0 (Shift Register)–– fOSC /12 Mode 1 (8-bit UART) Mode 3 (9-bit UART) X 0 Determined by timer 1 overflow rate: (2SMOD × timer 1 overflow rate)/32 – 1 Determined by timer 2 overflow rate: Timer 2 overflow rate/16 Mode 2 (9-bit UART) 0 fOSC /64 fOSC /32 MCS04017 SCON.7/ SCON.6 (SM0/ SM1) Mode 1 Mode 3 Mode 2 Mode 0÷ 6 fOSC /2 Timer 1 Overflow Only one mode can be selected PCON.7 (SMOD) ÷ 2 Baudrate Clock Note: The switch configuration shows the reset state c513ao_ds_0200.frm Page 27 Wednesday, August 30, 2000 12:45 PM

Data Sheet 29 02.00 Figure 16 Interrupt Request Sources c513ao_ds_0200.frm Page 29 Wednesday, August 30, 2000 12:45 PM

Data Sheet 30 02.00 If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. Table 8 Interrupt Vector Addresses Interrupt Source Request Flags Vector Address External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt USART serial port interrupt Timer 2 interrupt Synchronous Serial Channel interrupt (SSC) Wake-up from power-down mode IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 WCOL+TC 0003 H 000BH 0013H 001BH 0023H 002BH 0043H 007BH Table 9 Interrupt Source Structure Interrupt Source Priority External Interrupt 0 Synchronous Serial Channel Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Universal Serial Channel Timer 2 Interrupt IE0 WCOL OR TC TFO IE1 TF1 RI OR TI TF2 OR EXF2 High Low c513ao_ds_0200.frm Page 30 Wednesday, August 30, 2000 12:45 PM

Data Sheet 31 02.00 Fail Save Mechanisms The C513AO offers enhanced fail-safe mechanisms which allow automatic recovery from a software upset or a hardware failure:

A programmable Watchdog Timer (WDT) has variable time-out period from 512 µs up to approx. 1.1 sec. at 12 MHz
An Oscillator Watchdog (OWD) monitors the on-chip oscillator and forces the microcontroller into reset state if the on-chip oscillator fails. It also provides the clock for a fast internal reset after power-on. The Watchdog Timer in the C513AO is a 15-bit timer which is incremented by a count rate of either fCYCLE /2 or fCYCLE /32 (fCYCLE = fOSC /12). That is, the machine clock is divided by a fixed divide-by-two prescaler and an optional divide-by-16 prescaler arranged in series. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 17 shows the block diagram of the watchdog timer unit. Figure 17 Block Diagram of the Watchdog Timer The Watchdog Timer can be started by software (bit SWDT in SFR WDCON); but, it cannot be stopped during active mode of the device. If the software fails to clear the Watchdog Timer, an internal reset will be initiated. The reset cause can be examined by software (status flag WDTS in WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. During a refresh, the content of the SFR WDTREL is transferred to SFR WDTH, i.e. the upper 7-bit of the watchdog timer. It must be noted, however, that the watchdog timer is stopped during the idle mode and power down mode of the processor. c513ao_ds_0200.frm Page 31 Wednesday, August 30, 2000 12:45 PM

Data Sheet 32 02.00 Oscillator Watchdog The Oscillator Watchdog (OWD) unit is used for three functions:

Monitoring the on-chip oscillator’s function The watchdog supervises the on-chip oscillator’s frequency. If the frequency is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset. If the failure condition disappears (that is, if the on-chip oscillator has a higher frequency than the RC oscillator), the device executes a final reset phase of typically 1 ms to allow the oscillator to stabilize. Then, the oscillator watchdog reset is released and the device resumes program execution.
Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for reset before the on-chip oscillator has started. The oscillator watchdog unit reset works identically to the monitoring function.
Control of external wake-up from software power-down mode When power-down mode is terminated by a low level at the INT0 pin, the oscillator watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In power-down mode, the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is terminated. When the on-chip oscillator has a frequency higher than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms to allow the on-chip oscillator to stabilize. Note: The Oscillator Watchdog unit is always enabled. Figure 18 shows the block diagram of the Oscillator Watchdog unit. c513ao_ds_0200.frm Page 32 Wednesday, August 30, 2000 12:45 PM

Data Sheet 33 02.00 Figure 18 Block Diagram of the Oscillator Watchdog c513ao_ds_0200.frm Page 33 Wednesday, August 30, 2000 12:45 PM

Data Sheet 34 02.00 Power Saving Modes The C513AO provides three basic power-saving modes: Idle Mode, Slow-down Mode, and Power- down Mode.

Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to function. Idle mode is entered by software and can be left by an interrupt or reset.
Slow down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32nd of their normal operating frequency and also reduces power consumption.
Power down mode The operation of the C513AO is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. This power down mode is entered by software and can be left by reset or a short low pulse at pin P3.2/INT0 In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. Table 10 gives a general overview of the entry and exit procedures of the power saving modes. Table 10 Power Saving Modes Overview Mode Entering Example Leaving by Remarks Idle mode ORL PCON, #01 H Occurrence of an any enabled interrupt CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Hardware reset Slow Down Mode In normal mode: ORL PCON,#10 H ANL PCON,#0EF H or Hardware reset Internal clock rate is reduced to 1/32 of its nominal frequency With idle mode: ORL PCON,#11 H Occurrence of any enabled interrupt and the instruction ANL PCON,#0EF H CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with 1/32 of its nominal frequencyHardware reset Power Down Mode ORL PCON, #02 H Hardware reset Oscillator is stopped; contents of on-chip RAM and SFRs are maintained; Short low pulse at pin P3.2/INT0 c513ao_ds_0200.frm Page 34 Wednesday, August 30, 2000 12:45 PM

Data Sheet 35 02.00 Absolute Maximum Ratings Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS ) the voltage on VDD pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings. Operating Conditions Parameter Symbol Limit Values Unit Notes min. max. Storage temperature TST – 65 150 ° C – Voltage on VDD pins with respect to ground (VSS ) VDD – 0.5 6.5 V – Voltage on any pin with respect to ground (VSS ) VIN – 0.5 VDD + 0.5 V – Input current on any pin during overload condition – – 10 10 mA – Absolute sum of all input currents during overload condition Power dissipation PDISS –t . b . d . W – Parameter Symbol Limit Values Unit Notes min. max. Supply voltage VDD 4.25 5.5 V – Ground voltage VSS 0V – Ambient temperature SAB-C513AO SAF-C513AO TA TA –4 0 ° C – CPU clock fCPU 3.5 16 MHz – c513ao_ds_0200.frm Page 35 Wednesday, August 30, 2000 12:45 PM

Data Sheet 36 02.00 Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C513AO and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (C ontroller C haracteristics): The logic of the C513AO will provide signals with the respective characteristics. SR (System R equirement): The external system must provide signals with the respective characteristics to the C513AO. DC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage Pins except EA , RESET EA pin RESET pin VIL SR VIL1 SR VIL2 SR – 0.5 – 0.5 – 0.5 0.2 VDD – 0.1 0.2 VDD – 0.3 0.2 VDD + 0.1 V V V Input high voltage Pins except XTAL1, RESET XTAL1 pin RESET pin VIH SR VIH1 SR VIH2 SR

0.6 VDD

0.7 VDD

VDD + 0.5 VDD + 0.5 VDD + 0.5 V V V Output low voltage Ports 1, 2, 3 (except P1.2, P1.4) Port 0, ALE, PSEN P1.2, P1.4 pull-up transistor resistance VOL CC VOL1 CC RDSON CC 0.45 0.45 120 V V Ω I OL = 1.6 mA1) I OL = 3.2 mA1) VOL = 0.45 V Output High Voltage Ports 1, 2, 3 Port 0 in external bus mode, ALE, PSEN P1.2, P1.4 pull-up transistor resistance VOH CC VOH1 CC RDSON CC 2.4 0.9 VDD 2.4 0.9VDD 120 V V V V Ω IOH = – 80 µA, IOH = – 10 µA IOH = – 800 µA, IOH = – 80 µA2) VOH = 0.9 VDD Logic 0 input current Ports 1, 2, 3 IIL SR – 10 – 70 µA VIN = 0.45 V Logical 0-to-1 transition current, Ports 1, 2, 3 ITL SR – 65 – 650 µA V I N = 2 V Input Leakage Current Port 0, EA P1.2, P1.3, P1.5 as SSC inputs ILI CC – ± 1 µA0 . 4 5 <VIN < VDD Input high current to RESET for reset IIH CC 5 100 µA0 . 6 < VIN < VDD c513ao_ds_0200.frm Page 36 Wednesday, August 30, 2000 12:45 PM

Data Sheet 37 02.00 Notes see next page. Power Supply Current Input low current to XTAL1 IIL2 CC –– 2 0 µA V IN = 0.45 V Pin capacitance C IO CC –1 0 p F fC = 1 MHz, T A = 25 °C Overload current IOV SR – ± 5m A 8) 9) Parameter Symbol Limit Values Unit Test Condition typ.10) max. Active mode C513AO-2E 12 MHz

16 MHz

10.3 13.1 13.0 16.6 mA mA C513AO-2R 12 MHz 6.9 8.5 9.0 10.9 mA mA Idle mode C513AO-2E 12 MHz 5.7 6.8 7.2 8.7 mA mA C513AO-2R 12 MHz 4.1 4.8 5.5 6.0 mA mA Active mode with slow-down enabled C513AO-2E 12 MHz 4.5 5.1 5.7 6.5 mA mA C513AO-2R 12 MHz 3.3 3.6 4.1 4.5 mA mA Idle mode with slow-down enabled C513AO-2E 12 MHz 3.7 4.0 4.7 5.1 mA mA C513AO-2R 12 MHz 2.6 2.8 3.3 3.5 mA mA Power-down mode C513AO-2E IPD 8.8 50 µA VDD =2 … 5.5 V 3) C513AO-2R IPD 1.28 20 µA VDD =2 … 5.5 V 3) DC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. c513ao_ds_0200.frm Page 37 Wednesday, August 30, 2000 12:45 PM

Data Sheet 38 02.00 Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA =P o r t 0=VDD ; RESET = VSS ; XTAL2 = N.C.; XTAL1 =VSS ; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA). 4) IDD (active mode) is measured with: XTAL2 driven with tCLCH , tCHCL =5n s , VIL= VSS +0 . 5V , VIH = VDD – 0.5 V; XTAL1 = N.C.; EA = PE/SWD = Port 0 = Port 6 =V DD ; HWPD = VDD ; RESET = VDD ; all other pins are disconnected. IDD would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH , tCHCL =5n s , VIL= VSS +0 . 5V , VIH = VDD – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 =VDD ; all other pins are disconnected. 6) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH , tCHCL =5n s , VIL = VSS +0 . 5V , VIH = V DD – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ;P o r t 0=VDD ; all other pins are disconnected. 7) IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH , tCHCL =5n s , VIL= VSS +0 . 5V , VIH = V DD – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ;P o r t 0=VDD ; all other pins are disconnected. 8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 9) Not 100% tested, guaranteed by design characterization. 10)The typical IDD values are periodically measured at TA = + 25 °C and VDD = 5 V but not 100% tested. c513ao_ds_0200.frm Page 38 Wednesday, August 30, 2000 12:45 PM

Data Sheet 39 02.00 Figure 19 IDD Diagram MCD04314 fOSC DDΙ MHz mA DD typΙ ΙDD max Active Mode Active Mode Idle Mode Idle Mode 2.5 7.5 12.5 17.5 468 10 12 14 16 Active + Slow Down Mode Idle + Slow Down Mode C513AO-2E MCD04315 fOSC DDΙ MHz mA DD typΙ ΙDD max Active Mode Active Mode Idle Mode Idle Mode 468 10 12 14 16 Active + Slow Down Mode Idle + Slow Down Mode C513AO-2R c513ao_ds_0200.frm Page 39 Wednesday, August 30, 2000 12:45 PM

Data Sheet 40 02.00 Power Supply Current Calculation Formula Note: fosc is the oscillator frequency in MHz. IDD values are given in mA. Parameter Symbol Formula Active mode C513-2E IDD typ IDD max 0.70 × fOSC + 1.8 0.91 × fOSC + 2.0 C513-2R IDD typ IDD max 0.40 × fOSC + 2.1 0.48 × fOSC + 3.2 Idle mode C513-2E IDD typ IDD max 0.29 × fOSC + 2.2 0.36 × fOSC + 2.9 C513-2R IDD typ IDD max 0.18 × fOSC + 1.9 0.13 × fOSC + 3.9 Active mode with slow-down enabled C513-2E IDD typ IDD max 0.15 × fOSC + 2.6 0.20 × fOSC + 2.9 C513-2R IDD typ IDD max 0.08 × fOSC + 2.4 0.10 × fOSC + 2.9 Idle mode with slow-down enabled C513-2E IDD typ IDD max 0.09 × fOSC + 2.5 0.12 × fOSC + 3.2 C513-2R IDD typ IDD max 0.05 × fOSC + 2.0 0.05 × fOSC + 2.7 c513ao_ds_0200.frm Page 40 Wednesday, August 30, 2000 12:45 PM

Data Sheet 41 02.00 AC Characteristics (16 MHz) (Operating Conditions apply) (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) *) Interfacing the C513AO to devices with float times up to 55 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 16 MHz min. max. min. max. Program Memory Characteristics ALE pulse width tLHLL CC 85 –2 tCLCL – 40 – ns Address setup to ALE tAVLL CC 33 – tCLCL – 30 – ns Address hold after ALE tLLAX CC 28 – tCLCL – 35 – ns ALE low to valid instruction intLLIV SR – 150 – 4 tCLCL – 100 ns ALE to PSEN tLLPL CC 38 – tCLCL – 25 – ns PSEN pulse width tPLPH CC 153 – 3 tCLCL – 35 – ns PSEN to valid instruction intPLIV SR –8 8 – 3 tCLCL – 100 ns Input instruction hold after PSENtPXIX SR 0 – 0–n s Input instruction float after PSEN tPXIZ SR –4 3 – tCLCL – 20 ns Address valid after PSEN tPXAV CC 48 – tCLCL – 8 – ns Address to valid instr in tAVIV SR – 198 – 5 tCLCL – 115 ns Address float to PSEN tAZPL CC 0 – 0–n s c513ao_ds_0200.frm Page 41 Wednesday, August 30, 2000 12:45 PM

Data Sheet 42 02.00 AC Characteristics (16 MHz, cont’d) (Operating Conditions apply) (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Parameter Symbol Limit Values Unit 1/tCLCL = 3.5 MHz to 16 MHz min. max. min. max. External Data Memory Characteristics RD pulse width tRLRH CC 275 –6 tCLCL – 100 – ns WR pulse width tWLWH CC 275 – 6 tCLCL – 100 – ns Address hold after ALE tLLAX2 CC 90 – 2 tCLCL – 35 – ns RD to valid data in tRLDV SR – 148 – 5 tCLCL – 165 ns Data hold after RD tRHDX SR 0–0 – n s Data float after RD tRHDZ SR –5 5 – 2 tCLCL – 70 ns ALE to valid data in tLLDV SR – 350 – 8 tCLCL – 150 ns Address to valid data in tAVDV SR – 398 – 9 tCLCL – 165 ns ALE to WR or RD tLLWL CC 138 238 3 tCLCL – 50 3 tCLCL + 50 ns Address valid to WR or RD tAVWL CC 120 – 4 tCLCL – 130 – ns WR or RD high to ALE high tWHLH CC 23 103 tCLCL – 40 tCLCL + 40 ns Data valid to WR transition tQVWX CC 13 – tCLCL – 50 – ns Data setup before WR tQVWH CC 288 – 7 tCLCL – 150 – ns Data hold after WR tWHQX CC 13 – tCLCL – 50 – ns Address float after RD tRLAZ CC –0– 0 n s c513ao_ds_0200.frm Page 42 Wednesday, August 30, 2000 12:45 PM

Data Sheet 43 02.00 Synchronous Serial Channel (SSC) Interface Characteristics External Clock Drive Characteristics Parameter Symbol Limit Values Unit

16 MHz Clock

min. max. Clock Cycle Time: Master Mode Slave Mode tSCLK CC tSCLK SR 500 450 ns ns Clock High Time tSCH CC/SR 1) This parameter is ‘CC’ in Master Mode, and ‘SR’ in Slave Mode. 200 –n s Clock Low Time tSCL CC/SR 1) 200 – ns Data Output Delay tDC C – 100 ns Data Output Hold tHO CC 0–n s Data Input Setup tSS R 80 – ns Data Input Hold tHI SR 80 – ns TC Bit Set Delay tDTC CC – 16 tCLCL ns Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 16 MHz min. max. Oscillator period tCLCL SR 62.5 285 ns High time tCHCX SR 15 tCLCL – tCLCX ns Low time tCLCX SR 15 tCLCL – tCHCX ns Rise time tCLCH SR –1 5 n s Fall time tCHCL SR –1 5 n s c513ao_ds_0200.frm Page 43 Wednesday, August 30, 2000 12:45 PM

Data Sheet 44 02.00 Figure 20 Program Memory Read Cycle MCT00096 ALE PSEN Port 2 LHLLt A8 - A15 A8 - A15 A0 - A7 Instr.IN A0 - A7Port 0 tAVLL PLPH t tLLPL tLLIV tPLIV tAZPL tLLAX tPXIZ tPXIX tAVIV tPXAV c513ao_ds_0200.frm Page 44 Wednesday, August 30, 2000 12:45 PM

Data Sheet 45 02.00 Figure 21 Data Memory Read Cycle MCT00097 ALE PSEN Port 2 WHLHt Port 0 RD tLLDV tRLRHtLLWL tRLDV tAVLL tLLAX2 tRLAZ tAVWL tAVDV tRHDX tRHDZ A0 - A7 from Ri or DPL from PCL A0 - A7 Instr. INData IN A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH c513ao_ds_0200.frm Page 45 Wednesday, August 30, 2000 12:45 PM

Data Sheet 46 02.00 Figure 22 Data Memory Write Cycle MCT00098 ALE PSEN Port 2 WHLHt Port 0 WR tWLWHtLLWL tQVWX tAVLL tLLAX2 tQVWH tAVWL tWHQX A0 - A7 from Ri or DPL from PCL A0 - A7 Instr.INData OUT A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH c513ao_ds_0200.frm Page 46 Wednesday, August 30, 2000 12:45 PM

Data Sheet 48 02.00 OTP Memory Characteristics (C513AO-2E only) Programming Mode Timing Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit min. max. PALE Pulse Width tPAW 35 –n s PMSEL Set-up to PALE Rising Edge tPMS 10 – – Address Set-up to PALE, PROG, or PRD Falling Edge tPAS 10 – ns Address Hold after PALE, PROG, or PRD Falling Edge tPAH 10 – ns Address, Data Set-up to PROG or PRD tPCS 100 – ns Address, Data Hold after PROG or PRD tPCH 0–n s PMSEL Set-up to PROG or PRD tPMS 10 – ns PMSEL Hold after PROG or PRD tPMH 10 – ns PROG Pulse Width tPWW 100 – µs PRD Pulse Width tPRW 100 – ns Address to Valid Data out tPAD –7 5 n s PRD to Valid Data out tPRD –2 0 n s Data Hold after PRD tPDH 0–n s Data float after PRD tPDF –2 0 n s PROG High between two Consecutive PROG Low Pulses tPWH1 1– µs PRD High between two Consecutive PRD Low Pulses tPWH2 100 – ns XTAL Clock Period tCLKP 62.5 286 ns c513ao_ds_0200.frm Page 48 Wednesday, August 30, 2000 12:45 PM

Data Sheet 49 02.00 Figure 25 Programming Code Byte - Write Cycle Timing A8-13 MCT04318 PALE PMSEL1, 0 Port 2 Port 0 PROG tPMS tPAW tPAS tPAH H, H A0-7 D0-7 tPWHtPWWtPCS Notes: PRD must be high during a programming write cycle tPCH c513ao_ds_0200.frm Page 49 Wednesday, August 30, 2000 12:45 PM

Data Sheet 50 02.00 Figure 26 Verify Code Byte - Read Cycle Timing A8-13 MCT04319 PALE PMSEL1, 0 Port 2 Port 0 PRD tPMS tPAW tPAS tPAH H, H A0-7 tPAD D0-7 tPDH tPRD tPWHtPRW tPCH tPCS Notes: PROG must be high during a programming read cycle tPDF c513ao_ds_0200.frm Page 50 Wednesday, August 30, 2000 12:45 PM

Data Sheet 52 02.00 OTP Verification Mode Characteristics Note: ALE pin described below is not the OTP Programming Mode pin PALE Figure 29 OTP Verification Mode Parameter Symbol Limit Values Unit min. typ max. ALE Pulse Width tAWD –2 tCLCL –n s ALE Period tACY – 12 tCLCL –n s Data Valid after ALE tDVA ––4 tCLCL ns Data Stable after ALE tDSA 8 tCLCL ––n s P3.5 Set-up to ALE Low tAS – tCLCL –n s Oscillator Frequency 1/ tCLCL 4–6M H z MCT04322 ALE Port 0 P3.5 tACY tAWD tDSA tDVA tAS Data Valid c513ao_ds_0200.frm Page 52 Wednesday, August 30, 2000 12:45 PM

Data Sheet 54 02.00 Figure 32 Recommended Oscillator Circuits for Crystal Oscillator MCS04317 3.5-16 MHz C C Crystal Mode: C = 20 pF ± 10 pF (incl. stray capacitance) Crystal Oscillator Mode External Oscillator Signal Driving from External Source XTAL2 XTAL1 N.C. XTAL2 XTAL1 c513ao_ds_0200.frm Page 54 Wednesday, August 30, 2000 12:45 PM

Data Sheet 55 02.00 Package Outlines GPD05055 3.7±0.3 0.5 min 5.1 max 40 21 12 0 50.9-0.5 0.25 max 0.25+0.1 14 -0.3 15.24+1.2 15.24±0.2 Index Marking 0.25 40x Plastic Package, P-DIP-40-2 (Plastic Dual In-Line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device c513ao_ds_0200.frm Page 55 Wednesday, August 30, 2000 12:45 PM

Data Sheet 56 02.00 GPL05102 Plastic Package, P-LCC-44-1 (Plastic Lead Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device c513ao_ds_0200.frm Page 56 Wednesday, August 30, 2000 12:45 PM

Data Sheet 57 02.00 GPM 05622 Plastic Package, P-MQFP-44-2 (Plastic Metric Quad Flat Pack) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device c513ao_ds_0200.frm Page 57 Wednesday, August 30, 2000 12:45 PM

Summary

8-bit CMOS Microcontroller 02.00

Description