C508

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Never stop thinking. Microcontrollers User’s Manual, May 2001 C508 8-Bit CMOS Microcontroller

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

User’s Manual, May 2001 Never stop thinking. C508 8-Bit CMOS Microcontroller

Enhanced Hooks Technology TM is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. C508 User’s Manual Revision History: 2001-05 Previous Version: 1999-10 Page Subjects (major changes since last revision) 3-14, 3-15, 8-2 Reset value of SFR WDTH is corrected. 6-84 Block diagram of the Combined Multi-Channel PWM Modes is updated. − “Phase Delay Timer” - related description is removed. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

User’s Manual I-1 2001-05

3.4.3 Accesses to XRAM using the Registers R0/R1

4.2 PSEN

User’s Manual I-2 2001-05

User’s Manual I-3 2001-05

6.3.4.5 Software Controlled State Switching in Multi-Channel

User’s Manual I-4 2001-05 8.2.1

User’s Manual 1-1 2001-05

1 Introduction

The C508 is a member of the Infineon Technologies C500 family of 8-bit microcontrollers. It is fully compatible to the standard 8051 microcontroller. Its features include extended power saving provisions, 256 × 8 on-chip RAM, 32K × 8 on-chip program memory, RFI related improvements, and the Capture Compare Unit (CCU) which is useful in motor control applications. The C508 has an internal PLL and, with a maximum CPU clock rate of 20 MHz, it achieves a 300 ns instruction cycle time. The C508 operates with internal and/or external program memory. The C508-4R contains 32K × 8 on-chip program memory (ROM version) while the C508-4E has 32K × 8 One-Time Programmable program memory (OTP version). In this document, the term C508 refers to both versions unless otherwise noted. Figure 1-1 shows the various functional units of the C508 and Figure 1-2 shows the simplified logic symbol of the C508. Figure 1-1 C508 Functional Units MCB04022 I/O I/O I/O I/O On-Chip Emulation Support Module Watchdog Timer Timer 2 10-Bit ADC Oscillator Watchdog XRAM

1 K x 8

32 K x 8

8 Datapointers

User’s Manual 1-2 2001-05 Listed below is a summary of the main features of the C508 microcontroller:  Fully compatible to standard 8051 microcontroller  Superset of the 8051 architecture with eight datapointers  10 to 20 MHz internal CPU clock (using built-in PLL with a factor of 2) – external clock of 5 - 10 MHz at 50% duty cycle – 300 ns instruction cycle time at 20 MHz CPU clock  32 Kbytes on-chip ROM/OTP (with optional ROM protection)  256 bytes on-chip RAM  1024 bytes on-chip XRAM  Six 8-bit ports, – Ports 1 and 2 with enhanced current sinking capabilities of 10 mA per pin (total max. of 100 mA) – Port 4 with pure analog/digital input channels  Three 16-bit timers/counters – Timer 0 /1 (C501 compatible) – Timer 2 with four channels for 16-bit capture/compare operation  Capture/Compare Unit (CCU) for PWM (Pulse Width Modulation) signal generation – 3-channel, 16-bit capture/compare unit – 1-channel, 10-bit compare unit  Full-duplex serial interface with programmable baudrate generator (USART)  8-channel 10-bit A/D Converter  19 interrupt vectors with four priority levels  On-chip emulation support logic (Enhanced Hooks Technology)  Programmable 15-bit Watchdog Timer  Oscillator Watchdog  Fast Power On Reset  Power Saving Modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through P3.2/INT0 or P5.7/ INT7  ALE switch-off capability for reduction in RFI emission  P-MQFP-64-1, P-SDIP-64-2 packages  Temperature ranges: SAB-C508 TA = 0 to 70 °C SAF-C508 TA = -40 to 85 °C

User’s Manual 1-3 2001-05 Figure 1-2 Logic Symbol MCL04023 C508 Port 2 8-Bit Digital I/O Port 3 8-Bit Digital I/O Port 4 8-Bit Digital/ Analog Inputs Port 5 8-Bit Digital I/O XTAL1 XTAL2 RESET EA ALE PSEN VDD VSS Port 1 8-Bit Digital I/O Port 0 8-Bit Digital I/O VDDA VSSA VAREF VAGND

User’s Manual 1-4 2001-05

1.1 Pin Configuration

This section shows the pin configurations of the C508 microcontroller in the P-MQFP-64-1 and the P-SDIP-64-2 packages. Figure 1-3 Pin Configuration for P-MQFP-64-1 Package (top view) MCP04024 P2.5/A13 49 P2.4/A12 50 51P2.3/A11 52P2.2/A10 P2.1/A9 53 54P2.0/A8 55VSS 57P0.0/AD0 58P0.1/AD1 P0.2/AD2 59 60P0.3/AD3 61P0.4/AD4 P0.5/AD5 62 63P0.6/AD6 64P0.7/AD7 P2.6/A14 P2.7/A15 PSENALE 45 44 V DD XTAL1 42 41 XTAL2 P3.7/RDP3.6/WR 39 38 P3.5/T1 P3.4/T0P3.3/INT1 36 35 P3.2/INT0 P3.1/TxDP3.0/RxD 32 P1.0/COUT3 31 P1.1/CTRAP 30 P1.2/CC0 P1.3/COUT029 28 P1.4/CC1 27 P1.5/COUT1 P1.6/CC226 25 P1.7/COUT2

24 VSS

22 P5.0/T2CC0/INT3 21 P5.1/T2CC1/INT4 P5.2/T2CC2/INT520 19 P5.3/T2CC3/INT6 18 P5.4/INT2 P5.5/INT917 VDD RESET EA V DDA P4.0/AN0 P4.1/AN1 P4.2/AN2P4.3/AN3 P4.4/AN4 P4.5/AN5P4.6/AN6 11 12 P4.7/AN7 13 14 15 P5.7/INT7 P5.6/INT8 V SSA V AREF V AGND VDD V SS C508

User’s Manual 1-5 2001-05 Figure 1-4 shows the pin configuration of the C508 in the P-SDIP-64-2 package. Figure 1-4 Pin Configuration for P-SDIP-64-2 Package (top view) MCP04025 C508 P0.0/AD0 1 P0.1/AD1 2 3P0.2/AD2 P0.3/AD3 4 5P0.4/AD4 6P0.5/AD5 P0.6/AD6 7 8P0.7/AD7 9RESET EA 10 11VDDA P4.0/AN0 P4.1/AN1 P4.2/AN2 P4.3/AN3 P4.4/AN4 P4.5/AN5 18 P4.6/AN6 19 20P4.7/AN7 P5.7/INT7 P5.6/INT8 24 P5.5/INT9 25 26P5.4/INT2 P5.3/T2CC3/INT6 27 VSSA VAREF VAGND P5.2/T2CC2/INT5 P5.1/T2CC1/INT4 P5.0/T2CC0/INT3 VDD VSS

64 VDD

62 P2.0/A8 P2.1/A961 60 P2.2/A10 59 P2.3/A11 P2.4/A1258 57 P2.5/A13 56 P2.6/A14 P2.7/A1555

54 PSEN

53 ALE

50 XTAL1

48 P3.7/RD 47 P3.6/WR P3.5/T146 45 P3.4/T0 44 P3.3/INT1 P3.2/INT043 42 P3.1/TxD 41 P3.0/RxD P1.0/COUT340 39 P1.1/CTRAP 38 P1.2/CC0 P1.3/COUT037 36 P1.4/CC1 35 P1.5/COUT1 P1.6/CC234 33 P1.7/COUT2 VSS VDD VSS

User’s Manual 1-6 2001-05

1.2 Pin Definitions and Functions

This section describes all external signals of the C508 and their functions. Table 1-1 Pin Definitions and Functions Symbol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64 P1.0-P1.7 32 - 25 40 - 33 I/O Port 1 is an 8-bit quasi-bidirectional port with internal pull- up transistors. Port 1 pins can be used for digital input/output. Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 1 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pull-up transistors. The output latch corresponding secondary function must be programmed to a one (1) for that function to operate. As secondary functions, Port 1 contains the capture/compare inputs/outputs as well as the CCU trap input. Port 1 pins have LED drive capability of up to 10 mA sinking current per pin. The secondary functions from the CCU unit are assigned to the pins of Port 1 as follows: P1.0 / COUT3 10-bit compare channel output P1.1 / CTRAP CCU trap input P1.2 / CC0 Input/Output of capture/compare Channel 0 P1.3 / COUT0 Output of capture/compare Channel 0 P1.4 / CC1 Input/Output of capture/compare Channel 1 P1.5 / COUT1 Output of capture/compare Channel 1 P1.6 / CC2 Input/Output of capture/compare Channel 2 P1.7 / COUT2 Output of capture/compare Channel 2 RESET 1 9 I RESET A high level on this pin for one machine cycle while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD.

User’s Manual 1-7 2001-05 P3.0-P3.7 33 - 40 41 - 48 I/O Port 3 is an 8-bit quasi-bidirectional port with internal pull- up transistors. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 3 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pull-up transistors. The output latch corresponding secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR The secondary functions are assigned to the pins of Port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External Interrupt 0 Input/Timer 0 gate control input P3.3 / INT1 External Interrupt 1 Input/Timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from Port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

User’s Manual 1-8 2001-05 P2.0-P2.7 54 - 47 62 - 55 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pull-up transistors. Port 2 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pull-up transistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-up transistors when issuing 1’s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), Port 2 issues the contents of the P2 special function register and uses only the internal pull-up transistors. As I/O functions, Port 2 pins also have LED drive capability of up to 10 mA sinking current per pin. XTAL1 42 50 I XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. XTAL2 41 49 O XTAL2 Output of the inverting oscillator amplifier. P4.0-P4.7 5 - 12 13 - 20 I Port 4 is an 8-bit uni-directional input port to the A/D converter. Port 4 pins can be used for digital input, if voltage levels simultaneously meet the specifications for high/low input voltages and for the eight multiplexed analog inputs. Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

User’s Manual 1-9 2001-05 PSEN 46 54 O The Program Strobe Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every one and a half oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. ALE 45 53 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every one and a half oscillator periods except during an external data memory access. When instructions are executed from internal ROM (EA = 1) the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. EA 21 0 I External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than 8000H. When held at low level, the C508 fetches all instructions from external program memory. This pin should not be driven during reset operation. P0.0-P0.7 57 - 64 1 - 8 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-up transistors when issuing 1’s. Port 0 also outputs the code bytes during program verification in the C508-4R. External pull-up resistors are required during program verification. Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

User’s Manual 1-10 2001-05 P5.0-P5.7 22 - 15 30 - 23 I/O Port 5 is a an 8-bit quasi-bidirectional I/O port with internal pull-up transistors. Port 5 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 5 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pull-up transistors. As secondary functions, Port 5 contains the interrupt and Timer 2 capture/compare pins. They are assigned to the pins as follows: P5.0/T2CC0/INT3 T2 Compare/Capture output 0/ Interrupt 3 input P5.1/T2CC1/INT4 T2 Compare/Capture output 1/ Interrupt 4 input P5.2/T2CC2/INT5 T2 Compare/Capture output 2/ Interrupt 5 input P5.3/T2CC3/INT6 T2 Compare/Capture output 3/ Interrupt 6 input P5.4/INT2 Interrupt 2 input P5.5/INT9 Interrupt 9 input P5.6/INT8 Interrupt 8 input P5.7/INT7 Interrupt 7 input VSS 24, 43, 55 32, 51, 63 – Ground (0 V) VDD 23, 44, 56 31, 52, 64 – Power Supply (+5 V) VDDA 31 1 – Analog Power Supply (+5 V) VSSA 41 2 – Analog Ground (0 V) VAREF 13 21 – Reference Voltage for the A/D Converter. VAGND 14 22 – Reference Ground for the A/D Converter. 1) I= I n p u t O=O u t p u t Table 1-1 Pin Definitions and Functions (cont’d) Symbol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

User’s Manual 2-1 2001-05

2 Fundamental Structure

The C508 is fully compatible with the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C508 incorporates a CPU with eight datapointers, a 10-bit A/D Converter, a 16-bit Capture/Compare Unit, a Timer 2 with capture/compare functions, an improved interrupt structure with four priority levels, built-in PLL with a fixed factor of 2, and an XRAM data memory, as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C508 microcontroller.

User’s Manual 2-2 2001-05 Figure 2-1 Block Diagram of the C508 C508 MCB04026 Oscillator Watchdog OSC & Timing PLL, factor of 2 CPU

4 PWM Channels

S&H XRAM 1024 x 8 RAM 256 x 8 ROM/OTP

User’s Manual 2-3 2001-05

2.1 CPU

The C508 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 10 MHz external crystal (giving a 20 MHz CPU clock), 58% of the instructions execute in 300 ns. For an 8 MHz crystal, the corresponding time is 375 ns. The Central Processing Unit (CPU) of the C508 consists of the instruction decoder, the arithmetic section, and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. These internal signals have an effect on the source and destination of data transfers and control the Arithmetic/Logic Unit (ALU) processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the ALU, an A register, a B register, and a Program Status Word (PSW) register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations: add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement, and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations such as set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set- and-clear, and move to/from carry. Between any addressable bit (or its complement) and the carry flag, the ALU can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Beyond the CPU functionality of the C501/8051 standard microcontroller, the C508 contains eight datapointers. For complex applications with peripherals located in the external data memory space or extended data storage capacity, this proved to be a “bottle neck” for the 8051’s communication to the external world. Programming in high- level languages (PLM51, C51, PASCAL51) especially requires extended RAM capacity as well as fast access to this additional RAM because of the reduced code efficiency of these languages. Accumulator ACC is the symbol for the Accumulator Register. The mnemonics for accumulator- specific instructions, however, refer to the Accumulator simply as A.

User’s Manual 2-4 2001-05 Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. Special Function Register PSW (Address D0H) Reset Value: 00 H B Register The B Register is used during multiply and divide and serves as both source and destination. For other instructions, it can be treated as another scratch pad register. Bit Function CY Carry Flag Used by arithmetic instructions. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag 0 RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instructions. F1 General Purpose Flag 1 P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/ even number of “one” bits in the accumulator. CY AC F0 RS1 RS0 OV F1 PD0H PSW D7H D6H D5H D4H D3H D2H D1H D0H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H-07H 0 1 Bank 1 selected, data address 08 H-0FH 1 0 Bank 2 selected, data address 10 H-17H 1 1 Bank 3 selected, data address 18 H-1FH

User’s Manual 2-5 2001-05 Stack Pointer The Stack Pointer (SP) Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution; that is, it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07 H after a reset. This causes the stack to begin at location = 08H above register bank zero. The SP can be read or written under software control.

2.2 CPU Timing

The C508 has no clock prescaler. Therefore, a machine cycle of the C508 consists of six states (3 oscillator periods). Each state is divided into a Phase 1 half and a Phase 2 half. Thus, a machine cycle consists of 3 oscillator periods, numbered S1P1 (State 1, Phase 1) through S6P2 (State 6, Phase 2). Each state lasts for half an oscillator period. Typically, arithmetic and logic operations take place during Phase 1 and internal register-to-register transfers take place during Phase 2. The diagrams in Figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the Address Latch Enable (ALE) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the Instruction Register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figure 2-2 (a) and (b) show the timings for a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C508 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete: they take four cycles. Normally, two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timings for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.

User’s Manual 2-6 2001-05 Figure 2-2 Fetch Execute Sequence S5S2S1 S3 S4 S6 Read Opcode Read Next Opcode Again a) 1-byte, 1-Cycle Instruction, e.g. INC A S5S2S1 S3 S4 S6 Read Opcode Read 2nd byte Read Next Opcode OSC (XTAL2) ALE P1 P2 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 Read Next Opcode (Discard) b) 2-byte, 1-Cycle Instruction, e.g. ADD A #Data S5S2S1 S3 S4 S6 Read Opcode S1 S2 S3 S5S4 S6 c) 1-byte, 2-Cycle Instruction, e.g. INC DPTR Read Next Opcode (Discard) Read Next Opcode Again MCD04027 S5S2S1 S3 S4 S6 Read Opcode (MOVX) d) MOVX (1-byte, 2-Cycle) S1 S2 S3 S5S4 S6 Read Next Opcode (Discard) No Fetch Access of External Memory No ALE ADDR DATA Read Next Opcode Again No Fetch

User’s Manual 3-1 2001-05

3 Memory Organization

The C508 CPU manipulates operands in the following five address spaces: – Up to 64 Kbytes of program memory: 32K ROM for the C508-4R : 32K OTP for the C508-4E – Up to 64 Kbytes of external data memory – 256 bytes of internal data memory – 1024 bytes of internal XRAM data memory – a 128-byte special function register area. Figure 3-1 illustrates the memory address spaces of the C508. Figure 3-1 C508 Memory Map MCS04029 Special Function Regs. FFH 80H Direct Addr. Indirect Addr. Internal RAM 00H 7FH Internal RAM "Internal Data Space" Internal XRAM (1 Kbyte) FFFFH FC00H Ext. Data Memory 0000H FBFFH Ext. Data Memory "Data Space" 8000H FFFFH Ext. "Code Space" Ext. (EA = 0) 7FFFH 0000H Int. (EA = 1) Alternatively

User’s Manual 3-2 2001-05

3.1 Program Memory, “Code Space”

The C508-4R has 32 Kbytes of Read-Only program Memory (ROM), while the C508-4E provides 32 Kbytes of OTP program memory. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C508-4R executes program code out of the internal ROM unless the program counter address exceeds 7FFF H. Address locations 8000 H through FFFF H are then fetched from the external program memory. If the EA pin is held low, the C508 fetches all instructions from the external program memory.

3.2 Data Memory, “Data Space”

The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks: the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128-byte Special Function Register (SFR). While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1F H in the lower RAM area. The next 16 bytes, locations 20 H through 2F H, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal RAM area, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal XRAM is located in the external address memory area at addresses FC00 H to FFFFH. Using MOVX instruction with addresses pointing to this address area, allows access to either internal XRAM or external data RAM.

3.3 General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks of eight General Purpose Registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the Program Status Word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in Chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The eight general purpose registers of the selected register bank may be accessed by register addressing. With register addressing, the instruction op code indicates which register is to be used. For indirect addressing, R0 and R1 are used as pointers or index registers to address internal or external memory (for example: MOV @R0).

User’s Manual 3-3 2001-05 Reset initializes the stack pointer to location 07 H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if more than one register bank is required, the SP should be initialized to a different location of the RAM which is not used for data storage.

3.4 XRAM Operation

The XRAM in the C508 is a memory area that is logically located at the upper end of the external data memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory, the same instruction types (MOVX) must be used for accessing the XRAM.

3.4.1 XRAM Controller Access Control

Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external signal generation during XRAM accesses. Special Function Register SYSCON (Address B1 H) Reset Value: XX10XX01 B Bit Function XMAP1 XRAM visible access control Control bit for RD/WR signals during XRAM accesses. If addresses are outside the XRAM address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0: The signals RD and WR are not activated during accesses to the XRAM. XMAP1 = 1: Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM. In this mode, address and data information during XRAM accesses are visible externally. XMAP0 Global XRAM access enable/disable control XMAP0 = 0: The access to XRAM is enabled. XMAP0 = 1: The access to XRAM is disabled (default after reset). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP –B1H SYSCON Bit No. MSB LSB – XMAP1–– XMAP0 The functions of the shaded bits are not described here.

User’s Manual 3-4 2001-05 When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM, RD and WR become active and Port 0 and Port 2 drive the actual address/data information which is read/written from/to XRAM. This feature allows checking of the internal data transfers to XRAM. When Ports 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set; otherwise, the I/O function of the Port 0 and Port 2 lines is interrupted. After a reset operation, bit XMAP0 is set. This means that the accesses to XRAM are generally disabled. In this case, all accesses using MOVX instructions within the address range of FC00 H to FFFFH generate external data memory bus cycles. When XMAP0 is cleared, the access to XRAM is enabled and all accesses using MOVX instructions with an address in the range of FC00H to FFFFH will access the internal XRAM. Bit XMAP0 is hardware protected. If it is cleared once (that is, if internal XRAM access enabled), it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism is implemented by an asymmetric latch at XMAP0 bit. An unintentional disabling of XRAM could be dangerous as indeterminate values could be read from the external bus. To avoid this, the XMAP0 bit is forced to ‘1’ only by a reset operation. Additionally, during reset, an internal capacitor is charged. So the reset status is a disabled XRAM. After a ‘0’ is written to XMAP0 bit (that is, discharging the capacitor), it is not possible to set it back again to ‘1’ due to the charge time of the capacitor. On the other hand, any distortion (such as a software hang up, noise, etc.) also cannot charge this capacitor. Thus, the stable status is the enabled XRAM. The clear instruction for the XMAP0 bit should be integrated into the program initialization routine before XRAM is used. In extremely noisy systems, the user may have redundant clear instructions.

User’s Manual 3-5 2001-05

3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)

The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect addressing. These instructions are: – MOVX A, @DPTR (Read) – MOVX @DPTR, A (Write) For accessing the XRAM, the effective address stored in DPTR must be in the range of FC00H to FFFFH.

3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing

Mode) The 8051 architecture also provides instructions for accesses to the external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: – MOVX A, @Ri (Read) MOVX @Ri, A (Write) A special page register is implemented in the C508 to enable accessing the XRAM with the MOVX @Ri instructions as well; that is, XPAGE serves the same function for the XRAM as Port 2 does for external data memory. Special Function Register XPAGE (Address 91 H) Reset Value: 00 H Figure 3-2 to Figure 3-4 show the dependencies of XPAGE and Port 2 addressing in order to illustrate the differences in accessing XRAM, external RAM, or the use of Port 2 as an I/O-port. Bit Function XPAGE.7-0 XRAM high address XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are used to access internal XRAM. XPAGE 76543210 .5 .4 .391H Bit No. MSB LSB

User’s Manual 3-6 2001-05 Figure 3-2 Write Page Address to Port 2 Moving the page address to Port 2 by using either the immediate addressing instruction (MOV P2, #pageaddress) or the direct addressing instruction (MOV P2, PAL; where ‘PAL’ is the internal RAM location containing the page address) will write the page address to Port 2 and also to the XPAGE-Register. When external RAM is to be accessed in the XRAM address range, the XRAM must be disabled. When the additional external RAM is to be addressed in an address range 0000 H to FC00H, the XRAM may remain enabled. MCB02112 XRAM Port 0 Address/Data Page Address Write to Port 2 Port 2 XPAGE

User’s Manual 3-7 2001-05 Figure 3-3 Write Page Address to XPAGE “MOV XPAGE, #pageaddress ” or “MOV XPAGE, PAL ”, where ‘PAL’ is internal RAM location containing the page address, will write the page address only to the XPAGE register. Port 2 is thus available for addresses or for I/O data. MCB02113 XRAM Port 0 Port 2 Address/Data Address/ Write to XPAGE I/O-Data XPAGE

User’s Manual 3-8 2001-05 Figure 3-4 Use of Port 2 as I/O Port With a write to Port 2, the XRAM address in XPAGE register will be overwritten because of the concurrent write to Port 2 and the XPAGE register. So, whenever XRAM is used and the XRAM address differs from the byte written to the Port 2 latch, it is absolutely necessary to rewrite XPAGE with the page address. Example: I/O data at Port 2 shall be AAH. A byte shall be fetched from XRAM at address FF30H. MOV R0, #30H ; MOV P2, #0AAH ; P2 shows AA H and XPAGE contains AAH MOV XPAGE, #0FFH ; P2 still shows AA H but XRAM is addressed MOVX A, @R0 ; the contents of XRAM at FF30 H is moved to the accumulator MCB02114 XRAM Port 0 Address/Data Write I/O Data I/O-Data to Port 2 XPAGE Port 2

User’s Manual 3-9 2001-05 The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM address range, an external access is performed. For the C508, the content of XPAGE must be FCH - FFH in order to use the XRAM. The software must distinguish two cases, if the MOVX @Ri instructions with paging will be used: a) Access to XRAM: The upper address byte must be written to XPAGE or P2; both writes select the XRAM address range. b) Access to external memory: The upper address byte must be written to P2; XPAGE will be automatically loaded with the same address in order to deselect the XRAM.

3.4.4 Reset Operation of the XRAM

The contents of the XRAM are not affected by a reset. After power-up, the contents are undefined, while they remain unchanged during and after a reset, as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the effect on the contents of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a two-cycle instruction): Reset during 1 st cycle: The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle: The old value in XRAM is overwritten by the new value.

3.4.5 Behavior of Port 0 and Port 2

The behavior of Port 0 and Port 2 during a MOVX access depends on the control bits in the SYSCON Register and on the state of Pin EA. Table 3-1 lists the various operating conditions. It shows the following characteristics: a) Use of P0 and P2 pins during the MOVX access. Bus: The pins work as an external address/data bus. If (internal) XRAM is accessed, the data written to the XRAM can be seen on the bus in debug mode. I/O: The pins work as Input/Output lines under control of their latch. b) Activation of the RD and WR pin during the access. c) Use of internal (XRAM) or external XDATA memory. The shaded areas in Table 3-1 describe the standard operation for each C500 device without on-chip XRAM.

User’s Manual 3-10 2001-05 Table 3-1 - Behavior of P0/P2 and RD /WR During MOVX Accesses EA = 0 EA = 1 XMAP1, XMAP0 XMAP1, XMAP0 00 10 X1 00 10 X1 MOVX @DPTR DPTR XRAM address range a)P0/P2→Bus b)RD/WR active c)ext. memory is used a)P0/P2→Bus b)RD/WR active c)ext. memory is used a)P0/P2→Bus b)RD/WR active c)ext. memory is used a)P0/P2→Bus b)RD/WR active c)ext. memory is used a)P0/P2→Bus b)RD/WR active c)ext. memory is used a)P0/P2→Bus b)RD/WR active c)ext. memory is used DPTR XRAM address range a)P0/P2→Bus (RD/WR-Data) b)RD/WR inactive c)XRAM is used a)P0/P2→Bus (RD/WR-Data) b)RD/WR active c)XRAM is used a)P0/P2→Bus b)RD/WR active c) ext. memory is used a)P0/P2→I/O b)RD/WR inactive c)XRAM is used a)P0/P2→Bus (RD/WR-Data) b)RD/WR active c)XRAM is used a)P0/P2→Bus b)RD/WR active c) ext. memory is used MOVX @ Ri XPAGE XRAM addr. page range a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used XPAGE XRAM addr. page range a)P0→Bus (RD/WR-Data) P2→I/O b)RD/WR inactive c)XRAM is used a)P0 →Bus (RD/WR-Data) P2→I/O b)RD/WR active c)XRAM is used a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used a)P0/P2→I/O b)RD/WR inactive c)XRAM is used a)P0 →Bus (RD/WR-Data) P2→I/O b)RD/WR active c)XRAM is used a)P0→Bus P2→I/O b)RD/WR active c)ext. memory is used modes compatible to 8051/C501 family

User’s Manual 3-11 2001-05

3.5 Special Function Registers

With the exception of the program counter and the four general purpose register banks, the registers reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. One special function register of the C508 (PCON1) is located in the mapped special function register area. To access the mapped special function register area, bit RMAP in the special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (0). Special Function Register SYSCON (Address B1 H) Reset Value: XX10XX01 B As long as bit RMAP is set, the mapped special function register area can be accessed. This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. All Special Function Registers (SFRs) with addresses whose address bits 0-2 are 0 (such as: 80 H, 88H, 90H, 98H, … , F0H, F8H) are bit-addressable. The 81 SFRs in the standard and mapped SFR areas include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C508 are listed in Table 3-2 and Table 3-3. In Table 3-2, they are organized in groups which refer to the functional blocks of the C508. Table 3-3 illustrates the contents of the SFRs in numeric order by their addresses. Bit Function RMAP Special Function Register Map bit RMAP = 0: Access to the non-mapped (standard) special function register area is enabled. RMAP = 1: Access to the mapped special function register area is enabled. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP –B1H SYSCON Bit No. MSB LSB – XMAP1–– XMAP0 The functions of the shaded bits are not described here.

User’s Manual 3-12 2001-05 Table 3-2 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP SYSCON VR02) VR12) VR22) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 H F0H 83H 82H 92H D0H 81H B1H FCH FDH FEH 00H 00H 00H 00H XXXXX000B 00H 07H XX10XX01B C5H 08H5) A/D- Converter ADCON01) ADCON1 ADDATH ADDATL A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Start Register Low Byte H DCH D9H DAH 00X00000B 01XXX000B 00H 00XXXXXXB Interrupt System IEN01) IEN11) IEN2 IEN3 IP01) IP1 TCON1) T2CON1) SCON1) IRCON EINT Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register External Interrupt Control Register H B8H 9AH BEH A9H B9H 88H C8H 98H C0H FBH 00H X0000000B XX0000XXB XXX000XXB 00H XX000000B 00H 00H 00H X0000000B XX000000B XRAM XPAGE SYSCON1) Page Address Register for Extended on-chip XRAM and CAN Controller System Control Register 91H B1H 00H XX10XX01B Ports P0 Port 0 Port 1 Port 2 Port 3 Port 4, Analog/Digital Input Port 5 H 90H A0H B0H DBH F8H FFH FFH FFH FFH FFH

User’s Manual 3-13 2001-05 Serial Channel ADCON01) PCON1) SBUF SCON SRELL SRELH A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, Low Byte Serial Channel Reload Register, High Byte H 87H 99H 98H AAH BAH 00X00000B 00H XXH 00H D9H XXXXXX11B Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register H 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Timer 2 CCEN T2CCH1 T2CCH2 T2CCH3 T2CCL1 T2CCL2 T2CCL3 CRCH CRCL TH2 TL2 T2CON Compare/Capture Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Comp./Rel./Capt. Register, High Byte Comp./Rel./Capt. Register, Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

User’s Manual 3-14 2001-05 Compare/ Capture Unit CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 TRCON COTRAP CCIR CCIE CT2CON CP2L CP2H CMP2L CMP2H BCON Compare Timer 1 Control Register Compare Timer 1 Period Register, Low Byte Compare Timer 1 Period Register, High Byte Compare Timer 1 Offset Register, Low Byte Compare Timer 1 Offset Register, High Byte Capture/Compare Mode Select Register 0 Capture/Compare Mode Select Register 1 Compare Output Initialization Register Capture/Compare Register 0, Low Byte Capture/Compare Register 0, High Byte Capture/Compare Register 1, Low Byte Capture/Compare Register 1, High Byte Capture/Compare Register 2, Low Byte Capture/Compare Register 2, High Byte Trap Enable Control Register Compare Output In Trap State Register Capture/Compare Interrupt Request Flag Reg. Capture/Compare Interrupt Enable Register Compare Timer 2 Control Register Compare Timer 2 Period Register, Low Byte Compare Timer 2 Period Register, High Byte Compare Timer 2 Compare Register, Low Byte Compare Timer 2 Compare Register, High Byte Block Commutation Control Register H DEH DFH E6H E7H E3H E4H E2H F2H F3H F4H F5H F6H F7H FFH F9H E5H D6H F1H D2H D3H D4H D5H D7H 00010000B 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H XXXXXX00B 00H XXXXXX00B 00H Watchdog Timer WDTL WDTH WDTREL IEN01) IEN11) IP01) Watchdog Timer Register, Low Byte Watchdog Timer Register, High Byte Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 H 85H 86H A8H B8H A9H 00H X0000000B 00H 00H 00H 00H Power Save Modes PCON1) PCON12) Power Control Register Power Control Register 1 87H 88H 00H 0XX0XXXXB 1) This special function register is listed repeatedly as some bits of it also belong to other functional blocks. 2) This SFR is a mapped SFR. To access this SFR, bit RMAP in SFR SYSCON must be set. 3) Bit-addressable special function registers. 4) “X” means that the value is undefined and the location is reserved. 5) The content of this SFR varies with the actual step of the C508 (e.g. 01 H for C508-4E, first step and 11 H for C508-4R, first step). Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

User’s Manual 3-15 2001-05 Table 3-3 Contents of the SFRs, SFRs in Numeric Order by Address Addr Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 85H WDTH X000- 0000B 86H WDTREL 00 H WDT PSEL 87H PCON 00 H SMOD PDS IDLS SD GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 3) PCON1 0XX0- XXXXB 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 92H DPSEL XXXX- X000B 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI 9A IEN2 XX00- 00XXB –– ECT1 ECCM ECT2 ECEM –– A0H A8H 2) IEN0 00H EA WDT ET2 ES ET1 EX1 ET0 EX0

User’s Manual 3-16 2001-05 B0H 2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B1H SYSCON XX10- XX01B –– EALE RMAP –– XMAP1 XMAP B8H 2) IEN1 X000- 0000B – SWDT EX6 EX5 EX4 EX3 EX2 EADC B9H IP1 XX00- 0000B BAH SRELH XXXX- XX11B BEH IEN3 XXX0- 00XXB C0H 2) IRCON X000- 0000B – TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC C1H CCEN 00 H COCA COCA COCA COCA COCA COCA COCA COCA C8H 2) T2CON 0000- X0X0B T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 D0H 2) PSW 00H CY AC F0 RS1 RS0 OV F1 P D3H CP2H XXXX. XX00B D5H CMP2H XXXX. XX00B Table 3-3 Contents of the SFRs, SFRs in Numeric Order by Address (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

User’s Manual 3-17 2001-05 D6H CCIE 00 H ECTP ECTC CC2 FEN CC2 REN CC1 FEN CC1 REN CC0 FEN CC0 REN D7H BCON 00 H BCMP BCEM PWM1 PWM0 EBCE BCER R BCEN BCM1 BCM0 D8H 2) ADCON0 00X0- 0000B BD CLK – BSY ADM MX2 MX1 MX0 DAH ADDATL 00XX- XXXXB DCH ADCON1 01XX- X000B ADCL1 ADCL0 ––– MX2 MX1 MX0 E0H E1H CT1CON 0001- 0000B CTM ETRP STE1 CT1 RES CT1R CLK2 CLK1 CLK0 E2H COINI FF H COUT COUT XI COUT CC2I COUT CC1I COUT CC0I E3H CMSEL0 00 H CMSE L13 CMSE L12 CMSE L11 CMSE L10 CMSE L03 CMSE L02 CMSE L01 CMSE L00 E4H CMSEL1 00 H ESMC NMCS 0 0 CMSE L23 CMSE L22 CMSE L21 CMSE L20 E5H CCIR 00 H CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R F0H F1H CT2CON 0001- 0000B CT2P ECT2O STE2 CT2 RES CT2R CLK2 CLK1 CLK0 Table 3-3 Contents of the SFRs, SFRs in Numeric Order by Address (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

User’s Manual 3-18 2001-05 F8H F9H COTRAP 00 H BCT SEL RES COUT2 T CC2T COUT1 T CC1T COUT0 T CC0T FBH EINT XX00- 0000B –– IEX9 I9FR IEX8 I8FR IEX7 I7FR FCH3)4) VR0 C5 H 11000101 FDH3)4) VR1 08 H 00001000 FEH3)4) FFH TRCON 00 H TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN 1) X means that the value is undefined and the location is reserved. 2) Bit-addressable special function registers. 3) SFR is located in the mapped SFR area. To access this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual step of the C508 (e.g. 01 H for C508-4E, first step and 11 H for C508-4R, first step). Table 3-3 Contents of the SFRs, SFRs in Numeric Order by Address (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

User’s Manual 4-1 2001-05

4 External Bus Interface

The C508 allows for external memory expansion. The functionality and implementation of the external bus interface are identical to the common interface for the 8051 architecture with one exception. The exception is the suppression of the ALE signal generation when the C508 is used in systems with no external memory. Resetting the EALE bit in SFR SYSCON gates off the ALE signal. This feature reduces RFI emissions of the system.

4.1 Accessing External Memory

It is possible to distinguish between accesses to external program memory and accesses to external data memory or other peripheral components. This distinction is possible because hardware accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and Port 2 (with exceptions) are used to provide data and address signals. In this section, only the Port 0 and Port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri).

4.1.1 Role of P0 and P2 as Data/Address Bus

When used to access external memory, Port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, Port 0 is disconnected from its own port latch, and the address/data signal drives both FETs in the Port 0 output buffers. Thus, in this application, the Port 0 pins are not open-drain outputs and do not require external pull-up resistors. During any access to external memory, the CPU writes FF H to the Port 0 latch (the special function register), thus obliterating whatever information the Port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on Port 2, where it is held for the duration of the read or write cycle. During this time, the Port 2 lines are disconnected from the Port 2 latch (the special function register). Thus, the Port 2 latch does not need to contain ‘1’s and the contents of the Port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a Port 2 pin outputs an address bit that is a ‘1’, strong pull-ups will be used for the entire read/write cycle and not only for two oscillator periods.

User’s Manual 4-2 2001-05 Figure 4-1 External Program Memory Execution PCL OUT PCH OUT One Machine Cycle One Machine Cycle OUT PCH IN INST (A) without MOVX PCL OUT valid PCL OUT valid PCL OUT valid PCL OUT valid ALE PSEN RD RD PSEN ALE valid PCL OUT valid PCL OUT MOVX with (B) IN DATA IN INSTINST IN DPH OUT OR P2 OUT One Machine CycleOne Machine Cycle S6S5S4S3S2S1S6S5S4S3S2S1 MCD02575 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 OUT PCH PCH OUTOUT PCH PCH OUT OUT PCHPCH OUT P0 INST IN PCL OUT IN INST OUT PCL INST IN PCL OUT IN INST P0 PCL OUT DPL or Ri valid PCL OUT INST IN

User’s Manual 4-3 2001-05

4.1.2 Timing

The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN , RD , WR and information on Port 0 and Port 2, is illustrated in Figure 4-1 a) and b). Data memory: In a write cycle, the data byte to be written appears on Port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at Port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe.

4.1.3 External Program Memory Access

The external program memory is accessed under two conditions: – whenever signal EA is active (low) or – whenever the program counter (PC) content is greater than 7FFFH When the CPU is executing out of external program memory, all eight bits of Port 2 are dedicated to an output function and must not be used for general-purpose I/O. The contents of the Port 2 SFR, however, are not affected. During external program memory fetches, Port 2 lines output the high byte of the PC, and during accesses to external data memory, they output either DPH or the Port 2 SFR (determined by whether external data memory access is a MOVX @DPTR or a MOVX @Ri).

4.2 PSEN , Program Store Enable

The read strobe for external program memory fetches is PSEN . It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated, its timing is not the same as for RD . A complete RD cycle, including activation and deactivation of ALE and RD , takes three oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN , takes 1.5 oscillator periods. (The execution sequence for these two types of read cycles is shown in Figure 4-1 a) and b).

4.3 Overlapping External Data and Program Memory Spaces

In some applications, it is desirable to execute a program from the same physical memory that is used for storing data. In the C508, the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory. As the PSEN cycle is faster than the RD cycle, the external memory must be fast enough to adapt to the PSEN cycle.

User’s Manual 4-4 2001-05

4.4 ALE, Address Latch Enable

The C508 allows the ALE output signal to be switched off. If the internal ROM is used (EA = 1 and PC ≤ 7FFFH) and ALE is switched off by EALE = 0, then, ALE will go active only during external data memory accesses (MOVX instructions). If EA = 0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset, ALE generation is enabled. Special Function Register SYSCON (Address B1H) Reset Value: XX10XX01B Bit Function EALE Enable ALE output EALE = 0: ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA =1 ) . With EA = 1, ALE is automatically generated at MOVX instructions. EALE = 1: ALE generation is enabled. If EA = 0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP –B1H SYSCON Bit No. MSB LSB – XMAP1–– XMAP0 The shaded bits are not described in this section.

User’s Manual 4-5 2001-05

4.5 Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information about the internal operation of the controllers. Emulation of on-chip ROM-based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology requires embedded logic in the C500 and allows the C500 when used with an EH-IC, to function in a manner similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the various versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover, and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, Port 2 and some of the control lines of the C500 based MCU are used by the Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer information about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. MCS02647 SYSCON PCON TCON RESET EA PSEN ALE Port 0 Port 2 I/O Ports Optional Port 3 Port 1 C500 MCU Interface Circuit Enhanced Hooks RPort 0RPort 2 RTCON RPCON RSYSCON TEA TALE TPSEN EH-IC Target System Interface ICE-System Interface to Emulation Hardware

User’s Manual 4-6 2001-05

4.6 Eight Datapointers for Faster External Bus Access

4.6.1 The Importance of Additional Datapointers

The standard 8051 architecture provides only one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit “move immediate” to this datapointer and an increment instruction, any other pointer handling must be handled bytewise. For complex applications with peripherals located in the external data memory space or extended data storage capacity, this factor turned out to be a “bottle neck ” for the 8051 ’s communication to the external world. In particular, programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages.

4.6.2 Implementation of the Eight Datapointers

Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility with the 8051 instruction set. This instruction set, however, allows the handling of only one single 16-bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses and 100% compatibility with 8051 architecture), the C508 contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user ’s program may keep up to eight 16-bit addresses resident in these registers; but, only one register at a time is selected to be the datapointer. Thus, the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (Data Pointer Select register). All instructions of the C508 which handle the datapointer, therefore, affect only one of the eight pointers which is addressed by DPSEL at that very moment. Figure 4-3 illustrates the addressing mechanism. A 3-bit field in register DPSEL points to the DPTRx currently used. Any standard 8051 instruction (such as MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx.

User’s Manual 4-7 2001-05 Special Function Register DPSEL (Address 92H) Reset Value: XXXXX000 B Figure 4-3 Accessing of External Data Memory via Multiple Datapointers

4.6.3 Advantages of Multiple Datapointers

This mechanism for addressing external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction to select a new datapointer is sufficient. lf the program uses only one datapointer, then it must save the old value (with two 8-bit instructions) and load the new address, byte-by-byte. This not only takes more time, it also requires additional space in the internal RAM. Bit Function DPSEL.2-0 Data Pointer Select bits DPSEL.2-0 defines the number of the actual active data pointer, DPTR0-7. DPSEL 76543210 –––92H Bit No. MSB LSB .2 .1–– .0 DPH(83 ) DPL(82 ) DPTR0 DPTR7 .0.1.2----- DPSEL(92 ) DPSEL Selected Data- pointer.2 .1 .0 DPTR 0000 0 0 1 DPTR 1 0 1 0 DPTR 2 0 1 1 DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 1 1 0 DPTR 6 1 1 1 DPTR 7 MCD00779 External Data Memory H HH

User’s Manual 4-8 2001-05

4.6.4 Application Example and Performance Analysis

The following example demonstrates the involvement of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: 1FFF H Start address of table in external RAM: 2FA0 H Example 1: Using only One Datapointer (Code for a C501) Initialization Routine MOV LOW(SRC_PTR), #0FFH ;Initialize shadow_variables with source_pointer MOV HIGH(SRC_PTR), #1FH MOV LOW(DES_PTR), #0A0H ;Initialize shadow_variables with destination_pointer MOV HIGH(DES_PTR), #2FH Table Look-up Routine under Real Time Conditions ; Number of cycles PUSH DPL ;Save old datapointer 2 PUSH DPH ; 2 MOV DPL, LOW(SRC_PTR) ;Load Source Pointer 2 MOV DPH, HIGH(SRC_PTR) ; 2 INC DPTR ;Increment and check for end of table ;(execution time CJNE … ;not relevant for this consideration) – MOVC A,@DPTR ;Fetch source data byte from ROM table 2 MOV LOW(SRC_PTR), DPL ;Save source_pointer and 2 MOV HIGH(SRC_PTR), DPH ;load destination_pointer 2 MOV DPL, LOW(DES_PTR) ; 2 MOV DPH, HIGH(DES_PTR) ; 2 INC DPTR ;Increment destination_pointer ;(ex. time not relevant) – MOVX @DPTR, A ;Transfer byte to destination address 2 MOV LOW(DES_PTR), DPL ;Save destination_pointer 2 MOV HIGH(DES_PTR),DPH ; 2 POP DPH ;Restore old datapointer 2 POP DPL ; 2 ;Total execution time (machine cycles): 28

User’s Manual 4-9 2001-05 Example 2: Using Two Datapointers (Code for a C508) Initialization Routine MOV DPSEL, #06H ;Initialize DPTR6 with source pointer MOV DPTR, #1FFFH MOV DPSEL, #07H ;Initialize DPTR7 with destination pointer MOV DPTR, #2FA0H Table Look-up Routine under Real Time Conditions ; Number of cycles PUSH DPSEL ;Save old source pointer 2 MOV DPSEL, #06H ;Load source pointer 2 INC DPTR ;Increment and check for end of table ;(execution time CJNE … ;not relevant for this consideration) – MOVC A,@DPTR ;Fetch source data byte from ROM table 2 MOV DPSEL, #07H ;Save source_pointer and ;load destination_pointer 2 MOVX @DPTR, A ;Transfer byte to destination address 2 POP DPSEL ;Save destination pointer and ;restore old datapointer 2 ;Total execution time (machine cycles): 12 The example above shows that utilization of the C508’s multiple datapointers can make external bus accesses twice as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, as well. For some applications in which all eight datapointers are employed, this means that a C508 program has up to 24 bytes (16 variables and 8 stack bytes) of the internal RAM available for other uses.

User’s Manual 4-10 2001-05

4.7 ROM/OTP Protection for the C508-4R / C508-4E

The C508-4R allows protection of the contents of the internal ROM against unauthorized read out. The type of ROM protection is fixed with the ROM mask. Therefore, users of the C508-4R version must define whether ROM protection has to be selected or not. The C508-4E OTP version also allows program memory protection at several levels (see Chapter 10.6). The program memory protection for the C508-4E can be activated after programming of the device. The C508-4R devices, which operate from internal ROM, are always checked for correct ROM contents during production test. Therefore, unprotected as well as protected ROMs must provide a procedure to verify the ROM contents. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C508- 4R and the ROM data byte is output at Port 0. ROM verification mode 2, which is used to verify ROM protected devices, operates differently. In this mode, ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations, the state of the P3.5 pin shows whether the last 16 bytes have been verified as expected. This mechanism provides very high security for ROM protection. Only the owner of the ROM code and the manufacturer who knows the contents of the ROM can read out and verify it. The behavior of the move code instruction, when the code is executed from the external ROM, is such that accessing a code byte from a protected on-chip ROM address is not possible. In this case, the byte accessed will be invalid.

4.7.1 Unprotected ROM Mode

If the ROM is unprotected, ROM verification mode 1 as shown in Figure 4-4 is used to read out the contents of the ROM. Please refer to the AC specifications in the C508 Data Sheet for the AC timing characteristics of the ROM verification modes. Figure 4-4 ROM Verification Mode 1 MCS04096 Address 1 Data 1 OUT Address 2 Data 2 OUT P1.0-P1.7 P2.0-P2.6 Port 0 PSEN, P2.7 = VSS ALE, EA = VIH/VIH2 RESET = VIH1 Inputs:

User’s Manual 4-11 2001-05 ROM verification mode 1 is selected if the inputs PSEN , ALE, EA, and RESET are put to the specified logic level. Then, the 15-bit address of the internal ROM byte to be read is applied to the Port 1 and Port 2 lines. After a delay, Port 0 outputs the content of the addressed ROM cell. In ROM verification mode 1, the C508 must be provided with a system clock at the XTAL pins and pull-up resistors on the Port 0 lines.

4.7.2 Protected ROM/OTP Mode

If the C508-4R ROM is protected by mask (or C508-4E OTP is used in protection level 1), ROM/OTP verification mode 2 is used to verify the contents of the ROM, as shown in Figure 4-5. Please refer the AC specifications in the C508 Data Sheet for detailed timing characteristics of the ROM verification modes. Figure 4-5 ROM Verification Mode 2 ROM/OTP verification mode 2 is selected if the inputs PSEN , EA, and ALE are put to the specified logic levels. When RESET goes inactive, the ROM/OTP verification mode 2 sequence is started. The C508 outputs an ALE signal with a period of 12TCL and expects data bytes at Port 0. The data bytes at Port 0 are assigned to the ROM addresses in the following way: Verify Result for previous 16 bytes of data: Low: Verify Error High: Verify OK Data for Addr. 0 Data for Addr. 1 Data for Addr. 2 MCS04097 RESET ALE Port 0 P3.5 12TCL 6TCL 1st ALE pulse after RESET Latch Latch Latch Latch Latch Inputs: ALE = VSS PSEN, EA = /VIH VIH2 RESET = Data for Addr. X 16+1* Data for Addr. X 16* Data for Ad. X 16-1* Note: Please refer to C 508 data sheet for the definition of TCL.

User’s Manual 4-12 2001-05 1. Data Byte = contents of internal ROM/OTP address 0000 H 2. Data Byte = contents of internal ROM/OTP address 0001 H 3. Data Byte = contents of internal ROM/OTP address 0002 H 16. Data Byte = contents of internal ROM/OTP address 000F H The C508 does not output any address information during the ROM/OTP verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse, the ROM/OTP address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally. Between two ALE pulses, the data at Port 0 is latched (at 6TCL after ALE rising edge) and is compared internally with the ROM/OTP contents of the actual address. If a verify error is detected, the error condition is stored internally. After each 16 th data byte, the cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This means that P3.5 stays at a static level (low for fail and high for pass) while the next 16 bytes are checked. The output of P3.5 will be updated according to the cumulated verify result of the previous 16 bytes of data. In ROM verification mode 2, the C508 must be provided with a system clock at the XTAL pins. Figure 4-6 shows an application example of external circuitry which allows verification of a protected ROM inside the C508-4R in ROM/OTP verification mode 2. When RESET goes inactive, the C508 starts the ROM/OTP verify sequence. Its ALE is clocking a 15-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the contents of the internal (protected) ROM/OTP. The verify detect logic typically displays the state of the verify error output at P3.5. P3.5 can be latched with the falling edge of ALE. The CY signal of the address counter indicates to the verify detect logic the end of the internal ROM verification.

User’s Manual 4-13 2001-05 Figure 4-6 ROM/OTP Verification Mode 2 - External Circuitry Example MCS04098 VDD 15-Bit Address Counter S CLK CY 2 kΩ Verity Detect Logic Compare Code ROM C508-4R C508-4E RESET Port 0 CS OE D0-D7 A0-A14 EA PSEN ALE P3.5 VDD

User’s Manual 4-14 2001-05

4.8 Version Registers

Version Registers are typically used for adapting the programming firmware to specific device characteristics such as ROM/OTP size etc. Three Version Registers are implemented in the C508. They can be read during normal program execution mode as mapped SFRs when the bit RMAP in SFR SYSCON is set.

Reset and System Clock Operation User’s Manual 5-1 2001-05

5 Reset and System Clock Operation

5.1 Hardware Reset Operation

The hardware reset function incorporated in the C508 allows easy automatic startup with minimal additional hardware and forces the controller into a predefined default state. The hardware reset function can also be used during normal operation to restart the device. This is particularly useful for terminating the power-down mode. The hardware reset is applied externally to the C508. Additionally, there are three internal reset sources: the Watchdog Timer, the Oscillator Watchdog, and the PLL. This section deals with the external hardware reset only. The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (six oscillator periods) while the oscillator is running. The internal reset is executed during the second machine cycle while the oscillator is running and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (External stimulation of these lines during reset activates several reserved test modes. This, in turn, may cause unpredictable output operations at several port pins). At the reset pin, a pull-down resistor is connected internally to VSS to allow a power-up reset using only an external capacitor. An automatic power-up reset can be obtained, when VDD is applied, by connecting the reset pin to VDD via a capacitor. After VDD has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. The time required for a reset operation includes the oscillator startup time, the PLL lock time, and the time for two machine cycles, must be at least 10 - 20 ms, under normal conditions. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally ( Figure 5-1 b). In each case, it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive.

Reset and System Clock Operation User’s Manual 5-2 2001-05 Figure 5-1 Reset Circuitries A correctly executed reset leaves the processor in a defined state. The program execution starts at location 0000H. After reset is internally accomplished, the port latches of Ports 0, 1, 2, 3, and 5 default to FF H. This leaves Port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (Ports 1, 3 and 5) output a one (1). Port 2 lines output a zero after reset, if the EA pin is held low; or one if EA is held high. Port 4 is a uni-directional input port. It has no internal latch; therefore, the contents of the Special Function Register P4 depend on the levels applied to Port 4. The internal SFRs are set to their initial states as defined in Table 3-2. The contents of the internal RAM and XRAM of the C508 are not affected by a reset. The contents are undefined after power-up; the contents remain unchanged during reset if the power supply is not turned off. MCS04030 C508 RESET VDD + C508 RESET C508 RESET& VDD a) b) c)

Reset and System Clock Operation User’s Manual 5-3 2001-05

5.2 Fast Internal Reset after Power-On

The C508 uses the Oscillator Watchdog unit for a fast internal reset procedure after power-on. The clock source is provided by the RC Oscillator during the internal reset procedure. When the on-chip oscillator is stabilized, its clock output is multiplied by a fixed factor of two by the on-chip PLL. The clock from the PLL is then provided as the system clock. Thus, the system clock frequency is twice the external oscillator frequency. Figure 5-2 shows the power-on sequence under the control of the oscillator watchdog. Normally, devices in the 8051 family do not enter their default reset states before the on- chip oscillator starts. This is because the external reset signal must be internally synchronized and processed to bring the device into the correct reset state. The start up time of the oscillator can be relatively long, especially if a crystal is used (typically 10 ms). During this period, the pins have an undefined state which could have severe effects – especially to actuators connected to port pins. The Oscillator Watchdog unit in the C508 avoids this situation because its RC Oscillator starts working within a very short startup time after power-on (typically less than 2 µs). The on-chip oscillator that feeds the PLL has not started yet, and, thus, the PLL remains unlocked. As long as the PLL is not locked, the watchdog uses the RC Oscillator output as the clock source for the chip. This allows the part to be correctly reset and also brings all ports to the defined state (see Figure 5-2, II). The exception is Port 1 which is used as compare/capture outputs. These pins will be set to their default levels as soon as the external reset is active. This is illustrated in Figure 5-3. Under worst case conditions (fast VDD rise time - such as 1 µs, measured from VDD = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is: – Typ.: 18 µs – Max.: 34 µs The RC oscillator will already run at a VDD below 4.25 V (lower specification limit). Therefore, at slower VDD rise times, the delay time will be less than the two values given above. After the on-chip oscillator has started ( Figure 5-2, III) and the PLL is locked, the Oscillator Watchdog detects the correct function. Then, the watchdog continues to hold the reset active for a time period of 768 cycles (maximum) of the RC oscillator clock to ensure that a stable clock is available from the PLL (Figure 5-2, IV). Subsequently, the system clock is supplied by the PLL and the oscillator watchdog ’s reset is released (Figure 5-2, V). However, an externally applied reset still remains active and the device does not start program execution before the external reset is also released (Figure 5-2, VI).

Reset and System Clock Operation User’s Manual 5-4 2001-05 Figure 5-2 Power-On Reset of the C508 MCD04031 Ports (except P1) VDD On-chip Osc. PLL RC Osc. RESET RESET I II III IV V VI Power On undef. Port typ. 18 µs max. 34 µs Clock from RC-Oscillator, Reset at Ports, PLL starts with base frequency but still unlocked On- Chip Osc starts PLL locks; Final Reset Sequence by Osc.WD; (max. 768 RC Clock Cycles) Port remains in Reset because of active ext. Reset Signal Start of program execution undef.

Reset and System Clock Operation User’s Manual 5-6 2001-05

5.3 Hardware Reset Timing

This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in State 5 Phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level), the internal reset procedure is started. It needs two complete machine cycles to put the complete device into its correct reset state. In that state, all special function registers contain their default values, the port latches contain ‘1’s, etc. Note that this reset procedure is also performed if there is no clock available to the device. (This is done by the Oscillator Watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least two machine cycles; after this time, the C508 remains in its reset state as long as the signal is active. When the signal goes inactive, this transition is recognized in the following State 5 Phase 2 of the machine cycle. Then, the processor starts its address output (when configured for external ROM) in the following State 5 Phase 1. One phase later (State 5 Phase 2) the first falling edge at pin ALE occurs. Figure 5-4 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE, there is a time period of at least one machine cycle but less than two machine cycles. Figure 5-4 CPU Timing after Reset MCT02092 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 P1 P2 PCL OUT PCH OUT PCH OUT One Machine Cycle RESET ALE Inst. in OUT PCL

Reset and System Clock Operation User’s Manual 5-7 2001-05

5.4 Clock Generation

The top-level view of the system clock generation of the C508 is shown in Figure 5-5. Figure 5-5 Block Diagram of the Clock Generation The clock generation block consists of the RC oscillator, the on-chip oscillator, and the PLL. At power-on reset, the RC oscillator takes a shorter time to start in comparison to the on- chip oscillator (typically 2 µs versus 10 ms). While the on-chip oscillator is still unstable, the PLL remains unlocked. Thus, the RC clock is provided as the system clock. When the on-chip oscillator has stabilized, the PLL locks within 1 ms, providing a clock frequency twice that of the on-chip oscillator ’s frequency. The system clock source is now switched to the PLL clock. External reset from the pin should be released only after this stage.

5.5 PLL Operation

Within 1 ms after stable oscillations of the input clock within the specified frequency range, the PLL will be synchronous with this clock at a frequency twice that of the input frequency. In other words, the PLL locks onto its input clock. Since the PLL constantly adapts to the external clock to remain locked, the CPU clock generated has a slight variation known as jitter. This jitter is irrelevant for longer time periods. For short periods (one to four CPU clock cycles), it remains below 4%. When the PLL detects a missing input clock signal, it releases the lock signal. Consequently, an internal reset will be active until the PLL is locked again. This may occur if the input clock is unstable or fails completely; for example, due to a broken crystal. In this case, an Oscillator Watchdog reset will also occur. MCB04033 Control Logic PLL Clkout Lock ClkinFreq Comp. Lock System Clock RC Osc On-Chip Osc fRC or fOSC fRC fOSCXTAL1 XTAL2 fPLL

Reset and System Clock Operation User’s Manual 5-8 2001-05 When software power-down mode is entered, the PLL is powered down together with the RC oscillator and the on-chip oscillator. In this mode, the PLL is marked unlocked; however, no internal resets will be generated.

5.6 Oscillator and Clock Circuit

XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components such as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states, and machine cycles. Figure 5-6 shows the recommended oscillator circuit. Figure 5-6 Recommended Oscillator Circuit In this application, the on-chip oscillator is used as a crystal-controlled, positive- reactance oscillator. (A more detailed schematic is given in Figure 5-7). The on-chip oscillator is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. In this circuit, 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. It is recommended that the manufacturer of the ceramic resonator be consulted for value specifications of these capacitors. MCS04034 XTAL1 C508 XTAL2 5-10 MHz C C C = 20 pF + 10 pF for crystal operation (incl. Stray Capacitance) Crystal Oscillator Mode XTAL1 XTAL2 External Oscillator Signal N.C. Driving from External Source

On-Chip Peripheral Components User’s Manual 6-1 2001-05

6 On-Chip Peripheral Components

This chapter provides detailed information about all on-chip peripherals of the C508 except for the integrated interrupt controller, which is described separately in Chapter 7.

6.1 Parallel I/O

The C508 has one 8-bit analog or digital input port and five 8-bit I/O ports. Port 4 is a uni- directional input port. Port 0 is an open-drain bi-directional I/O port; Ports 1, 2, 3, and 5 are quasi-bi-directional I/O ports with internal pull-up transistors. This means that when these ports are configured as inputs, they will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of Ports 0 and 2 and the input buffers of Port 0 are also used for accessing external memory. In this application, Port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue emitting the P2 SFR contents. In this function, Port 0 is not an open-drain port, but uses a strong internal pull-up FET. Port 4 provides the analog input channels to the A/D Converter.

6.1.1 Port Structures

The C508 generally allows digital I/O on 32 lines grouped into four bi-directional 8-bit ports and analog/digital input on one unidirectional 8-bit port. Except for Port 4 which is the uni-directional input port, each port bit consists of a latch, an output driver, and an input buffer. Read and write accesses to the I/O Ports P0-P5 (except P4) are performed via their corresponding Special Function Registers. When Port 4 is used as analog input, an analog channel is switched to the A/D Converter through a 3-bit multiplexer, which is controlled by three bits in SFR ADCON (see Chapter 6.5). Port 4 lines may also be used as digital inputs. In this case, they are addressed as an input port via SFR P4. Since Port 4 has no internal latch, the contents of SFR P4 only depend on the levels applied to the input lines. It makes no sense to output a value to this input-only port by writing to the SFR P4. This will have no effect. The parallel I/O ports of the C508 can be grouped into four different types which are listed in Table 6-1.

On-Chip Peripheral Components User’s Manual 6-2 2001-05 Type A and B port pins are standard C501 compatible I/O port lines which can be used for digital I/O. Type A port (Port 0) is also designed for accessing external data or program memory. Type B port lines are located at Port 2, Port 3, and Port 5 to provide alternate functions for the serial interface, LED drive interface, and PWM signals; or are used as control outputs during external data memory accesses. Type C port (Port 4) provides the analog input port. Type D port lines can be switched to push-pull drive capability when they are used as compare outputs of the CAPCOM unit. As already mentioned, Port 1, 3, and 5 are provided for multiple alternate functions. These functions are listed in Table 6-2: Table 6-1 C508 Port Structure Types Type Description A Standard digital I/O ports which can also be used for external address/data bus. B Standard multifunctional digital I/O port lines. C Digital/analog uni-directional input port. D Standard digital I/O with push-pull drive capability.

On-Chip Peripheral Components User’s Manual 6-3 2001-05 Table 6-2 Alternate Functions of Ports 1, 3 and 5 Port Alternate Function Port Type Function P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 COUT3 CTRAP CC0 COUT0 CC1 COUT1 CC2 COUT2 RxD TxD INT0 INT1 WR RD T2CC0 / INT3 T2CC1 / INT4 T2CC2 / INT5 T2CC3 / INT6 INT2 INT9 INT8 INT7 D D D D D D D D B B B B B B B B B B B B B B B B 10-bit compare channel output CCU trap input CAPCOM Channel 0 input/output CAPCOM Channel 0 output CAPCOM Channel 1 input/output CAPCOM Channel 1 output CAPCOM Channel 2 input/output CAPCOM Channel 2 output Serial port’s receiver data input (asynchronous) or data input/output (synchronous) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input External interrupt 1 input Timer 0 external counter input Timer 1 external counter input External data memory write strobe External data memory read strobe T2 Compare/Capture output 0/External interrupt 3 input T2 Compare/Capture output 1/External interrupt 4 input T2 Compare/Capture output 2/External interrupt 5 input T2 Compare/Capture output 3/External interrupt 6 input External interrupt 2 input External interrupt 9 input External interrupt 8 input External interrupt 7 input

On-Chip Peripheral Components User’s Manual 6-4 2001-05

6.1.2 Standard I/O Port Circuitry

Figure 6-1 is a functional diagram of a typical bit latch and I/O buffer which make up the core of each of the five I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop which will clock in a value from the internal bus in response to a “write-to-latch” signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a “read-latch” signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a “read-pin” signal from the CPU. Some instructions that read from a port (that is, from the corresponding port SFR P0 to P4) activate the “read-latch” signal, while others activate the “read-pin” signal. Figure 6-1 Basic Structure of a Port Circuitry Q MCS04041 Read Latch Port Latch D CLK QInt. Bus Write to Latch Read Pin Port Pin Port Driver Circuit

On-Chip Peripheral Components User’s Manual 6-5 2001-05 The output drivers of Port 1, 2, 3, and 5 have internal pull-up FETs (see Figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1). This means for Figure 6-2, Q = 0, which turns off the output driver FET n1. Then, for Ports 1 to 5, except Port 4, the pin is pulled high by the internal pull-ups, but can be pulled low by an external source. When externally pulled low, the port pins source current ( IIL or ITL). For this reason, these ports are called “quasi-bi-directional”. Figure 6-2 Basic Output Driver Circuit of Ports 1, 2, 3, and 5 Q MCS04042 Read Latch Bit Latch D CLK QInt. Bus Write to Latch Read Pin VDD Port Pin Internal Pull Up Arrangement

On-Chip Peripheral Components User’s Manual 6-6 2001-05

6.1.2.1 Port 0 Circuitry

Port 0, in contrast to Ports 1 to 5, is considered a “true” bidirectional port because its pins float when configured as inputs. Thus, this port differs in not having internal pull-ups. The pull-up FET in the P0 output driver (see Figure 6-3) is used only when the port is emitting ‘1’s during the external memory accesses. Otherwise, the pull-up is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a ‘1’ to the port latch leaves both output FETs off and the pin floats. In this condition, it can be used as high-impedance input. If Port 0 is configured as a general I/O port and must emit logic high-level (1); then, external pull-ups are required. Figure 6-3 Port 0 Circuitry MUX MCS04043 Read Latch Bit Latch D CLK Q Q Int. Bus Write to Latch Read Pin VDD Port Pin Addr./ Data Control

On-Chip Peripheral Components User’s Manual 6-7 2001-05

6.1.2.2 Port 1, Port 3, and Port 5 Circuitry

The pins of Ports 1, 3, and 5 are multifunctional. They are port pins and also serve to implement special features as listed in Table 6-2. Figure 6-4 is a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR must contain a one (1); otherwise, the pull-down FET is on and the port pin is stuck at ‘0’. After reset, all port latches contain ones (1). Figure 6-4 Ports 1, 3, and 5 Circuitry MCS04044 Read Latch Bit Latch D CLK Q Q Int. Bus Write to Latch Read Pin Alternate Output Function VDD Port Pin Internal Pull Up Arrangement Alternate Input Function

On-Chip Peripheral Components User’s Manual 6-8 2001-05

6.1.2.3 Port 2 Circuitry

As shown in Figure 6-3 and in Figure 6-5, the output drivers of Ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application, these two ports cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P0/P2 SFR remains unchanged. As an address/data bus, Port 0 uses a pull-up FET as shown in Figure 6-3. When a 16-bit address is used, Port 2 uses the additional strong pull-ups p1 (Figure 6-5a) to emit ‘1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity. Figure 6-5 Port 2 Circuitry Port 0 can be used for I/O functions if no external bus cycles are generated using data or code memory accesses. MUX MCS04045 Read Latch Bit Latch D CLK Q Q Int. Bus Write to Latch Read Pin VDD Port Pin Internal Pull Up Arrangement Addr. Control

On-Chip Peripheral Components User’s Manual 6-9 2001-05 Figure 6-5a Port 2 Pull-up Arrangement Port 2 in I/O function works in a manner similar to the Type B port driver circuitry (Chapter 6.1.3.1); whereas, in address output function it works similar to Port 0 circuitry. MUX MCS04046 Q VDD Port Pin Addr. Control Delay

1 State

=1 =1 VSS Input Data (Read Pin)

On-Chip Peripheral Components User’s Manual 6-10 2001-05

6.1.3 Detailed Output Driver Circuitry

In fact, the pull-ups mentioned before and included in Figure 6-2, Figure 6-4, and Figure 6-5 are pull-up arrangements. The differences which apply to the various port types available in the C508 are described in the following sections.

6.1.3.1 Type B Port Driver Circuitry

Figure 6-6 shows the output driver circuit of the type B multifunctional digital I/O port lines. The basic circuitry of these ports is shown in Figure 6-4. The pull-up arrangement of type B port lines has one n-channel pull-down FET and three pull-up FETs: Figure 6-6 Driver Circuit of Type B Port Pins – The pull-down FET n1 is an n-channel type. It is a very strong driver transistor which is capable of sinking high currents ( IOL); it is only activated if a ‘0’ is programmed to the port pin. A short circuit to VDD must be avoided if the transistor is turned on, since the high current might destroy the FET. This also means that no ‘0’ must be programmed into the latch of a pin that is used as input. – The pull-up FET p1 is a p-channel type. It is activated for two oscillator periods (S1P1 and S1P2) if a 0-to-1 transition is programmed to the port pin; that is, a ‘1’ is programmed to the port latch which contained a ‘0’. The extra pull-up can drive a similar current as the pull-down FET n1. This provides a fast transition of the logic levels at the pin. – The pull-up FET p2 is a p-channel type. It is always activated when a ‘1’ is in the port latch, thus providing the logic high output level. This pull-up FET sources a MCS04047 Q VDD Port Pin =1 Delay =1 =1 VSS Input Data (Read Pin)

On-Chip Peripheral Components User’s Manual 6-11 2001-05 much lower current than p1; therefore, the pin may also be tied to ground, for example, when used as input with logic low input level. – The pull-up FET p3 is a p-channel type. It is activated only if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pull-up current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level; for example, when used as input. In this configuration, only the weak pull-up FET p2 is active, which sources the current IIL. If, in addition, the pull-up FET p3 is activated, a higher current can be sourced (ITL). Thus, additional power consumption can be avoided if port pins are used as inputs with a low level applied. However, the driving capability is stronger if a logic high level is output. The activating and deactivating of the four different transistors translates into four states possible for the pins: – Input low state (IL), p2 active only – Input high state (IH) = steady output high state (SOH) p2 and p3 active – Forced output high state (FOH), p1, p2 and p3 active – Output low state (OL), n1 active If a pin is used as input and a low level is applied, it will be in IL state; if a high level is applied, it will switch to IH state. If the latch is loaded with a ‘0’, the pin will be in OL state. If the latch holds a ‘0’ and is loaded with a ‘1’, the pin will enter FOH state for two cycles and then switch to SOH state. If the latch holds a ‘1’ and is reloaded with a ‘1’, no state change will occur. At the beginning of power-on reset, the pins will be in IL state (latch is set to ‘1’, voltage level on pin is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will remain in this state or will switch to IH (= SOH) state. If it is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3’s trip point after some time and p3 will turn on and provide a strong ‘1’. Note, however, that if the load exceeds the drive capability of p2 ( IIL), the pin might remain in the IL state and provide a week 1 until the first 0-to-1 transition occurs on the latch. Until this happens, the output level might stay below the trip point of the external circuitry. The same is true if a pin is used as a bi-directional line and the external circuitry is switched from output to input when the pin is held at ‘0’ and the load then exceeds the p2 drive capabilities. If the load exceeds IIL, the pin can be forced to ‘1’ by writing a ‘0’ followed by a ‘1’ to the port pin.

On-Chip Peripheral Components User’s Manual 6-12 2001-05

6.1.3.2 Type D Port Driver Circuitry

The driver and control structure of the port pins used for Compare output functions have a port structure which allows a true push-pull output driving capability (Type D). This output driver characteristic is only enabled/used when the corresponding port lines are used as Compare outputs. The push-pull port structure is illustrated in Figure 6-7. Figure 6-7 Driver Circuit of Type D Port Pins MCS04048 VDD Port Pin =1 Delay =1 =1 VSS Input Data (Read Pin) Enable Push-Pull Q

On-Chip Peripheral Components User’s Manual 6-13 2001-05

6.1.4 Port Timing

When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during Phase 1 of any clock period (during Phase 2 the output buffer holds the value it noticed during the previous Phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next Phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (that is: MOV A, P1), the port pin is actually sampled in State 5 Phase 1 or Phase 2, depending on the port and the alternative functions. Figure 6-8 illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an “edge”. For example, when used as counter input. In this case, an “edge” is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, certain requirements must be met on the pulse length of signals in order to avoid signal “edges” not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once. Figure 6-8 Port Timing MCT04049 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 Old Data New Data P1 active (driver transistor) Input sampled: e.g.: MOV A, P1 or XTAL2 Port

On-Chip Peripheral Components User’s Manual 6-14 2001-05

6.1.5 Port Loading and Interfacing

The output buffers of Ports 1 to 5, except Port 4 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be looked up in the DC characteristics in the Data Sheet of the C508. The corresponding parameters are VOL and VOH. The same applies to Port 0 output buffers. They do, however, require external pull-ups to drive floating inputs, except when being used as the address/data bus. When used as inputs, it must be noted that the Ports 1 to 5 (except Port 4) are not floating but have internal pull-up transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters ITL and IIL in the DC characteristics specify these currents). Port 0 however, has floating inputs when used for digital input.

On-Chip Peripheral Components User’s Manual 6-15 2001-05

6.1.6 Read-Modify-Write Feature of Ports 0 to 5 (Except Port 4)

Some port-reading instructions read the latch and others read the pin. The instructions reading the latch read a value, possibly change it, and then rewrite it to the latch. These are called “read-modify-write” instructions. They are listed in Table 6-3. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, respectively, is performed by reading the SFR P0, P2 and P3; for example, “MOV A, P3 ” reads the value from Port 3 pins, while “ANL P3, #0AAH” reads from the latch, modifies the value, and writes it back to the latch. It may not be obvious that the last three instructions in Table 6-3 are read-modify-write instructions, but they are. This is because they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch. Read-modify-write instructions are directed to the latch rather than the pin to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a ‘1’ is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor (approx. 0.7 V, that is, a logic low level!) and interpret it as ‘0’. For example, when modifying a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to the latch. However, reading the latch rater than the pin will return the correct value of ‘1’. Table 6-3 “Read-Modify-Write”-Instructions Instruction Function ANL Logic AND; for example: ANL P1, A ORL Logic OR; for example: ORL P2, A XRL Logic exclusive OR; for example: XRL P3, A JBC Jump if bit is set and clear bit; for example: JBC P1.1, LABEL CPL Complement bit; for example: CPL P3.0 INC Increment byte; for example: INC P4 DEC Decrement byte; for example: DEC P5 DJNZ Decrement and jump if not zero; for example: DJNZ P3, LABEL MOV Px.y, C Move carry bit to bit y of Port x CLR Px.y Clear bit y of Port x SETB Px.y Set bit y of Port x

On-Chip Peripheral Components User’s Manual 6-16 2001-05

6.2 Timers/Counters

The C508 contains three 16-bit timers/counters, Timer 0, Timer 1 and Timer 2. They are useful in many applications for timing and counting. In its “timer” function, the timer register is incremented every machine cycle. Thus, it can be thought of as counting machine cycles. Since a machine cycle consists of three oscillator periods, the counter rate is 1/3 of the oscillator frequency. In its “counter” function, the timer register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0 or T1 (alternate functions of P3.4 or P3.5 respectively). In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (six oscillator periods) to recognize a transition from 1-to-0, the maximum count rate is 1/6 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle.

6.2.1 Timer/Counter 0 and 1

Timer/counter 0 and 1 of the C508 are fully compatible with timer/counter 0 and 1 of the C501 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer. Timer/counter 1 in this mode holds its count. The effect is the same as setting TR1 = 0. External inputs INT0 and INT1 can be programmed to function as a gate for timer/ counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers: TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/counter 1. These may be combined into one timer configuration depending on the mode that is established. The functions of the timers are controlled by two Special Function Registers TCON and TMOD. In the following descriptions, the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of Timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for Timer 0. If not explicitly noted, this applies also to Timer 1.

On-Chip Peripheral Components User’s Manual 6-17 2001-05

6.2.1.1 Timer/Counter 0 and 1 Registers

Seven special function registers control the operation of timer/counter 0 and 1: – TL0/TH0 and TL1/TH1 – counter registers, low and high part – TCON and IEN0 – control and interrupt enable – TMOD – mode select Special Function Register TL0 (Address 8AH) Reset Value: 00 H Special Function Register TH0 (Address 8CH) Reset Value: 00 H Special Function Register TL1 (Address 8BH) Reset Value: 00 H Special Function Register TH1 (Address 8DH) Reset Value: 00 H Bit Function TLx.7-0 x=0 - 1 Timer/counter 0/1 low register THx.7-0 x=0 - 1 Timer/counter 0/1 high register .7 .6 .5 .48AH TL0 Bit No. 76543210 MSB LSB .3 .2 .1 .0 Operating Mode Description 0 “TLx” holds the 5-bit prescaler value. 1 “TLx” holds the lower 8-bit part of the 16-bit timer/counter value. 2 “TLx” holds the 8-bit timer/counter value. 3 TL0 holds the 8-bit timer/counter value; TL1 is not used. Operating Mode Description 0 “THx” holds the 8-bit timer/counter value. 1 “THx” holds the higher 8-bit part of the 16-bit timer/counter value. 2 “THx” holds the 8-bit reload value. 3 TH0 holds the 8-bit timer value; TH1 is not used.

On-Chip Peripheral Components User’s Manual 6-18 2001-05 Special Function Register TCON (Address 88H) Reset Value: 00 H Special Function Register IEN0 (Address A8H) Reset Value: 00 H Bit Function TF1 Timer 1 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR1 Timer 1 run control bit Set/cleared by software to turn timer/counter 1 ON/OFF. TF0 Timer 0 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR0 Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. ET1 Timer 1 overflow interrupt enable If ET1 = 0, the timer 1 interrupt is disabled. ET0 Timer 0 overflow interrupt enable If ET0 = 0, the timer 0 interrupt is disabled. 8FH 8EH 8DH 8CH 8BH 8AH 89H 88H TF1 TR1 TF0 TR088H TCON Bit No. 76543210 MSB LSB IE1 IT1 IE0 IT0 The shaded bits are not used for controlling timer/counter 0 and 1. AFH AEH ADH ACH ABH AAH A9H A8H EA WDT ET2 ES0A8H IEN0ET1 EX1 ET0 EX0

On-Chip Peripheral Components User’s Manual 6-19 2001-05 Special Function Register TMOD (Address 89H) Reset Value: 00 H Bit Function GATE Gating control When set, timer/counter “x” is enabled only while “INT x” pin is high and “TRx” control bit is set. When cleared timer “x” is enabled whenever “TRx” control bit is set. C/T Counter or timer select bit Set for counter operation (input from “Tx” input pin). Cleared for timer operation (input from internal system clock). Mode select bits Gate C/T M1 M089H TMOD Bit No. 76543210 MSB LSB Gate C/T M1 M0 Timer 1 Control Timer 0 Control M1 M0 Function 0 0 8-bit timer/counter: “THx” operates as 8-bit timer/counter “TLx” serves as 5-bit prescaler 0 1 16-bit timer/counter. “THx” and “TLx” are cascaded; there is no prescaler 1 0 8-bit auto-reload timer/counter. “THx” holds a value which is to be reloaded into “TLx” each time it overflows

11 T i m e r 0 :

TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1: Timer/counter 1 stops

On-Chip Peripheral Components User’s Manual 6-20 2001-05

6.2.1.2 Mode 0

Putting either Timer/counter 0 or Timer/counter 1 into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 6-9 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all ‘1’s to all ‘0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all eight bits of TH0 and the lower 5 bits of TL0. The upper three bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for Timer 0 as for Timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding Timer 1 signals in Figure 6-9. There are two different gate bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). Figure 6-9 Timer/Counter 0, Mode 0: 13-Bit Timer/Counter MCS04050 OSC ÷3 TL0 (5 Bits) =1 ≥1 P3.4/T0 P3.2/INT0 Gate TR0 Control C/T = 1 C/T = 0 TF0 InterruptTH0 (8 Bits) Pin Pin

On-Chip Peripheral Components User’s Manual 6-21 2001-05

6.2.1.3 Mode 1

Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 6-10. Figure 6-10 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter MCS04051 OSC ÷3 TL0 (8 Bits) =1 ≥1 P3.4/T0 P3.2/INT0 Gate TR0 Control C/T = 1 C/T = 0 TF0 InterruptTH0 (8 Bits) Pin Pin

On-Chip Peripheral Components User’s Manual 6-22 2001-05

6.2.1.4 Mode 2

Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 6-11. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. Figure 6-11 Timer/Counter 0, 1, Mode 2: 8-Bit Timer/Counter with Auto-Reload MCS04052 OSC ÷3 TL0 (8 Bits) =1 ≥1 P3.4/T0 P3.2/INT0 Gate TR0 Control C/T = 1 C/T = 0 TF0 Interrupt TH0 (8 Bits) Reload Pin Pin

On-Chip Peripheral Components User’s Manual 6-23 2001-05

6.2.1.5 Mode 3

Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3 on Timer 0 is shown in Figure 6-12. TL0 uses the Timer 0 control bits: C/T , Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in mode 3 and when TR1 is set, Timer 1 can be turned on by switching it to any mode other than 3 and off by switching it into its own mode 3, or can still be used by the serial channel as a baudrate generator, or in fact, in any application not requiring an interrupt from timer 1 itself. Figure 6-12 Timer/Counter 0, Mode 3: Two 8-Bit Timers/Counters MCS04053 OSC ÷3 TL0 (8 Bits) =1 ≥1 P3.4/T0 P3.2/INT0 Gate TR0 TR0 Control C/T = 1 C/T = 0 TF0 Interrupt Timer Clock TH0 (8 Bits) TF1 Interrupt TR1 Pin Pin

On-Chip Peripheral Components User’s Manual 6-24 2001-05

6.2.2 Timer/Counter 2 with Additional Compare/Capture/Reload

Timer 2 with additional Compare/Capture/reload features is one of the most powerful peripheral units of the C508. lt can be used for various digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. Timer 2 is designed to support various automotive control applications as well as industrial applications (frequency generation, digital-to-analog conversion, process control etc.). Please note that the functionality of this timer is not equivalent to the functionality of Timer 2 of the C501. The C508 Timer 2 used in combination with the Compare/Capture/reload registers allows the following operating modes: – Compare: Up to 4 PWM output signals with 65535 steps at maximum, and 300 ns resolution – Capture: Up to 4 high speed Capture inputs with 300 ns resolution – Reload: Modulation of timer 2 cycle time The block diagram in Figure 6-13 shows the general configuration of Timer 2 with the additional Compare/Capture/reload registers. The I/O pins which can be used for Timer 2 control are located as multifunctional port functions at Port 5 (see Figure 6-4). Table 6-4 Alternate Port Functions of Timer 2 Pin Symbol Function P5.0 / T2CC0 / INT3 Compare output/Capture input for CRC Register P5.1 / T2CC1 / INT4 Compare output/Capture input for CC Register 1 P5.2 / T2CC2 / INT5 Compare output/Capture input for CC Register 2 P5.3 / T2CC3 / INT6 Compare output/Capture input for CC Register 3

On-Chip Peripheral Components User’s Manual 6-25 2001-05 Figure 6-13 Timer 2 Block Diagram MCB04054 16-Bit Comparator T2CCL3/ T2CCH3 Input/ Output Control P5.0/ T2CC0/ INT3 16-Bit Comparator T2CCL2/ T2CCH2 16-Bit Comparator T2CCL1/ T2CCH1 16-Bit Comparator CRCL/ CRCH Capture Timer 2 TL2 TH2 Compare TF2 Reload Interrupt Request Reload ÷ 3 ÷ 6 OSC T2I0 = '1' and T2I1 = '0' T2PS P5.1/ T2CC1/ INT4 P5.2/ T2CC2/ INT5 P5.3/ T2CC3/ INT6

On-Chip Peripheral Components User’s Manual 6-26 2001-05

6.2.2.1 Timer 2 Registers

This section describes all Timer 2 related special function registers. The interrupt related SFRs are also included in this section. Table 6-5 summarizes the Timer 2 SFRs. The T2CON Timer 2 control register is a bit-addressable register which controls the Timer 2 function and the Compare mode of registers CRC, T2CC1 to T2CC3. Table 6-5 Special Function Registers of the Timer 2 Unit Symbol Description Address T2CON TL2 TH2 CCEN CRCL CRCH T2CCL1 T2CCH1 T2CCL2 T2CCH2 T2CCL3 T2CCH3 IEN0 IEN1 IRCON Timer 2 Control Register Timer 2, Low Byte Timer 2, High Byte Compare/Capture enable register Compare/Reload/Capture register, low byte Compare/Reload/Capture register, high byte Compare/Capture Register 1, Low Byte Compare/Capture Register 1, High Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, Low Byte Compare/Capture Register 3, High Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Control Register H CCH CDH C1H CAH CBH C2H C3H C4H C5H C6H C7H A8H B8H C0H

On-Chip Peripheral Components User’s Manual 6-27 2001-05 Special Function Register T2CON (Address C8H) Reset Value: 00 H Bit Function T2PS Prescaler select bit When set, Timer 2 is clocked with 1/6 of the oscillator frequency. When cleared, Timer 2 is clocked with 1/3 of the oscillator frequency. I3FR External interrupt 3 falling / rising edge flag Used for Capture function in combination with register CRC. If set, a Capture to register CRC (if enabled) will occur on a positive transition at pin P5.0/T2CC0/INT3 T2R1 T2R0 Timer 2 Reload enable T2CM Compare mode bit for registers CRC, T2CC1 through T2CC3 T2I1 T2I0 Timer 2 input selection CFH CEH CDH CCH CBH CAH C9H C8H T2PS I3FR I2FR T2R1C8H T2CON Bit No. 76543210 MSB LSB T2CM T2I1 T2I0 The shaded bits are not used for controlling Timer/counter 2. T2R0 T2R0 T2R1 Function 0 0 Reload disabled 0 1 Auto-Reload upon Timer 2 overflow (TF2) 1 X Prohibited. Do not use this combination. T2CM Function

0 Compare mode 0 is selected

1 Compare mode 1 is selected

0 0 No input selected, Timer 2 stops 1 0 Timer function: input frequency = fosc/3 (T2PS = 0) or fosc/6 (T2PS = 1) X 1 Prohibited. Do not use this combination.

On-Chip Peripheral Components User’s Manual 6-28 2001-05 Special Function Register TL2 (Address CCH) Reset Value: 00 H Special Function Register TH2 (Address CDH) Reset Value: 00 H Special Function Register CRCL (Address CAH) Reset Value: 00 H Special Function Register CRCH (Address CBH) Reset Value: 00 H Bit Function TL2.7-0 Timer 2 Value Low Byte The TL2 register holds the low byte of the 16-bit Timer 2 count value. TH2.7-0 Timer 2 Value High Byte The TH2 register holds the high byte of the 16-bit Timer 2 count value. CRCL.7-0 Reload Register Low Byte CRCL is the low byte of the 16-bit reload register of Timer 2. It is also used for Compare/Capture functions. CRCH.7-0 Reload Register High Byte CRCH is the high byte of the 16-bit reload register of Timer 2. It is also used for Compare/Capture functions. .7 .6 .5 .4CCH TL2 Bit No. 76543210 MSB LSB .3 .2 .1 LSB

On-Chip Peripheral Components User’s Manual 6-29 2001-05 Special Function Register IEN0 (Address A8H) Reset Value: 00 H Special Function Register IRCON (Address C0H) Reset Value: X0000000 B Bit Function ET2 Timer 2 Overflow/External Reload Interrupt Enable If ET2 = 0, the timer 2 interrupt is disabled. If ET2 = 1, the timer 2 interrupt is enabled. TF2 Timer 2 Overflow Flag Set by a timer 2 overflow and must be cleared by software. If the Timer 2 interrupt is enabled, TF2 = 1 will cause an interrupt. − TF2 IEX6 IEX5C0H IRCON Bit No. C7 H IEX4 IEX3 IEX2 IADC C6H C5H C4H C3H C2H C1H C0H The shaded bits are not used in Timer/counter 2 interrupt control. EA WDT ET2 ESA8H IEN0 Bit No. AF H MSB LSB ET1 EX1 ET0 EX0 AEH ADH ACH ABH AAH A9H A8H

On-Chip Peripheral Components User’s Manual 6-30 2001-05 Special Function Register CCEN (Address C1H) Reset Value: 00 H Bit Function COCAH3 COCAL3 Compare/Capture mode for CC register 3 COCAH2 COCAL2 Compare/Capture mode for CC register 2 COCAH3 COCAL3 COCAH2 COCAL2C1H CCEN Bit No. 76543210 MSB LSB COCAH1 COCAL1 COCAH0 COCAL0 COCAH3 COCAL3 Function 0 0 Compare/Capture disabled 0 1 Capture on rising edge at pin P5.3 / T2CC3 / INT6 1 0 Compare enabled 1 1 Capture on write operation into register CCL3 COCAH2 COCAL2 Function 0 0 Compare/Capture disabled 0 1 Capture on rising edge at pin P5.2 / T2CC2 / INT5 1 0 Compare enabled 1 1 Capture on write operation into register CCL2

On-Chip Peripheral Components User’s Manual 6-31 2001-05 COCAH1 COCAL1 Compare/Capture mode for CC register 1 COCAH0 COCAL0 Compare/Capture mode for CRC register Bit Function COCAH1 COCAL1 Function 0 0 Compare/Capture disabled 0 1 Capture on rising edge at pin P5.1 / T2CC1 / INT4 1 0 Compare enabled 1 1 Capture on write operation into register CCL1 COCAH0 COCAL0 Function 0 0 Compare/Capture disabled 0 1 Capture on falling/rising edge at pin P5.0 / T2CC0 / INT3 1 0 Compare enabled 1 1 Capture on write operation into register CRCL

On-Chip Peripheral Components User’s Manual 6-32 2001-05

6.2.2.2 Timer 2 Operation

Timer 2, which is a 16-bit-wide register, operates as a timer with its count rate derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/3 or 1/6 of the oscillator frequency. Thus, the 16-bit timer register (consisting of TH2 and TL2) is either incremented in every machine cycle or in every second machine cycle. The prescaler is selected by bit T2PS in special function register T2CON. lf T2PS is cleared, the input frequency is 1/3 of the oscillator frequency. If T2PS is set, the 2:1 prescaler gates 1/6 of the oscillator frequency to the timer. The timer overflow flag TF2 in SFR IRCON is set when there is a roll-over of the count from all ‘1’s to all ‘0’s. The flag TF2 can generate an interrupt and it must be cleared by the interrupt service routine.

On-Chip Peripheral Components User’s Manual 6-33 2001-05 Reload of Timer 2 The reload mode for Timer 2 is selected by bits T2R0 and T2R1 in SFR T2CON. To enable the reload mode, bit T2R0 must be cleared and bit T2R1 set. Figure 6-14 shows the configuration of Timer 2 in reload mode. When Timer 2 rolls over from all ‘1’s to all ‘0’s, it not only sets TF2 but also causes the Timer 2 registers to be loaded with the 16-bit value in the CRC registers, which are preset by software. The reload will happen in the same machine cycle in which TF2 is set, thus overwriting the count value 0000H. Figure 6-14 Timer 2 in Reload Mode MCS04055 TL2 TH2 TF2 Timer 2 Interrupt Request Reload Input Clock CRCL CRCH T2R0 = '0' and T2R1 = '1'

On-Chip Peripheral Components User’s Manual 6-34 2001-05

6.2.2.3 Compare Function of Registers CRC, T2CC1 to T2CC3

The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a Compare/Capture register is compared with the contents of the timer register. lf the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin, and an interrupt is requested. The contents of a compare register can be regarded as a “time stamp ” at which a dedicated output reacts in a predefined way (with either a positive or negative transition). Variation of this “time stamp” somehow changes the wave of a rectangular output signal at a port pin. As a variation of the duty cycle of a periodic signal, this may be used for pulse width modulation as well as for a continually controlled generation of any kind of square waveforms. Two Compare modes are implemented to cover a wide range of possible applications. The compare modes 0 and 1 are selected by bit T2CM in special function register T2CON. In both compare modes, the new value arrives at the port pin 1 within the same machine cycle in which the internal compare signal is activated. The four registers CRC, T2CC1 to T2CC3 are multifunctional as they additonally provide a capture, compare or reload capability (reload capability for CRC register only). A general selection of the function is done in register CCEN. Please note that the compare interrupt CC0 can be programmed to be negative or positive transition activated. The internal compare signal (not the output signal at the port pin!) is active as long as the timer 2 contents is equal to the one of the appropriate compare registers, and it has a rising and a falling edge. Thus, when using the CRC register, it can be selected whether an interrupt should be caused when the compare signal goes active or inactive, depending on bit I3FR in T2CON. For the CC registers 1 to 3 an interrupt is always requested when the compare signal goes active (see Figure 6-16).

6.2.2.3.1 Compare Mode 0

In mode 0, when the timer and compare register contents match, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the port will have no effect. Figure 6-15 shows a functional diagram of a port latch in compare mode 0. The port latch is directly controlled by the two signals timer overflow and compare. The input line from the internal bus and the write-to-latch line are disconnected when compare mode 0 is enabled. Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the inductance of a DC or AC motor). Mode 0 may also be used for providing output clocks with initially defined period and duty cycle. This is the mode which needs the least CPU time. Once set up, the output goes on oscillating without any

On-Chip Peripheral Components User’s Manual 6-36 2001-05 Figure 6-17 Function of Compare Mode 0

6.2.2.3.2 Modulation Range of a PWM Signal in Compare Mode 0

Generally, it can be said that for every PWM generation in compare mode 0 with n-bit wide compare registers there are 2n different settings for the duty cycle. Starting with a constant low level (0% duty cycle) as the first setting, the maximum possible duty cycle would then be: (1 - 1/2n) × 100% This means that a variation of the duty cycle from 0% to real 100% can never be reached if the compare register and timer register have the same length. There is always a spike which is as long as the timer clock period. This “spike” may either appear when the compare register is set to the reload value (limiting the lower end of the modulation range) or it may occur at the end of a timer period. This spike in CCx register configuration of timer 2 in compare mode 0 is divided into two halves. One half is at the beginning when the contents of the compare register are equal to the reload value of the timer and the other half is when the compare register is equal to the maximum value of the timer register (that is, FFFF H). Refer to Figure 6-18 where the maximum and minimum duty cycles of a compare output signal are illustrated. MCD04058 Contents of Timer 2 Timer Count = Reload Value Timer Count = FFFFH Timer Count = Compare Value Interrupt can be generated on overflow Compare Output (P5.x/T2CCx) Interrupt can be generated on compare-match

On-Chip Peripheral Components User’s Manual 6-37 2001-05 Timer 2 is incremented with every machine clock ( fOSC/6); thus, both these spikes are approximately 150 ns long at 20-MHz operational frequency. Figure 6-18 PWM Signal Modulation Range (generated with a Timer 2/CCx Register Combination in Compare Mode 0*) The following illustrates the calculation of The modulation range for a PWM signal. To calculate with reasonable numbers, a reduction of the resolution to 8-bit is used. Otherwise (for the maximum resolution of 16-bit) the modulation range would be so severely limited that it would be negligible. Example: Case: Timer 2 in auto-reload mode. Contents of reload register CRC = FF00 H Restriction of modulation range = 1 / (256 × 2) × 100% = 0.195% This leads to a variation of the duty cycle from 0.195% to 99.805% for a timer 2/CCx register configuration when 8 of the 16 bits are used. MCD04059 a) CCHx/CCLx = 0000H or = CRCH/CRCL (maximum duty cycle) P5.x H L Appr.1/2 Machine Cycle b) CCHx/CCLx = FFFFH (minimum duty cycle) P5.x H L Appr.1/2 Machine Cycle

On-Chip Peripheral Components User’s Manual 6-38 2001-05

6.2.2.3.3 Compare Mode 1

In compare mode 1, the software adoptively determines the transition of the output signal. lt is commonly used when output signals are not related to a constant signal period (as in a standard PWM Generation) but must be controlled very precisely with high resolution and without jitter. In compare mode 1, both transitions of a signal can be controlled. Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity. lf compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, one can choose whether the output signal is to make a new transition (1- to-0 or 0-to-1, depending on the actual pin level) or should keep its old value at the time the Timer 2 count matches the stored compare value. Figure 6-19 and Figure 6-20 show functional diagrams of the timer/compare register/ port latch configuration in compare mode 1. In this function, the port latch consists of two separate latches. The upper latch (which acts as a “shadow latch”) can be written under software control, but its value will only be transferred to the output latch (and thus to the port pin) in response to a compare match. Note that the double latch structure is transparent as long as the internal compare signal is active. While the compare signal is active, a write operation to the port will then change both latches. This may become important when driving Timer 2 with a slow external clock. In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch. A read-modify-write instruction will read the user-controlled “shadow latch” and write the modified value back to this “shadow-latch”. A standard read instruction will read the pin of the corresponding compare output, as usual.

On-Chip Peripheral Components User’s Manual 6-39 2001-05 Figure 6-19 Port Latch in Compare Mode 1 MCS04060 Port Latch D CLK Q Q VDD Port Pin Internal Bus Write to Latch Read Latch Read Pin Compare Register Circuit Compare Reg. Timer Circuit Timer Register Comparator 16-Bit 16-Bit Compare Match Shadow Latch D CLK Q Port Circuit

On-Chip Peripheral Components User’s Manual 6-40 2001-05 Figure 6-20 Timer 2 with Registers CCx in Compare Mode 1 MCS04061 I3FR IEXx Interrupt Shaded function for CRC only P5.3/ T2CC3/ INT6 P5.0/ T2CC0/ INT3 Port Latch Circuit Timer 2 TH2 TL2 Overflow Comparator Compare Signal Compare Register CCx 16-Bit 16-Bit Output Latch P5.7 Shadow Latch Interrupt ... (CCx stands for CRC, T2CC1 to T2CC3, IEXx stands for IEX3 to IEX6)

On-Chip Peripheral Components User’s Manual 6-41 2001-05

6.2.2.4 Using Interrupts in Combination with the Compare Function

The compare service of registers CRC, T2CC1, T2CC2 and T2CC3 are assigned to alternate output functions at port pins P5.0 to P5.3. Another option of these pins is that they can be used as external interrupt inputs. However, when using the port lines as compare outputs then the input line from the port pin to the interrupt system is disconnected (but the pin ’s level can still be read under software control). Thus, a change of the pin ’s level will not cause a setting of the corresponding interrupt flag. In this case, the interrupt input is directly connected to the (internal) compare signal thus providing a compare interrupt. The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next “compare match”. The principle is that the internal compare signal (generated at a match between timer count and register contents) not only manipulates the compare output but also sets the corresponding interrupt request flag. Thus, the current task of the CPU is interrupted if the priority of the Compare interrupt is higher than the present task priority and the corresponding interrupt service routine is called. This service routine then sets up all the necessary parameters for the next compare event. Advantages when Using Compare Interrupts First, there is no danger of unintentional overwriting a Compare register before a match has been reached. This could happen when the CPU writes to the compare register without knowing about the actual Timer 2 count. Second, and the most interesting advantage of the compare feature, is that the output pin is exclusively controlled by hardware; therefore, it is completely independent from any service delay which in real time applications could be disastrous. The compare interrupt in turn is not sensitive to such delays since it loads the parameters for the next event. This in turn is supposed to happen after a sufficient amount of time. Please note the following special case where a program using compare interrupts could show a “surprising” behavior. The configuration has already been mentioned in the description of compare mode 1. The fact that the compare interrupts are transition activated becomes important when driving Timer 2 with a slow external clock. In this case it should be carefully considered that the compare signal is active as long as the Timer 2 count is equal to the contents of the corresponding compare register, and that the compare signal has a rising and a falling edge. Furthermore, the “shadow latches” used in compare mode 1 are transparent while the compare signal is active. Thus, with a slow input clock for Timer 2, the comparator signal is active for a long time (i.e. high number of machine cycles) and therefore a fast interrupt controlled reload of the compare register could not only change the “shadow latch” - as probably intended - but also the output buffer.

On-Chip Peripheral Components User’s Manual 6-42 2001-05 When using the CRC, an interrupt should be generated when the compare signal goes active or inactive, depending on the status of bit I3FR in T2CON. Initializing the interrupt to be negative transition triggered is advisable in the above case. Then the compare signal is already inactive and any write access to the port latch changes only the contents of the “shadow-latch”. Note that for T2CC1 to T2CC3 registers, an interrupt is always requested when the compare signal goes active. The second configuration which should be noted is the compare function combined with negative transition activated interrupts. lf the port latch of Port P5.0 contains a ‘1’, the interrupt request flags IEX3 will immediately be set after enabling the compare mode for the CRC register. The reason is that first the external interrupt input is controlled by the pin’s level. When the compare option is enabled, the interrupt logic input is switched to the internal compare signal, which carries a low level when no true comparison is detected. So, the interrupt logic sees a 1-to-0 edge and sets the interrupt request flag. An unintentional generation of an interrupt during compare initialization can be prevented if the request flag is cleared by software after the compare is activated and before the external interrupt is enabled.

On-Chip Peripheral Components User’s Manual 6-43 2001-05

6.2.2.5 Capture Function

Each of the Compare/Capture registers T2CC1 to T2CC3 and the CRC register can be used to latch the current 16-bit value of the Timer 2 registers TL2 and TH2. Two different modes are provided for this function. In mode 0, an external event latches the Timer 2 contents to a dedicated capture register. In mode 1, a capture will occur upon writing to the low order byte of the dedicated 16-bit capture register. This mode allows the software to read the contents of Timer 2 “on-the-fly”. In mode 0, the external event causing a capture is: – For T2CC registers 1 to 3: a positive transition at pins T2CC1 to T2CC3 of Port 5 – For the CRC register: a positive or negative transition at the corresponding pin, depending on the status of the bit I3FR in SFR T2CON. lf the edge flag is cleared, a capture occurs in response to a negative transition. lf the edge flag is set, a capture occurs in response to a positive transition at pin P5.0 / T2CC0 / INT3 In both cases, the appropriate Port 5 pin is used as input and the port latch must be programmed to contain a one (1). The external input is sampled in every machine cycle. When the sampled input shows a low (high) level in one cycle and a high (low) in the next cycle, a transition is recognized. The Timer 2 contents are latched to the appropriate capture register in the cycle following the one in which the transition was identified. In mode 0: a transition at the external capture inputs of registers T2CC1 to T2CC3 will also set the corresponding external interrupt request flags IEX4 to IEX6. lf the interrupts are enabled, an external capture signal will cause the CPU to vector to the appropriate interrupt service routine. In mode 1: a capture occurs in response to a write instruction to the low order byte of a capture register. The write-to-register signal (example, write-to-CRCL) is used to initiate a capture. The value written to the dedicated capture register is irrelevant for this function. The Timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction. In this mode no interrupt request will be generated. Figure 6-21 illustrates the operation of the CRC register, while Figure 6-22 shows the operation of the Compare/Capture registers 1 to 3. The two capture modes can be established individually for each capture register by bits in SFR CCEN (Compare/Capture enable register). That means, in contrast to the compare modes, it is possible to simultaneously select mode 0 for one capture register and mode 1 for another register.

On-Chip Peripheral Components User’s Manual 6-45 2001-05

6.3 Capture/Compare Unit (CCU)

The Capture/Compare Unit (CCU) of the C508 has been designed for applications which demand digital signal generation and/or event capturing (such as pulse width modulation or pulse width measuring). It consists of a 16-bit three-channel Capture/Compare unit (CAPCOM) and a 10-bit one-channel Compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non-overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. For motor control applications, both units (CAPCOM and COMP) may generate versatile multichannel PWM signals. For brushless DC motors, dedicated control modes are supported which are controllable by either software or hardware (hall sensors). Figure 6-23 Capture/Compare Unit Block Diagram Control CC Channel 0 (CCH0, CCL0) CC Channel 1 (CCH1, CCL1) CC Channel 2 (CCH2, CCL2) MCB04064 Prescaler Offset Register (CT1OFH,CT1OFL) Compare Timer 1 (16-Bit) Period Register (CCPH, CCPL) Mode Select Register (CMSEL0, CMSEL1) Trap/Initialization Registers (COINI, COTRAP , TREN) Port Control Logic Cntrl. Register (CT1CON) 16-Bit Capture/Compare Unit (CAPCOM) CC0 COUT0 CC1 COUT1 CC2 COUT2 2fOSC Compare Reg. (CMP2H, CMP2L) Prescaler Compare Timer 2 (10-Bit) Period Register (CP2H, CP2L) Cntrl. Register (CT2CON) 10-Bit Compare Unit (COMP) 2fOSC Block Commutation Control (BCON) INT0 INT1 INT2 COUT3 CTRAP

On-Chip Peripheral Components User’s Manual 6-46 2001-05

6.3.1 General Capture/Compare Unit Operation

The Compare Timer 1 and 2 are free running, processor clock coupled 16-bit/10-bit timers; each of which has a count rate with a maximum of 2 fOSC up to fOSC/64. The compare timer operations with its possible compare output signal waveforms are shown in Figure 6-24. Figure 6-24 CAPCOM Unit Basic Operating Modes MCD04065 0000H CCx COUTx Compare Value Period Value a) Standard PWM (Edge Aligned) Offset { CCx COUTx Compare Value Period Value Standard PWM (Single Edge Aligned) with programmable dead time (tOFF) Compare Timer 1 Operating Mode 0 0000H CCx COINI=0 COUTx COINI=1 Compare Value Period Value c) Symmetrical PWM (Center Aligned) Compare Timer 1 Operating Mode 1 CCx COINI=0 COUTx COINI=1 Compare Value Period Value Symmetrical PWM (Center Aligned) with programmable dead time (tOFF) Offset { tOFF tOFF : Interrupt can be generated tOFF

On-Chip Peripheral Components User’s Manual 6-47 2001-05 Both compare timers start counting from 0000 H upwards to a count value stored in the period registers. If the value stored in the period register is reached, they are reset (operating mode 0, both compare timers) or the count direction is changed from up- counting to down-counting (operating mode 1, only Compare Timer 1) Using operating mode 0, edge aligned PWM signals can be generated. Using operating mode 1, center aligned PWM signals can be generated. Compare Timer 1 can be programmed for both operating modes while Compare Timer 2 always works in operating mode 0 with one output signal COUT3. Figure 6-24 a) and c) show the function of these basic operating modes. Compare Timer 1 has an additional 16-bit offset register, which consists of the high byte stored in CT1OFH and the low byte stored in CT1OFL. If the value stored in CT1OFF is 0, the compare timer operates as shown in Figure 6-24 a) and c). If the value stored in CT1OFF is not zero, the compare timer operates as shown in Figure 6-24 b) and d). In operating mode 0, Compare Timer 1 is always reset after its value has been equal to the value stored in period register. In operating mode 1, the count direction of the compare timer is changed from up- to down-counting when its value has reached the value stored in the period register. The count direction is changed from down- to up-counting when the compare timer value has reached 0000 H. Generally, the compare outputs CCx are always assigned to a match condition with the compare timer value directly, where as the compare outputs COUTx are assigned to a match condition with the compare timer value plus the offset value. Therefore, signal waveforms with non-overlapping signal transitions as shown in Figure 6-24 b) and d) can be generated. Further, the initial logic output level of the CAPCOM channel outputs can be selected in compare mode. This allows waveforms to be generated with inverting signal polarities. In capture mode of the CAPCOM unit, the value of Compare Timer 1 is stored in the capture registers on a signal transition at pins CCx. The compare unit COMP is a 10-bit compare unit which can be used to generate a Pulse Width Modulated signal. This PWM output signal drives the output pin COUT3. In burst mode and in the PWM modes, the output of the COMP unit can be switched to the COUTx outputs. The block commutation control logic allows to generate versatile multi-channel PWM output signals. In one of these modes, the block commutation mode, signal transitions at the three external interrupt inputs are used to trigger the PWM signal generation logic. Depending on these signal transitions, the six I/O lines of the CAPCOM unit, which are decoupled in block commutation mode from the three Capture/Compare channels, are driven as static or PWM modulated outputs. CAPCOM channel 0 can be used in block commutation mode for a capture operation (speed measurement) which is triggered by each transition at the external interrupt inputs. Further, the multi-channel PWM mode signal generation can be also triggered by the period of Compare Timer 1. These operating modes are referenced as multi-channel PWM modes.

On-Chip Peripheral Components User’s Manual 6-48 2001-05 Using the CTRAP input signal of the C508, the compare outputs can be put immediately into their state as defined in COTRAP register. The CCU unit has four main interrupt sources with their specific interrupt vectors. Interrupts can be generated at the Compare Timer 1 period match or count-change events, at the Compare Timer 2 period match event, at a CAPCOM Compare match or Capture event, and at a CAPCOM emergency event. An emergency event occurs if an active CTRAP signal is detected or if an error condition in block commutation mode is detected. All interrupt sources can be enabled/disabled individually.

On-Chip Peripheral Components User’s Manual 6-49 2001-05

6.3.2 CAPCOM Unit Operation

6.3.2.1 CAPCOM Unit Clocking Scheme

The CAPCOM unit is controlled by the 16-bit Compare Timer 1. Compare Timer 1 is the timing base for all compare and capture capabilities of the CAPCOM unit. The input clock for Compare Timer 1 is directly coupled to the system clock of the C508. Its frequency can be selected via three bits of the CT1CON register in a range of 2 fOSC up to fOSC/64. For the understanding of the following timing diagrams, Figure 6-25 shows the internal clocking scheme of the CAPCOM unit. The internal input clock of the CAPCOM unit is a symmetrical clock with 50% duty cycle. The clock transitions (edges) of the CAPCOM internal input clock are used for different actions. At clock edge 1, the Compare Timer 1 is clocked to the next count value and with clock edge 2, the compare outputs CCx and COUTx are toggled/set to the new logic level if required. Figure 6-25 CAPCOM Unit Clocking Scheme Generally, the CAPCOM clocking scheme shown above is also valid for the COMP (Compare Timer 2) unit. MCD04066 2fOSC 1 2 fOSC fOSC/2 fOSC/4 Input clock of CT1 1 2 1 2 1 2 min. 50 ns (@ 10 MHz oscillator clock) 1 increment/decrement of compare timer 1 2 change/modify logic level at CCx/COUTx

On-Chip Peripheral Components User’s Manual 6-50 2001-05

6.3.2.2 CAPCOM Unit Operating Mode 0

Figure 6-26 shows the details of the CAPCOM unit timing in operating mode 0. Figure 6-26 Compare Timer 1 Mode 0 In the example above, Compare Timer 1 counts from 0000 H up to 0007H (value stored in CCPH/CCPL). The offset registers CT1OFH/CT1OFL have a value of 0000 H. If programmed in compare mode, two output signals (CCx and COUTx) are assigned to the related CAPCOM channel x. The mode select bits in the SFRs CMSEL0 and MCT04067 Time CT1 Value CCP = 7 Period Reg. Offset Reg. CT1OFF = 0 Start of CT1 (CC = 0) (CC = 1) (CC = 4) (CC ≥ 7) (CC = 0) (CC = 1) (CC = 4) (CC ≥ 7) 100% Duty Cycles: 87.5% 50% 100% 87.5% 50% CCx or COUTxCOINI bit is "0" (active high signals) CCx or COUTxCOINI bit is "1" (active low signals) "0" "1" CC CCP CC1O : content of the CCxH/CCxL compare registers : content of the CCPH/CCPL period register : content of the CT1OFH/CT1OFL offset register

On-Chip Peripheral Components User’s Manual 6-51 2001-05 CMSEL1 define which of these two outputs will be controlled by the CAPCOM channel. In Figure 6-26 only the CCx signal is shown, but the same or the inverted waveform can be generated at the COUTx outputs. After reset all CCx/COUTx pins are at high level, driven by a weak pull-up. With the programming of the CMSEL1 or CMSEL0 registers, all affected compare outputs are switched to push-pull mode and start driving an initial level which is defined by the bits in SFR COINI. In Figure 6-26, the upper five waveforms are assigned to a CCx pin with the appropriate bit in COINI cleared while the lower five waveforms are assigned to a CCx pin with the appropriate bit in COINI set. When the count value of the Compare Timer 1 is incremented and the new value matches the value stored in the corresponding compare register, the related compare output changes its logic state. When the compare timer is reset to 0000 H the related compare output changes its logic state again. With the scheme shown in Figure 6-26, output waveforms with duty cycles between 0% and 100% can be generated. For a compare register value of 0000H, the output will remain at high level (COINI bit = 0) or low level (COINI bit = 1), representing a duty cycle of 100%. If the value stored in the compare register is greater than or equals to the value of the period register, a low level (COINI bit = 0) or high level (COINI bit = 1) corresponds to a duty cycle of 0%. Figure 6-27 shows the waveform generation in operating mode 0 when the offset register has a value which is not equal 0000 H (example: CT1OFH/CT1OFL = 0002 H). Using Compare Timer 1 with an offset value not equal 0 is used to generate single edge aligned signals with a constant delay between one of the two signal transitions. Compare Timer 1 always counts from 0000H up to the value stored in CCP, if the value in the offset register is not equal 0. With reset (count value 0000 H) of the Compare Timer 1, the CCx and COUTx will always change their logic state. During the up-counting phase, CCx will change the logic state when the compare timer value is equal to the compare register value; and COUTx will change the logic state when the compare timer value plus the offset value matches the value stored in the compare register. In Figure 6-27 the waveforms a) and b) show an example for a waveform of two signals with a constant delay of their rising edge. A compare register value of 3 is assumed. Using inverted signal polarity (SFR COINI), signal c) can be generated at COUTx. If the value in the offset register plus the value of the period register is less than or equal to the value stored in the compare register, a static ‘1’ or a static ‘0’ (depending on COINI content) will be generated at COUTx (see Figure 6-27 d) and e)). Therefore, CCx will also stay at a static level if the compare register value is greater than the value stored in the period register.

On-Chip Peripheral Components User’s Manual 6-52 2001-05 Figure 6-27 Compare Timer 1 with Offset not equal 0 – Mode 0 MCT04293 Offset Reg. CT1OF = 2 CCP = 7 Period Reg. CT1+CT1OFF CT1 CT1 Start of CT1 CCx COUTx COUTx COUTx COUTx t OFF OFF t t OFF "0" 0% 100% content of the CCxH/CCxL compare registers content of the CCPH/CCPL period register: CCP CC Count Value Time PinCOINICC > CT1OF + CCP CT1OF= CT1OF : content of the CT1OFH/CT1OFL offset registers

On-Chip Peripheral Components User’s Manual 6-53 2001-05

6.3.2.3 CAPCOM Unit Operating Mode 1

Using Compare Timer 1 in operating mode 1, two symmetric output signals with constant dead time tOFF at each signal transition can be generated per channel. Figure 6-28 shows the operating mode 1 timing in detail. Figure 6-28 Compare Timer 1 with Offset not equal to 0 - Mode 1 In the example above, Compare Timer 1 counts from 0000 H up to 0007H (value stored in period register CCPH/CCPL) and then counts down again to 0000 H. The maximum and minimum (0000H) values of the Compare Timer 1 always occur once in the count value sequence. In the example shown in Figure 6-28, the offset registers have a value of 0002H. With the programming of the CMSEL1 or CMSEL0 registers, all affected compare outputs are switched to push-pull mode and start driving an initial level defined by the bits in SFR COINI. In operating mode 0, two compare output signals, CCx and COUTx, are assigned to the related CAPCOM channel. The compare outputs CCx change their state if a match of Compare Timer 1 content and the corresponding compare register occurs. The compare outputs COUTx change their state when a match of Compare Timer 1 content plus the value stored in the offset registers and the corresponding compare register has occurred. If the value in the offset register plus the value of the period register is less than or equal to the value stored in the compare register, a static ‘1’ or a static ‘0’ (depending MCT04294 CT1+CT1OFF CT1 Time Count Value Period Reg. CCP = 7 CT1OF = 2 Offset Reg. Start of CT1 COINI Bit = 0 CCx (CC = 5) COUTx (CC = 5) COINI Bit = 0 COINI Bit = 1 COUTx (CC = 5) t OFF t OFF t OFF 57% 57% 29% Duty Cycles: CC CCP : content of the CCPH/CCPL period register content of the CCxH/CCxL compare registers CT1OF : content of the CT1OFH/CT1OFL offset registers

On-Chip Peripheral Components User’s Manual 6-54 2001-05 on COINI content) will be generated at COUTx. In the same way, CCx will also stay at a static level if the compare register value is greater than the value stored in the period register.

6.3.2.4 CAPCOM Unit Timing Relationships

Depending on the operating mode of the Compare Timer 1, compare output signals can be generated with a maximum period and resolution as shown in Figure 6-29. This example also demonstrates the reloading of the compare and period registers which occurs when Compare Timer 1 reaches the count value 0000

On-Chip Peripheral Components User’s Manual 6-56 2001-05 Compare Timer 1 period and duty cycle values can be calculated using the formulas given below. Following abbreviations are used. pv = period value, stored in the period registers CCPH/CCPL ov = offset value, stored in the offset registers CT1OFH/CT1OFL cv = compare value, stored in the Capture/Compare registers CCHx/CCLx Operating Mode 0: Operating Mode 1: Table 6-6 Resolution and Period of the Compare Timer 1 (at fOSC = 10 MHz) Compare Timer 1 Input Clock Operating Mode 0 Operating Mode 1 Resolution Period Resolution Period 2 fOSC fOSC fOSC / 2 fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 fOSC / 64 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 µs 3.2 µs 6.4 µs 100ns - 3.28 ms 200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms 1.6 µs - 52.43 ms 3.2 µs - 104.86 ms 6.4 µs - 209.72 ms 12.8 µs - 419.43 ms 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 µs 3.2 µs 6.4 µs 200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms 1.6 µs - 52.43 ms 3.2 µs - 104.86 ms 6.4 µs - 209.71 ms 12.8 µs - 419.42 ms 25.6 µs - 838.85 ms Period value = pv + 1 Duty cycle of CCx outputs = 1 _ cv pv + 1 × 100% Duty cycle of COUTx outputs = 1 _ cv - ov pv + 1 × 100% Period value = 2 × pv Duty cycle of CCx outputs = 1 _ cv pv × 100% Duty cycle of COUTx outputs = 1 _ cv - ov pv × 100%

On-Chip Peripheral Components User’s Manual 6-57 2001-05

6.3.2.5 Burst Mode of CAPCOM / COMP Unit

In burst mode, both units of the CCU are combined in a way that the CAPCOM outputs COUTx or CCx and COUTx (controlled by bit BCMP in SFR BCON) are modulated by the output signal of the COMP unit. Using the burst mode, the CAPCOM unit operates in compare mode and the COMP unit provides a PWM signal which is switched to the COUTx outputs. This PWM signal typically has a higher frequency than the compare output signal of the CAPCOM unit. Figure 6-30 shows the waveform generation using the burst mode. Figure 6-30 Burst Mode Operation MCT04295 Time Count Value Period Register Register Compare Compare Timer 1 (CT1OFF = 0) Start of CT1 COUTx =(COINI = 1) (COINI = 0) COUTx Compare Timer 2 COUT3 (COINI = 1) COUTx COUTx (COINI = 0) CMSELx3 = 0 Burst Mode Disabled COUTXI = 0 COUT3I = 0 COUT3I = 0 COUTXI = 1 COUT3I = 1 COUTXI = 1 COUT3I = 1 COUTXI = 0 Note: If the Bits COUT3I and COUTXI in the COINI register are identical, COUT3 and the burst signals at COUTx have the same polarity.

On-Chip Peripheral Components User’s Manual 6-58 2001-05 Burst mode of a COUTx output is enabled by the bit CMSELx3, located in the mode select registers CMSEL0 and CMSEL1. Figure 6-30 shows four CAPCOM output signals with different initial logic states with burst mode disabled (CMSELx3 = 0) and burst mode enabled (CMSELx3 = 1). Generally, the CCx outputs cannot operate in burst mode. Optionally, the signal at COUTx may have inverted polarity than the PWM signal which is available at pin COUT3. Depending on the corresponding initial compare output level bit in COINI, either a low or high level for the non-modulated state at the COUTx pins can be selected. Burst mode can be enabled in both operating modes of the Compare Timer 1. The burst mode as shown in Figure 6-30 is only valid if the block commutation mode of the CCU is disabled (bit BCEN of SFR BCON cleared). Modulation of the compare output signals at COUTx is switched on (COUT3 signal is switched to COUTx) when the Compare Timer 1 contents plus the value stored in the Compare Timer 1 offset register are equal to or greater than the value stored in the compare register of CAPCOM channel x.

6.3.2.6 CAPCOM Unit in Capture Mode

The three channels of the CAPCOM unit can be individually programmed to operate in capture mode. In capture mode, each CAPCOM channel offers one capture input at pin CCx. Compare Timer 1 runs either in operating mode 0 or 1. A rising or/and falling edge at CCx will copy the actual value of the Compare Timer 1 into the Compare/Capture registers. Interrupts can be generated selectively at each transition of the capture input signal. Capture mode is selected by writing the mode select registers CMSEL1 and CMSEL0 with the appropriate values. The bit combinations in CMSEL0 and CMSEL1 also define the signal transition type (falling/rising edge) which generates a capture event. If a CAPCOM channel is enabled for capture mode, its CCx input is sampled with 1/(4 TCL) (i.e. 2 fOSC = twice external oscillator clock rate). Consecutive capture events, generated through signal transitions at a CCx capture input, overwrite the corresponding 16-bit Compare/Capture register contents. This must be considered when successive signal transitions are processed.

On-Chip Peripheral Components User’s Manual 6-59 2001-05

6.3.2.7 Trap Function of the CAPCOM Unit in Compare Mode

When a channel of the CAPCOM unit operates in compare mode, its output lines can be decoupled in trap mode from the CAPCOM pulse generation. The trap mode is controlled by the external signal CTRAP . The CTRAP signal is sampled at each phase of the oscillator clock cycle. If a low is detected, the trap flag TRF of register TRCON is set and CCx or COUTx compare outputs are switched immediately to the logic state as defined by the bits in COTRAP if that particular channel has been enabled for trap function. The compare outputs of the channels which are not enabled for trap function will have their last output levels maintained. For safety reasons, it is recommended that trap function be enabled. If CT1RES = 0, Compare Timer 1 continues its operation but no compare output signal will be generated. If CT1RES = 1, Compare Timer 1 is reset when CTRAP becomes active. When CTRAP is sampled inactive (high) again, the compare channel outputs are synchronously switched to the compare channel output signal generation when Compare Timer 1 has reached the count value 0000H. The trap function is controlled by bits in the TRCON register. The general enable function of the external CTRAP signal is controlled by one bit (TRPEN). Further, each CAPCOM compare channel output can be enabled/disabled selectively for trap function. Figure 6-31 shows the trap function for the two outputs CCx and COUTx of one compare channel x. The timing diagram implies that the trap function is enabled at the CCx and COUTx outputs. At reference point 1) in Figure 6-31 CTRAP becomes active and at reference point 2) the trap state is released again synchronously to the Compare Timer 1 count state 0000H. If the trap function is enabled and CTRAP becomes active, bit TRF (trap flag) in SFR TRCON is set and a CCU emergency interrupt will be generated if the related interrupt enable bits are set. The flag TRF is level sensitive and must be cleared by software. The trap function used in block commutation mode differs from the trap function described above. In particular, the synchronization scheme is different (see Chapter 6.3.4.6).

On-Chip Peripheral Components User’s Manual 6-60 2001-05 Figure 6-31 Trap Function of the CAPCOM Unit MCT04296 a) Trap Function in CAPCOM Operating Mode 0 Period Value Compare Value Offset CT1+CT1OFF CT1 Trap State Trap State CCx COUTx CTRAP b) Trap Function in CAPCOM Operating Mode 1 CT1+CT1OFF CT1 Trap State Period Value Compare Value Offset CCx COUTx CTRAP Trap State Note: The state of the CCx and COUTx signals in trap state is defined by the corresponding bits in COTRAP

On-Chip Peripheral Components User’s Manual 6-61 2001-05

6.3.2.8 CAPCOM Registers

The CAPCOM unit of the C508 contains several special function registers. Table 6-7 provides an overview of the CAPCOM related registers. The following sections describe the CAPCOM registers in detail. Table 6-7 Special Function Registers of the CAPCOM Unit Unit Symbol Description Address CAPCOM Capture / Compare Unit CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE COINI TRCON COTRAP Compare Timer 1 Control Register Compare Timer 1 Period Register, Low Byte Compare Timer 1 Period Register, High Byte Compare Timer 1 Offset Register, Low Byte Compare Timer 1 Offset Register, High Byte Capture/Compare Mode Select Register 0 Capture/Compare Mode Select Register 1 Capture/Compare Register 0, Low Byte Capture/Compare Register 0, High Byte Capture/Compare Register 1, Low Byte Capture/Compare Register 1, High Byte Capture/Compare Register 2, Low Byte Capture/Compare Register 2, High Byte Capture/Compare Interrupt Request Flag Register Capture/Compare Interrupt Enable Register Compare output initialization register Trap Enable Register Compare Output in Trap State Register H DEH DFH E6H E7H E3H E4H F2H F3H F4H F5H F6H F7H E5H D6H E2H FFH F9H

On-Chip Peripheral Components User’s Manual 6-62 2001-05 Writing the CAPCOM Period/Offset/Compare Registers on-the-Fly If Compare Timer 1 is running, then the period, offset or compare registers can be written with modified values for generating new periods or duty cycles of the compare output signals. For proper synchronization purposes, a special mechanism for updating of the 16-bit offset, period, and compare registers is implemented in the C508. This mechanism is based on shadow latches. When new values for offset, period, or compare registers have been written into the shadow latches, the real register update operation must be initiated by setting bit STE1 (shadow transfer enable) in SFR CT1CON. When this bit is set, the content of the shadow latches is transferred to the real registers when Compare Timer 1 has reached its period value or zero value. This applies to both operating modes 0 and 1. When the register transfer has been executed, STE1 is reset by hardware. So the software can recognize when the register transfer has occurred. When Compare Timer 1 is started by setting the run bit CT1R the first time after reset, a shadow register transfer into the real registers is automatically executed. In this case STE1 must not be set. Care must be taken when programming a new compare value. If the new compare value is greater than or equal to the period value, the reload should be delayed till the next zero match (Compare Timer 1 reaches 0000 H) instead of the approaching period match (Compare Timer 1 reaches period value). This can be achieved by setting bit STE1 only in the period match interrupt service routine. If the desired compare value is less than the offset value, the COUT bits in COINI register must be inverted first, before the reload is allowed.

On-Chip Peripheral Components User’s Manual 6-63 2001-05 Compare Timer 1 Control Register The 16-bit Compare Timer 1 is controlled by the bits of the CT1CON register. With this register the count mode, the trap interrupt enable, the compare timer start/stop and reset, and the timer input clock rate is controlled. Special Function Register CT1CON (Address E1H) Reset Value: 00010000 B Bit Function CTM Compare Timer 1 operating mode selection CTM = 0 selects operating mode 0 (up count) and CTM = 1 selects operating mode 1 (up/down count) for Compare Timer 1. ETRP CCU emergency trap interrupt enable If ETRP = 1, the emergency interrupt for the CCU trap signal is enabled. STE1 CAPCOM unit shadow latch transfer enable When STE1 is set, the content of the Compare Timer 1 period, Compare and offset registers (CCPH, CCPL, CCHx, CCLx, CT1OFH, CT1OFL) is transferred to its real registers when Compare Timer 1 reaches the next time the period value or value 0000 H. After the shadow transfer event, STE1 is reset by hardware. CLK2 CLK1 CLK0 Compare Timer 1 input clock selection The input clock for the Compare Timer 1 is derived from the clock rate fOSC of the C508 via a programmable prescaler. The following table shows the programmable prescaler ratios. CTM ETRP STE1 CT1RES CT1R CLK2 CLK1 CLK0E1H CT1CON 76543210 Bit No. MSB LSB CLK2 CLK1 CLK0 Function 0 0 0 Compare timer 1 input clock is 2 fOSC 0 0 1 Compare timer 1 input clock is fOSC 0 1 0 Compare timer 1 input clock is fOSC/2 0 1 1 Compare timer 1 input clock is fOSC/4 1 0 0 Compare timer 1 input clock is fOSC/8 1 0 1 Compare timer 1 input clock is fOSC/16 1 1 0 Compare timer 1 input clock is fOSC/32 1 1 1 Compare timer 1 input clock is fOSC/64

On-Chip Peripheral Components User’s Manual 6-64 2001-05 Note: When software power-down mode is entered with CT1RES bit of SFR CT1CON set, the Compare Timer 1 is reset after the execution of a wake-up from power- down mode procedure. When CT1RES is cleared before software power-down mode is entered and a wake-up from power-down mode procedure has been executed, the Compare Timer 1 is not reset. Depending on the state of bit CT1R at power-down mode entry, the Compare Timer 1 either stops (CT1R = 0) or continues (CT1R = 1) counting after a wake-up from power-down mode procedure. Further details of the power-down mode are provided in Chapter 9.2. CT1RES CT1R Compare timer 1 reset control Compare timer 1 run/stop control These two bits control the start, stop, and reset function of Compare Timer 1. CT1RES is used to reset Compare Timer 1 and CT1R is used to start and stop the Compare Timer 1. The following table shows the functions of these two bits: Note for Capture mode: Setting CT1R = 0 and CT1RES = 1 after a capture event will destroy the value stored in the capture register CCx. Therefore, CT1RES should be set to 0 in capture mode. Reason: if CT1R = 0 and CT1RES = 1 all shadow registers are transparent (switched directly) to the real registers. Bit Function CT1RES CT1R Function 0 0 Compare Timer 1 is stopped and holds its value; the compare outputs stay in the logic state as they are. 1 0 Compare Timer 1 is stopped and reset; compare outputs are set to the logic state as defined in SFR COINI (default after reset). 00 → 1 Compare Timer 1 starts. Before CT1R is set the first time, the CMSEL register should be programmed (enable Capture/Compare functions). 10 → 1 Compare Timer 1 starts running from count value 0000 H; compare outputs are set to the logic state as defined in SFR COINI. 01 → 0 Compare Timer 1 is stopped and holds its value; the Compare outputs drive their actual logic state. 11 → 0 Compare Timer 1 is stopped and reset to 0000 H; Compare outputs are set to the logic state as defined in SFR COINI.

On-Chip Peripheral Components User’s Manual 6-65 2001-05 Compare Timer 1 Period Registers The Compare Timer 1 period registers CCPH and CCPL store the 16-bit value for the Compare Timer 1 count period. CCPH holds the high byte of the 16-bit period value and CCPL holds the low byte. If CCPH/CCPL is written, shadow latches are always loaded. The contents of these shadow latches are transferred to the real registers when STE1 is set and the Compare Timer 1 reaches its period value (operating mode 0) or count value 0000 H (operating mode 1). When the Compare Timer 1 period registers are read, shadow latches are always accessed. Special Function Register CCPL (Address DEH) Reset Value: 00 H Special Function Register CCPH (Address DFH) Reset Value: 00 H Bit Function CCPL.7 - 0 Compare Timer 1 period value, low byte The 8-bit value in the CCPL register is the low byte of the 16-bit period value of Compare Timer 1 (shadow latch). CCPH.7 - 0 Compare Timer 1 period value, high byte The 8-bit value in the CCPH register is the high byte of the 16-bit period value of Compare Timer 1 (shadow latch). Bit No. MSB LSB 76543210

On-Chip Peripheral Components User’s Manual 6-66 2001-05 Compare Timer 1 Offset Registers The CT1OFH and CT1OFL registers contain the value for the Compare Timer 1. CT1OFH holds the high byte of the 16-bit offset value and CT1OFL holds the low byte. For the detection of a compare match event, which results in changing polarity of a COUTx compare output signal, the content of CT1OFH/CT1OFL is always added to the actual value of the Compare Timer 1. The value stored in the offset registers has no effect on the signal generation at the CCx compare outputs. If the Compare Timer 1 offset registers are written, shadow latches are always loaded. The content of these shadow latches is transferred to the real registers when STE1 is set and the Compare Timer 1 reaches its period value or count value 0000 H. When the Compare Timer 1 offset registers are read, shadow latches are always accessed. Special Function Register CT1OFL (Address E6H) Reset Value: 00 H Special Function Register CT1OFH (Address E7H) Reset Value: 00 H To generate correct dead times for PWM signals, the offset value stored in CT1OFH/ CT1OFL must be lower than the values stored in the compare registers. Bit Function CT1OFL.7 - 0 8-bit Compare Timer 1 offset value, low byte The 8-bit value in the CT1OFL register is the low byte of the offset value for Compare Timer 1 (shadow latch). CT1OFH.7 - 0 8-bit Compare Timer 1 offset value, high byte The 8-bit value in the CT1OFH register is the high byte of the offset value for Compare Timer 1 (shadow latch). Bit No. MSB LSB 76543210

On-Chip Peripheral Components User’s Manual 6-67 2001-05 Capture/Compare Channel Mode Select Registers The capture/compare channels of the CAPCOM unit can operate individually either in compare mode or in capture mode. The CMSEL0 and CMSEL1 registers contain the mode select bits for the CAPCOM unit. Special Function Register CMSEL0 (Address E3H) Reset Value: 00 H Special Function Register CMSEL1 (Address E4H) Reset Value: 00 H Bit Function ESMC Enable software controlled multi-channel PWM modes If ESMC = 0, switching of the follower state in 4-/5-/6-phase multi-channel PWM mode is controlled by Compare Timer 1 reaching its period value. If ESMC = 1, switching of the follower state in 4-/5-/6-phase multi-channel PWM mode is controlled by bit NMCS. NMCS Next multi-channel PWM state Setting bit NMCS (with ESMC set) will select the follower state in the 4/5/6-phase multi-channel PWM mode, which is taken into account at the output pins, when Compare Timer 1 is 0. Bit NMCS is reset by hardware in the next clock cycle after it has been set. CMSELx3 x=0 - 2 Switching Compare Timer 2 output signal to COUTx If CMSELx3 is set and compare mode is selected for the outputs COUTx, the output signal of the 10-bit Compare unit, typically a higher frequency signal, is switched (modulated) to the COUTx pin. The state of the corresponding COINI bit at the start of Compare Timer 1 defines the logic level of the CAPCOM channel output signal at which the COMP output signal is output to COUTx. COINI is set: The COMP output is switched to COUTx during the low phase of the CAPCOM channel X signal. COINI is cleared: The COMP output is switched to COUTx during the high phase of the CAPCOM channel X signal. CMSEL CMSEL CMSEL CMSEL CMSEL CMSELE3H CMSEL0 76543210 Bit No. MSB LSB ESMC NMCS 0 0 CMSEL CMSEL CMSELE4H CMSEL1 76543210 13 12 11 02 01 00 22 21 20 CAPCOM Channel 2 CAPCOM Channel 1 CAPCOM Channel 0 CMSEL CMSEL CMSEL

On-Chip Peripheral Components User’s Manual 6-68 2001-05 In compare mode, the two output signals of a CAPCOM channel can be enabled selectively. In capture mode, the type of signal transition which will generate a capture event can be chosen. CMSELx2- 0 x = 0-2 CAPCOM Capture/Compare mode enable bits The CMSEL registers are used to select/enable the operating mode and the output/input pin configuration of the capture/compare channels. Each CAPCOM channel can be programmed individually for either compare or capture operation. Note: Only CC0/COUT0 can be analog inputs if not selected as compare output. Bit Function CMSEL CMSEL CMSEL Mode 000C o m p a r e o u t p u t s d i s a b l e d ; No compare output signal is generated; CCx and COUTx are normal I/O pins. 001C o m p a r e o u t p u t o n p i n C C x e nabled; COUTx is normal I/O pin. 010C o m p a r e o u t p u t o n p i n C O U T x enabled; CCx is normal I/O pin. 011C o m p a r e o u t p u t s o n p i n s C C x a n d C O U T x enabled. 100C a p t u r e m ode enabled; signal transitions at CCx do not generate a capture event. COUTx is a normal I/O pin or analog input pin. 101C a p t u r e m o d e enabled; CCx is configured as a Capture input and a rising edge at CCx transfers compare timer 1 content into the capture register. COUTx is a normal I/O pin or analog input pin. 110C a p t u r e m o d e enabled; CCx is configured as a Capture input and a falling edge at CCx transfers compare timer 1 content into the capture register. COUTx is a normal I/O pin or analog input pin. 111C a p t u r e m o d e enabled; CCx is configured as a capture input. Rising and falling edge at CCx transfer the compare timer 1 content into the capture register. COUTx is a normal I/O pin or analog input pin.

On-Chip Peripheral Components User’s Manual 6-69 2001-05 Capture/Compare Registers of CAPCOM Unit The capture/compare registers are 16-bit registers, organized as two 8-bit byte-wide registers. Each of the three CAPCOM channels has one capture/compare register. In compare mode, they hold a compare value which typically defines the duty cycle of the output signals. In capture mode, the actual Compare Timer 1 value is transferred into the Capture/Compare registers at a Capture event. If CCLx/CCHx is written, shadow latches are always loaded. The content of these shadow latches is transferred to the real registers when STE1 is set and the Compare Timer 1 reaches its period value (operating mode 0) or count value 0000 H (operating mode 1). When the Capture/Compare registers are read, the real registers are always accessed because of capture mode. Special Function Registers CCL0/CCH0 (Addresses F2H / F3H) Reset Value: 00 H Special Function Registers CCL1/CCH1 (Addresses F4H / F5H) Reset Value: 00 H Special Function Registers CCL2/CCH2 (Addresses F6H / F7H) Reset Value: 00 H Bit Function CCLx.7 - 0 x=0 - 2 Capture/Compare value, low byte The 8-bit value in the CCLx register is the low byte of the 16-bit capture/compare value of channel x. CCHx.7 - 0 x=0 - 2 Capture/Compare value, high byte The 8-bit value in the CCHx register is the low byte of the 16-bit capture/compare value of channel x. Bit No. MSB LSB 76543210

On-Chip Peripheral Components User’s Manual 6-70 2001-05 Capture/Compare Interrupt Request Flags/Register The interrupt flags of the CAPCOM capture/compare match and Compare Timer 1 interrupt are located in the register CCIR. All CAPCOM capture/compare match interrupt flags are set by hardware and must be cleared by software. A capture/compare match interrupt is generated by setting of a CCxR bit (x = 0-2) if the corresponding enable bits are set. The Compare Timer 1 interrupt is triggered by the CT1FP or CT1FC bits of SFR CCIR. Special Function Register CCIR (Address E5 H) Reset Value: 00 H Bit Function CT1FP Compare Timer 1 period flag Compare Timer 1 operating mode 0: CT1FP is set if Compare Timer 1 reaches the period value. Compare Timer 1 operating mode 1: CT1FP is set if Compare Timer 1 reaches the period value and changes the count direction from up- to down counting Bit CT1FP must be cleared by software. If Compare Timer 1 interrupt is enabled, the setting of CT1FP will generate a Compare Timer 1 interrupt. CT1FC Compare Timer 1 count direction change flag This flag can only be set if Compare Timer 1 runs in operating mode 1 (CTM = 1). CT1FC is set when Compare Timer 1 reaches count value 0000 H and changes the count direction from down- to up-counting. If Compare Timer 1 interrupt is enabled, the setting of CT1FC will generate a Compare Timer 1 interrupt. Bit CT1FC must be cleared by software. Bit No. MSB LSB CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0RE5H CCIR 76543210 CAPCOM Channel 0 CAPCOM Channel 1 CAPCOM Channel 2

On-Chip Peripheral Components User’s Manual 6-71 2001-05 CCxR x=0 - 2 Capture/Compare match on up-count flag Capture Mode: CCxR is set at a low-to-high transition (rising edge) of the corresponding CCx Capture input signal. Compare Mode: CCxR is set if the Compare timer 1 value matches the Compare register CCx value during the up-count phase. CCxF x=0 - 2 Capture/Compare match on down-count flag Capture Mode: CCxF is set at a high-to-low transition (falling edge) of the corresponding CCx capture input signal. Compare Mode: CCxF is set if the Compare Timer 1 value matches the compare register CCx value during the down-count phase (only in Compare Timer 1 operating mode 1). Bit Function

On-Chip Peripheral Components User’s Manual 6-72 2001-05 Capture/Compare Interrupt Enable Register The bits of the interrupt enable register CCIE control the specific interrupt enable/disable functions of the CAPCOM part of the Capture/Compare unit. The bits ECTP and ECTC control the Compare Timer 1 period/count change interrupt. Depending on the mode in which Compare Timer 1 is running, interrupts can be generated at a period match or a count direction change event. The lower 6 bits of CCIE are the CAPCOM channel specific interrupt enable/disable control bits for the capture or compare match interrupt. The functions of these bits depend on the selected mode (capture or compare) of a capture/compare channel. In compare mode, compare channel specific interrupts can be generated at a match event between compare register content and compare timer 1 count value during the up- or down-counting phase of Compare Timer 1. In capture mode, capture channel specific interrupts can be generated selectively at rising or falling or both edges of the capture input signals at CCx. Special Function Registers CCIE (Address D6 H) Reset Value: 00 H Bit Function ECTP Enable Compare Timer 1 period interrupt If ECTP = 0, the Compare Timer 1 period interrupt is disabled. Compare Timer 1 operating mode 0: If ECTP = 1, an interrupt is generated when Compare Timer 1 reaches the period value. Compare timer 1 operating mode 1: If ECTP = 1, an interrupt is generated when Compare Timer 1 reaches the period value and changes the count direction from up- to down-counting. MSB LSB CCIEECTP ECTC CC2FEN CC2REN CC1FEN CC1REN CC0FEN CC0REN Bit No. D6H 76543210

On-Chip Peripheral Components User’s Manual 6-73 2001-05 ECTC Enable Compare Timer 1 count direction change interrupt status If ECTC = 0, the Compare Timer 1 count change interrupt is disabled. Compare timer 1 operating mode 0: Bit has no effect on the interrupt generation. Compare timer 1 operating mode 1: If ECTC = 1, an interrupt is generated when Compare Timer 1 reaches count value 0000 H and changes its count direction from down- to up-counting. CCxREN (x = 0-2) Capture/Compare rising edge interrupt enable Capture Mode: If CCxREN is set, an interrupt is generated at a low-to-high transition (rising edge) of the corresponding CCx input signal. Compare Mode: If CCxREN is set, an interrupt is generated if the Compare Timer 1 value matches the compare register CCx value during the up-counting phase of the Compare Timer 1. This function is available in both Compare Timer 1 operating modes. CCxFEN (x = 0-2) Capture/Compare falling edge interrupt enable Capture Mode: If CCxFEN is set, an interrupt is generated at a high-to-low transition (falling edge) of the corresponding CCx input signal. Compare Mode: If CCxFEN is set, an interrupt is generated only in Compare timer mode 1 if the Compare Timer 1 value matches the Compare register CCx value during the down-counting phase of the Compare Timer 1. This function is available only in Compare Timer 1 operating mode 1. Bit Function

On-Chip Peripheral Components User’s Manual 6-74 2001-05 Compare Output Initialization Register COINI The six lower bits of the COINI register define the initial values (passive levels) of the Port 1 lines, which are programmed to be used as a compare output. If an output of the CAPCOM unit is enabled for compare mode operation by writing the corresponding bit combination into the CMSEL0/CMSEL1 registers, the compare output is switched into push-pull mode and starts driving an initial logic level as defined by the bits of the COINI register. Bit COUTXI controls an inverter for the COMP unit output signal, when it is wired to the CCx and COUTx outputs in burst or multi-channel PWM mode. COUT3I defines the initial logic level at COUT3 before Compare Timer 2 is started as well as the logic state when COUT3 is disabled by setting bit ECT2O in SFR CT2CON (see Figure 6-32). The COINI register should be written prior to the starting of the compare timers. Any write operation to the COINI register when the compare timer is running will affect the compare output signals immediately and drive the logic value as defined by the bits of COINI. A PWM output signal of the C508 basically consists of two phases, an inactive phase and an active phase. The inactive phase of a PWM output signal is defined by the bit in the register COINI. A ‘1’ in bit location 0 to 5 of COINI defines the high level of the corresponding PWM compare output signal as its inactive phase. With a ‘0’, a low level is selected as the inactive phase.

On-Chip Peripheral Components User’s Manual 6-75 2001-05 Special Function Register COINI (Address E2H) Reset Value: FF H Bit Function COUT3I COUT3 initial logic level This bit defines the initial logic state of the output COUT3 before Compare Timer 2 is started the first time. Further, COUT3I defines the logic state of output COUT3 when bit ECT2O (CT2CON.6) is reset (COUT3 disabled). COUTXI Compare Timer 1 output signal inversion in burst and block commutation When COUTXI is set, the output signal of Compare Timer 2 which is wired to the compare outputs COUTx (x = 0-2) in burst or block commutation mode is inverted. CCxI, COUTxI (x = 0-2) Compare output initial value Bits at even bit positions (0, 2, 4) are assigned to the CCx compare outputs. Bits at odd bit positions (1, 3, 5) are assigned to the COUTx compare outputs. CCxI, COUTxI = 0: If Compare Timer 1 is not running (after reset), an output CCx/COUTx (x = 0-2) is switched into push-pull mode and starts driving an initial value of 0 when this CCx/COUTx output is programmed as compare output by writing the corresponding bit combination into the CMSEL0/CMSEL1 registers. CCxI, COUTxI = 1: If Compare Timer 1 is not running (after reset), an output CCx/COUTx (x = 0-2) is switched into push-pull mode and starts driving an initial value of 1 when this CCx/COUTx output is programmed as compare output by writing the corresponding bit combination into the CMSEL0/CMSEL1 registers. The COINI values are valid only for capture/compare outputs enabled for compare mode operation. COUT3I COUTXI COUT2I CC2I COUT1I CC1I COUT0I CC0IE2H COINI 76543210 Bit No. MSB LSB CAPCOM Channel 0 CAPCOM Channel 1 CAPCOM Channel 2

On-Chip Peripheral Components User’s Manual 6-76 2001-05 Trap Enable Register The trap enable register TREN is used to enable selectively the compare outputs of the three CAPCOM channels for switching it into high or low level in the trap state as defined by the bits of the COTRAP register. Additionally, for a general enable of the trap function, bit TRPEN must be set. The TRF flag indicates when a low level is detected at the CTRAP input signal. Special Function Register TRCON (Address FFH) Reset Value: 00 H Bit Function TRPEN External CTRAP trap function enable bit This bit is a general enable bit for the trap function of the CTRAP input signal. TRPEN = 0: External trap input CTRAP is disabled (default after reset). TRPEN = 1: External trap input CTRAP is enabled; TRF Trap flag TRF is set by hardware if the trap function is enabled (TRPEN = 1) and the CTRAP level becomes active (low). If enabled, an interrupt is generated when TRF is set. TRF must be reset by software. TREN5-0 Trap enable control bits Bits at even bit positions (0, 2, 4) are assigned to the CCx Compare outputs. Bits at odd bit positions (1, 3, 5) are assigned to the COUTx Compare outputs. TRENx = 0: Compare channel output provides CAPCOM output signal in trap state. TRENx = 1: Compare channel output is enabled to set the logic level of the compare output CCx or COUTx in the trap state to a logic state as defined by the corresponding bits of the COTRAP register. When writing TREN0-5, bit TRF should be reset to 0. Otherwise, setting TREN0-5 will generate a software trap interrupt. CAPCOM Channel 0 CAPCOM Channel 1 CAPCOM Channel 2 TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0FFH TRCON 76543210 Bit No. MSB LSB

On-Chip Peripheral Components User’s Manual 6-77 2001-05 Compare Output in Trap State Register The six lower bits of the COTRAP register define the values of Port 1 pins 2 to 7, which are programmed to be used as compare outputs, when a trap state is entered. Bit 6 is reserved and must always be written with a ‘0’. Bit 7 selects either one of the two block commutation tables for rotate left that is provided. Special Function Register COTRAP (Address F9H) Reset Value: 00 H Bit Function BCTSEL Block Commutation Table (Rotate Left) Select BCTSEL = 0: The table for 60° phase angle will be selected. BCTSEL = 1: The table for 0° phase angle will be selected. RES Reserved This bit must always be written with a ‘0’. Writing a ‘1’ to this bit is prohibited. CCxT, COUTxT (x = 0-2) Compare output level in trap condition Bits at even positions (0, 2, 4) are assigned to the CCx compare outputs. Bits at odd positions (1, 3, 5) are assigned to the COUTx compare outputs. CCxT, COUTxT = 0: If the compare timer is running, the compare channel output CCx, COUTx (x = 0-2) will be switched to 0 level in trap state if the channel is enabled for trap function. CCxT, COUTxT = 1: If the compare timer is running, the compare channel output CCx, COUTx (x = 0-2) will be switched to 1 level in trap state if the channel is enabled for trap function. CAPCOM Channel 0 CAPCOM Channel 1 CAPCOM Channel 2 RES COUT2T CC2T COUT1T CC1T COUT0T CC0TF9H COTRAP 76543210 Bit No. MSB LSB BCTSEL

On-Chip Peripheral Components User’s Manual 6-78 2001-05

6.3.3 Compare (COMP) Unit Operation

The Capture/Compare Unit of the C508 also provides a 10-bit Compare Unit (COMP) which operates as a single channel pulse generator with a pulse width modulated output signal. This output signal is available at the output pin COUT3 of the C508. In the combined multi-channel PWM modes and in burst mode of the CAPCOM unit the output signal of the COMP unit can also be switched to the output signals COUTx or CCx. Figure 6-32 shows the block diagram and the pulse generation scheme of the COMP unit (for example: the initial value of COUT3 is set to 0). Figure 6-32 COMP Unit: Block Diagram and Pulse Generation Scheme MCB04069 Pulse Generation Match Port Pin COUT3 COUTXI (COINI.6) COUT3I (COINI.7) CT2 Value Start of CT2 COUT3 (COUT3I = 0) Time COUT3 (COUT3I = 1) Reset of CT2 To CAPCOM Output Control ECT20 CMP2H/CMP2L CP2H/CP2L Programmable Prescaler Period Registers CP2H/CP2L Compare Timer 2 10-Bit Up Counter Control Register CT2CON Comparator Compare Registers CMP2H/CMP2L 2fOSC 000

On-Chip Peripheral Components User’s Manual 6-79 2001-05 The COMP unit has a 10-bit up-counter (Compare Timer 2, CT2) which starts counting from 000H up to the value stored in the period register and then is again reset. This Compare Timer 2 operation is similar to the operating mode 0 of Compare Timer 1. When the count value of CT2 matches the value stored in the compare registers CMP2H/CMP2L, COUT3 toggles its logic state. When Compare Timer 2 is reset to 000 COUT3 toggles again its logic state. COUT3 is only an output pin. After a reset operation COUT3 drives a high level as defined by the reset value (= 1) of bit COUT3I of SFR COINI. When Compare Timer 2 is running (bit CT2R in SFR CT2CON is set), bit ECT2O in SFR CT2CON allows the disconnection of COUT3 from Compare Timer 2 signal generation. In this case, the logic value of COUT3I (bit COINI.7) is put to the COUT3 output. When ECT2O is set thereafter, the Compare Timer 2 output signal is again switched to the COUT3 output. In the combined multi-channel PWM modes and in the burst mode, the Compare Timer 2 output signal can also be switched to the CAPCOM output pins COUT0, COUT1, and COUT3. In these modes, the polarity of the modulated output signal at COUT2-0 can be inverted by setting bit COUTXI (COINI.6)

6.3.3.1 COMP Registers

The COMP unit has five SFRs which are listed in Table 6-8. The Compare Timer 2 period and compare registers store a 10-bit value, organized in two bytes. For proper synchronization purposes, these registers are not written directly. Each value of a write operation to these registers is stored in shadow latches. The transfer of these shadow latches into the real registers is synchronized with the Compare Timer 2 value 000 H and controlled by bit STE2. When the period or compare value is changed by writing the corresponding SFR, the setting of bit STE2 (CT2CON.5) enables the write transfer of the shadow registers into the real registers. This shadow latch transfer happens when the Compare Timer 2 reaches the count value 000 H the next time after STE2 has been set. With the automatic transfer of the shadow latches to the real registers, bit STE2 is reset by hardware. When the Compare Timer 2 period and compare registers are initialized after reset, bit STE2 must also be set to enable the shadow latch transfer when Compare Timer 2 is started the first time. Note: Read operations with the Compare Timer 2 period and compare registers always access the shadow registers and not the real registers. Table 6-8 Special Function Registers of the COMP Unit Unit Symbol Description Address COMP Compare Unit CT2CON CP2L CP2H CMP2L CMP2H Compare Timer 2 control register Compare Timer 2 period register, low byte Compare Timer 2 period register, high byte Compare Timer 2 Compare register, low byte Compare Timer 2 Compare register, high byte H D2H D3H D4H D5H

On-Chip Peripheral Components User’s Manual 6-80 2001-05 Compare Timer 2 Control Register The 10-bit Compare Timer 2 is controlled by the bits of the CT2CON register. With this register the count mode, the timer input clock rate, and the compare timer reset function is controlled. Special Function Register CT2CON (Address F1H) Reset Value: 00010000 B Bit Function CT2P Compare Timer 2 period flag When the Compare Timer 2 value matches with the Compare Timer 2 period register value, bit CT2P is set. If the Compare Timer 2 interrupt is enabled, the setting of CT2P will generate a Compare Timer 2 interrupt. Bit CT2P must be cleared by software. ECT2O Enable Compare timer 2 output When ECT2O is cleared and Compare Timer 2 is running, output COUT3 is put into the logic state as defined by bit COUT3I which is located in SFR COINI.6. When ECT2O is set and Compare Timer 2 is running, the Compare Timer 2 output COUT3 is enabled and outputs the PWM signal of the COMP unit. STE2 COMP unit shadow latch transfer enable When STE2 is set, the content of the Compare Timer 2 period and compare latches (CP2H, CP2L, CMP2H, CMP2L) is transferred to its real registers when Compare Timer 2 reaches the period value. After the shadow transfer event, STE2 is reset by hardware. CT2P ECT2O CT2RES CT2R CLK2 CLK1 CLK0F1H CT2CON 76543210 Bit No. MSB LSB STE2

On-Chip Peripheral Components User’s Manual 6-81 2001-05 Note: With a reset operation (external or internal) Compare Timer 2 is reset (000H) and stopped. When software power-down mode is entered with CT2RES bit of SFR CT2CON set, the Compare Timer 2 is reset after the execution of a wake-up from CT2RES CT2R Compare Timer 2 reset control Compare Timer 2 run/stop control These two bits controls the start, stop, and reset function of the Compare Timer 2. CT2RES is used to reset Compare Timer 2; and CT2R is used to start or stop Compare Timer 2. The following table shows the functions of these two bits: ECT2O must be set for COUT3 signal output enable. CLK2 CLK1 CLK0 Compare Timer 2 input clock selection The input clock for the Compare Timer 2 is derived from the clock rate fOSC of the C508 via a programmable prescaler. The following table shows the programmable prescaler ratios. Bit Function CT2RES CT2R Function 0 0 Compare Timer 2 is stopped; compare output COUT3 stays in the logic state as it is. 0 1 Compare Timer 2 is running. If CT2R is set the first time after reset, COUT3 is set to the logic state as defined by bit COUT3I of SFR COINI. 1 0 Compare Timer 2 is stopped and reset. The output COUT3 is set to the logic state as defined by bit COUT3I of SFR COINI (default after reset). 1 1 Compare Timer 2 is further running. CLK2 CLK1 CLK0 Function 0 0 0 Compare Timer 2 input clock is 2 fOSC 0 0 1 Compare Timer 2 input clock is fOSC 0 1 0 Compare Timer 2 input clock is fOSC/2 0 1 1 Compare Timer 2 input clock is fOSC/4 1 0 0 Compare Timer 2 input clock is fOSC/8 1 0 1 Compare Timer 2 input clock is fOSC/16 1 1 0 Compare Timer 2 input clock is fOSC/32 1 1 1 Compare Timer 2 input clock is fOSC/64

On-Chip Peripheral Components User’s Manual 6-82 2001-05 power-down mode procedure. When CT2RES is cleared before software power down mode is entered and a wake-up from power-down mode procedure has been executed, the Compare Timer 2 is not reset. Depending on the state of bit CT2R at power down mode entry, the Compare Timer 2 either stops (CT2R = 0) or continues (CT2R = 1) counting after a wake-up from power-down mode procedure. Further details of the power-down mode are described in Chapter 9.2. Compare Timer 2 Period Registers The Compare Timer 2 period registers CP2L/CP2H hold the 10-bit value for the Compare Timer 2 period. When the Compare Timer 2 value is equal to the value stored in the period register, the COUT3 signal changes from inactive to active state. If CP2H/ CP2L is written, only shadow latches are written. The content of these latches is transferred to the real registers at compare timer count value 000 H, using bit STE2 of SFR CT2CON. When the Compare Timer 2 period registers CP2L/CP2H are read, the shadow registers are always accessed. Special Function Register CP2L (Address D2H) Reset Value: 00 H Special Function Register CP2H (Address D3H) Reset Value: XXXXXX00 B Bit Function CP2L.7 - 0 Compare Timer 2 period value, low byte The CP2L register holds the lower 8 bits of the 10-bit period value for Compare Timer 2 (shadow latch). CP2H.1 - 0 Compare Timer 2 period value, high bits The CP2H register holds most significant two bits of the 10-bit period value for Compare Timer 2 (shadow latch). – Reserved bits Bit No. MSB LSB 76543210

On-Chip Peripheral Components User’s Manual 6-83 2001-05 Compare Timer 2 Compare Registers The compare registers CMP2H/CMP2L of Compare Timer 2 hold the 10-bit compare value which defines the duty cycle of the output signal at COUT3. When the Compare Timer 2 value is equal to the value stored in the CMP2H/CMP2L register, the COUT3 signal changes from passive to active state. If CMP2H/CMP2L is written, only shadow latches are written. The content of these latches is transferred to the real registers when compare timer count value 000 H is reached and bit STE2 of SFR CT2CON has been set. When the compare registers CMP2H/CMP2L are read, the shadow registers are always accessed. Special Function Registers CMP2L (Address D4H) Reset Value: 00 H Special Function Registers CMP2H (Address D5H) Reset Value: XXXXXX00 B Bit Function CMP2L.7 - 0 Compare Timer 2 compare value, low byte The CMP2L register holds the lower 8 bits of the 10-bit compare value for Compare Timer 2. CMP2H.1 - 0 Compare Timer 2 compare value, high bits The CMP2H register holds most significant two bits of the 10-bit Compare value for Compare Timer 2. – Reserved bits Bit No. MSB LSB 76543210

On-Chip Peripheral Components User’s Manual 6-84 2001-05

6.3.4 Combined Multi-Channel PWM Modes

The CCU of the C508 has been designed to support also motor control or inverter applications which have a demand for specific multi-channel PWM signal generation. In these combined multi-channel PWM modes the CAPCOM unit (Compare Timer 1) and the COMP unit (Compare Timer 2) of the C508 CCU are working together. In the combined multi-channel PWM modes the signal generation of the CCx and COUTx PWM outputs can basically be controlled either by the interrupt inputs INT0 to INT2 (block commutation mode) or by the operation of Compare Timer 1 or by software (multi-channel PWM mode). In the active phase of a combined multi-channel PWM mode, Compare Timer 1 compare output signal or the Compare Timer 2 output signal or both can be switched selectively to the CCx or COUTx PWM output lines. The combined multi-channel PWM modes are controlled by the BCON (block commutation control) register. Figure 6-33 shows the block diagram of the multi-channel PWM mode logic which is integrated in the C508. Figure 6-33 Block Diagram of the Combined Multi-Channel PWM Modes MCB02608 Port 1 Control Logic CC0 CC1 CC2 COUT0 COUT1 COUT2 Trap Control CTRAP Channel 0 in Capture Mode 16-Bit Compare Timer 1 Combined Multi-Channel PWM Control (BCON) INT0 INT1 INT2 PWM Timer 2 Compare 10-Bit COUT3 CCU Emergency Interrupt Capture Interrupt Period/ Comp. Match Interrupt

On-Chip Peripheral Components User’s Manual 6-85 2001-05 In block commutation mode, a well defined incoming digital signal pattern of e.g. hall sensor signals, which are applied to the INT0-2 inputs, is sampled. Each transition at the INT0-2 inputs results in a change of the state of the PWM outputs. In block commutation mode, all six PWM output signals CCx and COUTx (x = 0-2) are outputs. According to a block commutation table ( Table 6-10), the outputs CCx are put either to a low or high state while the outputs COUTx are switched to the PWM signal which is generated by the 10-bit Compare Timer 2 (COMP unit). For monitoring of sensor input signal timing in block commutation mode, the signal transitions at INT0-2 can also generate an interrupt (if enabled) and a capture event at channel 0 of the CAPCOM unit (Compare Timer 1). For emergency cases, (trap function of CTRAP input signal) the six outputs CCx and COUTx can be put selectively to the levels as defined by the first six bits in COTRAP register. At the multi-channel PWM modes of the C508, a change of the PWM output states (active or inactive) is triggered by Compare Timer 1, which is running either in operating mode 0 or 1. If its count value reaches 0000H, the PWM output signal changes its state according to a well defined state table. The multi-channel PWM modes consists of three modes: – 4-phase multi-channel PWM mode (4 PWM output signals) – 5-phase multi-channel PWM mode (5 PWM output signals) – 6-phase multi-channel PWM mode (6 PWM output signals)

On-Chip Peripheral Components User’s Manual 6-86 2001-05

6.3.4.1 Control Register BCON

The BCON register controls the selection of multi-channel PWM modes. It also contains the block commutation interrupt enable and status bit/flag. Special Function Register BCON (Address D7H) Reset Value: 00 H Bit Function BCMP BCEM In multi-channel PWM mode: Machine polarity If BCMP is set and multi-channel PWM mode is selected (PWM1, 0 ≠ 0, 0), all enabled compare outputs COUTx and CCx are switched to the Compare Timer 2 output signal during their active phase. If BCMP is cleared, only the COUTx outputs are switched to the Compare Timer 2 output signal during the active phase in multi-channel PWM mode. CMSELx3 must be set for that functionality. In block commutation mode: Error mode select bit If BCEM is set in block commutation mode, in rotate right or rotate left mode additionally a “wrong follower” condition causes the setting of BCERR if EBCE is set. PWM1 PWM0 Multi-channel PWM mode selection These bits select the operating mode of the multi-channel PWM modes. EBCE Enable interrupt of block commutation mode error If EBCE is set, the emergency interrupt for a block commutation mode error condition of the CCU is enabled. In block commutation mode, an emergency error condition occurs if a false signal state at INT2 - INT0 or a wrong follower state (if selected by bit BCEM) is detected (see also Table 6-10). BCMP PWM1 PWM0 EBCE BCERR BCEN BCM1 BCM0D7H BCON 76543210 Bit No. MSB LSB BCEM PWM1 PWM0 Function 0 0 Block commutation mode (for hall sensor inputs) 0 1 4-phase multi-channel PWM mode 1 0 5-phase multi-channel PWM mode 1 1 6-phase multi-channel PWM mode

On-Chip Peripheral Components User’s Manual 6-87 2001-05 Note: When a multi-channel PWM mode is initiated the first time after reset, BCON must be written twice: first write operation with bit BCEN cleared and all other bits set/ cleared as required (BCM1, 0 must be 0, 0 for idle mode), followed by a second write operation with the same BCON bit pattern of the first write operation but with BCEN set. After this second BCON write operation, Compare Timer 1 can be started (setting CT1R in CT1CON) and thereafter BCM1, 0 can be put into another mode than idle mode. BCERR Block commutation mode error flag In block commutation mode BCERR is set in rotate right or rotate left mode if after a transition at INTx all INTx inputs are at high or low level. Additionally, in rotate right or rotate left mode a “wrong follower” condition according to Table 6-10 can cause the setting of BCERR (see description of bit BCEM). If the block commutation interrupt is enabled (EBCE = 1), the setting of BCERR will generate a CCU emergency interrupt. BCERR must be reset by software. BCEN Block commutation enable If BCEN is set, the multi-channel PWM modes of the CAPCOM unit as selected by the bits PWM1/PWM0 are enabled for operation. Before BCEN bit is set, all required PWM Compare outputs should be programmed to operate as compare outputs by writing the registers CMSEL1/CMSEL0. BCM1 BCM0 Multi-channel PWM mode output pattern selection Additionally to bits PWM1 and PWM0, these two control bits select the output signal pattern in all multi-channel PWM modes. The detailed signal pattern information is given in Table 6-10 to Table 6-13. Bit Function BCM1 BCM0 Function

00 I d l e m o d e

On-Chip Peripheral Components User’s Manual 6-88 2001-05

6.3.4.2 Signal Generation in Multi-Channel PWM Modes

The multi-channel PWM modes of the C508 use the pins CCx and COUTx for compare output signal generation. Before signal generation of a multi-channel PWM mode can be started, the COINI register should be programmed with the logic value of the multi- channel PWM inactive phase. After this, the output pins which are required for the multi- channel PWM signal generation must be programmed to operate as compare outputs by writing the mode select registers CMSEL0 and CMSEL1. Table 6-9 shows the CMSEL0/ CMSEL1 register bits which are required for the full operation of the multi-channel PWM modes. Note: The abbreviation “X” means don’t care. The abbreviation “Y” (bit CMSELx.3) represents the burst mode bit. If Y = 0 the signal generation at the COUTx pins is controlled by Compare Timer 1. If Y = 1 the signal generation at the COUTx pins is also controlled by Compare Timer 1 but modulated by Compare Timer 2. Output Signals During the Active Phase An active phase of a compare output signal in multi-channel PWM mode can be controlled either by the CAPCOM unit (Compare Timer 1) and/or modulated by Compare Timer 2. The selection is done by bit CMSELx.3 (see note below Table 6-9). Figure 6-34 shows the different possibilities for controlling the active phase of a compare output signal using Compare Timer 1. Compare Timer 1 may operate either in mode 0 or mode 1. In multi-phase mode, the block commutation logic switches from one state to the next state when Compare Timer 1 reaches the value 0000 H. As an active phase always lasts for two states, the duration of an active phase is determined by Compare Timer 1 reaching 0000 H twice. As shown in Figure 6-34a, a compare output signal CCx or COUTx of a CAPCOM channel is either at low or high level during the whole active phase when the value stored in the Compare Timer 1 offset registers (CT1OFH, CT1OFL) and the value stored in its compare registers (CCHx, CCLx) is equal 0000 H. When the compare value is not equal 0000H and less or equal the period value, the active phase of the related compare output signal CCx or COUTx is controlled by the CAPCOM unit as shown in Figure 6-34b. Table 6-9 Programming of Multi-Channel PWM Compare Outputs Multi-Channel PWM Mode CMSEL1 CMSEL0 Block commutation / 6-phase multi-channel PWM XXXX Y011B Y011 Y011B 5-phase multi-channel PWM Y010 Y011 B 4-phase multi-channel PWM Y010 Y001 B

On-Chip Peripheral Components User’s Manual 6-89 2001-05 Figure 6-34 Compare Timer 1 Controlled Active Phase of the Multi-Channel PWM Modes (with CMSELx.3 = 0) No transitions in active phase (offset and compare value = 0) CAPCOM transitions in active phase (0 < compare value Compare Timer 1 Compare Timer 1 Mode 1 COUTx CCx COUTx Mode 0 CCx : Active Phase Compare Timer 1 Compare Timer 1 COUTx Mode 1 CCx COUTx CCx Mode 0 COINI Bit = 1 COINI Bit = 1 Mode 1 COUTx CCx Compare Timer 1 Compare Timer1 COUTx CCx Mode 0 MCT02609 period value; offset value = 0) Compare Timer 1 Mode 1 CCx COUTx Compare Timer 1 COUTx CCx Mode 0 COINI Bit = 0 COINI Bit = 0

On-Chip Peripheral Components User’s Manual 6-91 2001-05

6.3.4.3 Block Commutation PWM Mode

In block commutation mode the INT0-2 inputs are sampled once each processor cycle. If the input signal combination at INT0-2 changes its state, the outputs CCx and COUTx are set to their new state according to Table 6-10. Table 6-10 Block Commutation Control Table Mode (BCM1, BCM0) INT0 - INT2 Inputs CC0 - CC2 Outputs COUT0 - COUT2 Outputs INT0 INT1 INT2 CC0 CC1 CC2 COUT0 COUT1 COUT2 Rotate left1) Rotate right1) 1) If one of these two combinations of INTx signals is detected in rotate left or rotate right mode, bit BCERR flag is set. If enabled, a CCU emergency interrupt can be generated. When these states (error states) are reached, idle state is entered immediately. 0 0 0 inactive inactive inactive inactive inactive inactive 1 1 1 inactive inactive inactive inactive inactive inactive Rotate left, 60° phase shift (BCTSEL = 0, default) 1 0 1 inactive inactive active active inactive inactive 1 0 0 inactive active inactive active inactive inactive 1 1 0 inactive active inactive inactive inactive active 0 1 0 active inactive inactive inactive inactive active 0 1 1 active inactive inactive inactive active inactive 0 0 1 inactive inactive active inactive active inactive Rotate left, ° phase shift (BCTSEL - 1) 1 0 1 inactive inactive active inactive active inactive 1 0 0 inactive inactive active active inactive inactive 1 1 0 inactive active inactive active inactive inactive 0 1 0 inactive active inactive inactive inactive active 0 1 1 active inactive inactive inactive inactive active 0 0 1 active inactive inactive inactive active inactive Rotate right 1 1 0 active inactive inactive inactive active inactive 1 0 0 active inactive inactive inactive inactive active 1 0 1 inactive active inactive inactive inactive active 0 0 1 inactive active inactive active inactive inactive 0 1 1 inactive inactive active active inactive inactive 0 1 0 inactive inactive active inactive active inactive Slow down X X X inactive inactive inactive active active active Idle 2) X X X inactive inactive inactive inactive inactive inactive

On-Chip Peripheral Components User’s Manual 6-92 2001-05 Two tables are available for “rotate left” direction. The first table is identical to the one in C504 which has a 60 ° phase shift. It is selected if bit BCTSEL of SFR COTRAP is cleared. The second table has 0° phase shift, and it is selected if bit BCTSEL is set. After reset, the first table is selected by default. This option is provided as a feature so that a wider range of motors can be operated at optimum performance. In block commutation mode, any signal transition at INT0-2 generates a capture pulse for CAPCOM channel 0 (CCH0/CCL0), independently from the selected INT0-2 signal transition type as defined in the SFR TCON (for INT0 and INT1) and SFR T2CON (for INT2). 2) Idle state is also entered when a “wrong follower” is detected (if bit BCON.7 = BCEM is set). When idle state is entered, the BCERR flag is always set. Idle state can only be left when the BCERR flag is reset by software.

On-Chip Peripheral Components User’s Manual 6-94 2001-05

6.3.4.4 Compare Timer 1 Controlled Multi-Channel PWM Modes

Using the multi-channel PWM modes of the C508, several Compare Timer 1 controlled PWM waveforms can be generated: – 4-phase multi-channel PWM waveforms – 5-phase multi-channel PWM waveforms – 6-phase multi-channel PWM waveforms The basic waveforms of these three Compare Timer 1 controlled PWM modes are shown in the following three figures, Figure 6-37 to Figure 6-39. The figures show waveforms for different COINI values with the resulting active/inactive phases and rotate right / rotate left condition. All three figures assume that Compare Timer 1 operates with 100% duty cycle (compare and offset registers = 0000 H) and without Compare Timer 2 modulation. Compare Timer 1 duty cycles less than 100% or Compare timer 2 modulation in the multi-channel PWM modes are shown in Figure 6-34 and Figure 6-35. Figure 6-37 Basic Compare Timer 1 Controlled 4-Phase PWM Timing MCT02612 12341234 Start Compare Timer 1 CC0 COUT1 CC2 COUT2 State No. Low = Active Phase Phase Active High = State No. COUT2 CC2 COUT1 CC0 Timer 1 Compare Start 123412 4321 BTiming in rotate left mode (BCM1, 0 = 1, 0) with COINI XX111111 Timing in rotate right mode (BCM1, 0 = 0, 1) with COINI XX000000 B

On-Chip Peripheral Components User’s Manual 6-95 2001-05 Figure 6-38 Basic Compare Timer 1 Controlled 5-Phase PWM Timing MCT02614 1234512345 Start Compare Timer 1 CC0 COUT1 CC2 COUT0 COUT2 State No. Low = Active Phase Phase Active High = State No. COUT2 COUT0 CC2 COUT1 CC0 Timer 1 Compare Start 451234512 BTiming in rotate right mode (BCM1, 0 = 0, 1) with COINI XX000000b) Timing in rotate left mode (BCM1, 0 = 1, 0) with COINI XX111111 Ba)

On-Chip Peripheral Components User’s Manual 6-96 2001-05 Figure 6-39 Basic Compare Timer 1 Controlled 6-Phase PWM Timing MCT02615 12345612345 Start Compare Timer 1 CC0 COUT1 CC2 COUT0 CC1 COUT2 State No. Low = Active Phase Phase Active High = State No. COUT2 CC1 COUT0 CC2 COUT1 CC0 Timer 1 Compare Start 45612345612 BTiming in rotate right mode (BCM1, 0 = 0, 1) with COINI XX000000b) Timing in rotate left mode (BCM1, 0 = 1, 0) with COINI XX111111 Ba)

On-Chip Peripheral Components User’s Manual 6-97 2001-05 Table 6-11 to Table 6-13 show the basic signal pattern definitions of the three multi- channel PWM modes. They also include information about slow down mode and idle mode (bits BMC1, 0 = 0, 0 and 1, 1). Note: In the inactive phase the PWM outputs drive a logic state as defined by the related bits in register COINI. During the active phase, the PWM outputs can be modulated by CT1 and/or CT2. Note: In the inactive phase, the PWM outputs drive a logic state as defined by the related bits in register COINI. During the active phase, the PWM outputs can be modulated by CT1 and/or CT2. Table 6-11 4-Phase PWM Timing State Table Actual State and PWM Phase Follower State (No.) No. Output Signals BCM1, BCM0 = CC0 COUT1 CC2 COUT2 0, 1 1, 0 0, 0 1, 1 0 i n a c t i v e i n a c t i v e i n a c t i v e i n a c t i v e 2105 1 a c t i v e i n a c t i v e i n a c t i v e a c t i v e 4205 2 a c t i v e a c t i v e i n a c t i v e i n a c t i v e 1305 3 i n a c t i v e a c t i v e a c t i v e i n a c t i v e 2405 4 i n a c t i v e i n a c t i v e a c t i v e a c t i v e 3105 5 i n a c t i v e a c t i v e i n a c t i v e a c t i v e 2105 Table 6-12 5-Phase PWM Timing State Table Actual State and PWM Phase Follower State (No.) No. Output Signals BCM1, BCM0 = CC0 COUT1 CC2 COUT0 COUT2 0, 1 1, 0 0, 0 1, 1 0 i n a c t i v e i n a c t i v e i n a c t i v e i n a c t i v e i n a c t i v e 2106 1 a c t i v e i n a c t i v e i n a c t i v e i n a c t i v e a c t i v e 5206 2 a c t i v e a c t i v e i n a c t i v e i n a c t i v e i n a c t i v e 1306 3 i n a c t i v e a c t i v e a c t i v e i n a c t i v e i n a c t i v e 2406 4 i n a c t i v e i n a c t i v e a c t i v e a c t i v e i n a c t i v e 3506 5 i n a c t i v e i n a c t i v e i n a c t i v e a c t i v e a c t i v e 4106 6 i n a c t i v e a c t i v e i n a c t i v e a c t i v e a c t i v e 2106

On-Chip Peripheral Components User’s Manual 6-98 2001-05 Note: In the inactive phase, the PWM outputs drive a logic state as defined by the related bits in register COINI. During the active phase, the PWM outputs can be modulated by CT1 and/or CT2. Table 6-13 6-Phase PWM Timing State Table Actual State and PWM Phase Follower State (No.) No. Output Signals BCM1, BCM0 = CC0 COUT1 CC2 COUT0 CC1 COUT2 0, 1 1, 0 0, 0 1, 1 0 inactive inactive inactive inactive inactive inactive 2 1 0 7 1 active active inactive inactive inactive inactive 5 2 0 7 2 inactive active active inactive inactive inactive 1 3 0 7 3 inactive inactive active active inactive inactive 2 4 0 7 4 inactive inactive inactive active active inactive 3 5 0 7 5 inactive inactive inactive inactive active active 4 6 0 7 6 active inactive inactive inactive inactive active 5 1 0 7 7 inactive active inactive active inactive active 2 1 0 7

On-Chip Peripheral Components User’s Manual 6-99 2001-05

6.3.4.5 Software Controlled State Switching in Multi-Channel PWM

In the 4-/5-/6-phase multi-channel PWM modes, the Compare Timer 1 overflow controlled switching of the follower state can be switched off. Instead of the Compare Timer 1 overflow, a setting of bit NMCS in SFR CMSEL1 selects the follower state, which is defined in the Table 6-11 to Table 6-13. Bit ESMC in SFR CMSEL1 enables the software controlled state switching. If this software controlled 4-/5-/6-phase multi-channel PWM mode generation is selected, the Compare Timer 1 can be used for PWM signal generation (compare mode) in order to modulate the outputs. It can be further used, for example, for timer based interrupt generation. The waveforms of a PWM output signal in the multi-channel PWM modes can be selected as shown in Figure 6-34 (static low or high during active phase) or as shown in Figure 6-35 (Compare Timer 2 controlled modulation during active phase). Figure 6-40 shows for the 5-pole PWM timing the possible waveforms of the active phase when the software controlled state switching in the multi-channel PWM modes is selected.

On-Chip Peripheral Components User’s Manual 6-100 2001-05 Figure 6-40 Software Controlled State Switching in 5-Phase Multi-Channel PWM Mode Static Level during Active Phase: When bit ESMC in SFR CMSEL1 is set, static active or passive output levels during the active phase of a multi-phase PWM timing are generated when the following conditions are met: – The 16-bit offset register of Compare Timer 1 must be 0000 H (CT1OFH = CT1OFL = 00H) – static active: compare values = 0000 H static passive: compare values > period value – The bits CMSELx3 (x = 0-2) in the SFRs CMSEL0/CMSEL1 must be 0. The logic state of the inactive/active phases at the CCx and COUTx outputs is defined by the bits in SFR COINI. MCD04073 1Bit NMCS CC0 COUT1 CC2 COUT0 COUT2 State No. 1 2 3 4 1 2 3 4 5 1 Static level during active phase (at CCx and COUTx outputs) Compare timer 2 modulation during active phase (at CCx and COUTx output!) Setting bit NMCS by software 5-Phase Multi-Channel PWM Mode: Rotate Left Mode (BCM1, 0 = 1, 0) with COINI XX111111 B Active Phase

On-Chip Peripheral Components User’s Manual 6-101 2001-05 Compare Timer 2 Controlled Active Phase at COUTx: When bit ESMC in SFR CMSEL1 is set, Compare Timer 2 controlled output levels at COUTx during the active phase of a multi-pole PWM timing are generated when the following conditions are met: – The 16-bit offset register of Compare Timer 1 must be 0000H (CT1OFH = CT1OFL = 00H) – The 16-bit capture/compare registers must be 0000H (CCL0 = CCH0 = CCL1 = CCH1 = CCL2 = CCH2 = 00H) – Bits CMSELx3 (x = 0-2) in the SFRs CMSEL0/CMSEL1 must be set – Compare Timer 2 must be enabled and initialized for compare output signal generation Both, the CCx and the COUTx outputs can be controlled by Compare Timer 2. A combination of outputs modulated by Compare Timer 1 and/or Compare Timer 2 is supported.

6.3.4.6 Trap Function in Multi-Channel Block Commutation Mode

The trap function in block commutation mode is similar to the trap function described in Chapter 6.3.2.7, “Trap Function of the CAPCOM Unit in Compare Mode”. But there is one difference: when CTRAP becomes inactive (high), the CCx and COUTx outputs are again switched back to the PWM pulse generation when Compare Timer 2 reaches the count value 000H (instead of Compare Timer 1 in all other modes). All other trap functions of the multi-channel PWM modes are identical as described in Chapter 6.3.2.7.

On-Chip Peripheral Components User’s Manual 6-102 2001-05

6.4 Serial Interface

The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive register. (However, if the first byte still has not been read before reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes (one synchronous mode, three asynchronous modes). The baudrate clock for the serial port is derived from the oscillator frequency (Modes 0 and 2) or generated either by Timer 1 or a dedicated baudrate generator (Modes 1 and 3). Mode 0, Shift Register (Synchronous) Mode: Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted/received with the Least Significant Bit (LSB) first. The baudrate is fixed at 1/ 3 of the oscillator frequency (see Chapter 6.4.4 for more detailed information). Mode 1, 8-Bit USART, Variable Baudrate: Ten bits are transmitted through TxD or received through RxD: a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in special function register SCON. The baudrate in Mode 1 is variable (see Chapter 6.4.5 for more detailed information). Mode 2, 9-Bit USART, Fixed Baudrate: Eleven bits are transmitted through TxD or received through RxD: a start bit (0), 8 data bits (LSB first), a programmable 9 th bit, and a stop bit (1). On transmit, the 9 th data bit (TB8 in SCON) can be assigned to the value of ‘0’ or ‘1’. Alternatively, the parity bit (P, in the PSW) could be moved into TB8 an example. On receive, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is ignored. The baudrate is programmable to either 1/8 or 1/16 of the oscillator frequency (see Chapter 6.4.6 for more detailed information). Mode 3, 9-Bit USART, Variable Baudrate: Eleven bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baudrate. The baudrate in Mode 3 is variable (see Chapter 6.4.6 for more detailed information).

On-Chip Peripheral Components User’s Manual 6-103 2001-05 In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. The serial interface also provides interrupt requests when transmission or reception of a frame is completed. The corresponding interrupt request flags are TI or RI, respectively. See Chapter 7 for more details about the interrupt structure. The interrupt request flags, TI and RI, can also be used for polling the serial interface, if the serial interrupt is not to be used (that is, serial interrupt is not enabled).

6.4.1 Multiprocessor Communication

Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9 th bit goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One use of this feature in multiprocessor systems is described here. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9 th bit is ‘1’ in an address byte and ‘0’ in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves which were not being addressed keep their SM2s set and ignore the incoming data bytes. SM2 has no effect in Mode 0. In Mode 1, it can be used to check the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

6.4.2 Serial Port Registers

The serial port control and status register is the special function register SCON. This register contains not only the mode selection bits, but also the 9 th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). SBUF is the receive and transmit buffer of serial interface. Writing to SBUF loads the transmit register and initiates transmission. Reading out SBUF accesses a physically separate receive register.

On-Chip Peripheral Components User’s Manual 6-104 2001-05 Special Function Register SCON (Address 98H) Reset Value: 00 H Special Function Register SBUF (Address 99H) Reset Value: XX H Bit Function SM0 SM1 Serial Port 0 operating mode selection bits SM2 Enable serial port multiprocessor communication in Modes 2 and 3 In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit is not received. In Mode 0, SM2 should be 0. REN Enable receiver of serial port Set by software to enable serial reception. Cleared by software to disable serial reception. TB8 Serial port transmitter bit 9 TB8 is the 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by software as desired. RB8 Serial port receiver bit 9 In Modes 2 and 3, RB8 is the 9th data bit that is received. In Mode 1, if SM2 = 0, RB8 is the stop bit that is received. In Mode 0, RB8 is not used. 9FH 9EH 9DH 9CH 9BH 9AH 99H 98H SM0 SM1 SM2 REN98H SCON Bit No. MSB LSB TB8 RB8 TI RI 99H SBUF 76543210 Serial Interface Buffer Register SM0 SM1 Selected operating mode 0 0 Serial mode 0: Shift register, fixed baudrate ( fOSC/3) 0 1 Serial mode 1: 8-bit USART, variable baudrate 1 0 Serial mode 2: 9-bit USART, fixed baudrate ( fOSC/8 or fOSC/16) 1 1 Serial mode 3: 9-bit USART, variable baudrate

On-Chip Peripheral Components User’s Manual 6-105 2001-05 TI Serial port transmitter interrupt flag TI is set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. TI must be cleared by software. RI Serial port receiver interrupt flag RI is set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (exception see SM2). RI must be cleared by software. Bit Function

On-Chip Peripheral Components User’s Manual 6-106 2001-05

6.4.3 Baudrate Generation

There are several possibilities to generate the baudrate clock for the serial port, depending on the mode in which it is operating. To clarify the terminology, something should be said about the difference between “baudrate clock” and “baudrate”. The serial interface requires a clock rate which is 16 times the baudrate for internal synchronization. Therefore, the baudrate generators must provide a “baudrate clock” to the serial interface which - there divided by 16 - results in the actual “baudrate”. However, all formulae given in the following section already include the factor and calculate the final baudrate. The baudrate of the serial port is controlled by two bits which are located in the special function registers as shown below. Special Function Register ADCON0 (Address D8 H) Reset Value: 00X00000 B Special Function Register PCON (Address 87H) Reset Value: 00 H Note: Bit CLK of SFR ADCON0 must be written with a ‘0’. Bit Function BD Baudrate generator enable When set, the baudrate of the serial interface is derived from the dedicated baudrate generator. When cleared (default after reset), baudrate is derived from the timer 1 overflow rate. SMOD Double baudrate When set, the baudrate of serial interface in Modes 1, 2, 3 is doubled. After reset this bit is cleared. – Reserved bits for future use. Read by CPU returns undefined values. SMOD PDS IDLS SD87H PCON Bit No. MSB LSB GF1 GF0 PDE IDLE 76543210 BD CLK – BSYD8H ADCON0ADM MX2 MX1 MX0 DFH DEH DDH DCH DBH DAH D9H D8H The shaded bits are not used for controlling the baudrate.

On-Chip Peripheral Components User’s Manual 6-107 2001-05 Figure 6-41 shows the configuration for the baudrate generation of the serial port. Figure 6-41 Baudrate Generation for the Serial Port Depending on the programmed operating mode different paths are selected for the baudrate clock generation. Figure 6-41 shows the dependencies of the serial port baudrate clock generation on the two control bits and from the mode which is selected in the special function register SCON.

6.4.3.1 Baudrate in Mode 0

The baudrate in Mode 0 is fixed to:

6.4.3.2 Baudrate in Mode 2

The baudrate in Mode 2 depends on the value of bit SMOD in special function register PCON. If SMOD = 0 (which is the value after reset), the baudrate is 1/16 of the oscillator frequency. If SMOD = 1, the baudrate is 1/8 of the oscillator frequency. MCS04074 SCON.7/ SCON.6 (SM0/SM1) Mode 1 Mode 3 Mode 2 Mode 0 2fOSC Timer 1 Overflow Only one mode can be selected PCON.7 (SMOD) ÷ 2 Baudrate Clock Note: The switch configuration shows the reset state ADCON0.7 (BD) Baudrate Generator (SRELH SRELL) ÷ 6 Mode 0 baudrate = oscillator frequency Mode 2 baudrate = oscillator frequency

2 SMOD

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6.4.3.3 Baudrate in Mode 1 and 3

In these modes the baudrate is variable and can be generated alternatively by a baudrate generator or by Timer 1.

6.4.3.3.1 Using the Internal Baudrate Generator

In Modes 1 and 3, the C508 can use an internal baudrate generator for the serial port. To enable this feature, bit BD (bit 7 of special function register ADCON0) must be set. Bit SMOD (PCON.7) controls a divide-by-2 circuit which affect the input and output clock signal of the baudrate generator. After reset the divide-by-2 circuit is active and the resulting overflow output clock will be divided by 2. The input clock of the baudrate generator is 2 × fOSC (output of PLL). Figure 6-42 Serial Port Input Clock when using the Baudrate Generator The baudrate generator consists of a free running upward counting 10-bit timer. On overflow of this timer (next count step after counter value 3FF H) there is an automatic 10-bit reload from the registers SRELL and SRELH. The lower 8 bits of the timer are reloaded from SRELL, while the upper two bits are reloaded from bit 0 and 1 of register SRELH. The baudrate timer is reloaded by writing to SRELL. MCS04075 PCON.7 (SMOD) ÷ 2 Baudrate Clock0 SRELH SRELL.1 .0 Baudrate Generator 10-Bit Timer Overflow Input Clock2fOSC

On-Chip Peripheral Components User’s Manual 6-109 2001-05 Special Function Register SRELH (Address BAH) Reset Value: XXXXXX11 B Special Function Register SRELL (Address AAH) Reset Value: D9 H After reset, SRELH and SRELL have a reload value of 3D9H. With this reload value, the baudrate generator has an overflow rate of (input clock)/39. With 10 MHz oscillator frequency, a reload value of 37EH is required to achieve the commonly used baudrates of 4800 baud (SMOD = 0) and 9600 baud (SMOD = 1) at a deviation of 0.16%. With the baudrate generator as clock source for the serial port in Modes 1 and 3, the baudrate can be determined as follows: Bit Function SRELH.0-1 Baudrate generator reload high value Upper two bits of the baudrate timer reload value. SRELL.0-7 Baudrate generator reload low value Lower 8 bits of the baudrate timer reload value. – Reserved bits for future use. Read by CPU returns undefined values. AAH SRELL Bit No. MSB LSB LSB BAH SRELHMSB 76543210 The shaded bits are not used for reload operation. Mode 1, 3 baudrate = 16 × (baudrate generator overflow rate) 2SMOD × oscillator frequency Baudrate generator overflow rate = 210 - SREL with SREL = SRELH.1 - 0, SRELL.7 - 0

On-Chip Peripheral Components User’s Manual 6-110 2001-05

6.4.3.3.2 Using Timer 1 to Generate Baudrates

When Timer 1 is used as the baudrate generator in Modes 1 and 3, the baudrates are determined by the Timer 1 overflow rate and the value of SMOD as follows: The Timer 1 interrupt should be disabled in this application. Timer 1, itself, can be configured for either “timer” or “counter” operation, and in any of its operating modes. In most typical applications, it is configured for “timer” operation in the auto-reload mode (high nibble of TMOD = 0010B). In this case the baudrate is given by the formula: Very low baudrates can be achieved with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the timer to run as 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt for a 16-bit software reload. Mode 1, 3 baudrate = (Timer 1 overflow rate)32 2SMOD Mode 1, 3 baudrate = 2SMOD × oscillator frequency

On-Chip Peripheral Components User’s Manual 6-111 2001-05

6.4.4 Details about Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted/received with the LSB first. The baudrate is fixed at fOSC/3. Figure 6-43 shows a simplified functional diagram of the serial port in Mode 0. The associated timing is illustrated in Figure 6-44. Transmission is initiated by any instruction that uses SBUF as a destination register. The “Write-to-SBUF” signal at S6P2 also loads a ‘1’ into the 9th position of the transmit shift register and tells the TX control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between “Write-to-SBUF”, and activation of SEND. SEND enables the output of the shift register to the alternative output function line of P3.0, and also enables SHIFT CLOCK to the alternative output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1 and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register are shifted to the right one position. As data bits shift out to the right, ‘0’s come in from the left. When the Most Significant Bit (MSB) of the data byte is at the output position of the shift register, the ‘1’ that was initially loaded into the 9 th position is just to the left of the MSB, and all positions to the left of that contain ‘0’s. This condition flags the TX control block to do one last shift and then deactivate SEND and set TI. Both of these actions occur at S1P1 of the 10 th machine cycle after “Write-to-SBUF”. Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 of the next machine cycle, the RX control unit writes the bits “1111 1110” to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternative output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bit comes in from the right, ‘1’s shift out to the left. When the ‘0’ which was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX control block to do one last shift and load SBUF. At S1P1 of the 10 th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set.

On-Chip Peripheral Components User’s Manual 6-112 2001-05 Figure 6-43 Serial Interface, Mode 0, Functional Diagram MCS02101 Internal Bus SBUF Zero Detector D S CLK Q Shift Send TX Control Start TX Clock TI RX Control Start RI Receive Shift Serial Port Interrupt Input Shift Register SBUF Internal Bus Write to SBUF ShiftLoad SBUF Read SBUF RXD P3.0 Alt. Output Function Function Output P3.1 Alt. TXD Shift Clock REN RI RX Clock Function Input P3.0 Alt. RXD 01 111111 Shift Baud Rate Clock

On-Chip Peripheral Components User’s Manual 6-113 2001-05 Figure 6-44 Serial Interface, Mode 0, Timing Diagram S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S D0 D1 D2 D3 D4 D5 D6 D7 ALE Write to SBUF Send Shift RXD (Data Out) S6P2 TXD (Shift Clock) S3P1 S6P1 Write to SCON (Clear RI) Shift Receive RI RXD (Data In) TXD (Shift Clock) D0 D1 D2 D3 D4 D5 D6 D7 S5P TI MCT02102 ReceiveTransmit

On-Chip Peripheral Components User’s Manual 6-114 2001-05

6.4.5 Details about Mode 1

Ten bits are transmitted through TxD or received through RxD: a start bit (0), eight data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The baudrate is determined either by the Timer 1 overflow rate or by the internal baudrate generator. Figure 6-45 shows a simplified functional diagram of the serial port in Mode 1. Timing associated with transmit and receive is illustrated in Figure 6-46. Transmission is initiated by an instruction that uses SBUF as a destination register. The “Write-to-SBUF” signal also loads a ‘1’ into the 9 th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission starts at the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “Write-to-SBUF” signal). The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, ‘0’s are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the ‘1’ which was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain ‘0’s. This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after “Write-to- SBUF”. Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of sixteen times the established baudrate. When a transition is detected, the divide-by-16 counter is immediately reset. The input shift register is written with 1FF H and reception of the rest of the frame will proceed. The sixteen states of the counter divide each bit time into 16 ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least two of the three samples. This is done for the noise rejection. If the value accepted during the first bit time is not ‘0’, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection or false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, ‘1’s shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which in Mode 1 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0, and 2. either SM2 = 0, or the received stop bit = 1

On-Chip Peripheral Components User’s Manual 6-115 2001-05 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the eight data bits go into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit resumes looking for a 1-to-0 transition in RxD.

On-Chip Peripheral Components User’s Manual 6-116 2001-05 Figure 6-45 Serial Interface, Mode 1, Functional Diagram MCS02103 Internal Bus SBUF Zero Detector D S CLK Q Data Send 1-to-0 Transition Detector TX Control ShiftStart TX Clock RX ControlStart Load Shift SBUF Sample Bit Detector (9Bits) Input Shift Register 1FF SBUF Internal Bus Write to SBUF TXD Baud Rate Clock RXD Shift Load SBUF Read SBUF ÷ 16 ÷ 16 RX Interrupt Port Serial 1 TI RI H

On-Chip Peripheral Components User’s Manual 6-117 2001-05 Figure 6-46 Serial Interface, Mode 1, Timing Diagram MCT02104 to SBUF D7 Stop BitD6D5D4D3D2D1D0Start Bit TI TXD Shift Data S1P1 Send D0Start Bit D1 D2 D3 D4 D5 D6 D7 Stop Bit ÷ 16 Reset Receive Transmit Write TX Clock Clock RX RXD Sample Times Bit Detector Shift RI

On-Chip Peripheral Components User’s Manual 6-118 2001-05

6.4.6 Details about Modes 2 and 3

Eleven bits are transmitted through TxD or received through RxD: a start bit (0), eight data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB8) can be assigned the value of ‘0’ or ‘1’. On reception, the 9 th data bit goes into RB8 in SCON. The baudrate is programmable to either 1/16 or 1/32 the oscillator frequency in Mode 2 (When bit SMOD in SFR PCON (87H) is set, the baudrate is fOSC/16). In Mode 3, the baudrate clock is generated by Timer 1, which is incremented by a rate of fOSC/6 or by the internal baudrate generator. Figure 6-47 shows a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register. The associated timings for transmit/receive are illustrated in Figure 6-48. Transmission is initiated by any instruction that uses SBUF as a destination register. The “Write-to-SBUF” signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission starts at the next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the “Write-to-SBUF” signal.) Transmission begins with the activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a ‘1’ (the stop bit) into the 9 th bit position of the shift register. Thereafter, only ‘0’s are clocked in. Thus, as data bits shift out to the right, ‘0’s are clocked in from the left. When TB8 is at the output position of the shift register, the stop bit is just to the left of TB8, and all positions to the left of that contain ‘0’s. This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after “Write-to-SBUF”. Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times the established baudrate. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FF H is written to the input shift register. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least two of the three samples. If the value accepted during the first bit time is not ‘0’, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bit come from the right, ‘1’s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and to set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated:

On-Chip Peripheral Components User’s Manual 6-119 2001-05 1. RI = 0, and 2. Either SM2 = 0 or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first eight data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit resumes looking for a 1-to-0 transition at the RxD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8 or RI.

On-Chip Peripheral Components User’s Manual 6-120 2001-05 Figure 6-47 Serial Interface, Mode 2 and 3, Functional Diagram MCS02105 Internal Bus TB8 SBUF Zero Detector D S CLK Q Data Send 1-to-0 Transition Detector ÷ 16 TX Control ShiftStart TX Clock TI RX ControlStart RI Load Shift SBUF RX Clock Serial Port Interrupt Sample Bit Detector (9Bits) Input Shift Register 1FF SBUF Internal Bus Write to SBUF TXD Baud Rate Clock RXD Shift Load SBUF Read SBUF ÷ 16 Stop Bit Generation

On-Chip Peripheral Components User’s Manual 6-121 2001-05 Figure 6-48 Serial Interface, Mode 2 and 3, Timing Diagram MCT02587 Write to SBUF TX Clock D7 TB8 Stop BitD6D5D4D3D2D1D0Start Bit Stop Bit Gen. TI TXD Shift Data Mode 2 : S6P1 Send RX Clock RX D0Start Bit D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Bit Detector Sample Times Shift RI ÷ 16 Reset Receive Transmit Mode 3 : S1P1

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6.5 A/D Converter

The C508 includes a high performance / high speed 10-bit A/D Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D Converter provides the following features: – 8 input channels (Port 4), which can also be used as digital inputs – 10-bit resolution – Single or continuous conversion mode – Internal start-of-conversion trigger capability – Interrupt request generation after each conversion – Using successive approximation conversion technique via a capacitor array – Built-in hidden calibration of offset and linearity errors The externally applied reference voltages must be held at a fixed value within the specifications. The main functional blocks of the A/D Converter are shown in Figure 6-49.

6.5.1 A/D Converter Operation

An internal start of a single A/D conversion is triggered by a write-to-ADDATL instruction. The start procedure itself is independent of the value which is written to ADDATL. When single conversion mode is selected (bit ADM = 0) only one A/D conversion is performed. In continuous mode (bit ADM = 1), a new A/D conversion is triggered automatically upon completion of a previous conversion, until bit ADM is reset. The busy flag BSY (ADCON0.4) is automatically set when an A/D conversion is in progress. After completion of the conversion, it is reset by hardware. This flag is read only; a write has no effect. The interrupt request flag IADC (IRCON.0) is set when an A/ D conversion is completed. The bits MX0 to MX2 in special function register ADCON0 and ADCON1 are used for selection of the analog input channel. The bits MX0 to MX2 are represented in both registers ADCON0 and ADCON1; however these bits are present only once. Therefore, there are two methods of selecting an analog input channel. If a new channel is selected in ADCON1, the change is automatically done in the corresponding bits MX0 to MX2 in ADCON0; and vice versa. Port 4 is an input port. These pins can be used either for digital input functions or as the analog inputs of the A/D Converter. If less than 8 analog inputs are required, the unused inputs are free for digital input functions. Any unused inputs should be connected to VSSA.

On-Chip Peripheral Components User’s Manual 6-123 2001-05 Figure 6-49 Block Diagram of the A/D Converter MCB04076 IEN1 (B8H) IRCON (C0H) P4 (DBH) ADCON1 (DCH) ADCON0 (D8H) P4.7 ADCL1 BD SWDT EX6 EX5 EX4 EX3 EX2 EADC TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC ADCL0 - - - MX2 MX1 MX0 CLK - BSY ADM MX2 MX1 MX0 MCB A/D Converter ADDATH (D9H) ADDATL (DAH) S&HMUX Clock Prescaler ÷ 32, 16, 8, 4 2fOSC LSB Internal Bus Internal Bus Conversion Clock fADC Input Clock fIN VAREF VAGND Start of conversion Write to ADDATL Single/ Continuous Mode Port 4 Shaded bit locations are not used in ADC-functions.

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6.5.2 A/D Converter Registers

This section describes the bits/functions of all registers which are used by the A/D Converter. Special Function Register ADDATH (Address D9H) Reset Value: 00 H Special Function Register ADDATL (Address DAH) Reset Value: 00XXXXXX B The registers ADDATH and ADDATL hold the 10-bit conversion result in left justified data format. The most significant bit of the 10-bit conversion result is bit 7 of ADDATH. The least significant bit of the 10-bit conversion result is bit 6 of ADDATL. To get a 10-bit conversion result, both ADDAT registers must be read. If an 8-bit conversion result is required, only the reading of ADDATH is necessary. The data remains in ADDAT until it is overwritten by the next converted data. ADDAT can be read or written under software control. lf the A/D Converter of the C508 is not used, register ADDATH can be used as an additional general purpose register. 76543210 D9H ADDATH LSBDAH ADDATL Bit No. MSB LSB MSB .1 .0

On-Chip Peripheral Components User’s Manual 6-125 2001-05 Special Function Register ADCON0 (Address D8H) Reset Value: 00X00000 B Special Function Register ADCON1 (Address DCH) Reset Value: 01XXX000 B The shaded bits are not used for A/D Converter control. Bit Function – Reserved bits for future use BSY Busy flag This flag indicates whether a conversion is in progress (BSY = 1). The flag is cleared by hardware when the conversion is completed. ADM A/D conversion mode When set, continuous A/D conversion is selected. If cleared during a running A/D conversion, the conversion is stopped at its end. MX2 - MX0 A/D Converter input channel select bits Bits MX2-0 can be written or read either in ADCON0 or ADCON1. The channel selection done by writing to ADCON 1(0) overwrites the selection in ADCON 0(1) when ADCON 1(0) is written after ADCON 0(1). The analog inputs are selected according the following table: 76543210 – BSY ADM MX2 MX1 MX0D8H ADCON0 ADCL1 MX2 MX1 MX0DCH ADCON1 Bit No. MSB LSB ADCL0 CLKBD –– – MX2 MX1 MX0 Selected Analog Input 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 P4.0 / AN0 P4.1 / AN1 P4.2 / AN2 P4.3 / AN3 P4.4 / AN4 P4.5 / AN5 P4.6 / AN6 P4.7 / AN7

On-Chip Peripheral Components User’s Manual 6-126 2001-05 Note: Generally, before entering the power-down mode, an A/D conversion in progress must be stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit or waiting for the A/D conversion interrupt. In continuous conversion mode, bit ADM must be cleared and the last A/D conversion must be terminated before entering the power-down mode. Note: Bit CLK of SFR ADCON0 must be written with a ‘0’. A single A/D conversion is started by writing to SFR ADDATL with dummy data. A continuous conversion is started under the following conditions: – By setting bit ADM during a running single A/D conversion – By setting bit ADM when at least one A/D conversion has occurred after the last reset operation. – By writing ADDATL with dummy data after bit ADM has been set (if no A/D conversion has occurred after the last reset operation). When bit ADM is reset by software in continuous conversion mode, the current A/D conversion in progress will not be interrupted; it will be completed as the last conversion. ADCL1 ADCL0 A/D Converter clock prescaler selection ADCL1 and ADCL0 select the prescaler ratio for the A/D conversion clock fADC. Depending on the clock rate fOSC of the C508, fADC must be adjusted in a way that the resulting conversion clock fADC is less than or equal to 2 MHz (see Chapter 6.5.3). The prescaler ratio is selected according to the following table: Bit Function ADCL1 ADCL0 Prescaler Ratio divide by 4 divide by 8 (default after reset) divide by 16 divide by 32

On-Chip Peripheral Components User’s Manual 6-127 2001-05 The A/D Converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON. Special Function Register IEN1 (Address B8H) Reset Value: X0000000 B Special Function Register IRCON (Address C0H) Reset Value: X0000000 B The shaded bits are not used for A/D Converter control. Bit Function EADC Enable A/D Converter interrupt If EADC = 0, the A/D Converter interrupt is disabled. IADC A/D Converter interrupt request flag Set by hardware at the end of an A/D conversion. Must be cleared by software. C7H C6H C5H C4H C3H C2H C1H C0H IEX6 IEX5 IEX4 IEX3 IEX2 IADCC0H IRCONTF2− − SWDT EX6 EX5B8H IEN1 Bit No. BFH MSB LSB EX4 EX3 EX2 EADC BEH BDH BCH BBH BAH B9H B8H

On-Chip Peripheral Components User’s Manual 6-128 2001-05

6.5.3 A/D Converter Clock Selection

The ADC uses two clock signals for operation: the conversion clock fADC (= 1/tADC) and the input clock fIN (= 1/tIN). fADC is derived from the C508 system clock, 2 × fOSC, which is twice the crystal frequency applied at the XTAL pins via the ADC clock prescaler as shown in Figure 6-50. The input clock fIN is equal to 2 × fOSC. The conversion clock fADC is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which ensures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. The table in Figure 6-50 shows the prescaler ratio which must be selected by ADCL1 and ADCL0 for typical system clock rates. Up to 8 MHz external crystal frequency, the selected prescaler ratio must be at least 8. Between 8 MHz and 10 MHz, a prescaler ratio of at least 16 must be selected. A prescaler ratio of 32 can used for any of the above frequency ranges. A prescaler ratio of 4 should be used only when the C508 is operating in slowdown mode. Figure 6-50 A/D Converter Clock Selection MUX ÷ 4 ÷ 8 ÷ 16 ÷ 32 Conversion Clock fADC A/D Converter 2fOSC ADCL0ADCL1 fADC max = 2 MHzCondition: fIN = 2fOSC = 4 TCL1) fADC [MHz] MCB04102 Oscillator Clock Rate (fOSC) fIN [MHz] Prescaller Ratio

5 MHz

8 MHz

10 MHz

÷ 8 ÷ 8 ÷ 16 1.25 1.25 Input Clock fIN 1) Note: Please refer to the C508 Data Sheet for the definition of TCL.

On-Chip Peripheral Components User’s Manual 6-129 2001-05 The duration of an A/D conversion is a multiple of the period of the fIN clock signal. The calculation of the A/D conversion time is shown in the next section.

6.5.4 A/D Conversion Timing

An A/D conversion is started by writing into the SFR ADDATL with dummy data. A write to SFR ADDATL will start a new conversion even if a conversion is currently in progress. The conversion begins with the next machine cycle, and the BSY flag in SFR ADCON0 will be set. The A/D conversion procedure is divided into three parts: – Sample phase ( tS), used for sampling the analog input voltage. – Conversion phase (tCO), used for the real A/D conversion (includes calibration). – Write result phase ( tWR), used for writing the conversion result into the ADDAT registers. The total A/D conversion time is defined by tADCC which is the sum of the two phase times tS and tCO. The duration of the three phases of an A/D conversion is specified by their corresponding timing parameter as shown in Figure 6-51. Figure 6-51 A/D Conversion Timing tADCC MCT04078 BSY Bit Sample Phase Conversion Phase Start of an AD conversion Result is written into ADDAT tS tCO tWR Write Result Phase tADCC tWR = tINA/D Conversion Time Cycle Time tADCC = tS + tCO PS = Prescaler value Prescaler Ratio (= PS) tS tCO 64 x tIN 32 x tIN 16 x tIN 8 x tIN 320 x tIN 160 x tIN 80 x tIN 40 x tIN 384 x tIN 192 x tIN 96 x tIN 48 x tIN

On-Chip Peripheral Components User’s Manual 6-131 2001-05 Depending on the selected prescaler ratio (see Figure 6-50), three different relationships between machine cycles and A/D conversion are possible. The A/D conversion is started when SFR ADDATL is written with dummy data. This write operation may take one or two machine cycles. In Figure 6-52, the instruction MOV ADDATL,#0 starts the A/D conversion (machine cycle X-1 and X). The total A/D conversion (sample, conversion, and calibration phase) is finished with the end of the 8th, 16th, 32nd, or 64th machine cycle after the A/D conversion start. In the next machine cycle, the conversion result is written into the ADDAT registers; and this result can be read in the same cycle (for example, MOV A, ADDATL). If continuous conversion is selected (bit ADM set), the next conversion is started with the beginning of the machine cycle which follows the write result cycle. The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the beginning of the write result cycle. If continuous conversion is selected, BSY is set again with the beginning of the machine cycle which follows the write result cycle. The interrupt flag IADC is set at the end of the A/D conversion. If the A/D Converter interrupt is enabled and the A/D Converter interrupt is prioritized to be serviced immediately, the first instruction of the interrupt service routine will be executed in the third machine cycle which follows the write result cycle. IADC must be reset by software. Depending on the application, typically there are three methods to handle the A/D conversion in the C508. – Software delay The machine cycles of the A/D conversion are counted and the program executes a software delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. This is the fastest method to get the result of an A/D conversion. – Polling BSY bit The BSY bit is polled and the program waits until BSY = 0. Attention: a polling JB instruction which is two machine cycles long, possibly may not recognize the BSY = 0 condition during the write result cycle in the continuous conversion mode. – A/D conversion interrupt After the start of an A/D conversion the A/D Converter interrupt is enabled. The result of the A/D conversion is read in the interrupt service routine. If other C508 interrupts are enabled, the interrupt latency must be regarded. Therefore, this software method is the slowest method to get the result of an A/D conversion. Depending on the oscillator frequency of the C508 and the selected divider ratio of the conversion clock prescaler, the total time of an A/D conversion is calculated according to Figure 6-51 and Table 6-14. Figure 6-53 on the next page shows the minimum A/D conversion time in relation to the oscillator frequency fOSC. The minimum conversion time is 6 µs and can be achieved at fOSC of 8 (or whenever fADC = 2 MHz).

On-Chip Peripheral Components User’s Manual 6-132 2001-05 Note: The prescaler ratios in Table 6-14 are minimum values. Figure 6-53 Minimum A/D Conversion Time in Relation to Oscillator Clock Table 6-14 A/D Conversion Time for Dedicated System Clock Rates fOSC [MHz] Prescaler Ratio PS fADC [MHz] Sample Time tS [µs] Total Conversion Time tADCC [µs] 5 MHz ÷ 8 1.25 1.6 9.6 6 MHz ÷ 8 1.5 1.33 8

8 MHz ÷ 82 1 6

10 MHz ÷ 16 1.25 1.6 9.6 MCT04080 56789 1 0 fOSCMHz tADCC µs ÷ 8 ÷ 16 tADCCmin = 6 µs

On-Chip Peripheral Components User’s Manual 6-133 2001-05

6.5.5 A/D Converter Calibration

The C508 A/D Converter includes hidden internal calibration mechanisms which assure a safe functionality of the A/D Converter according to the DC characteristics. The A/D Converter calibration is implemented in a way that a user program which executes A/D conversions is not affected by its operation. Further, the user program has no control over the calibration mechanism. The calibration itself executes two basic functions: – Offset calibration: correction of offset errors of comparator and the capacitor network – Linearity calibration: correction of the binary-weighted capacitor network The A/D Converter calibration operates in two phases. The first phase is the calibration after a reset operation and the second is the calibration at each A/D conversion. The calibration phases are controlled by a state machine in the A/D Converter. This state machine executes the calibration phases and stores the calibration results dynamically in a small calibration RAM. After a reset operation, the A/D calibration is automatically started. In this reset calibration phase which takes 3328 fADC clocks, alternating offset and linearity calibration is executed. Therefore, at 8 MHz oscillator frequency, and with a default prescaler value of 8, a reset calibration time of approximately 1.664 ms is reached. For achieving a proper reset calibration, the fADC prescaler value must satisfy the condition fADC max ≤ 2 MHz. If this condition is not met, at a specific oscillator frequency with the default prescaler value after reset, the fADC prescaler must be adjusted immediately after reset by setting bits ADCL1 and ADCL0 in SFR ADCON1 to a suitable value. It is also recommended to have the proper voltages, as specified in the Data Sheet, applied at the VAREF and VAGND pins before the reset calibration has started. After the reset calibration phase, the A/D Converter is calibrated according to its DC characteristics. Nevertheless, during the reset calibration phase, single or continuous A/ D conversion can be executed. In this case, it must be regarded that the reset calibration is interrupted and continued after the end of the A/D conversion. Therefore, interrupting the reset calibration phase by A/D conversions extends the total reset calibration time. If the specified total unadjusted error (TUE) needs to be valid for an A/D conversion, it is recommended to start the first A/D conversion after reset when the reset calibration phase has been completed. Depending on the oscillator frequency used, the reset calibration phase can be possibly shortened by setting ADCL1 and ADCL0 (prescaler value) to its final value immediately after reset. After the reset calibration, a second calibration mechanism is initiated. This calibration is coupled to each A/D conversion. With this second calibration mechanism, alternatively, offset and linearity calibration values, which are stored in the calibration RAM, are checked when an A/D conversion is executed. These values are corrected if required.

User’s Manual 7-1 2001-05

7 Interrupt System

The C508 provides nineteen interrupt vectors with four priority levels. Nine interrupt requests are generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, Serial Channel, A/D Converter, and the Capture/Compare Unit with four interrupts); ten interrupts may be triggered externally. Four of the external interrupts (INT3 , INT4, INT5 and INT6) can also be generated by Timer 2 in the capture/compare mode. The wake-up from power-down mode interrupt has a special functionality which allows the software power-down mode to be terminated by a short negative pulse at pins P3.2/ INT0 or P5.7/INT7. The nineteen interrupt sources are divided into six groups. Each group can be programmed to one of the four interrupt priority levels.

7.1 Structure of the Interrupt System

Figure 7-1 through Figure 7-5 provide a general overview of the interrupt sources and illustrate the request and control flags described in the following sections.

User’s Manual 7-2 2001-05 Figure 7-1 Interrupt Structure, Overview Part 1 MCS04081 EX2 IEN1.1 IEX2 IRCON.1I2FR T2CON.5 P5.4/ INT2 0043H 0003H Highest Priority Level Polling Sequence EA IEN0.7 IP1.1 IP0.1 000BH 004BH Bit Addressable Request flag is cleared by hardware EX0 IEN0.0 IE0 TCON.1IT0 TCON.0 P3.2/ INT0 EADC IEN1.0 IADC IRCON.0 A/D Converter IP1.0 IP0.0 ET0 IEN0.1 TF0 TCON.5 Timer 0 Overflow Lowest Priority Level

User’s Manual 7-3 2001-05 Figure 7-2 Interrupt Structure, Overview Part 2 MCS04082 P5.0/ T2CC0/ INT3 EX7 IEX7 EINT.1I7FR EINT.0 P5.7/ INT7 0093H 0013H Highest Priority Level Lowest Priority Level EA IEN0.7 IP1.2 IP0.2 0053H 00D3H Bit Addressable Request flag is cleared by hardware EX3 IEN1.2 IEN3.2 IEX3 IRCON.2I3FR T2CON.6 ECEM IEN2.2 ETRP CT1CON.6 EBCE BCON.4 TRF TRCON.6 BCERR BCON.3 CCU Emergency Interrupt EX1 IEN0.2 IE1 TCON.3IT1 TCON.2 P3.3/ INT1 Polling Sequence

User’s Manual 7-4 2001-05 Figure 7-3 Interrupt Structure, Overview Part 3 MCS04083 EX8 IEX8 EINT.3I8FR EINT.2 P5.6/ INT8 009BH 001BH Highest Priority Level Lowest Priority Level EA IEN0.7 IP1.3 IP0.3 005BH 00DBH Bit Addressable Request flag is cleared by hardware ET1 IEN0.3 TF1 TCON.7 Timer 1 Overflow ECT2 IEN2.3 CT2P CT2CON.7 Compare Timer 2 Interrupt P5.1/ T2CC1/ INT4 EX4 IEN1.3 IEN3.3 IEX4 IRCON.3 Polling Sequence

User’s Manual 7-5 2001-05 Figure 7-4 Interrupt Structure, Overview Part 4 MCS04084 ES IEN0.4 ES SCON.1 SCON.0USART CC0REN CCIE0.0 CC0R CCIR.0 CC0FEN CCIE0.1 CC0F CCIR.1 P1.2/ CC0 CC1REN CCIE0.2 CC1R CCIR.2 CC1FEN CCIE0.3 CC1F CCIR.3 P1.4/ CC1 CC2REN CCIE0.4 CC2R CCIR.4 CC2FEN CCIE0.5 CC2F CCIR.5 P1.6/ CC2 ECCM IEN2.4 Capture/Compare Match Interrupt EX5 IEN1.4 IEN3.4 IEX5 IRCON.4 P5.2/ T2CC2/ INT5 EX9 IEX9 EINT.5I9FR EINT.4 P5.5/ INT9 00A3H 0023H Highest Priority Level Lowest Priority Level EA IEN0.7 IP1.4 IP0.4 0063H 00E3H Bit Addressable Request flag is cleared by hardware RI Polling Sequence

User’s Manual 7-6 2001-05 Figure 7-5 Interrupt Structure, Overview Part 5 MCS04085 P5.3/ T2CC3/ INT6 00ABH 002BH Highest Priority Level Lowest Priority Level Polling Sequence EA IEN0.7 IP1.5 IP0.5 006BH Bit Addressable Request flag is cleared by hardware EX6 IEN1.5 IEX6 IRCON.5 ECT1 IEN2.5 ECTP CCIE.7 ECTC CCIE.6 CT1FP CCIR.7 CT1FC CCIR.6 Compare Timer 1 Interrupt ET2 IEN0.5 TF2 IRCON.6 Timer 2 Overflow

User’s Manual 7-7 2001-05

7.2 Interrupt Registers

7.2.1 Interrupt Enable Registers

Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the Interrupt Enable Registers IEN0, IEN1, IEN2 and IEN3. Register IEN0 also contains the global disable bit (EA), which can be cleared to disable all interrupts at once. Generally, all interrupt enable bits are cleared to 0 after reset; the corresponding interrupts are disabled. The SFR IEN0 contains the enable bits for the external interrupts 0 and 1, the timer interrupts, and the USART interrupt. Special Function Register IEN0 (Address A8 H) Reset Value: 00 H Bit Function EA Enable/disable all interrupts If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ET2 Timer 2 overflow/external reload interrupt enable If ET2 = 0, the Timer 2 interrupt is disabled. If ET2 = 1, the Timer 2 interrupt is enabled. ES Serial channel (USART) interrupt enable If ES = 0, the Serial Channel Interrupt 0 is disabled. If ES = 1, the Serial Channel Interrupt 0 is enabled. ET1 Timer 1 overflow interrupt enable If ET1 = 0, the Timer 1 interrupt is disabled. If ET1 = 1, the Timer 1 interrupt is enabled. EX1 External interrupt 1 enable If EX1 = 0, the external interrupt 1 is disabled. If EX1 = 1, the external interrupt 1 is enabled. EA WDT ET2 ESA8H IEN0 Bit No. AF H MSB LSB ET1 EX1 ET0 EX0 AEH ADH ACH ABH AAH A9H A8H The shaded bits are not used for interrupt control.

User’s Manual 7-8 2001-05 ET0 Timer 0 overflow interrupt enable If ET0 = 0, the timer 0 interrupt is disabled. If ET0 = 1, the timer 0 interrupt is enabled. EX0 External interrupt 0 enable If EX0 = 0, the external interrupt 0 is disabled. If EX0 = 1, the external interrupt 0 is enabled. Bit Function

User’s Manual 7-9 2001-05 The SFR IEN1 contains the enable bits for the external interrupts 2 to 6, and the A/D Converter interrupt. Special Function Register IEN1 (Address B8H) Reset Value: X0000000 B Bit Function EX6 External interrupt 6/Timer 2 capture/compare interrupt 3 enable If EX6 = 0, external interrupt 6 is disabled. If EX6 = 1, external interrupt 6 is enabled. EX5 External interrupt 5/Timer 2 capture/compare interrupt 2 enable If EX5 = 0, external interrupt 5 is disabled. If EX5 = 1, external interrupt 5 is enabled. EX4 External interrupt 4/Timer 2 capture/compare interrupt 1 enable If EX4 = 0, external interrupt 4 is disabled. If EX4 = 1, external interrupt 4 is enabled. EX3 External interrupt 3/Timer 2 capture/compare interrupt 0 enable If EX3 = 0, external interrupt 3 is disabled. If EX3 = 1, external interrupt 3 is enabled. EX2 External interrupt 2 enable If EX2 = 0, external interrupt 2 is disabled. If EX2 = 1, external interrupt 2 is enabled. EADC A/D Converter interrupt enable If EADC = 0, the A/D Converter interrupt is disabled. If EADC = 1, the A/D Converter interrupt is enabled. – SWDT EX6 EX5B8H IEN1 Bit No. MSB LSB EX4 EX3 EX2 EADC The shaded bits are not used for interrupt control. BFH BEH BDH BCH BBH BAH B9H B8H

User’s Manual 7-10 2001-05 The SFR IEN2 contains the enable bits for the four interrupts from the Capture/Compare Unit (CCU). Special Function Register IEN2 (Address 9AH) Reset Value: XX0000XX B Bit Function ECT1 Compare Timer 1 interrupt enable If ECT1 = 0, the compare timer 1 interrupt is disabled. If ECT1 = 1, the compare timer 1 interrupt is enabled. ECCM Compare/Capture match interrupt enable If ECCM = 0, the compare/capture match interrupt is disabled. If ECCM = 1, the compare/capture match interrupt is enabled. ECT2 Compare Timer 2 interrupt enable If ECT2 = 0, the compare timer 2 interrupt is disabled. If ECT2 = 1, the compare timer 2 interrupt is enabled. ECEM CCU emergency interrupt enable If ECEM = 0, the emergency interrupt of the CCU is disabled. If ECEM = 1, the emergency interrupt of the CCU is enabled. –– ECT1 ECCM9AH IEN2 Bit No. 7 MSB LSB ECT2 ECEM –– 65 4 321 0

User’s Manual 7-11 2001-05 The SFR IEN3 contains the enable bits for the external interrupts 7 to 9. Special Function Register IEN3 (Address BEH) Reset Value: XXX000XX B Bit Function EX9 External interrupt 9 enable If EX9 = 0, external interrupt 9 is disabled. If EX9 = 1, external interrupt 9 is enabled. EX8 External interrupt 8 enable If EX8 = 0, external interrupt 8 is disabled. If EX8 = 1, external interrupt 8 is enabled. EX7 External interrupt 7 enable If EX7 = 0, external interrupt 7 is disabled. If EX7 = 1, external interrupt 7 is enabled. ––– EX9BEH IEN3 Bit No. 7 MSB LSB EX8 EX7 –– 65 4 321 0

User’s Manual 7-12 2001-05

7.2.2 Interrupt Request Flags

The request flags for the various interrupt sources are located in several Special Function Registers. This section describes the locations and meanings of these interrupt request flags in detail. Special Function Register TCON (Address 88 H) Reset Value: 00 H Each of the external interrupts 0 and 1 (P3.2/INT0 and P3.3/INT1 ) can be level- activated or negative transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the flag which generated this interrupt is cleared by the hardware when the service routine is vectored to – but, only if the interrupt was transition-activated. lf, however, the interrupt was level-activated, the requesting external source controls the request flag directly, rather than the on-chip hardware. Bit Function TF1 Timer 1 overflow flag Set by hardware on timer/counter 1 overflow. Cleared by hardware when processor vectors to interrupt routine. TF0 Timer 0 overflow flag Set by hardware on timer/counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine. IE1 External Interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when processor vectors to interrupt routine. IT1 External Interrupt 1 level/edge trigger control flag If IT1 = 0, low level triggered external interrupt 1 is selected. If IT1 = 1, falling edge triggered external interrupt 1 is selected. IE0 External Interrupt 0 request flag Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when processor vectors to interrupt routine. IT0 External Interrupt 0 level/edge trigger control flag If IT0 = 0, low level triggered external interrupt 0 is selected. If IT0 = 1, falling edge triggered external interrupt 0 is selected. TF1 TR1 TF0 TR088H TCON Bit No. 8F H MSB LSB IE1 IT1 IE0 IT0 8EH 8DH 8CH 8BH 8AH 89H 88H The shaded bits are not used for interrupt control.

User’s Manual 7-13 2001-05 The Timer 0 and Timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set by a rollover in their respective timer/counter registers. When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. Special Function Register T2CON (Address C8H) Reset Value: 0000X0X0 B The external interrupt 2 (INT2) can be either positive or negative transition-activated, depending on bit I2FR in register T2CON. The flag that actually generates this interrupt is bit IEX2 in register IRCON. The flag IEX2 is cleared by hardware when the service routine is vectored to. As with the external interrupt 2, the external interrupt 3 (INT3 ) can be either positive or negative transition-activated, depending on bit I3FR in register T2CON. The flag that actually generates this interrupt is bit IEX3 in register IRCON. In addition, this flag will be set if a compare event occurs at pin P5.0/T2CC0/INT3 , regardless of the compare mode established and the transition at the respective pin. The flag IEX3 is cleared by hardware when the service routine is vectored to. The external interrupts 4 (INT4), 5(INT5) and 6(INT6) are positive transition-activated. The flags that actually generate these interrupts are bits IEX4, IEX5 and IEX6 in register IRCON. These flags will also be set if a compare event occurs at the corresponding Pins P5.1/T2CC1/INT4, P5.2/T2CC2/INT5 and P5.3/T2CC3/INT6, regardless of the compare mode established and the transition at the respective pin. When an interrupt is generated, the flag that generated it is cleared by hardware when the service routine is vectored to. Bit Function I2FR External interrupt 2 rising/falling edge control flag If I2FR = 0, the external interrupt 2 is activated by a falling edge at P5.4/INT2 If I2FR = 1, the external interrupt 2 is activated by a rising edge at P5.4/INT2. I3FR External interrupt 3 rising/falling edge control flag If I3FR = 0, the external interrupt 3 is activated by a falling edge at P5.0/ T2CC0/INT3 If I3FR = 1, the external interrupt 3 is activated by a rising edge at P5.0/ T2CC0/INT3. T2PS I3FR I2FR T2RC8H T2CON Bit No. CF H MSB LSB – T2CM – T2I CEH CDH CCH CBH CAH C9H C8H The shaded bits are not used for interrupt control.

User’s Manual 7-14 2001-05 Special Function Register IRCON (Address C0H) Reset Value: X0000000 B Bit Function TF2 Timer 2 overflow flag Set by a Timer 2 overflow and must be cleared by software. If the Timer 2 interrupt is enabled, TF2 = 1 will cause an interrupt. IEX6 External interrupt 6 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at P5.3/T2CC3/INT6. Cleared when the interrupt is processed. IEX5 External interrupt 5 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at P5.2/T2CC2/INT5. Cleared when the interrupt is processed. IEX4 External interrupt 4 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at P5.1/T2CC1/INT4. Cleared when the interrupt is processed. IEX3 External interrupt 3 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at P5.0/T2CC0/INT3 . Cleared when the interrupt is processed. IEX2 External interrupt 2 edge flag Set by hardware when external interrupt edge was detected or when a compare event occurred at P5.4/INT2. Cleared when the interrupt is processed. IADC A/D Converter interrupt request flag Set by hardware at the end of an A/D conversion. Must be cleared by software. – TF2 IEX6 IEX5C0H IRCON Bit No. C7 H MSB LSB IEX4 IEX3 IEX2 IADC C6H C5H C4H C3H C2H C1H C0H

User’s Manual 7-15 2001-05 The Timer 2 interrupt is generated by bit TF2 in register IRCON. This flag is not cleared by hardware when the service routine is vectored to. It should be cleared by software. The A/D Converter interrupt is generated by IADC bit in register IRCON. If an interrupt is generated, the converted result in ADDAT is valid on the first instruction of the interrupt service routine. lf continuous conversion is established, IADC is set once during each conversion. lf an A/D Converter interrupt is generated, flag IADC will need to be cleared by software.

User’s Manual 7-16 2001-05 Special Function Register EINT (Address FBH) Reset Value: XX000000 B The external interrupts 7(INT7), 8(INT8) and 9(INT9) can be either positive or negative transition-activated, depending on bits I7FR, I8FR and I9FR in register EINT. The flags that actually generate these interrupts are bits IEX7, IEX8 and IEX9 in the same register EINT. They are cleared by hardware when the respective service routine is vectored to. Bit Function IEX9 External interrupt 9 edge flag Set by hardware when external interrupt edge was detected. Cleared by hardware when processor vectors to the interrupt routine. I9FR External interrupt 9 rising/falling edge control flag If I9FR = 0, the external interrupt 9 is activated by a negative edge transition at P5.5/INT9. If I9FR = 1, the external interrupt 9 is activated by a positive edge transition at P5.5/INT9. IEX8 External interrupt 8 edge flag Set by hardware when external interrupt edge was detected. Cleared by hardware when processor vectors to the interrupt routine. I8FR External interrupt 8 rising/falling edge control flag If I8FR = 0, the external interrupt 8 is activated by a negative edge transition at P5.6/INT8. If I8FR = 1, the external interrupt 8 is activated by a positive edge transition at P5.6/INT8. IEX7 External interrupt 7 edge flag Set by hardware when external interrupt edge was detected. Cleared by hardware when processor vectors to the interrupt routine. I7FR External interrupt 7 rising/falling edge control flag If I7FR = 0, the external interrupt 7 is activated by a negative edge transition at P5.7/INT7. If I7FR = 1, the external interrupt 7 is activated by a positive edge transition at P5.7/INT7. –– IEX9 I9FRFBH EINT Bit No. 7 MSB LSB IEX8 I8FR IEX7 I7FR 6 5 43 210

User’s Manual 7-17 2001-05 Special Function Register SCON (Address. 98H) Reset Value: 00 H The serial interface interrupt is generated by a logical OR of flag RI and TI in SFR SCON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine will normally need to determine whether it was the receive interrupt flag or the transmission interrupt flag which generated the interrupt, and the corresponding bit will need to be cleared by software. The interrupt request flags of the CAPCOM capture/compare match interrupt are located in the register CCIR. All CAPCOM capture/compare match interrupt flags are set by hardware and must be cleared by software. A capture/compare match interrupt is generated with the setting of a CCxR bit (x = 0-2) if the corresponding enable bits are set. These enable bits are contained in register CCIE. The Compare Timer 1 interrupt request flags – CT1FP or CT1FC – are also located in the register CCIR. Each flag has a corresponding enable bit which is located in the register CCIE. However, the Compare Timer 2 interrupt request flag, CT2P, is located in register CT2CON. The CCU emergency interrupt can be triggered by either bit TRF located in register TRCON or by bit BCERR located in register BCON. Each flag has an enable bit. For bit TRF, it is located in register CT1CON; whereas, for bit BCERR, it is found in register BCON. Bit Function TI Serial interface transmitter interrupt flag Set by hardware at the end of a serial data transmission. Must be cleared by software. RI Serial interface receiver interrupt flag Set by hardware if a serial data byte has been received. Must be cleared by software. SM0 SM1 SM2 REN98H SCON Bit No. 9F H MSB LSB TB8 RB8 TI RI 9EH 9DH 9CH 9BH 9AH 99H 98H The shaded bits are not used for interrupt control.

User’s Manual 7-18 2001-05 Special Function Register CCIR (Address E5H) Reset Value: 00 H Bit Function CT1FP Compare Timer 1 period flag Compare Timer 1 operating mode 0: CT1FP is set if Compare Timer 1 reaches the period value. Compare Timer 1 operating mode 1: CT1FP is set if Compare Timer 1 reaches the period value and changes the count direction from up- to down counting. Bit CT1FP must be cleared by software. If Compare Timer 1 interrupt is enabled, the setting of CT1FP will generate a Compare Timer 1 interrupt. CT1FC Compare Timer 1 count direction change flag This flag can only be set if Compare Timer 1 runs in operating mode 1 (CTM = 1). CT1FC is set when Compare Timer 1 reaches count value 0000 H and changes the count direction from down- to up-counting. If Compare Timer 1 interrupt is enabled, the setting of CT1FC will generate a Compare Timer 1 interrupt. Bit CT1FC must be cleared by software. CCxR x=0-2 Capture/Compare match on up-count flag Capture Mode: CCxR is set at a low-to-high transition (rising edge) of the corresponding CCx capture input signal. Compare Mode: CCxR is set if the Compare Timer 1 value matches the compare register CCx value during the up-count phase. CCxF x=0-2 Capture/Compare match on down-count flag Capture Mode: CCxF is set at a high-to-low transition (falling edge) of the corresponding CCx capture input signal. Compare Mode: CCxF is set if the Compare Timer 1 value matches the compare register CCx value during the down- count phase (only in Compare Timer 1 operating mode 1). Bit No. MSB LSB CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0RE5H CCIR 76543210 CAPCOM Channel 0 CAPCOM Channel 1 CAPCOM Channel 2

User’s Manual 7-19 2001-05 Special Function Registers CCIE (Address D6H) Reset Value: 00 H Bit Function ECTP Enable Compare Timer 1 period interrupt If ECTP = 0, the compare timer 1 period interrupt is disabled. Compare Timer 1 operating mode 0: If ECTP = 1, an interrupt is generated when Compare Timer 1 reaches the period value. Compare Timer 1 operating mode 1: If ECTP = 1, an interrupt is generated when Compare Timer 1 reaches the period value and changes the count direction from up- to down-counting. ECTC Enable Compare Timer 1 count direction change interrupt status If ECTC = 0, the Compare Timer 1 count change interrupt is disabled. Compare Timer 1 operating mode 0: Bit has no effect on the interrupt generation. Compare Timer 1 operating mode 1: If ECTC = 1, an interrupt is generated when Compare Timer 1 reaches count value 0000 H and changes its count direction from down- to up-counting. CCxREN (x = 0-2) Capture/Compare rising edge interrupt enable Capture Mode: If CCxREN is set, an interrupt is generated at a low-to-high transition (rising edge) of the corresponding CCx input signal. Compare Mode: If CCxREN is set, an interrupt is generated if the Compare Timer 1 value matches the compare register CCx value during the up-counting phase of the Compare Timer 1. This function is available in both Compare Timer 1 operating modes. CCxFEN (x = 0-2) Capture/Compare falling edge interrupt enable Capture Mode: If CCxFEN is set, an interrupt is generated at a high-to-low transition (falling edge) of the corresponding CCx input signal. Compare Mode: If CCxFEN is set, an interrupt is generated only in compare timer mode 1 if the Compare Timer 1 value matches the compare register CCx value during the down-counting phase of the Compare Timer 1. This function is available only in Compare Timer 1 operating mode 1. MSB LSB CCIEECTP ECTC CC2FEN CC2REN CC1FEN CC1REN CC0FEN CC0REN Bit No. D6H 76543210

User’s Manual 7-20 2001-05 Special Function Register CT2CON (Address F1H) Reset Value: 00010000 B Special Function Register BCON (Address D7H) Reset Value: 00 H Bit Function CT2P Compare Timer 2 period flag When the Compare Timer 2 value matches the Compare Timer 2 period register value, bit CT2P is set. If the Compare Timer 2 interrupt is enabled, the setting of CT2P will generate a Compare Timer 2 interrupt. Bit CT2P must be cleared by software. Bit Function EBCE Enable interrupt of Block Commutation mode Error If EBCE is set, the emergency interrupt for a block commutation mode error condition of the CCU is enabled. In block commutation mode, an emergency error condition occurs if a false signal state at INT2 - INT0 or a wrong follower state (if selected by bit BCEM) is detected. BCERR Block Commutation mode Error flag In block commutation mode, BCERR is set in rotate right or rotate left mode if, after a transition at INTx, all INTx inputs are at high or low level. Additionally, in rotate right or rotate left mode, a “wrong follower” condition according to Table 6-10 can cause BCERR to be set (see description of bit BCEM). If the block commutation interrupt is enabled (EBCE = 1), the setting of BCERR will generate a CCU emergency interrupt. BCERR must be reset by software. CT2P ECT2O CT2RES CT2R CLK2 CLK1 CLK0F1H CT2CON 76543210 Bit No. MSB LSB STE2 The shaded bits are not used for interrupt control. BCMP PWM1 PWM0 EBCE BCERR BCEN BCM1 BCM0D7H BCON 76543210 Bit No. MSB LSB BCEM The shaded bits are not used for interrupt control.

User’s Manual 7-21 2001-05 Special Function Register TRCON (Address FFH) Reset Value: 00 H Special Function Register CT1CON (Address E1H) Reset Value: 00010000 B Bit Function TRF Trap flag TRF is set by hardware if the trap function is enabled (TRPEN = 1) and the CTRAP level becomes active (low). If enabled, an interrupt is generated when TRF is set. TRF must be reset by software. Bit Function ETRP CCU emergency trap interrupt enable If ETRP = 1, the emergency interrupt for the CCU trap signal is enabled. CAPCOM Channel 0 CAPCOM Channel 1 CAPCOM Channel 2 TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0FFH TRCON 76543210 Bit No. MSB LSB The shaded bits are not used for interrupt control. CTM ETRP STE1 CT1RES CT1R CLK2 CLK1 CLK0E1H CT1CON 76543210 Bit No. MSB LSB

User’s Manual 7-22 2001-05

7.2.3 Interrupt Priority Registers

The lower six bits of these two registers are used to define the Interrupt Priority level of the interrupt groups as they are defined in Table 7-1 in the next section. Special Function Register IP0 (Address A9H) Reset Value: 00 H Special Function Register IP1 (Address B9H) Reset Value: XX000000 B Bit Function IP1.x IP0.x Interrupt group Priority level bits (x = 0-5, see Table 7-1) B i t N o . 76543210 MSB LSB B i t N o . 76543210 The shaded bits are not used for interrupt control. IP1.x IP0.x Function 0 0 Interrupt group x is set to Priority level 0 (lowest) 0 1 Interrupt group x is set to Priority level 1 1 0 Interrupt group x is set to Priority level 2 1 1 Interrupt group x is set to Priority level 3 (highest)

User’s Manual 7-23 2001-05

7.3 Interrupt Priority Level Structure

The nineteen interrupt sources of the C508 are grouped according to the listing in Table 7-1. Each group of interrupt sources can be programmed individually to one of the four priority levels by setting or clearing one bit in the Special Function Register IP0 and one in IP1. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or a lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt source. lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. Thus, within each priority level there is a second priority structure determined by the polling sequence. This is illustrated in Table 7-2. Table 7-1 Interrupt Source Structure Interrupt Group Associated Interrupts

1 External

– A/D Converter interrupt

2 Timer 0 overflow – External

3 External

4 Timer 1 overflow Compare Timer 2

5 Serial channel

6 Timer 2 overflow Compare Timer 1

User’s Manual 7-24 2001-05 Within a group, the leftmost interrupt is serviced first, then the second and the third and the fourth, when available. The interrupt groups are serviced from top to bottom of the table. A low-priority interrupt can itself be interrupted by a higher-priority interrupt, but not by another interrupt of the same or a lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt source. If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. Thus, within each priority level there is a second priority structure which is illustrated in Table 7-2. The “priority-within-level” structure is used only to resolve simultaneous requests of the same priority level. Table 7-2 Interrupts - Priority-within-Level Interrupt Group Priority Bits of Interrupt Group Interrupt Source Priority High Priority Low Priority Priority 1 IP1.0 / IP0.0 IE0 – IADC – High Low 2 IP1.1 / IP0.1 TF0 – IEX2 – 3 IP1.2 / IP0.2 IE1 TRF + BCERR IEX3 IEX7 4 IP1.3 / IP0.3 TF1 CT2P IEX4 IEX8 5 IP1.4 / IP0.4 RI + TI CCxR + CCxF IEX5 IEX9 6 IP1.5 / IP0.5 TF2 CT1FP + CT1FC IEX6 –

User’s Manual 7-25 2001-05

7.4 Interrupt Handling

The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1. An interrupt of equal or higher priority is already in progress. 2. The current (polling) cycle is not in the final cycle of the instruction in progress. 3. The instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP0/ IP1. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP0/IP1, then at least one more instruction will be executed before any interrupt is vectored to; this delay guarantees that changes of the interrupt status can be observed by the CPU. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests. The polling cycle/LCALL sequence is illustrated in Figure 7-6. Figure 7-6 Interrupt Response Timing Diagram Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in Figure 7-6 then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed. MCT04086 C1 C2 C3 C4 C5 Interrupt is latched Interrupts are polled Long Call to Interrupt Vector Address Interrupt Routine

User’s Manual 7-26 2001-05 Thus, the processor acknowledges an interrupt request by executing a hardware- generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, while in other cases it does not; then this must be done by the user’s software. The hardware clears the external interrupt flags IE0 and IE1 only if they were transition-activated. The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the program counter with an address that depends on the source of the interrupt being vectored to, as shown in the following Table 7-3. Table 7-3 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003 H IE0 Timer 0 Overflow 000B H TF0 External Interrupt 1 0013 H IE1 Timer 1 Overflow 001B H TF1 Serial Channel 0023 H RI / TI Timer 2 Overflow 002B H TF2 A/D Converter 0043 H IADC External Interrupt 2 004B H IEX2 External Interrupt 3 0053 H IEX3 External Interrupt 4 005B H IEX4 External Interrupt 5 0063 H IEX5 External Interrupt 6 006B H IEX6 CAPCOM Emergency Interrupt 0093 H TRF/BCERR Compare Timer 2 Interrupt 009B H CT2P Capture/Compare Match Interrupt 00A3 H CCxF/CCxF, x = 0 to 2 Compare Timer 1 Interrupt 00AB H CT1FP/CT1FC External Interrupt 7 00D3 H IEX7 External Interrupt 8 00DB H IEX8 External Interrupt 9 00E3 H IEX9 Wake-up from power-down mode 007B H –

User’s Manual 7-27 2001-05 Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the two top bytes from the stack and reloads the program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level. A simple RET instruction would also have returned execution to the interrupted program; but, it would have left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of the same or lower priority level would be acknowledged.

7.5 External Interrupts

The external interrupts 0 and 1 can be programmed to be level-activated or negative- transition activated by setting or clearing bit ITx (x = 0 or 1), respectively, in register TCON. If ITx = 0, external interrupt x is triggered by a detected low level at the INTx pin. If ITx = 1, external interrupt x is negative edge-triggered. In this mode, if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx =1 then requests the interrupt. If the external interrupt 0 or 1 is level-activated, the external source must hold the request active until the requested interrupt is actually generated. Then, it must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. The external interrupts 2, 3, 7, 8, and 9 can be programmed to be either negative or positive transition-activated by setting or clearing bits I2FR or I3FR in register T2CON or bits I7FR, I8FR or I9FR in register EINT. If IxFR = 0 (x = 2, 3, 7, 8, or 9) then the external interrupt x is negative transition-activated. If IxFR = 1, the external interrupt is triggered by a positive transition. The external interrupts 4, 5, and 6 are activated only by a positive transition. As the external interrupt pins are sampled once in each machine cycle, an input high or low should be held for at least three oscillator periods to ensure sampling. lf the external interrupt is positive (negative) transition-activated, the external source must hold the request pin low (high) for at least one cycle, and then hold it high (low) for at least one cycle to ensure that the transition is recognized. In that way, the corresponding interrupt request flag will be set (see Figure 7-7). The external interrupt request flags will automatically be cleared by the CPU when the service routine is called.

User’s Manual 7-28 2001-05 Figure 7-7 External Interrupt Detection

7.6 Interrupt Response Time

If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request is blocked by one of the three previously listed conditions. If an interrupt of equal or higher priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than three cycles since the longest instructions (MUL and DIV) are only four cycles long; and, if the instruction in progress is RETI or a write access to registers IEN0, IEN1 or IP0, IP1 the additional wait time cannot be more than five cycles (a maximum of one more cycle to complete the instruction in progress, plus four cycles to complete the next instruction, if the instruction is MUL or DIV). Thus, in a single interrupt system, the response time is always more than three cycles and fewer than nine cycles. MCT01921 Level-Activated Interrupt P3.x/INTx e.g. P3.x/INTx Transition-Activated Interrupt > 1 Machine Cycle Low-Level Threshold > 1 Machine Cycle > 1 Machine Cycle Transition to be detected High-Level Threshold Low-Level Threshold

User’s Manual 8-1 2001-05

8 Fail Save Mechanisms

The C508 offers enhanced fail save mechanisms which allow automatic recovery from software or hardware failure: – A programmable Watchdog Timer (WDT) with variable time-out period from 153.6 µs to 314.573 ms at fOSC = 10 MHz. – An Oscillator Watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state if the on-chip oscillator fails. It also provides the clock for a fast internal reset after power-on.

8.1 Programmable Watchdog Timer

To protect the system against software failure, the user ’s program must clear this Watchdog Timer within a previously programmed time period. If the software fails to refresh the Watchdog Timer periodically, an internal reset will be initiated. The software can be designed so that the Watchdog times out if the program does not work properly. lt also times out if a software error is based on a hardware-related problem. The Watchdog Timer in the C508 is a 15-bit timer which is incremented by a count rate of fOSC/6 up to fOSC/96. The machine clock of the C508 is divided by two prescalers. One is a divide-by-two prescaler; the other is a divide-by-16 prescaler. To program the Watchdog Timer overflow rate, the upper seven bits of the Watchdog Timer can be written. Figure 8-1 shows the block diagram of the Watchdog Timer unit. Figure 8-1 Block Diagram of the Programmable Watchdog Timer MCS04087 fOSC/3 WDTL WDTH 14 8 70 6 WDTREL (86H) ÷ 16÷ 2 OWDS WDTS - - - - - - - WDT - - - - - - - SWDT - - - - - - Control Logic WDTPSELIP0 (A9H) WDT Reset-Request External HW Reset IEN0 (A8H) IEN1 (B8H)

User’s Manual 8-2 2001-05 SFRs WDTL and WDTH are read-only registers which hold the current watchdog timer value. They are write-protected in order to enhance the integrity of the watchdog timer as a fail safe mechanism. By reading these two registers, the current value of the watchdog timer can be obtained. Special Function Register WDTH (Address 85H) Reset Value: X0000000B Special Function Register WDTL (Address 84H) Reset Value: 00 H Bit Function WDTH.6 - 0 Watchdog Timer value, upper 7 bits. Loaded with WDTREL.6 - 0 after a watchdog timer refresh. WDTL.7 - 0 Watchdog Timer value, low byte. Reset to zero after a watchdog timer refresh. MSB LSB Bit No. 85H WDTH 76543210 − WDT Value, Upper 7 bits 84H WDTLWDT Value, Low Byte

User’s Manual 8-3 2001-05

8.1.1 Input Clock Selection

The input clock rate of the Watchdog Timer is derived from the system clock of the C508. There is a prescaler available which is software selectable and defines the input clock rate. This prescaler is controlled by bit WDTPSEL in the SFR WDTREL. Table 8-1 shows the resulting timeout periods at fOSC = 5, 8, and 10 MHz. Special Function Register WDTREL (Address 86H) Reset Value: 00 H Bit Function WDTPSEL Watchdog Timer Prescaler Select bit The Watchdog Timer is clocked through an additional divide-by- 16 prescaler when this bit is set. WDTREL.6 - 0 Watchdog Timer Reload Seven bit reload value for the high-byte of the Watchdog Timer. This value is loaded to WDTH when a refresh is triggered by a consecutive setting of the WDT and SWDT bits. Table 8-1 Watchdog Timer Time-Out Periods WDTREL Time-Out Period Comments fOSC = 5 MHz fOSC = 8 MHz fOSC = 10 MHz 00H 39.322 ms 24.576 ms 19.668 ms This is the default value 80H 629.146 ms 393.2 ms 314.573 ms Maximum time period 7FH 307.2 µs 192 µs 153.6 µs Minimum time period MSB LSB Bit No. WDT86H WDTREL 76543210 PSEL Reload Value

User’s Manual 8-4 2001-05

8.1.2 Watchdog Timer Control/Status Flags

The Watchdog Timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one status flag (located in SFR IP0). Special Function Register IEN0 (Address A8H) Reset Value: 00 H Special Function Register IEN1 (Address B8H) Reset Value: X0000000 B Special Function Register IP0 (Address A9H) Reset Value: 00 H Immediately after start, the Watchdog Timer is initialized to the reload value programmed in WDTREL.0-WDTREL.6. Register WDTREL is cleared to 00 H after an external HW reset, an Oscillator Watchdog power-on reset, or a Watchdog Timer reset. The lower seven bits of WDTREL can be loaded by software at any time. Bit Function WDT Watchdog Timer refresh flag Set to initiate a refresh of the Watchdog Timer. Must be set before SWDT is set to prevent an unintentional refresh of the Watchdog Timer. SWDT Watchdog Timer Start flag Set to activate the Watchdog Timer. If set after WDT has been set, a Watchdog Timer refresh is performed. WDTS Watchdog Timer Status flag Set by hardware when a Watchdog Timer reset occurred. Can be cleared and set by software. EA WDT ET2 ESA8H IEN0 AFH MSB LSB ET1 EX1 ET0 EX0 AEH ADH ACH ABH AAH A9H A8H − SWDT EX6 EX5B8H IEN1 BFH EX4 EX3 EX2 EADC BEH BDH BCH BBH BAH B9H B8H Bit No. 76543210 The shaded bits are not used for fail save control. Bit No. Bit No.

User’s Manual 8-5 2001-05

8.1.3 Starting the Watchdog Timer

The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped while the device is in active mode. An internal reset will be initiated if the software fails to clear the Watchdog Timer. The cause of the reset (either an external reset or a reset caused by the Watchdog) can be examined by software (status flag WDTS in IP0 is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR IEN0) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the Watchdog Timer is halted during the idle mode and power-down mode of the processor (see Chapter 9). It is not possible to use the idle mode in combination with the Watchdog Timer function. Therefore, even the Watchdog Timer cannot reset the device if one of the power saving modes has been entered accidentally.

8.1.4 Refreshing the Watchdog Timer

At the same time the Watchdog Timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. After the Watchdog has started, it cannot be stopped by software; but, can only be refreshed to the reload value by first setting bit WDT (IEN0.6) and by the next instruction setting SWDT (IEN1.6). Bit WDT will automatically be cleared during the second machine cycle after having been set. For this reason, setting SWDT bit must be a one cycle instruction (for example, SETB SWDT). This double-instruction refresh of the Watchdog Timer is implemented to minimize the chance of an unintentional reset of the Watchdog. The reload register WDTREL can be written to at any time, as mentioned previously. Therefore, a periodic refresh of WDTREL can be added to the above mentioned starting procedure of the Watchdog Timer. Thus, a wrong reload value, caused by a possible distortion during the write operation to the WDTREL, can be corrected by software.

User’s Manual 8-6 2001-05

8.1.5 Watchdog Reset and Watchdog Status Flag

lf the software fails to refresh the Watchdog in time, an internally generated Watchdog reset is entered at the counter state 7FFC H. The duration of the reset signal then depends on the prescaler selection (either 8 cycles or 128 cycles). This internal reset differs from an external reset only in so far as the Watchdog Timer is not disabled and bit WDTS (Watchdog Timer status, bit 6 in SFR IP0) is set. Figure 8-2 shows a block diagram of all reset requests in the C508 and the function of the Watchdog Status flags. The WDTS flag is a flip-flop which is set by a Watchdog Timer reset and cleared by an external HW reset. Bit WDTS allows the software to examine from which source the reset was activated. The Watchdog Timer Status flag can also be cleared by software. Figure 8-2 Watchdog Timer Status Flags and Reset Requests MCT04099 OWDS WDTS SetSet WDT Reset Request OWD Reset Request IP0 (A9H) RESET Internal Bus External HW Reset Request Synchro- nization Internal Reset Clear

User’s Manual 8-7 2001-05

8.2 Oscillator Watchdog Unit

The Oscillator Watchdog unit serves for three functions: – Monitoring the on-chip oscillator’s function The Watchdog supervises the on-chip oscillator ’s frequency. If it is lower than the frequency of the auxiliary RC oscillator in the Watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset. If the failure condition disappears (that is, the on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typically 1 ms to allow the oscillator to stabilize; then, the Oscillator Watchdog reset is released and the part starts program execution again. – Fast internal reset after power-on The Oscillator Watchdog unit provides a clock supply for the reset before the on- chip oscillator and the PLL have started. This is described in Chapter 5.2. – Control of external wake-up from software power-down mode When the software power-down mode is terminated by a low level at pins P3.2/INT0 or P5.7/INT7, the Oscillator Watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. The RC oscillator, the on-chip oscillator, and the PLL are stopped in power-down mode. They are started again when power-down mode is terminated. After the on-chip oscillator is stable and the PLL has been locked, the microcontroller starts program execution. Note: The Oscillator Watchdog unit is always enabled. Special Function Register IP0 (Address A9 H) Reset Value: 00 H The shaded bits are not used for fail save control. Bit Function OWDS Oscillator Watchdog Status flag Set by hardware when an Oscillator Watchdog reset occurrs. Can be set and cleared by software. MSB LSB Bit No. 76543210

User’s Manual 8-9 2001-05 is available from the RC oscillator. This internal Oscillator Watchdog reset has the same effect as an externally applied reset signal with the following exceptions: The Watchdog Timer Status flag WDTS is not reset (the Watchdog Timer is, however, stopped); and bit OWDS is set. This allows the software to examine error conditions detected by the Oscillator Watchdog unit even if an oscillator failure occurred in the meantime. If the frequency derived from the on-chip oscillator is again higher than the reference, the Oscillator Watchdog starts a final reset sequence which takes typically 1 ms. Within that time, the system clock is still supplied by the RC oscillator and the part is held in reset. This allows a reliable stabilization of the on-chip oscillator. When this happens, the PLL will be locked and its clock output will be switched over as the system clock. After that, the Oscillator Watchdog releases its internal reset request. If no other reset is applied at this time, the part will start program execution. If an external reset or a Watchdog Timer reset is active, however, the device will retain the reset state until the other reset request disappears. Furthermore, the status flag OWDS is set if the Oscillator Watchdog was active. The status flag can be evaluated by software to detect that a reset was caused by the Oscillator Watchdog. The flag OWDS can be set or cleared by software. An external reset request, however, also resets OWDS (and WDTS). The RC oscillator, the on-chip oscillator, and the PLL are stopped if software power- down mode is activated. Both oscillators and the PLL are again started in power-down mode when a low level is detected at either P3.2/INT0 or P5.7/INT7 and when bit EWPD in SFR PCON1 is set (wake-up from power-down mode enabled). Bit WS in SFR PCON1 selects the wake-up source. In this case, the Oscillator Watchdog does not execute an internal reset during startup of the on-chip oscillator. After the startup phase of the on- chip oscillator, the Watchdog generates a power-down mode wake-up interrupt. Detailed description of the wake-up from software power-down mode is given in Chapter 9.4.2.

User’s Manual 8-10 2001-05

8.2.2 Fast Internal Reset after Power-On

The C508 can use the Oscillator Watchdog unit for a fast internal reset procedure after power-on. Normally, the members of the 8051 family (for example: SAB 80C52) do not enter their default reset state before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed to bring the device into the correct reset state. The startup time of the oscillator can be relatively long (typ. 10 ms), especially if a crystal is used. During this time period, the pins have an undefined state which could have severe effect on such things as actuators connected to port pins. The Oscillator Watchdog unit avoids this situation in the C508. After power-on, the oscillator Watchdog’s RC oscillator starts working within a very short startup time (typ. less than 2 µs). The Watchdog circuitry then detects a failure condition for the on-chip oscillator because it has not yet started (a failure is always recognized if the Watchdog’s RC oscillator runs faster than the gated PLL clock output, as described in the previous section). As long as this condition is valid, the Watchdog uses the RC oscillator output as the clock source for the chip. This allows the chip to be correctly reset and brings all ports to the defined state. The exception is Port 1, which will be at its default state when external reset is active (see also Chapter 5 of this manual).

User’s Manual 9-1 2001-05

9 Power Saving Modes

The C508 provides two basic power saving modes: the idle mode and the power-down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode.

9.1 Power Saving Mode Control Registers

The functions of the power saving modes are controlled by bits located in the Special Function Registers PCON and PCON1. The SFR PCON is located at SFR address 87H. PCON1 is located in the mapped SFR area (RMAP = 1) at SFR address 88H. Bit RMAP, which controls the access to the mapped SFR area, is located in SFR SYSCON (B1H). Bits PDE and PDS selects the power-down mode; while bits IDLE and IDLS selects the idle mode. These bits are all located in SFR PCON. If the power-down mode and the idle mode are set at the same time, power down mode takes precedence. Furthermore, register PCON contains two general purpose flags. For example, the flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle mode. For this, an instruction that activates idle mode can also set one or both flag bits. When idle mode is terminated by an interrupt, the interrupt service routine can examine the flag bits. Special Function Register PCON (Address 87 H) Reset Value: 00 H Symbol Function PDS Power-Down Start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle Start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode. SD Slow Down mode bit When set, the slow down mode is enabled GF1 General purpose flag 1 MSB LSB 87H PCONSMOD PDS IDLS SD GF1 GF0 PDE IDLE 76543210 Bit No. The function of the shaded bit is not described in this section.

User’s Manual 9-2 2001-05 Special Function Register PCON1 (Mapped Address 88H) Reset Value: 0XX0XXXX B GF0 General purpose flag 0 PDE Power-Down Enable bit When set, starting of the power down is enabled IDLE IDLe mode Enable bit When set, starting of the idle mode is enabled Symbol Function EWPD External Wake-up from Power-Down enable bit Setting EWPD before entering power down mode, enables the external wake-up from power down mode capability (more details see Chapter 9.4.2). WS Wake-up from power-down source Select WS = 0: wake-up via pin P3.2/INT0 WS = 1: wake-up via pin P5.7/INT7. Pin P3.2/INT0 is selected as the default wake-up source after reset. – Reserved bits for future use. Read by CPU returns undefined values. Symbol Function MSB LSB 76543210 Bit No.

User’s Manual 9-3 2001-05

9.2 Idle Mode

In the idle mode, the oscillator of the C508 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D Converter, the Capture/Compare Unit, and all timers (with the exception of the Watchdog Timer) are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The reduction of power consumption, which can be achieved by this feature, depends on the number of peripherals running. If all timers are stopped, and the A/D Converter and the serial interfaces are not running, the maximum power reduction can be achieved. This state is also the test condition for the idle mode IDD. Thus, the user must be cautious in determining which peripheral should continue to run and which must be stopped during idle mode. Also the state of all port pins – either the pins controlled by their latches or controlled by their secondary functions – depends on the status of the controller when entering idle mode. Normally, the port pins hold the logical state they had at the time that the idle mode was activated. If some pins are programmed to serve as alternative functions, they still continue to output during idle mode if the assigned function is on. This especially applies to the serial interface in case it cannot finish reception or transmission during normal operation. The control signals ALE and PSEN are held at logic high levels. As in normal operation mode, the ports can be used as inputs during idle mode. Thus, a capture or reload operation can be triggered, the timers can be used to count external events, and external interrupts will be detected. The idle mode is a useful feature which makes it possible to “freeze” the processor ’s status – either for a predefined time or until an external event reverts the controller to normal operation, as discussed below. The Watchdog Timer is the only peripheral which is automatically stopped during idle mode.

User’s Manual 9-4 2001-05 The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5). The following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after being set. If one of these register bits is read, the value that appears is 0. This double instruction is implemented to minimize the chance of unintentionally entering of the idle mode which would render the Watchdog Timer’s task of system protection without effect. Note: PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle mode is obtained by byte-handling instructions, as shown in the following example: ORL PCON,#00000001B ;Set bit IDLE, bit IDLS must not be set ORL PCON,#00100000B ;Set bit IDLS, bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode. There are two ways to terminate the idle mode: – The idle mode can be terminated by activating any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced, and the next instruction to be executed after the RETI instruction will be the one following the instruction which set the bit IDLS. – The other way to terminate the idle mode is a hardware reset. Since the oscillator is still running, the hardware reset must be held active only for two machine cycles for a complete reset.

User’s Manual 9-5 2001-05

9.3 Slow Down Mode Operation

In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (for example, if the controller is waiting for an input signal). In CMOS devices, there is an almost linear dependence of the operating frequency and the power supply current, so, a reduction of the operating frequency results in reduced power consumption. The slow down mode is activated by setting the bit SD in SFR PCON. If the slow down mode is enabled, the clock signals for the CPU and the peripheral units are reduced to 1/32 of the nominal system clock rate. The controller actually enters the slow down mode after a short synchronization period (maximum of two machine cycles). The slow down mode is terminated by clearing bit SD. The slow down mode can be combined with the idle mode by performing the following double instruction sequence: ORL PCON,#00000001B; preparing idle mode: set bit IDLE (IDLS not set) ORL PCON,#00110000B; entering idle mode combined with the slow down mode: ; (IDLS and SD set) There are two ways to terminate the combined Idle and Slow Down Mode: – The idle mode can be terminated by activation of any enabled interrupt. CPU operation is resumed, and the interrupt will be serviced. The next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bits IDLS and SD. Nevertheless, the slow down mode stays enabled and if required termination must be done by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the power saving slow-down mode. – The other possibility of terminating the combined idle and slow down mode is a hardware reset. Since the oscillator is still running, the hardware reset must be held active for only two machine cycles for a complete reset.

User’s Manual 9-6 2001-05

9.4 Software Power Down Mode

In the software power-down mode, the RC oscillator, the on-chip oscillator which operates with the XTAL pins, and the PLL are all stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM, and the SFRs are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFRs. The port pins which serve the alternative output functions show the values they had at the end of the last cycle of the instruction which initiated the power-down mode. ALE and PSEN are held at logic low level (see Table 9-1). In the power-down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power- down mode is invoked, and that VDD is restored to its normal operating level before the power-down mode is terminated. The software power-down mode can be left either by an active reset signal or by a low signal at one of the wake-up source pins. Using reset to leave power-down mode puts the microcontroller with its SFRs into the reset state. Using either the P3.2/INT0 pin or the P5.7/INT7 pin to exit power-down mode starts the RC oscillator, the on-chip oscillator, and the PLL; and maintains the state of the SFRs, which have been frozen when power-down mode was entered. Leaving power-down mode should not be done before VDD is restored to its nominal operating level.

9.4.1 Invoking Software Power Down Mode

The software power-down mode is entered by two consecutive instructions. The first instruction must set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6). The following instruction must set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent setting of both bits, PDE and PDS, does not initiate the power-down mode. Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0. This double instruction is implemented to minimize the chance of unintentionally entering the power-down mode which could possibly “freeze” the chip ’s activity in an undesired status. PCON is not a bit-addressable register, so the above mentioned sequence for entering the power down mode is obtained by byte-handling instructions, as shown in the following example: ORL PCON,#00000010B;set bit PDE, bit PDS must not be set ORL PCON,#01000000B;set bit PDS, bit PDE must not be set, enter power down The instruction that sets bit PDS is the last instruction executed before going into power- down mode. When the double instruction sequence shown above is used, the power- down mode can only be left by a reset operation. If the external wake-up from power-

User’s Manual 9-7 2001-05 down capability must also be used, its function must be enabled using the following instruction sequence prior to executing the double instruction sequence shown above. ORL SYSCON,#00010000B ;set RMAP ORL PCON1,#80H ;enable wake-up from power down via P3.2/INT0 ANL SYSCON,#11101111B ;reset RMAP (for future SFR accesses) Setting EWPD automatically disables all interrupts still maintaining the actual values of the interrupt enable bits. In the above sequence, the value of register PCON1 should be modified for choosing a wake-up via the P5.7/INT7 (bit PCON1.4 should be set). Note: Before entering the power-down mode, an A/D conversion in progress must be stopped.

9.4.2 Exit from Software Power Down Mode

If power-down mode is left via a hardware reset, the microcontroller with its SFRs is put into the hardware reset state and the contents of RAM and XRAM are not changed. The reset signal that terminates the power-down mode also restarts the RC oscillator, the on- chip oscillator, and the PLL. The reset operation should not be activated before VDD is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). Figure 9-1 shows the procedure which must be executed when power-down mode is left via the P3.2/INT0 or the P5.7/INT7 wake-up capability.

User’s Manual 9-8 2001-05 Figure 9-1 Wake-up from Power Down Mode Procedure When the power down-mode wake-up capability has been enabled (bit EWPD in SFR PCON1 set) prior to entering power-down mode and bit WS in SFR PCON1 is cleared, the power-down mode can be left via P3.2/INT0 while executing the following procedure: 1. In power-down mode, pin P3.2/INT0 must be held at high level. 2. Power-down mode is left when P3.2/INT0 goes low for at least 10 µs (latch phase). The internal RC oscillator, the on-chip oscillator, and the PLL are started; the state of pin P3.2/INT0 is internally latched; and P3.2/INT0 can be set again to high level if required, after this delay. Thereafter, the Oscillator Watchdog unit controls the wake- up procedure in its start-up phase. 3. The Oscillator Watchdog unit starts operation. Typically, the on-chip oscillator takes about 5 ms to stabilize. 4. The PLL will be locked within 1ms after the on-chip oscillator clock is detected for stable nominal frequency. Subsequently, the microcontroller starts again to initiate the power down wake-up interrupt. The interrupt address of the first instruction to be executed after wake-up is 007BH. ALE and PSEN are in their power-down state up to this time. At the end of Phase 4, the CPU processes the interrupt call and, during these (3) Invalid AddressP2 PSEN ALE 00H 7BHInvalid Address/DataP0 1st Instr. of ISR Detailed Timing of Beginning of Phase 5 P3.2/INT0 or P5.7/INT7 (1) (2) (4) (5) Power Down Mode PLL Locked Phase Execution of interrupt at 007BH Latch Phase On-Chip Oscillator Start-Up Phase min. 10 µs typ. 5 m s max. 1 ms RETI Instruction MCT04089

User’s Manual 9-9 2001-05 two machine cycles, ALE and PSEN behave as shown in Figure 9-1 (that is, at the beginning of Phase 5). Instruction fetches during the interrupt call are, however, discarded. 5. After the RETI instruction of the power-down wake-up interrupt routine has been executed, the instruction which follows the double instruction sequence to initiate the power-down mode will be executed. The functionality of the peripheral units timer 0/ 1/2, Capture/Compare Unit, and WDT are frozen until end of Phase 5. All interrupts of the C508 are disabled from Phase 2 until the end of Phase 5. Other Interrupts can be first handled after the RETI instruction of the wake-up interrupt routine. The procedure to exit the software power-down mode via the P5.7/INT7 pin is identical to the above procedure except that in this case pin P5.7/INT7 replaces pin P3.2/INT0 , and bit WS in SFR PCON1 should be set prior to entering software power-down mode.

User’s Manual 9-10 2001-05

9.5 State of Pins in Software Initiated Power Saving Modes

In the idle mode and in the power-down mode, the status of port pins of the C508 is well defined status. They are listed in Table 9-1. This state of some pins also depends on the location of the code memory (internal or external). Table 9-1 Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Internal Code Memory Last Instruction Executed from External Code Memory Idle Power Down Idle Power Down ALE High Low High Low PSEN High Low High Low PORT 0 Data Data Float Float PORT 2 Data Data Address Data PORT 1, 3, 4, 5 Data / alternate outputs Data / last output Data / alternate outputs Data / last output

User’s Manual 10-1 2001-05

10 OTP Memory Operation

The C508-4E is the OTP version in the C508 microcontroller with a 32 Kbyte One-Time Programmable (OTP) program memory. Fast programming cycles are achieved (1 byte in 100 µs) with the C508-4E. Several levels of OTP memory protection can be selected as well.

10.1 Programming Configuration

During normal program execution, the C508-4E behaves like the C508-4R, which has 32 Kbyte of on-chip ROM. To program the device, the C508-4E must be put into the programming mode. Typically, this is not done in-system but using special programming hardware. In the programming mode, the C508-4E operates as a slave device similar to an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 V programming voltage. In the programming mode, Port 0 provides the bi-directional data lines and Port 2 is used for the multiplexed address inputs. The upper address information at Port 2 is latched with the signal PALE. For basic programming mode selection, the inputs RESET, PSEN EA/VPP, PALE and PMSEL1/0, and PSEL are used. Further, the inputs PMSEL1, 0 are required to select the access types (for example, program/verify data, write lock bits, etc.) in the programming mode. In programming mode, VDD/VSS and a clock signal at the XTAL pins must be applied to the C508-4E. The 11.5 V external programming voltage is input through the EA/VPP pin. Figure 10-1 shows the pins of the C508-4E required to control the OTP programming mode. Figure 10-1 Programming Mode Configuration MCP04090 C508-4E P0.0 - 7 PALE PMSEL0 PMSEL1 XTAL1 XTAL2 VDD VSS P2.0 - 7 Port 2 Port 0 PSEL PSEN RESET PRD PROG EA/VPP

User’s Manual 10-2 2001-05

10.2 Pin Configuration

Figure 10-2 shows the detailed pin configuration of the C508-4E device in programming mode for the P-MQFP-64-1 package. Figure 10-2 OTP Programming Mode Pin Configuration for P-MQFP-64-1 Package (top view) MCP04091 A5/A13 49 55VSS 57D0 A6/A14 PSENPROG 45 44 V DD XTAL1 42 41 XTAL2 N.C.N.C. 39 38 N.C. PALEPRD 36 35 PSEL PMSEL1PMSEL0 32 N.C. 22 N.C. VDD RESETEA/ V PP 23 4 56 7 89 10 11 12 13 14 15 16 VDD V SS C508-4E A4/A12 A3/A11 A2/A10 A1/A9 A0/A8 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

User’s Manual 10-3 2001-05 Figure 10-3 shows the detailed pin configuration of the C508-4E device in programming mode for P-SDIP-64-2 package. Figure 10-3 OTP Programming Mode Pin Configuration for P-SDIP-64-2 Package (top view) MCP04092 C508-4E D0 1 D1 2 3D2 D3 4 5D4 6D5 D6 7 8D7 9RESET EA/VPP 10 11N.C. VDD VSS

62 A0/A8

53 PROG

48 N.C.

45 PALE

44 PRD

42 PMSEL1

41 PMSEL0

N.C.40 39 N.C. VSS VDD VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. A1/A9 A2/A10 A3/A11 A4/A12 A5/A13 A6/A14 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

User’s Manual 10-4 2001-05

10.3 Pin Definitions

Table 10-1 contains the functional descriptions of all C508-4E pins which are required for OTP memory programming. Table 10-1 Pin Definitions and Functions of the C508-4E in Programming Mode Symbol Pin Number I/O 1) Function P-MQFP- 64-1 P-SDIP- 64-2 RESET 1 9 I Reset This input must be at static ‘1’ (active) level throughout the entire programming mode. PMSEL0 PMSEL1 I I Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1, 0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1, 0 is changed, PALE must be at low level. PSEL 35 43 I Basic programming mode select This input is used for the basic programming mode selection and must be switched according to Figure 10-4. PRD 36 44 I Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. PMSEL1 PMSEL0 Access Mode 00R e s e r v e d 0 1 Read signature bytes 1 0 Program/read lock bits 1 1 Program/read OTP memory byte

User’s Manual 10-5 2001-05 PALE 37 45 I Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1, 0 is changed. XTAL2 47 49 O XTAL2 Output of the inverting oscillator amplifier. XTAL1 48 50 I XTAL1 Input to the oscillator amplifier. VSS 24, 43, 55 32, 51, – Ground (0 V) must be applied in programming mode. VDD 23, 44, 56 31, 52, – Power Supply (+5 V) must be applied in programming mode. P2.0- P2.7 54 - 47 62 - 55 I Address lines P2.0-P2.7 are used as multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. PSEN 46 54 I Program store enable This input must be at static 0 level during the whole programming mode. PROG 45 53 I Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection, a low level must be applied to PROG Table 10-1 Pin Definitions and Functions of the C508-4E in Programming Mode (cont’d) Symbol Pin Number I/O 1) Function P-MQFP- 64-1 P-SDIP- 64-2

User’s Manual 10-6 2001-05 EA/VPP 21 0 – Programming voltage This pin must be at 11.5 V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation, this pin must be at VIH2 high level. This pin is also used for basic programming mode selection. For basic programming mode selection, a low level must be applied to EA VPP. P0.0- P0.7 57 - 64 1 - 8 I/O Data lines In programming mode, data bytes are transferred via the bi-directional D0-D7 lines which are located at Port 0. N.C. 3 - 12, 15 - 22, 25 - 32, 38 - 40 11 - 30, 33 - 40, 46 - 48 – Not Connected These pins should not be connected in programming mode. 1) I=I n p u t O = Output Table 10-1 Pin Definitions and Functions of the C508-4E in Programming Mode (cont’d) Symbol Pin Number I/O 1) Function P-MQFP- 64-1 P-SDIP- 64-2

User’s Manual 10-7 2001-05

10.4 Programming Mode Selection

The selection for the OTP programming mode can be separated into two different parts: – Basic programming mode selection – Access mode selection With basic programming mode selection, the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/ read, version byte read, and program/read lock byte operations.

10.4.1 Basic Programming Mode Selection

The basic programming mode selection scheme is shown in Figure 10-4. Figure 10-4 Basic Programming Mode Selection MCD04093 VDD 5 V Clock (XTAL1/ XTAL2) RESET "1" PSEN "0" PMSEL1,0 PROG PRD "1" "0" 0,1 PSEL PALE "0" EA/VPP VPP VIH2 0 V Ready for access mode selectionDuring this period signals are not actively driven Stable

User’s Manual 10-8 2001-05 The basic programming mode is selected by executing the following steps: – With a stable VDD, a clock signal is applied to the XTAL pins; the RESET pin is set to ‘1’ level and the PSEN pin is set to ‘0’. – PROG, PALE, PMSEL1 and EA/VPP are set to ‘0’ level; PRD, PSEL, and PMSEL0 are set to ‘1’. – PSEL is switched from ‘1’ to ‘0’ level and thereafter PROG is switched to ‘1’. – PMSEL1, 0 can now be changed; after EA /VPP has been set to VIH2 high level or to VPP, the OTP memory is ready for access. The pins RESET and PSEN must stay at static signal levels ‘1’ and ‘0’ respectively throughout the entire programming mode. With a falling edge of PSEL, the logic state of PROG and EA /VPP are internally latched. These two signals are now used as programming write pulse signal (PROG ) and as programming voltage input pin VPP. After the falling edge of PSEL , PSEL must stay at ‘0’ state during all programming operations. Note: If protection level 1 to 3 has been programmed (see Chapter 10.6) and the programming mode has been left, it is no longer possible to enter the programming mode!

10.4.2 OTP Memory Access Mode Selection

When the C508-4E has been put into the programming mode using the basic programming mode selection, several access modes of the OTP memory programming interface are available. The conditions for the different control signals of these access modes are listed in Table 10-2. The access modes from Table 10-2 are basically selected by setting the two PMSEL1, 0 lines to the required logic level. The PROG and PRD signal are the write and read strobe signal. Data is transferred via Port 0 and addresses are applied to Port 2. Table 10-2 Access Modes Selection Access Mode EA / VPP PROG PRD PMSEL Address (Port 2) Data (Port 0)10 Program OTP memory byte VPP H HHA 0 - A 7 A8-A14 D0-D7 Read OTP memory byte VIH H Program OTP lock bits VPP HH L – D1, D0 see Table 10-3Read OTP lock bits VIH H Read OTP version byte VIH H L H Byte addr. of version byte D0-D7

User’s Manual 10-9 2001-05 The following sections describe the details of the different access modes.

10.5 Program / Read OTP Memory Bytes

The program/read OTP memory byte access mode is defined by PMSEL1, 0 = 1, 1. It is initiated when the PMSEL1, 0 = 1, 1 is valid at the rising edge of PALE. With the falling edge of PALE, the upper addresses A8-A14 of the 15-bit OTP memory address are latched. After A8-A14 has been latched, A0-A7 is put on the address bus (Port 2). A0-A7 must be stable when PROG is low or PRD is low. If subsequent OTP address locations are accessed with constant address information at the high address lines A8-A14, A8-A14 must only be latched once (page address mechanism). Figure 10-5 shows a typical basic OTP memory programming cycle with a following OTP memory read operation. In this example, A0-A14 of the read operation are identical to A8-A14 of the proceeding programming operation. Figure 10-5 Programming / Verify OTP Memory Access Waveform If the address lines A8-A14 must be updated, PALE must be activated for the latching of the new A8-A14 value. Control, address, and data information must only be switched when the PROG and PRD signals are at high level. The PALE high pulse must always be executed if a different access mode has been used prior to the actual access mode. D0-D7D0-D7 A8- A14 A0-A7 MCT04094 1, 1 min. 100 ns min. 100 µs PMSEL1, 0 Port 2 PALE Port 0 PROG PRD

User’s Manual 10-10 2001-05 Figure 10-6 shows a waveform example of the program/read mode access for several OTP memory bytes. In this example, OTP memory locations 3FD H to 400 H are programmed. Thereafter, OTP memory locations 400H and 3FDH are read. Figure 10-6 Typical OTP Memory Programming / Verify Access Waveform MCT03364 PMSEL1, 0 PALE Port 2 Port 0 PROG PRD 1, 1 3FD 3FE 3FF 400 400 3FD

03 FD FE FF 04 00 00 03 FD

Data 1 Data 2 Data 3 Data 4 Data 1 Data 4

User’s Manual 10-11 2001-05

10.6 Lock Bits Programming / Read

The C508-4E has two programmable lock bits which, when programmed according to Table 10-3, provide four levels of protection for the on-chip OTP code memory. Note: ‘1’ means that the lock bit is unprogrammed; ‘0’ means that lock bit is programmed. For a, OTP verify operation at protection Level 1, the C508-4E must be put into the OTP verification mode. If a device is programmed with protection Level 2 or 3, it is no longer possible to verify the OTP contents of a customer rejected (FAR) OTP device. When a protection level has been activated by programming of the lock bits, the basic programming mode must be left for activation of the protection mechanisms. This means that after the activation of a protection level, further OTP program/verify operations are still possible if the basic programming mode is maintained. Table 10-3 Lock Bit Protection Types Lock Bits at D1, D0 Protection Level Protection Type D1 D0 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C508-4E, the state of the EA pin is not latched on reset. 1 0 Level 1 During normal operation of the C508-4E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to OTP verification mode 2. Further programming of the OTP memory is disabled (reprogramming security). 0 1 Level 2 Same as Level 1, but also OTP memory read operation using OTP verification mode is disabled. 0 0 Level 3 Same as Level 2, but additionally external code execution by setting EA = low during normal operation of the C508-4E is no longer possible. External code execution, initiated by an internal program (for example, by an internal jump instruction above the OTP memory boundary), is still possible.

User’s Manual 10-13 2001-05

10.7 Access of Version Bytes

The C508-4E and C508-4R provide three version bytes at address locations FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask of each microcontroller step. Therefore, the version bytes can be read but cannot be written. The three Version Registers hold such information as manufacturer code, device type, and stepping code. To read the version bytes, the control lines must be used in accordance with Table 10-2 and Figure 10-8. The address of the version byte must be applied at the Port 2 address lines. PALE must not be activated. Figure 10-8 Read Version Register(s) Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specific device characteristics such as OTP size, etc. Note: The three version bytes are implemented in such a way that they can be also be read during normal program execution mode as a mapped register with bit RMAP in SFR SYSCON set. The addresses of the version bytes in normal mode and programming mode are identical and, therefore, they are located in the SFR address range. FD MCT04095 0.1 VR0 FC FE VR2VR1 PMSEL1, 0 PALE Port 2 Port 0 PROG PRD

User’s Manual 11-1 2001-05 A A/D converter 6-122–6-133 Block diagram 6-123 Calibration mechanisms 6-133 Clock selection 6-128 Conversion time calculation 6-132 Conversion timing 6-129 General operation 6-122 Registers 6-124–6-127 System clock relationship 6-130 AC 2-4, 3-16 ADCL0 3-17 ADCL1 3-17 ADCL1-0 6-126 ADCON0 3-12, 3-13, 3-17, 6-106, 6-125 ADCON1 3-12, 3-17, 6-125 ADDATH 3-12, 3-17, 6-124 ADDATL 3-12, 3-17, 6-124 ADM 3-17, 6-125 ALE signal 4-4 B B 2-4, 3-12, 3-17 Basic CPU timing 2-5 BCEM 3-17, 6-86 BCEN 3-17, 6-87 BCER 3-17 BCERR 6-87, 7-20 BCM0 3-17, 6-87 BCM1 3-17, 6-87 BCMP 3-17, 6-86 BCTSEL 3-18 BD 3-17, 6-106 Block diagram 2-2 BSY 3-17, 6-125 C C/T 3-15, 6-19 CAN controller Access control 3-3 Capture/compare unit (CCU) 6-45–6-101 1-channel COMP unit 6-78–6-83 Block diagram 6-78 Pulse generation 6-78 Registers 6-79–6-83 Compare registers 6-83 CT2 control register 6-80 Period registers 6-82 Survey 6-79 3-channel CAPCOM unit 6-49–6-77 Burst mode 6-57 Capture mode 6-58 Clocking scheme 6-49 Operating mode 0 6-50–6-52 Operating mode 1 6-53 Period and resolution 6-55–6-56 Registers 6-61–6-77 Capture/compare registers 6-69 CT1 control register 6-63 Interrupt enable register 6-72 Interrupt request register 6-70 Mode select registers 6-67 Offset registers 6-66

11 Index

11.1 Keyword Index

This section lists a number of keywords which refer to specific details of the C508 in terms of its architecture, its functional units, or functions. Bold page number entries identify the main definition material for a topic.

User’s Manual 11-2 2001-05 Output initialization register 6-74 Period registers 6-65 Survey 6-61 Trap enable register 6-76 Write on-the-fly 6-62 Trap function 6-59 Basic operating modes 6-46 Block diagram 6-45 General operation 6-46 Multi-channel PWM modes 6-84–6-101 4-, 5-, 6-phase PWM mode 6-94–6-101 4-phase PWM timing 6-94 5-phase PWM timing 6-95 6-phase PWM timing 6-96 Block commutation mode 6-91, 6-93 Block diagram 6-84 Control register BCON 6-86 Output waveforms 6-89, 6-90 PWM state tables 6-97 Signal generation 6-88 State switching by software 6-99 Trap function 6-101 CC0F 3-17, 6-71, 7-18 CC0FEN 3-17, 6-73, 7-19 CC0I 3-17, 6-75 CC0R 3-17, 6-71, 7-18 CC0REN 3-17, 6-73, 7-19 CC0T 3-18 CC1F 3-17, 6-71, 7-18 CC1FEN 3-17, 6-73, 7-19 CC1I 3-17, 6-75 CC1R 3-17, 6-71, 7-18 CC1REN 3-17, 6-73, 7-19 CC1T 3-18 CC2F 3-17, 6-71, 7-18 CC2FEN 3-17, 6-73, 7-19 CC2I 3-17, 6-75 CC2R 3-17, 6-71, 7-18 CC2REN 3-17, 6-73, 7-19 CC2T 3-18 CCEN 3-13, 3-16, 6-30 CLK 3-17 CLK0 3-17, 6-63, 6-81 CLK1 3-17, 6-63, 6-81 CLK2 3-17, 6-63, 6-81 CMP2H 3-14, 3-16, 6-79, 6-83 CMP2L 3-14, 3-16, 6-79, 6-83 CMSEL0 3-14, 3-17, 6-61, 6-67 CMSEL00 3-17, 6-68 CMSEL01 3-17, 6-68 CMSEL02 3-17, 6-68 CMSEL03 3-17, 6-67 CMSEL1 3-14, 3-17, 6-61, 6-67 CMSEL10 3-17, 6-68 CMSEL11 3-17, 6-68 CMSEL12 3-17, 6-68 CMSEL13 3-17, 6-67 CMSEL20 3-17, 6-68 CMSEL21 3-17, 6-68 CMSEL22 3-17, 6-68 CMSEL23 3-17, 6-67 COCAH0 3-16, 6-31 COCAH1 3-16, 6-31 COCAH2 3-16, 6-30 COCAH3 3-16, 6-30 COCAL0 3-16, 6-31 COCAL1 3-16, 6-31 COCAL2 3-16, 6-30 COCAL3 3-16, 6-30 COINI 3-14, 3-17, 6-61, 6-75 COTRAP 3-14, 3-18, 6-61 COUT0I 3-17, 6-75

User’s Manual 11-3 2001-05 COUT0T 3-18 COUT1I 3-17, 6-75 COUT1T 3-18 COUT2I 3-17, 6-75 COUT2T 3-18 COUT3I 3-17, 6-75 COUTXI 3-17, 6-75 CPU Accumulator 2-3 B register 2-4 Basic timing 2-5 Fetch/execute diagram 2-6 Functionality 2-3 Program status word 2-4 Stack pointer 2-5 CPU timing 2-6 CRCH 3-13, 3-16, 6-28 CRCL 3-13, 3-16, 6-28 CT1FC 3-17, 6-70, 7-18 CT1FP 3-17, 6-70, 7-18 CT1OFH 3-14, 3-17, 6-61, 6-66 CT1OFL 3-14, 3-17, 6-61, 6-66 CT1R 3-17, 6-64 CT1RES 3-17, 6-64 CT2P 3-17, 6-80, 7-20 CT2R 3-17, 6-81 CT2RES 3-17, 6-81 CTM 3-17, 6-63 CY 2-4, 3-16 D Datapointers 4-6–4-9 Application examples 4-8–4-9 DPSEL register 4-7 Functionality 4-6 DPSEL 3-12, 3-15, 4-7 E EA 3-15, 7-7 EADC 3-16, 6-127, 7-9 EBCE 3-17, 6-86, 7-20 ECCM 3-15 ECEM 3-15 ECT1 3-15 ECT2 3-15 ECT2O 3-17, 6-80 ECTC 3-17, 6-73, 7-19 ECTP 3-17, 6-72, 7-19 EINT 3-12, 3-18, 7-16 Emulation concept 4-5 ES 3-15, 7-7 ESMC 3-17, 6-67 ETRP 3-17, 6-63, 7-21 EWPD 3-15, 9-2 EX0 3-15, 7-8 EX1 3-15, 7-7 EX2 7-9 EX3 3-16, 7-9 EX4 3-16, 7-9 EX5 3-16, 7-9 EX6 3-16, 7-9 Execution of instructions 2-5, 2-6 External bus interface 4-1 ALE signal 4-4 ALE switch-off control 4-4 Overlapping of data/program memory 4-3 Program memory access 4-3 Program/data memory timing 4-2 PSEN signal 4-3 Role of P0 and P2 4-1 F F0 2-4, 3-16 F1 2-4, 3-16

User’s Manual 11-4 2001-05 Fail save mechanisms 8-1–8-10 Fast power-on reset 5-3, 8-10 Features 1-2 Functional units 1-1 Fundamental structure 2-1 G GATE 3-15, 6-19 GF0 3-15, 9-2 GF1 3-15, 9-1 H Hardware reset 5-1 I I/O ports 6-1–6-45 I2FR 3-16, 7-13 I3FR 3-16, 6-27, 7-13 I7FR 3-18 I8FR 3-18 I9FR 3-18 IADC 3-16, 6-127, 7-14 IDLE 3-15, 9-2 Idle mode 9-3–9-4 IDLS 3-15, 9-1 IE0 3-15, 7-12 IE1 3-15, 7-12 IEN2 3-12, 3-15, 7-10 IEN3 3-12, 3-16, 7-11 IEX2 3-16 IEX3 3-16 IEX4 3-16 IEX5 3-16 IEX6 3-16 IEX7 3-18 IEX8 3-18 IEX9 3-18 INT0 3-16 INT1 3-16 Interrupt system 7-1–7-28 Interrupts Block diagram 7-2–7-6 Enable registers 7-7–7-15 External interrupts 7-27 Handling procedure 7-25 Priority registers 7-22 Priority within level structure 7-23 Request flags 7-12–7-20 Response time 7-28 Sources and vector addresses 7-26 IP1 3-12, 3-16, 7-22 IT0 3-15, 7-12 IT1 3-15, 7-12 L Logic symbol 1-3 M M0 3-15, 6-19 M1 3-15, 6-19 Memory organization 3-1 Data memory 3-2 General purpose registers 3-2 Memory map 3-1 Program memory 3-2 MX0 3-17 MX1 3-17 MX2 3-17 MX2-0 6-125 N NMCS 3-17, 6-67 O Oscillator operation 5-7–5-9 External clock source 5-9 On-chip oscillator circuitry 5-9 Recommended oscillator circuit 5-8 Oscillator watchdog 8-7–8-9 Block diagram 8-8 OTP memory 10-1–10-13 Access of Version Bytes 10-13

User’s Manual 11-5 2001-05 Basic Mode Selection 10-7 Pin Configuration 10-1 Program/read operation 10-9 OV 2-4, 3-16 OWDS 3-15, 8-7 P P 2-4, 3-16 P0 3-12, 3-15 P1 3-12, 3-15 P2 3-12, 3-15 P3 3-12, 3-16 P4 3-12, 3-17 P5 3-12 Parallel I/O 6-1–6-45 PCON1 3-14, 3-15, 9-2 PDE 3-15, 9-2 PDS 3-15, 9-1 Pin Configuration 1-4 Pin Definitions and functions (OTP Mode) 10-4–10-6 Ports 6-1–6-45 Alternate functions 6-3 Loading and interfacing 6-14 Output drivers circuitry 6-10 Mixed digital/analog I/O pins 6-12 Multifunctional digital I/O pins 6-10 Output/input sample timing 6-13 Read-modify-write operation 6-15 Types and structures 6-1 Port 0 circuitry 6-6 Port 1/3/4 circuitry 6-7 Port 2 circuitry 6-8 Standard I/O port circuitry 6-4–6-5 Power down mode by software 9-6–9-9 Power saving modes 9-1–9-10 Control registers 9-1–9-2 Idle mode 9-3–9-4 Slow down mode 9-5 Software power down mode 9-6–9-9 Entry procedure 9-6 Exit (wake-up) procedure 9-7 State of pins 9-10 Protected ROM verify timing 4-11 PSEN signal 4-3 PWM0 3-17, 6-86 PWM1 3-17, 6-86 R RB8 3-15, 6-103, 6-104 RD 3-16 REN 3-15, 6-104 Reset 5-1 Fast power-on reset 5-3 Hardware reset timing 5-6 Reset circuitries 5-2 RMAP 3-11, 3-16 ROM protection 4-10 Protected ROM mode 4-11 Protected ROM verification example 4-13 Unprotected ROM mode 4-10 RS0 2-4, 3-16 RS1 2-4, 3-16 RxD 3-16, 6-102 S SBUF 3-13, 3-15, 6-103, 6-104 SD 3-15, 9-1 Serial interface (USART) 6-102–6-121 Baudrate generation 6-106 with internal baud rate generator 6-108 with timer 1 6-110 Multiprocessor communication 6-103 Operating mode 0 6-111–6-113 Operating mode 1 6-114–6-117 Operating mode 2 and 3 6-118–6-121 Registers 6-103 SM0 3-15, 6-104 SM1 3-15, 6-104

User’s Manual 11-6 2001-05 SM2 3-15, 6-104 SMOD 3-15, 6-106 SP 2-5, 3-12, 3-15 Special Function Registers 3-11 Access with RMAP 3-11 Table - address ordered 3-15–3-18 Table - functional order 3-12–3-14 SRELH 3-13, 3-16, 6-109 SRELL 3-13, 3-15, 6-109 STE1 3-17, 6-63 STE2 3-17, 6-80 SWDT 3-16, 8-4 T T0 3-16 T1 3-16 T2CCH1 3-13, 3-16 T2CCH2 3-13, 3-16 T2CCH3 3-13, 3-16 T2CCL1 3-13, 3-16 T2CCL2 3-13, 3-16 T2CCL3 3-13, 3-16 T2CM 3-16, 6-27 T2I0 3-16, 6-27 T2I1 3-16, 6-27 T2PS 3-16, 6-27 T2R0 3-16, 6-27 T2R1 3-16, 6-27 TB8 3-15, 6-103, 6-104 TF0 3-15, 6-18, 7-12 TF1 3-15, 6-18, 7-12 TF2 3-16, 6-29, 7-14 TH0 3-13, 3-15, 6-17 TH1 3-13, 3-15, 6-17 TH2 3-13, 3-16, 6-28 Timer/counter 6-16 Timer/counter 0 and 1 6-16–6-23 Mode 0, 13-bit timer/counter 6-20 Mode 1, 16-bit timer/counter 6-21 Mode 2, 8-bit rel. timer/counter 6-22 Mode 3, two 8-bit timer/counter 6-23 Registers 6-17–6-19 Timer/counter 2 6-24–6-44 Block diagram 6-25 Capture function 6-43–6-44 Compare function 6-34–6-40 Compare mode 0 6-34–6-37 Compare mode 1 6-38–6-40 Compare mode interrupts 6-41 General operation 6-32 Port functions 6-24 Registers 6-26–6-30 Reload configuration 6-33 TL0 3-13, 3-15, 6-17 TL1 3-13, 3-15, 6-17 TL2 3-13, 3-16, 6-28 TMOD 3-13, 3-15, 6-19 TR0 3-15, 6-18 TR1 3-15, 6-18 TREN 3-18 TREN0 6-76 TREN1 3-18, 6-76 TREN2 3-18, 6-76 TREN3 3-18, 6-76 TREN4 3-18, 6-76 TREN5 3-18, 6-76 TRF 3-18, 6-76, 7-21 TRPEN 3-18, 6-76 TxD 3-16, 6-102 U Unprotected ROM verify timing 4-10 V Version registers 4-14 VR0 3-12, 3-18 VR1 3-12, 3-18 VR2 3-12, 3-18

User’s Manual 11-7 2001-05 W Watchdog timer 8-1–8-6 Block diagram 8-1 Control/status flags 8-4 Input clock selection 8-3 Refreshing of the WDT 8-5 Reset operation 8-6 Starting of the WDT 8-5 Time-out periods 8-3 WDT 3-15, 8-4 WDTH 3-15, 8-2 WDTL 3-15 WDTPSEL 3-15, 8-3 WDTREL 3-14, 3-15, 8-3 WDTS 3-15, 8-4 WR 3-16 WS 3-15, 9-2 X XMAP 3-16 XMAP0 3-3 XMAP1 3-3, 3-16 XPAGE 3-5, 3-12, 3-15 XRAM operation 3-3 Access control 3-3 Accessing through DPTR 3-5 Accessing through R0/R1 3-5 Behaviour of P2/P0 3-9 Reset operation 3-9 Table - P0/P2 during MOVX instr. 3-10 XPAGE register 3-5 Use of P2 as I/O port 3-8 Write page address to P2 3-6 Write page address to XPAGE 3-7

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