C508

C508 INFINEON | Alldatasheet

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Never stop thinking. Microcontrollers Data Sheet, August 2000 C508 8-Bit CMOS Microcontroller

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, August 2000 Never stop thinking. C508 8-Bit CMOS Microcontroller

Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. C508 Revision History: 2000-08 Previous Version: 1999-10 Page Subjects (major changes since last revision) several Typo errors corrected

27 Figure 10 corrected

We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com

C5088-Bit CMOS Microcontroller C500 Family C508

• Fully compatible to standard 8051 microcontroller
• Superset of the 8051 architecture with 8 datapointers
• 10 to 20 MHz internal CPU clock (using built-in PLL with a factor of 2) – external clock of 5 - 10 MHz at 50% duty cycle – 300 ns instruction cycle time at 20 MHz CPU clock
• 32 Kbyte on-chip ROM/OTP (with optional ROM protection)
• 256 byte on-chip RAM
• 1024 byte on-chip XRAM
• Six 8-bit ports – Ports 1 and 2 with enhanced current sinking capabilities of 10 mA (total max. of 100 mA) – Port 4 with pure analog/digital input channels Further features are listed next page. Figure 1 C508 Functional Units MCB04022 I/O I/O I/O I/O On-Chip Emulation Support Module Watchdog Timer Timer 2 10-Bit ADC Oscillator Watchdog XRAM

1 K x 8

32 K x 8

8 Datapointers

• Three 16-bit timers/counters – Timer 0/1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation
• Capture/compare unit for PWM signal generation – 3-channel, 16-bit capture/compare unit – 1-channel, 10-bit compare unit
• Full duplex serial interface with programmable baudrate generator (USART)
• 8-channel 10-bit A/D Converter
• 19 interrupt vectors with four priority levels
• On-chip emulation support logic (Enhanced Hooks Technology TM )
• Programmable 15-bit Watchdog Timer
• Oscillator Watchdog
• Fast Power On Reset
• Power Saving Modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through INT0 or INT7
• ALE switch-off capability for reduction in RFI emission
• P-MQFP-64-1, P-SDIP-64-2 packages
• Temperature ranges: SAB-C508 T A = 0 to 70°C SAF-C508 TA = – 40 to 85°C

Ordering Information

The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code indentifies:

• The derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery For the available ordering codes for the C508, please refer to the “Product Information Microcontrollers” which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code.

Figure 3 Pin Configuration for P-MQFP-64-1 Package (top view) MCP04024 P2.5/A13 49 P2.4/A12 50 51P2.3/A11 52P2.2/A10 P2.1/A9 53 54P2.0/A8 55V SS 57P0.0/AD0 58P0.1/AD1 P0.2/AD2 59 60P0.3/AD3 61P0.4/AD4 P0.5/AD5 62 63P0.6/AD6 64P0.7/AD7 P2.6/A14 P2.7/A15 PSENALE 45 44 V DD XTAL1 42 41 XTAL2 P3.7/RD P3.6/WR 39 38 P3.5/T1 P3.4/T0 P3.3/INT1 36 35 P3.2/INT0 P3.1/TxD P3.0/RxD 32 P1.0/COUT3 31 P1.1/CTRAP 30 P1.2/CC0 P1.3/COUT029 28 P1.4/CC1 27 P1.5/COUT1 P1.6/CC226 25 P1.7/COUT2

24 V SS

22 P5.0/T2CC0/INT3 21 P5.1/T2CC1/INT4 P5.2/T2CC2/INT520 19 P5.3/T2CC3/INT6 18 P5.4/INT2 P5.5/INT917 V DD RESET EA V DDA P4.0/AN0 P4.1/AN1 P4.2/AN2 P4.3/AN3 P4.4/AN4 P4.5/AN5 P4.6/AN6 11 12 P4.7/AN7 13 14 15 P5.7/INT7 P5.6/INT8 V SSA V AREF V AGND V DD V SS C508

Figure 4 Pin Configuration for P-SDIP-64-2 Package (top view) MCP04025 C508 P0.0/AD0 1 P0.1/AD1 2 3P0.2/AD2 P0.3/AD3 4 5P0.4/AD4 6P0.5/AD5 P0.6/AD6 7 8P0.7/AD7 9RESET EA 10 11V DDA P4.0/AN0 P4.1/AN1 P4.2/AN2 P4.3/AN3 P4.4/AN4 P4.5/AN5 18 P4.6/AN6 19 20P4.7/AN7 P5.7/INT7 P5.6/INT8 24 P5.5/INT9 25 26P5.4/INT2 P5.3/T2CC3/INT6 27 V SSA V AREF V AGND P5.2/T2CC2/INT5 P5.1/T2CC1/INT4 P5.0/T2CC0/INT3 V DD V SS

64 V DD

62 P2.0/A8 P2.1/A961 60 P2.2/A10 59 P2.3/A11 P2.4/A1258 57 P2.5/A13 56 P2.6/A14 P2.7/A1555

54 PSEN

53 ALE

50 XTAL1

48 P3.7/RD 47 P3.6/WR P3.5/T146 45 P3.4/T0 44 P3.3/INT1 P3.2/INT043 42 P3.1/TxD 41 P3.0/RxD P1.0/COUT340 39 P1.1/CTRAP 38 P1.2/CC0 P1.3/COUT037 36 P1.4/CC1 35 P1.5/COUT1 P1.6/CC234 33 P1.7/COUT2 V SS V DD V SS

Table 1 Pin Defintions and Functions Sym- bol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64 P1.0- P1.7 25 - 32 33 - 40 I/O Port 1 is an 8-bit quasi-bidirectional port with internal pull-up transistors. Port 1 pins can be used for digital input/output. Port 1 pins that have “1”s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 1 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup transistors. The output latch corresponding secondary function must be programmed to a one (1) for that function to operate. As secondary functions, Port 1 contains the capture/compare inputs/outputs as well as the CCU trap input. Port 1 pins have LED drive capability of up to 10 mA sinking current per pin. The secondary functions from the CCU unit are assigned to the pins of Port 1 as follows: P1.0/COUT3 10-bit compare channel output P1.1/CTRAP CCU trap input P1.2/CC0 Input/Output of capture/ compare channel 0 P1.3/COUT0 Output of capture/compare channel 0 P1.4/CC1 Input/Output of capture/ compare channel 1 P1.5/COUT1 Output of capture/compare channel 1 P1.6/CC2 Input/Output of capture/ compare channel 2 P1.7/COUT2 Output of capture/compare channel 2

A high level on this pin for one machine cycle while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VDD . P3.0- P3.7 33 - 40 41 - 48 I/O Port 3 is an 8-bit quasi-bidirectional port with internal pull-up transistors. Port 3 pins that have “1”s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, Port 3 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup transistors. The output latch corresponding secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR The secondary functions are assigned to the pins of Port 3 as follows: P3.0/RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1/TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2/INT0 External interrupt 0 input/timer 0 gate control input P3.3/INT1 External interrupt 1 input/timer 1 gate control input P3.4/T0 Timer 0 counter input P3.5/T1 Timer 1 counter input P3.6/WR WR control output; latches the data byte from port 0 into the external data memory P3.7/RD RD control output; enables the external data memory Table 1 Pin Defintions and Functions (cont’d) Sym- bol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

P2.0- P2.7 47 - 54 55 - 62 I/O Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup transistors. Port 2 pins that have “1”s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, Port 2 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup transistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing “1”s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), Port 2 issues the contents of the P2 special function register and uses only the internal pullup transistors. As I/O functions, Port 2 pins also have LED drive capability of up to 10 mA sinking current per pin. XTAL1 42 50 I XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. XTAL2 41 49 O XTAL2 Output of the inverting oscillator amplifier. Table 1 Pin Defintions and Functions (cont’d) Sym- bol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

P4.0- P4.7 5 - 12 13 - 20 I Port 4 is an 8-bit uni-directional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications for high/low input voltages and for the eight multiplexed analog inputs. PSEN 46 54 O The Program Strobe Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every one and a half oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. ALE 45 53 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every one and a half oscillator periods except during an external data memory access. When instructions are executed from internal ROM (EA = 1) the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. EA 21 0 I External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than 8000H . When held at low level, the C508 fetches all instructions from external program memory. This pin should not be driven during reset operation. Table 1 Pin Defintions and Functions (cont’d) Sym- bol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

P0.0- P0.7 57 - 64 1 - 8 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have “1”s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing “1”s. Port 0 also outputs the code bytes during program verification in the C508-4R. External pullup resistors are required during program verification. P5.0- P5.7 15 - 22 23 - 30 I/O Port 5 is a an 8-bit quasi-bidirectional I/O port with internal pullup transistors. Port 5 pins that have “1”s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, Port 5 pins being externally pulled low will source current ( IIL, in the DC characteristics) because of the internal pullup transistors. As secondary functions, Port 5 contains the interrupt and Timer 2 capture/compare pins. They are assigned to the pins as follows: P5.0/T2CC0/INT3 T2 Compare/Capture output 0/Interrupt 3 input P5.1/T2CC1/INT4 T2 Compare/Capture output 1/Interrupt 4 input P5.2/T2CC2/INT5 T2 Compare/Capture output 2/Interrupt 5 input P5.3/T2CC3/INT6 T2 Compare/Capture output 3/Interrupt 6 input P5.4/INT2 Interrupt 2 input P5.5/INT9 Interrupt 9 input P5.6/INT8 Interrupt 8 input P5.7/INT7 Interrupt 7 input Table 1 Pin Defintions and Functions (cont’d) Sym- bol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

VSS 24, 43, 55 32, 51, 63– Ground (0 V) VDD 23, 44, 56 31, 52, 64 – Power Supply ( +5V ) VDDA 31 1 – Analog Power Supply (+ 5 V) VSSA 41 2 – Analog Ground (0 V) VAREF 13 21 – Reference voltage for the A/D converter. VAGND 14 22 – Reference ground for the A/D converter. 1) I= I n p u t O = Output Table 1 Pin Defintions and Functions (cont’d) Sym- bol Pin Numbers I/O 1) Function P-MQFP-64 P-SDIP-64

Figure 5 Block Diagram of the C508 C508 MCB04026 Oscillator Watchdog OSC & Timing PLL, factor of 2 CPU

4 PWM Channels

S&H XRAM 1024 x 8 RAM 256 x 8 ROM/OTP

The C508 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 10 MHz external crystal (giving a 20 MHz CPU clock), 58% of the instructions execute in 300 ns. For an 8 MHz crystal, the corresponding time is 375 ns. Special Function Register PSW (Address D0 H ) Reset Value: 00 H Bit Function CY Carry Flag Used by arithmetic instructions. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag 0 RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instructions. F1 General Purpose Flag 1 P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/ even number of “one” bits in the accumulator. CY AC F0 RS1 RS0 OV F1 PD0 H PSW D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH

Reset and System Clock Operation The reset input is an active high input. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (6 oscillator periods) while the oscillator is running. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (External stimulation at these lines during reset activates several reserved test modes. This, in turn, may cause unpredictable output operations at several port pins). At the reset pin, a pull-down resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained, when VDD is applied, by connecting the reset pin to VDD via a capacitor. After VDD has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. The time required for a reset operation includes the oscillator start-up time, the PLL lock time and the time for 2 machine cycles, which must be at least 10 - 20 ms, under normal conditions. This requirement is typically met using a capacitor of 4.7 to 10 µF. The same considerations apply if the reset signal is generated externally. In each case, it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. Figure 7 shows the possible reset circuitries. Figure 7 Reset Circuitries MCS04030 C508 RESET V DD + C508 RESET C508 RESET& V DD a) b) c)

Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology TM , which requires embedded logic in the C500 allows the C500 when used with an EH-IC, to function in a manner similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer information about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. MCS02647 SYSCON PCON TCON RESET EA PSEN ALE Port 0 Port 2 I/O Ports Optional Port 3 Port 1 C500 MCU Interface Circuit Enhanced Hooks RPort 0RPort 2 RTCON RPCON RSYSCON TEA TALE TPSEN EH-IC Target System Interface ICE-System Interface to Emulation Hardware

reside in the special function register area. Table 3. In Table 2 they are organized in groups which refer to the functional blocks of

Table 2 Special Function Registers - Functional Blocks Block Symbol Name Addr. Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP SYSCON VR0 1) VR1 1) VR2 1) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 H F0H 83H 82H 92H D0 H 81H B1H FC H FD H FE H 00H 00H 00H 00H XXXXX000 B 00H 07H XX10XX01 B C5 H 08H3) A/D- Converter ADCON0 4) ADCON1 ADDATH ADDATL A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Start Register Low Byte H DC H D9 H DA H 00X00000B 01XXX000 B 00H 00XXXXXX B Interrupt System IEN04) IEN14) IEN2 IEN3 IP0 IP1 TCON T2CON 4) SCON 4) IRCON EINT Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register External Interrupt Control Register H B8 H 9AH BE H A9H B9H 88H C8 H 98H C0 H FB H 00H X0000000B XX0000XX B XXX000XX B 00H XX000000 B 00H 00H 00H X0000000B XX000000 B XRAM XPAGE SYSCON 4) Page Address Register for Extended on-chip XRAM and CAN Controller System Control Register H B1H 00H XX10XX01 B Ports P0 Port 0 Port 1 Port 2 Port 3 Port 4, Analog/Digital Input Port 5 H 90H A0 H B0 H DB H F8H FFH FFH FFH FFH FFH Serial Channel ADCON0 4) PCON 4) SBUF SCON SRELL SRELH A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte H 87H 99H 98H AA H BA H 00X00000B 00H XX H 00H D9 H XXXXXX11 B

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Timer 2 CCEN T2CCH1 T2CCH2 T2CCH3 T2CCL1 T2CCL2 T2CCL3 CRCH CRCL TH2 TL2 T2CON Compare/Capture Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Comp./Rel./Capt. Register, High Byte Comp./Rel./Capt. Register, Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register H C3 H C5 H C7 H C2 H C4 H C6 H CB H CA H CD H CC H C8 H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Compare/ Capture Unit CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 TRCON COTRAP CCIR CCIE CT2CON CP2L CP2H CMP2L CMP2H BCON Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Trap enable control register Compare output in trap state register Capture/compare interrupt request flag reg. Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register H DE H DF H E6H E7H E3H E4H E2H F2H F3H F4H F5H F6H F7H FFH F9H E5H D6 H F1H D2 H D3 H D4 H D5 H D7 H 00010000B 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H XXXXXX00 B 00H XXXXXX00 B 00H Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Addr. Contents after Reset

IEN14) IP04) Watchdog Timer Register, low byte Watchdog Timer Register, high byte Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 H 85H 86H A8 H B8 H A9H 00H 00H 00H 00H 00H 00H Power Save Modes PCON PCON1 6) Power Control Register Power Control Register 1 87H 88H 00H 0XX0XXXX B 1) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 2) Bit-addressable special function registers 3) The content of this SFR varies with the actual step of the C508 (e.g. 01H for the first step) 4) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 5) “X” means that the value is undefined and the location is reserved. 6) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Addr. Contents after Reset

Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 86H WDTREL 00 H WDT PSEL 87H PCON 00 H SMOD PDS IDLS SD GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 3) PCON1 0XX0- XXXX B 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 92H DPSEL XXXX- X000B 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI 9A IEN2 XX00- 00XX B – – ECT1 ECCM ECT2 ECEM – – A0H A8H 2) IEN0 00H EA WDT ET2 ES ET1 EX1 ET0 EX0

2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B1H SYSCON XX10- XX01 B – – EALE RMAP – – XMAP1 XMAP0 B8H 2) IEN1 X000- 0000B – SWDT EX6 EX5 EX4 EX3 EX2 EADC B9H IP1 XX00- 0000B BA H SRELH XXXX- XX11 B BE H IEN3 XXX0- 00XX B C0 H 2) IRCON X000- 0000B – TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC C1 H CCEN 00 H COCA COCA COCA COCA COCA COCA COCA COCA C8 H 2) T2CON 0000- X0X0 B T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 D0 H 2) PSW 00H CY AC F0 RS1 RS0 OV F1 P Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

D3 H CP2H XXXX. XX00 B D5 H CMP2H XXXX. XX00 B D6 H CCIE 00 H ECTP ECTC CC2 FEN CC2 REN CC1 FEN CC1 REN CC0 FEN CC0 REN D7 H BCON 00 H BCMP BCEM PWM1 PWM0 EBCE BCERR BCEN BCM1 BCM0 D8 H 2) ADCON0 00X0- 0000B BD CLK – BSY ADM MX2 MX1 MX0 DA H ADDATL 00XX- XXXX B DC H ADCON1 01XX- X000B ADCL1 ADCL0 – – – MX2 MX1 MX0 E0H E1H CT1CON 0001- 0000B CTM ETRP STE1 CT1 RES CT1R CLK2 CLK1 CLK0 E2H COINI FF H COUT COUT XI COUT CC2I COUT CC1I COUT CC0I E3H CMSEL0 00 H CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL E4H CMSEL1 00 H ESMC NMCS 0 0 CMSEL CMSEL CMSEL CMSEL E5H CCIR 00 H CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R F0H Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

The C508 has one 8-bit analog or digital input port and five 8-bit I/O ports. Port 4 is a uni- directional input port. Port 0 is an open-drain bi-directional I/O port, while Ports 1, 2, 3 and 5 are quasi-bi-directional I/O ports with internal pullup transistors. That means, when configured as inputs, these ports will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of Ports 0 and 2 and the input buffers of Port 0 are also used for accessing external memory. In this application, Port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 F1H CT2CON 0001- 0000B CT2P ECT2O STE2 CT2 RES CT2R CLK2 CLK1 CLK0 F8H F9H COTRAP 00 H BCT SEL PDTEN COUT CC2T COUT CC1T COUT CC0T FB H EINT XX00- 0000B – – IEX9 I9FR IEX8 I8FR IEX7 I7FR FC H 3)4)VR0 C5 H 11000101 FD H 3)4)VR1 08 H 00001000 FE H FFH TRCON 00 H TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0 1) “X” means that the value is undefined and the location is reserved. 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual step of the C508 (e.g. 01H for C508-4E, first step and 11H for C508-4R, first step). Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr. Register Content after Reset1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the Port 2 pins continue emitting the P2 SFR contents. In this function, Port 0 is not an open-drain port, but uses a strong internal pullup FET. Port 4 provides the analog input channels to the A/D converter. Port Structures The C508 generally allows digital I/O on 32 lines grouped into 4 bi-directional 8-bit ports and analog/digital input on one uni-directional 8-bit port. Except for Port 4 which is the uni-directional input port, each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0-P5 (except P4) are performed via their corresponding special function registers. When Port 4 is used as analog input, an analog channel is switched to the A/D converter through a 3-bit multiplexer, which is controlled by three bits in SFR ADCON. Port 4 lines may also be used as digital inputs. In this case they are addressed as an input port via SFR P4. Since Port 4 has no internal latch, the contents of SFR P4 only depends on the levels applied to the input lines. It makes no sense to output a value to these input-only port by writing to the SFR P4. This will have no effect. The parallel I/O ports of the C508 can be grouped into four different types which are listed in Table 4. Type A and B port pins are standard C501 compatible I/O port lines, which can be used for digital I/O. Type A port (Port 0) is also designed for accessing external data or program memory. Type B port lines are located at Port 2, Port 3 and Port 5 to provide alternate functions for the serial interface, LED drive interface, PWM signals, or are used as control outputs during external data memory accesses. Type C port (Port 4) provides the analog input port. Type D port lines can be switched to push-pull drive capability when they are used as compare outputs of the CAPCOM unit. Table 4 C508 Port Structure Types Type Description A Standard digital I/O ports which can also be used for external address/data bus. B Standard multifunctional digital I/O port lines. C Digital/analog uni-directional input port. D Standard digital I/O with push-pull drive capability.

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 5. In the timer function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is fOSC /3. Figure 10 Timer/Counter 0 and 1 Input Clock Logic In the “counter” function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC /6. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the input clock logic. Table 5 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock M1 M0 Internal 0 8-bit timer/counter with a divide-by-32 prescaler 0 0fOSC /3 × 2<prescaler> 1 16-bit timer/counter 1 0 fOSC /3 2 8-bit timer/counter with 8 bit auto-reload 1 1

3 Timer/Counter 0 used as one 8-bit timer/counter

OSC ÷3 =1 1 P3.4/T0 P3.5/T1 P3.2/INT0 P3.3/INT1 Control GATE TMOD TR0/1 TCON C/T TMOD Timer 0/1 Input Clock Pin Pin

Timer/Counter 2 with Additional Compare/Capture/Reload Timer 2 with additional compare/capture/reload features is one of the most powerful peripheral units of the C508. It can be used for all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. Timer 2 is designed to support various automotive control applications as well as industrial applications (frequency generation, digital-to-analog conversion, process control etc.). The C508 Timer 2 in combination with the compare/capture/reload registers allows the following operating modes: – Compare: up to 4 PWM output signals with 65535 steps at maximum, and 300 ns resolution – Capture: up to 4 high speed capture inputs with 300 ns resolution – Reload: modulation of timer 2 cycle time The block diagram in Figure 11 shows the general configuration of Timer 2 with the additional compare/capture/reload registers. The I/O pins which can be used for Timer 2 control are located as multifunctional port functions at Port 5. Figure 11 Timer 2 Block Diagram MCB04054 16-Bit Comparator T2CCL3/ T2CCH3 Input/ Output Control P5.0/ T2CC0/ INT3 16-Bit Comparator T2CCL2/ T2CCH2 16-Bit Comparator T2CCL1/ T2CCH1 16-Bit Comparator CRCL/ CRCH Capture Timer 2 TL2 TH2 Compare TF2 Reload Interrupt Request Reload ÷ 3 ÷ 6 OSC T2I0 = '1' and T2I1 = '0' T2PS P5.1/ T2CC1/ INT4 P5.2/ T2CC2/ INT5 P5.3/ T2CC3/ INT6

Timer 2, which is a 16-bit-wide register, operates as a timer with its count rate derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/3 or 1/6 of the oscillator frequency. Thus, the 16-bit timer register (consisting of TH2 and TL2) is either incremented in every machine cycle or in every second machine cycle. Compare Function of the Timer 2 The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a compare/capture register is compared with the contents of the timer register. If the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin, and an interrupt is requested. The contents of a compare register can be regarded as “time stamp” at which a dedicated output reacts in a predefined way (either with a positive or negative transition). Variation of this “time stamp” somehow changes the wave of a rectangular output signal at a port pin. As a variation of the duty cycle of a periodic signal, this may be used for pulse width modulation as well as for a continually controlled generation of any kind of square waveforms. Two compare modes are implemented to cover a wide range of possible applications. Compare Mode 0 In mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. It goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the port will have no effect. Figure 12 shows a functional diagram of a port latch in compare mode 0. The port latch is directly controlled by the two signals timer overflow and compare. The input line from the internal bus and the write-to-latch line are disconnected when compare mode 0 is enabled. Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the inductance of a DC or AC motor). Mode 0 may also be used for providing output clocks with initially defined period and duty cycle. This is the mode which needs the least CPU time. Once set up, the output goes on oscillating without any CPU intervention.

Figure 13 Port Latch in Compare Mode 1 Capture Function Two different modes are provided for this function. In mode 0, an external event latches the Timer 2 contents to a dedicated capture register. In mode 1, a capture will occur upon writing to the low order byte of the dedicated 16-bit capture register. This mode is provided to allow the software to read the Timer 2 contents “on-the-fly”. MCS04060 Port Latch D CLK Q Q V DD Port Pin Internal Bus Write to Latch Read Latch Read Pin Compare Register Circuit Compare Reg. Timer Circuit Timer Register Comparator 16-Bit 16-Bit Compare Match Shadow Latch D CLK Q Port Circuit

Capture/Compare Unit (CCU) The Capture/Compare Unit (CCU) of the C508 has been designed for applications which demand for digital signal generation and/or event capturing (e.g. pulse width modulation, pulse width measuring). It consists of a 16-bit three-channel capture/compare unit (CAPCOM) and a 10-bit one-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non-overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. For motor control applications, both units (CAPCOM and COMP) may generate versatile multichannel PWM signals. For brushless DC motors, dedicated control modes are supported which are either controlled by software or by hardware (hall sensors).

Figure 14 Block Diagram of the Capture/Compare Unit CCU General Capture/Compare Unit Operation The compare timers 1 and 2 are free running, processor clock coupled 16-bit/10-bit timers; each of which has a count rate with a maximum of 2fOSC up to fOSC /64. The compare timer operations with its possible compare output signal waveforms are shown in Figure 15. Control CC Channel 0 (CCH0, CCL0) CC Channel 1 (CCH1, CCL1) CC Channel 2 (CCH2, CCL2) MCB04064 Prescaler Offset Register (CT1OFH,CT1OFL) Compare Timer 1 (16-Bit) Period Register (CCPH, CCPL) Mode Select Register (CMSEL0, CMSEL1) Trap/Initialization Registers (COINI, COTRAP , TREN) Port Control Logic Cntrl. Register (CT1CON) 16-Bit Capture/Compare Unit (CAPCOM) CC0 COUT0 CC1 COUT1 CC2 COUT2 2fOSC Compare Reg. (CMP2H, CMP2L) Prescaler Compare Timer 2 (10-Bit) Period Register (CP2H, CP2L) Cntrl. Register (CT2CON) 10-Bit Compare Unit (COMP) 2fOSC Block Commutation Control (BCON) INT0 INT1 INT2 COUT3 CTRAP

Figure 15 Basic Operating Modes of the CAPCOM Unit The compare timer can be operated in both up count in mode 0 and up and down count in mode 1 for edge and center aligned PWM waveforms respectively with a programmable dead time dead time (tOFF ) between CCx and COUTx. MCD04065 0000H CCx COUTx Compare Value Period Value a) Standard PWM (Edge Aligned) Offset { CCx COUTx Compare Value Period Value Standard PWM (Single Edge Aligned) with programmable dead time (tOFF ) Compare Timer 1 Operating Mode 0 0000H CCx COINI=0 COUTx COINI=1 Compare Value Period Value c) Symmetrical PWM (Center Aligned) Compare Timer 1 Operating Mode 1 CCx COINI=0 COUTx COINI=1 Compare Value Period Value Symmetrical PWM (Center Aligned) with programmable dead time (tOFF ) Offset { tOFF tOFF : Interrupt can be generated tOFF

Further, the initial logic output level of the CAPCOM channel outputs can be selected in compare mode. This allows waveforms to be generated with inverting signal polarities. The compare unit COMP is a 10-bit compare unit which can be used to generate a pulse width modulated signal. This PWM output signal drives the output pin COUT3. In burst mode and in the PWM modes the output of the COMP unit can be switched to the COUTx outputs. The block commutation control logic allows to generate versatile multi-channel PWM output signals. In one of these modes, the block commutation mode, signal transitions at the three external interrupt inputs are used to trigger the PWM signal generation logic. Depending on these signal transitions, the six I/O lines of the CAPCOM unit, which are decoupled in block commutation mode from the three capture/compare channels, are driven as static or PWM modulated outputs. CAPCOM channel 0 can be used in block commutation mode for a capture operation (speed measurement) which is triggered by each transition at the external interrupt inputs. Further, the multi-channel PWM mode signal generation can be also triggered by the period of Compare Timer 1. These operating modes are referenced as multi-channel PWM modes. Using the CTRAP input signal of the C508, the compare outputs can be put immediately into their state as defined in COTRAP register. The CCU unit has four main interrupt sources with their specific interrupt vectors. Interrupts can be generated at the Compare Timer 1 period match or count-change events, at the Compare Timer 2 period match event, at a CAPCOM compare match or capture event, and at a CAPCOM emergency event. An emergency event occurs if an active CTRAP signal is detected or if an error condition in block commutation mode is detected. All interrupt sources can be enabled/disabled individually. Table 6 Resolution and Period of the Compare Timer 1 (at fOSC = 10 MHz) Compare Timer 1 Input Clock Operating Mode 0 Operating Mode 1 Resolution Period Resolution Period fOSC fOSC fOSC / 2 fOSC / 4 fOSC / 8 fOSC / 16 fOSC / 32 fOSC / 64 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 µs 3.2 µs 6.4 µs 100 ns - 3.28 ms 200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms 1.6 µs - 52.43 ms 3.2 µs - 104.86 ms 6.4 µs - 209.72 ms 12.8 µs - 419.43 ms 50 ns 100 ns 200 ns 400 ns 800 ns 1.6 µs 3.2 µs 6.4 µs 200 ns - 6.55 ms 400 ns - 13.11 ms 800 ns - 26.21 ms 1.6 µs - 52.43 ms 3.2 µs - 104.86 ms 6.4 µs - 209.71 ms 12.8 µs - 419.42 ms 25.6 µs - 838.85 ms

Compare (COMP) Unit Operation The Capture/Compare Unit CCU of the C508 also provides a 10-bit Compare Unit (COMP) which operates as a single channel pulse generator with a pulse width modulated output signal. This output signal is available at the output pin COUT3 of the C508. In the combined multi-channel PWM modes and in burst mode of the CAPCOM unit the output signal of the COMP unit can also be switched to the output signals COUTx or CCx. Figure 16 shows the block diagram and the pulse generation scheme of the COMP unit. Figure 16 COMP Unit: Block Diagram and Pulse Generation Scheme The COMP unit has a 10-bit up-counter (Compare Timer 2, CT2) which starts counting from 000 H up to the value stored in the period register and then is again reset. This Compare Timer 2 operation is equal to the operating mode 0 of Compare Timer 1. When the count value of CT2 matches the value stored in the compare registers CMP2H/ CMP2L, COUT3 toggles its logic state. When Compare Timer 2 is reset to 000H , COUT3 toggles again its logic state. In the combined multi-channel PWM modes and in the burst mode, the Compare Timer 2 output signal can also be switched to the CAPCOM output pins COUT0, COUT1, and COUT3. In these modes, the polarity of the modulated output signal at COUT2-0 can be inverted by setting bit COUTXI (COINI.6) Combined Multi-Channel PWM Modes The CCU of the C508 has been designed to support also motor control or inverter applications which have a demand for specific multi-channel PWM signal generation. In these combined multi-channel PWM modes the CAPCOM unit (Compare Timer 1) and the COMP unit (Compare Timer 2) of the C508 CCU are working together. MCB04101 Programmable Prescaler Period Registers CP2H/CP2L Compare Timer 2 10-Bit Up Counter Control Register CT2CON Comparator Compare Registers CMP2H/CMP2L Pulse Generation Match Port Pin COUT3 COUTXI (COINI.6) COUT3I (COINI.7) 2fOSC ECT20 To CAPCOM Output Control

Block Commutation PWM Mode In block commutation mode the INT0-2 inputs are sampled once each processor cycle. If the input signal combination at INT0-2 changes its state, the outputs CCx and COUTx are set to their new state according to Table 7. Table 7 Black Commutation Control Table Mode (BCM1,BCM0) INT0 - INT2 Inputs CC0 - CC2 Outputs COUT0 - COUT2 Outputs INT0 INT1 INT2 CC0 CC1 CC2 COUT0 COUT1 COUT2 Rotate left1) Rotate right1) 1) If one of these two combinations of INTx signals is detected in rotate left or rotate right mode, bit BCERR flag is set. If enabled, a CCU emergency interrupt can be generated. When these states (error states) are reached, immediately idle state is entered. 0 0 0 inactive inactive inactive inactive inactive inactive 1 1 1 inactive inactive inactive inactive inactive inactive Rotate left, 60° phase shift (BCTSEL = 0, default) 1 0 1 inactive inactive active active inactive inactive 1 0 0 inactive active inactive active inactive inactive 1 1 0 inactive active inactive inactive inactive active 0 1 0 active inactive inactive inactive inactive active 0 1 1 active inactive inactive inactive active inactive 0 0 1 inactive inactive active inactive active inactive Rotate left, 0° phase shift (BCTSEL = 1) 1 0 1 inactive inactive active inactive active inactive 1 0 0 inactive inactive active active inactive inactive 1 1 0 inactive active inactive active inactive inactive 0 1 0 inactive active inactive inactive inactive active 0 1 1 active inactive inactive inactive inactive active 0 0 1 active inactive inactive inactive active inactive Rotate right 1 1 0 active inactive inactive inactive active inactive 1 0 0 active inactive inactive inactive inactive active 1 0 1 inactive active inactive inactive inactive active 0 0 1 inactive active inactive active inactive inactive 0 1 1 inactive inactive active active inactive inactive 0 1 0 inactive inactive active inactive active inactive Slow down X X X inactive inactive inactive active active active Idle 2) Idle state is also entered when a “wrong follower” is detected (if bit BCON.7 = BCEM is set). When idle state is entered, the BCERR flag is always set. Idle state can only be left when the BCERR flag is reset by software. X X X inactive inactive inactive inactive inactive inactive

The serial port of the C508 is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The four modes of USART is illustrated in Table 8. Table 8 USART Operating Modes SM0 SM1 Selected Operating Mode 0 0 Serial mode 0: Shift register, fixed baud rate ( fOSC /3) Serial data enters and exits through RxD; TxD outputs the shift clock 0 1 Serial mode 1: 8-bit USART, variable baud rate 10 bits are transmitted (through TxD) or received (at RxD) 1 0 Serial mode 2: 9-bit USART, fixed baud rate ( fOSC /8 or fOSC /16) 11 bits are transmitted (through TxD) or received (at RxD) 1 1 Serial mode 3: 9-bit USART, variable baud rate 11 bits are transmitted (through TxD) or received (at RxD)

There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. Figure 18 Baud Rate Generation for the Serial Port For clarification, some terms regarding the difference between “baud rate clock” and “baud rate” should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators must provide a “baud rate clock” to the serial interface which - there divided by 16 - results in the actual “baud rate”. However, all formulas given in the following section already include the factor and calculate the final baud rate. Further, the abbreviation fOSC refers to the external clock frequency (oscillator or external input clock operation). Depending on the programmed operating mode different paths are selected for the baud rate clock generation. Figure 18 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the special function register SCON. MCS04074 SCON.7/ SCON.6 (SM0/SM1) Mode 1 Mode 3 Mode 2 Mode 0 2fOSC Timer 1 Overflow Only one mode can be selected PCON.7 (SMOD) ÷ 2 Baudrate Clock Note: The switch configuration shows the reset state ADCON0.7 (BD) Baudrate Generator (SRELH SRELL) ÷ 6

Table 9 below lists the values/formulas for the baud rate calculations of the serial interface with its dependencies of the control bits BD and SMOD. Table 9 Serial Interface - Baud Rate Dependencies Serial Interface Operating Modes Active Control Bits Baud Rate Calculation BD SMOD Mode 0 (Shift Register) –– fOSC / 3 Mode 1 (8-bit UART) Mode 3 (9-bit UART) 0 x Controlled by timer 1 overflow: (2SMOD × Timer 1 overflow rate) / 32 1 x Controlled by baud rate generator (2SMOD × fOSC ) / (16 × baud rate generator overflow rate) Mode 2 (9-bit UART) – 0 fOSC / 16 1 fOSC / 8

The C508 provides an A/D converter with the following features:

• 8 input channels (Port 4) which can also be used as digital inputs
• 10-bit resolution
• Single or continuous conversion mode
• Interrupt request generation after each conversion
• Using successive approximation conversion technique via a capacitor array
• Built-in hidden calibration of offset and linearity errors A/D Converter Clock Selection The ADC uses two clock signals for operation: the conversion clock fADC (= 1/tADC ) and the input clock fIN (= 1/tIN). fADC is derived from the C508 system clock 2 × fOSC which is twice the crystal frequency applied at the XTAL pins via the ADC clock prescaler as shown in Figure 19. The input clock fIN is equal to 2 × fOSC. The conversion clock fADC is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. Figure 19 A/D Converter Clock Selection MUX ÷ 4 ÷ 8 ÷ 16 ÷ 32 Conversion Clock fADC A/D Converter 2fOSC ADCL0ADCL1 fADC max = 2 MHzCondition: fIN = 2fOSC = 4 TCL1) fADC [MHz] MCB04102 Oscillator Clock Rate (fOSC ) fIN [MHz] Prescaller Ratio

5 MHz

8 MHz

10 MHz

÷ 8 ÷ 8 ÷ 16 1.25 1.25 Input Clock fIN 1) Note: Please refer to AC characteristics in this document for the definition of TCL.

Figure 20 Block Diagram of the A/D Converter MCB04076 IEN1 (B8H ) IRCON (C0 H ) P4 (DBH ) ADCON1 (DC H ) ADCON0 (D8 H ) P4.7 ADCL1 BD SWDT EX6 EX5 EX4 EX3 EX2 EADC TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC ADCL0 - - - MX2 MX1 MX0 CLK - BSY ADM MX2 MX1 MX0 MCB A/D Converter ADDATH (D9H ) ADDATL (DAH ) S&HMUX Clock Prescaler ÷ 32, 16, 8, 4 2fOSC LSB Internal Bus Internal Bus Conversion Clock fADC Input Clock fIN V AREF V AGND Start of conversion Write to ADDATL Single/ Continuous Mode Port 4 Shaded bit locations are not used in ADC-functions.

The C508 provides nineteen interrupt vectors with four priority levels. Nine interrupt requests are generated by the on-chip peripherals (Timer 0, Timer 1, Timer 2, Serial Channel, A/D Converter, and the Capture/Compare Unit with four interrupts) and ten interrupts may be triggered externally. Four of the external interrupts (INT3, INT4, INT5 and INT6) can also be generated by the timer 2 in capture/compare mode. The wake-up from power-down mode interrupt has a special functionality which allows the software power-down mode to be terminated by a short negative pulse at either pin P3.2/INT0 or pin P5.7/INT7. The nineteen interrupt sources are divided into six groups. Each group can be programmed to one of the four interrupt priority levels.

Figure 21 Interrupt Structure, Overview Part 1 MCS04081 EX2 IEN1.1 IEX2 IRCON.1I2FR T2CON.5 P5.4/ INT2 0043H 0003H Highest Priority Level Polling Sequence EA IEN0.7 IP1.1 IP0.1 000B H 004B H Bit Addressable Request flag is cleared by hardware EX0 IEN0.0 IE0 TCON.1IT0 TCON.0 P3.2/ INT0 EADC IEN1.0 IADC IRCON.0 A/D Converter IP1.0 IP0.0 ET0 IEN0.1 TF0 TCON.5 Timer 0 Overflow Lowest Priority Level

Figure 22 Interrupt Structure, Overview Part 2 MCS04082 P5.0/ T2CC0/ INT3 EX7 IEX7 EINT.1I7FR EINT.0 P5.7/ INT7 0093H 0013H Highest Priority Level Lowest Priority Level EA IEN0.7 IP1.2 IP0.2 0053H 00D3 H Bit Addressable Request flag is cleared by hardware EX3 IEN1.2 IEN3.2 IEX3 IRCON.2I3FR T2CON.6 ECEM IEN2.2 ETRP CT1CON.6 EBCE BCON.4 TRF TRCON.6 BCERR BCON.3 CCU Emergency Interrupt EX1 IEN0.2 IE1 TCON.3IT1 TCON.2 P3.3/ INT1 Polling Sequence

Figure 23 Interrupt Structure, Overview Part 3 MCS04083 EX8 IEX8 EINT.3I8FR EINT.2 P5.6/ INT8 009B H 001B H Highest Priority Level Lowest Priority Level EA IEN0.7 IP1.3 IP0.3 005B H 00DB H Bit Addressable Request flag is cleared by hardware ET1 IEN0.3 TF1 TCON.7 Timer 1 Overflow ECT2 IEN2.3 CT2P CT2CON.7 Compare Timer 2 Interrupt P5.1/ T2CC1/ INT4 EX4 IEN1.3 IEN3.3 IEX4 IRCON.3 Polling Sequence

Figure 24 Interrupt Structure, Overview Part 4 MCS04084 ES IEN0.4 ES SCON.1 SCON.0USART CC0REN CCIE0.0 CC0R CCIR.0 CC0FEN CCIE0.1 CC0F CCIR.1 P1.2/ CC0 CC1REN CCIE0.2 CC1R CCIR.2 CC1FEN CCIE0.3 CC1F CCIR.3 P1.4/ CC1 CC2REN CCIE0.4 CC2R CCIR.4 CC2FEN CCIE0.5 CC2F CCIR.5 P1.6/ CC2 ECCM IEN2.4 Capture/Compare Match Interrupt EX5 IEN1.4 IEN3.4 IEX5 IRCON.4 P5.2/ T2CC2/ INT5 EX9 IEX9 EINT.5I9FR EINT.4 P5.5/ INT9 00A3 H 0023H Highest Priority Level Lowest Priority Level EA IEN0.7 IP1.4 IP0.4 0063H 00E3 H Bit Addressable Request flag is cleared by hardware RI Polling Sequence

Figure 25 Interrupt Structure, Overview Part 5 MCS04085 P5.3/ T2CC3/ INT6 00AB H 002B H Highest Priority Level Lowest Priority Level Polling Sequence EA IEN0.7 IP1.5 IP0.5 006B H Bit Addressable Request flag is cleared by hardware EX6 IEN1.5 IEX6 IRCON.5 ECT1 IEN2.5 ECTP CCIE.7 ECTC CCIE.6 CT1FP CCIR.7 CT1FC CCIR.6 Compare Timer 1 Interrupt ET2 IEN0.5 TF2 IRCON.6 Timer 2 Overflow

Table 10 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003 H IE0 Timer 0 Overflow 000B H TF0 External Interrupt 1 0013 H IE1 Timer 1 Overflow 001B H TF1 Serial Channel 0023 H RI / TI Timer 2 Overflow 002B H TF2 A/D Converter 0043 H IADC External Interrupt 2 004B H IEX2 External Interrupt 3 0053 H IEX3 External Interrupt 4 005B H IEX4 External Interrupt 5 0063 H IEX5 External Interrupt 6 006B H IEX6 CAPCOM Emergency Interrupt 0093H TRF/BCERR Compare Timer 2 Interrupt 009BH CT2P Capture/Compare Match Interrupt 00A3H CCxF / CCxF, x = 0 to 2 Compare Timer 1 Interrupt 00ABH CT1FP / CT1FC External Interrupt 7 00D3 H IEX7 External Interrupt 8 00DB H IEX8 External Interrupt 9 00E3 H IEX9 Wake-up from power-down mode 007BH –

The C508 offers enhanced fail save mechanisms, which allow an automatic recovery from software or hardware failure: – a programmable watchdog timer (WDT), with variable time-out period from 153.6µs to 314.573 ms at fOSC = 10 MHz. – an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. Programmable Watchdog Timer To protect the system against software failure, the user’s program must clear this watchdog within a previously programmed time period. If the software fails to do this periodical refresh of the watchdog timer, an internal reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. It also times out if a software error is based on hardware-related problems. The Watchdog Timer in the C508 is a 15-bit timer, which is incremented by a count rate of fOSC /6 upto fOSC /96. The machine clock of the C508 is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. To program the Watchdog Timer overflow rate, the upper 7 bits of the Watchdog Timer can be written. Figure 26 shows the block diagram of the Watchdog Timer unit. Figure 26 Block Diagram of the Programmable Watchdog Timer MCS04087 fOSC /3 WDTL WDTH 14 8 70 6 WDTREL (86 H ) ÷ 16÷ 2 OWDS WDTS - - - - - - - WDT - - - - - - - SWDT - - - - - - Control Logic WDTPSELIP0 (A9H ) WDT Reset-Request External HW Reset IEN0 (A8H ) IEN1 (B8H )

The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped during active mode of the device. If the software fails to clear the Watchdog Timer an internal reset will be initiated. The cause of the reset (either an external reset or a reset caused by the watchdog) can be examined by software (status flag WDTS in IP0 is set). A refresh of the Watchdog Timer is done by setting bits WDT (SFR IEN0) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the Watchdog Timer is halted during the idle mode and power-down mode of the processor. Oscillator Watchdog Unit The Oscillator Watchdog unit serves for three functions:

• Monitoring of the on-chip oscillator’s function The watchdog supervises the on-chip oscillator’s frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset. If the failure condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typically 1 ms in order to allow the oscillator to stabilize; then, the Oscillator Watchdog reset is released and the part starts program execution again.
• Fast internal reset after power-on The Oscillator Watchdog unit provides a clock supply for the reset before the on-chip oscillator and the PLL have started.
• Control of external wake-up from software power-down mode When the software power-down mode is terminated by a low level at pins P3.2/INT0 or P5.7/INT7, the Oscillator Watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator, the on-chip oscillator and the PLL are stopped. They are started again when power-down mode is terminated. After the on- chip oscillator is stable and the PLL has been locked, the microcontroller starts program execution. Note: The Oscillator Watchdog unit is always enabled. Table 11 Watchdog Timer Time-Out Periods WDTREL Time-Out Period Comments fOSC = 5 MHz fOSC = 8 MHz fOSC = 10 MHz 00H 39.322 ms 24.576 ms 19.668 ms This is the default value 80H 629.146 ms 393.2 ms 314.573 ms Maximum time period 7FH 307.2 µs 192 µs1 5 3 . 6 µs Minimum time period

Figure 27 Functional Block Diagram of the Oscillator Watchdog Fast Internal Reset after Power-On Normally the members of the 8051 family (e.g. SAB 80C52) do not enter their default reset state before the on-chip oscillator starts. In the C508, after power-on, the Oscillator Watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 µs). The watchdog circuitry detects a failure condition for the on-chip oscillator because they have not yet started (a failure is always recognized if the watchdog’s RC oscillator runs faster than the gated PLL clock output). As long as this condition is valid the watchdog uses the RC oscillator output as the clock source for the chip. This allows the chip to be correctly reset and brings all ports to the defined state. The exception is Port 1, which will be at its default state when external reset is active. MCB04088 Frequency Comparator ÷ 5 Control Logic On-Chip Oscillator XTAL2 XTAL1 Control Logic P5.7/ INT7 P3.2/ INT0 EWPD (PCON1.0) WS (PCON1.4) Power-down mode activated Start/ stop Start/ stop fRC fOSC Delay f2 < f1 ≥1 RC Oscillator OWDS IP0 (A9H ) Power-down mode wake-up interrupt Internal Reset System Clock Generator System Clock (2 x fOCS )

The C508 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode.

• Idle Mode In the idle mode, the oscillator of the C508 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, the capture/compare unit, and all timers (with the exception of the Watchdog Timer) are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode.
• Slow Down Mode In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (for example, if the controller is waiting for an input signal). Since in CMOS devices, there is an almost linear dependence of the operating frequency and the power supply current, so, a reduction of the operating frequency results in reduced power consumption.
• Software Power Down Mode In the software power down mode, the RC oscillator, the on-chip oscillator which operates with the XTAL pins and the PLL are all stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ALE and PSEN are held at logic low level. This power down mode is entered by software and can be left by reset.

State of Pins in Software Initiated Power Saving Modes In the idle mode and power down mode, the port pins of the C508 have well defined states which is listed in the following Table 12. The state of some pins also depends on the location of the code memory (internal or external). In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked and the VDD is restored to its normal operation level, before the power down mode is terminated. Table 13 gives a general overview of the entry and exit procedures of the power saving modes. Table 12 Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Internal Code Memory Last Instruction Executed from External Code Memory Idle Power Down Idle Power Down ALE High Low High Low PSEN High Low High Low PORT 0 Data Data Float Float P O R T 2 D a t aD a t aA d d r e s s D a t a PORT 1, 3, 4, 5 Data / alternate outputs Data / last output Data / alternate outputs Data / last output

Table 13 Power Saving Modes Overview Mode Entering 2-Instruction Example Leaving by Remarks Idle Mode ORL PCON,#01 H ORL PCON,#20 H Occurance of any enabled interrupt CPU clock is stopped; CPU maintains its data; peripheral units are active (if enabled) and provided with clock Hardware Reset Slow Down Mode In normal mode: ORL PCON,#10 H ANL PCON,#0EF H or Hardware Reset Internal clock rate is reduced to a factor of 1/32 of the nominal system clock rate (1/16 of fOSC ) With idle mode: ORL PCON,#01 H ORL PCON,#30 H Occurance of any enabled interrupt to exit idle mode and the instruction ANL PCON,#0EF H to terminate slow down mode CPU clock is stopped; CPU maintains all its data; Peripheral units are active (if enabled) and provided with 1/32 of the nominal system clock rate (1/16 of fOSC ) Hardware Reset Software Power Down mode With external wake-up capability from power down enabled ORL SYSCON,#10 H ORL PCON1,#80 H (to wake-up via pin P3.2/INT0) or ORL PCON1,#90 H (to wake-up via pin P5.7/INT7) ANL SYSCON,#0EF H ORL PCON,#02 H ORL PCON,#40 H Hardware Reset Oscillator is stopped; Contents of on-chip RAM and SFR’s are maintained When P3.2/INT0 (or P5.7/ INT7) goes low for at least 10 µs (latch phase). But it is desired that the corresponding pin must be held at high level during the power down mode entry and up to the wake-up. With external wake-up capability from power down disabled ORL PCON,#02 H ORL PCON,#40 H Hardware Reset

Pin Configuration in Programming Mode Figure 29 OTP Programming Mode Pin Configuration for P-MQFP-64-1 Package (top view) MCP04091 A5/A13 49 55V SS 57D0 A6/A14 PSEN PROG 45 44 V DD XTAL1 42 41 XTAL2 N.C. N.C. 39 38 N.C. PALE PRD 36 35 PSEL PMSEL1 PMSEL0 32 N.C. 22 N.C. V DD RESETEA/ V PP 23 4 56 7 89 10 11 1213 14 1516 V DD V SS C508-4E A4/A12 A3/A11 A2/A10 A1/A9 A0/A8 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

Figure 30 OTP Programming Mode Pin Configuration for P-SDIP-64-2 Package (top view) MCP04092 C508-4E D0 1 D1 2 3D2 D3 4 5D4 6D5 D6 7 8D7 9RESET EA/V PP 10 11N.C. V DD V SS

62 A0/A8

53 PROG

48 N.C.

45 PALE

44 PRD

42 PMSEL1

41 PMSEL0

N.C.40 39 N.C. V SS V DD V SS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. A1/A9 A2/A10 A3/A11 A4/A12 A5/A13 A6/A14 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.

Table 14 contains the functional description of all C508-4E pins which are required for OTP memory programming. Table 14 Pin Definitions and Functions of the C508-4E in Programming Mode Symbol Pin Number I/O 1) Function P-MQFP-64-1 P-SDIP-64-2 RESET 1 9 I Reset This input must be at static ‘1’ (active) level throughout the entire programming mode. PMSEL0 PMSEL1 I I Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PSEL 35 43 I Basic programming mode select This input is used for the basic programming mode selection and must be switched according to Figure 31. PRD 36 44 I Programming mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. PALE 37 45 I Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1,0 is changed. XTAL2 47 49 O XTAL2 Output of the inverting oscillator amplifier. PMSEL1 PMSEL0 Access Mode 00R e s e r v e d 0 1 Read signature bytes 1 0 Program/read lock bits 1 1 Program/read OTP memory byte

Input to the oscillator amplifier. VSS 24, 43, 55 32, 51, 63 – Ground (0 V) must be applied in programming mode. VDD 23, 44, 56 31, 52, 64 – Power Supply (+ 5 V) must be applied in programming mode. P2.7- P2.0 47 - 54 55 - 62 I Address lines P2.0-P2.7 are used as multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. PSEN 46 54 I Program store enable This input must be at static ‘0’ level during the whole programming mode. PROG 45 53 I Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program and lock bit write operations. During basic programming mode selection, a low level must be applied to PROG EA /VPP 21 0 – Programming voltage This pin must be at 11.5 V (VPP ) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation, this pin must be at VIH2 high level. This pin is also used for basic programming mode selection. For basic programming mode selection a low level must be applied to EA/VPP . P0.7- P0.0 57 - 64 1 - 8 I/O Data lines In programming mode, data bytes are transferred via the bi-directional D7-D0 lines which are located at Port 0. N.C. 3 - 12, 15 - 22, 25 - 32, 38 - 40 11 - 30, 33 - 40, 46 - 48 – Not Connected These pins should not be connected in programming mode. 1) I = Input O=O u t p u t Table 14 Pin Definitions and Functions of the C508-4E in Programming Mode (cont’d) Symbol Pin Number I/O 1) Function P-MQFP-64-1 P-SDIP-64-2

Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts: – Basic programming mode selection – Access mode selection With basic programming mode selection, the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/ read, version byte read, and program/read lock byte operations. Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 31. Figure 31 Basic Programming Mode Selection MCD04093 V DD 5 V Clock (XTAL1/ XTAL2) RESET "1" PSEN "0" PMSEL1,0 PROG PRD "1" "0" 0,1 PSEL PALE "0" EA/V PP V PP V IH2 0 V Ready for access mode selectionDuring this period signals are not actively driven Stable

Table 15 Access Modes Selection Access Mode EA / V PP PROG PRD PMSEL Address (Port 2) Data (Port 0)10 Program OTP memory byte VPP H H H A0-A7 A8-A14 D0-D7 Read OTP memory byte VIH2 H Program OTP lock bits VPP HH L –D 1 , D 0 see Table 16 Read OTP lock bits VIH2 H Read OTP version byte VIH2 H L H Byte addr. of version byte D0-D7

Lock Bits Programming/Read The C508-4E has two programmable lock bits which, when programmed according to Table 16, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Note:A ‘1’ means that the lock bit is unprogrammed, a ‘0’ means that lock bit is programmed. Table 16 Lock Bit Protection Types Lock Bits at D1,D0 Protection Level Protection Type D1 D0 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C508-4E, the state of the EA pin is not latched on reset. 1 0 Level 1 During normal operation of the C508-4E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to OTP verification mode 2. Further programming of the OTP memory is disabled (reprogramming security). 0 1 Level 2 Same as Level 1, but also OTP memory read operation using OTP verification mode is disabled. 0 0 Level 3 Same as Level 2, but additionally external code execution by setting EA = low during normal operation of the C508-4E is no longer possible. External code execution, initiated by an internal program (e.g. by an internal jump instruction above the OTP memory boundary), is still possible.

Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS ) the voltage on VDD pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings. Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes min. max. Storage temperature TST –6 5 1 5 0 °C– Voltage on VDD pins with respect to ground (VSS ) VDD –0 . 5 6 . 5 V – Voltage on any pin with respect to ground (VSS ) VIN –0 . 5 VDD + 0.5 V – Input current on any pin during overload condition – – 10 10 mA – Absolute sum of all input currents during overload condition Power dissipation PDISS –t . b . d . W – Operating Conditions Parameter Symbol Limit Values Unit Notes min. max. Supply voltage VDD 4.5 5.5 V – Ground voltage VSS 0V – Ambient temperature SAB-C508 SAF-C508 TA TA –4 0 °C– Analog reference voltage VAREF 4 VDD + 0.1 V – Analog ground voltage VAGND VSS – 0.1 VSS + 0.2 V – Analog input voltage VAIN VAGND VAREF V– CPU clock fCPU 10 20 MHz –

The parameters listed in the following partly represent the characteristics of the C508 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (C ontroller C haracteristics) The logic of the C508 will provide signals with the respective characteristics. SR (System R equirements) The external system must provide signals with the respective characteristics to the C508. DC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditionmin. max. Input low voltage (except EA , RESET) VIL SR – 0.5 0.2 VDD – 0.1 Input low voltage (EA) VIL1 SR – 0.5 0.2 VDD – 0.3 Input low voltage (RESET) VIL2 SR – 0.5 0.2 VDD + 0.1 Input high voltage (except RESET, EA, XTAL1) VIH SR 0.2 VDD + 0.9VDD + 0.5 V – Input high voltage to RESET VIH1 SR 0.6 VDD VDD + 0.5 V – Input high voltage to EA VIH2 SR 0.7 VDD VDD + 0.5 V 1) 0.2 VDD + 0.9VDD + 0.5 V 2) Input high voltage to XTAL1 VIH3 SR 0.7 VDD VDD + 0.5 V – Output low voltage (Ports 3, 5) (Ports 1, 2) VOL CC 0.45 0.45 V V IOL = 1.6 mA3) IOL = 10 mA3) Output low voltage (Port 0, ALE, PSEN) VOL1 CC – 0.45 V IOL = 3.2 mA3) Output high voltage (Ports 1, 2, 3, 5) VOH CC 2.4 0.9VDD V V IOH =–8 0 µA IOH =–1 0 µA

(Port 0 in external bus mode, ALE, PSEN VOH2 CC 2.4 0.9VDD V V IOH =–8 0 0µA4) IOH =–8 0 µA4) Logic 0 input current (Ports 1, 2, 3, 5) IIL SR – 10 – 70 µA VIN =0 . 4 5V Logical 0-to-1 transition current (Ports 1, 2, 3, 5) ITL SR – 65 – 650 µA VIN =2V Input leakage current (Port 0, AN0-7 (Port 4), EA) ILI CC – ± 1 µA0 . 4 5 <VIN < VDD Pin capacitance C IO CC – 10 pF fc =1M H z , TA =2 5°C Overload current IOV SR – ± 5m A 11) 12) Programming voltage1) VPP SR 10.9 12.1 V 11.5 V ± 5% See the following pages for notes. DC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Conditionmin. max.

Parameter Symbol Limit Values Unit Test Conditiontyp.12) max.13) Active mode C508-4E 5 MHz 22.7 44.5 26.6 50.7 mA mA C508-4R 5 MHz t.b.d. t.b.d. t.b.d. t.b.d. mA mA Idle mode C508-4E 5 MHz 18.8 20.1 22.1 24.3 mA mA C508-4R 5 MHz t.b.d. t.b.d. t.b.d. t.b.d. mA mA Active mode with slow-down enabled C508-4E 5 MHz 6.5 8.8 7.5 10.0 mA mA C508-4R 5 MHz t.b.d. t.b.d. t.b.d. t.b.d. mA mA Idle mode with slow-down enabled C508-4E 5 MHz 6.4 8.2 7.5 9.2 mA mA C508-4R 5 MHz t.b.d. t.b.d. t.b.d. t.b.d. mA mA Power-down mode C508-4E IPD 0.5 20.0 µA VDD =2 …

5.5 V5)

Notes: 1) Applicable to C508-4E only. 2) Applicable to C508-4R only. 3) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a Schmitt-trigger, or use an address latch with a Schmitt-trigger strobe input. 4) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address lines are stabilizing. 5) IPD (power-down mode) is measured under following conditions: EA = Port 0 =VSS ; RESET = VSS ; XTAL2 = N.C.; XTAL1 =VSS ; VAGND = VSS ; VAREF = VDD ; all other pins are disconnected. 6) IDD (active mode) is measured with: XTAL1 driven with tR , tF =5n s , VIL= VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.; EA =P o r t 0=VDD ; RESET =VDD ; all other pins are disconnected. IDD would be slightly higher if the crystal oscillator is used (approx. 1 mA). 7) IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF = 5 ns, VIL= VSS +0 . 5V , VIH = VDD – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 =VDD ; all other pins are disconnected. 8) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF =5n s , VIL= VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 =VDD ; all other pins are disconnected; the microcontroller is put into slow-down mode by software. 9) IDD (idle mode with slow-down mode) is measured all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF =5n s , VIL= VSS + 0.5 V, VIH = VDD – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 =VDD ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down mode enabled by software. 10)Overload conditions under operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS – 0.5 V). The absolute sum of input currents on all port pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits. 11)Not 100% tested, guaranteed by design characterization 12)The typical IDD values are periodically measured at TA = + 25°C but not 100% tested. 13)The maximum IDD values are measured under worst case conditions (TA = 0°C or – 40°C and VDD =5 . 5V ) .

Power Supply Current Calculation Formulas Parameter Symbol Formula Active mode C508-4E IDD typ IDD max 4.37 × fOSC + 0.80 4.82 × fOSC + 2.53 C508-4R IDD typ IDD max t.b.d. t.b.d. Idle mode C508-4E IDD typ IDD max 0.25 × fOSC + 17.59 0.45 × fOSC + 19.81 C508-4R IDD typ IDD max t.b.d. t.b.d. Active mode with slow-down enabled C508-4E IDD typ IDD max 0.47 × fOSC + 4.17 0.50 × fOSC + 5.02 C508-4R IDD typ IDD max t.b.d. t.b.d. Idle mode with slow-down enabled C508-4E IDD typ IDD max 0.36 × fOSC + 4.61 0.35 × fOSC + 5.68 C508-4R IDD typ IDD max t.b.d. t.b.d.

Further timing conditions: tADC min = 500 ns and tIN = 1/(2 fOSC ) = 2 TCL A/D Converter Characteristics (Operating conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltageVAIN SR VAGND VAREF V 1) Sample time tS CC –6 4 × tIN 32 × tIN 16 × tIN 8 × tIN ns Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 4 Conversion cycle timetADCC CC – 384 × tIN 192 × tIN 96 × tIN 48 × tIN ns Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 4 Total unadjusted errorTUE CC – ± 2L S B VAGND ≤ VAIN ≤ VAREF Internal resistance of reference voltage source RAREF SR – tADC / 250 – 0.25 kΩ tADC in [ns]5)6) Internal resistance of analog source RASRC SR – tS / 500 – 0.25 kΩ tS in [ns]2)6) ADC input capacitance C AIN CC – 50 pF 6) Clock Calculation Table Clock Prescaler Ratio ADCL1, 0 tADC tS tADCC ÷ 32 1 1 32 × tIN 64 × tIN 384 × tIN ÷ 16 1 0 16 × tIN 32 × tIN 192 × tIN ÷ 8 0 1 8 × tIN 16 × tIN 96 × tIN ÷ 4 0 0 4 × tIN 8 × tIN 48 × tIN

Notes: 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 00H or FFH , respectively. 2) During the sample time the input capacitance C AIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE (max.) is tested at – 40≤ TA ≤ 85 °C; VDD ≤ 5.5 V; VAREF ≤ VDD + 0.1 V and VSS ≤ VAGND . It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. If a conversion is started during a reset calibration phase, TUE (max.) will be ± 6 LSB. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization.

Definition of Internal Timing The internal operation of the C508 is controlled by the internal CPU clock fCPU which is derived from the oscillator clock. The high time and the low time of the CPU clock at 50% duty cycle is referred to as a TCL. The specification of the external timing (AC Characteristics) is given in terms of this basic unit. Figure 33 Relationship between Oscillator and CPU Clock MCS04104 TCL fOSC TCL 4TCL fCPU

(Operating conditions apply) C L for Port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Parameter Symbol Limit Values Unit 10-MHz clock Duty Cycle 0.5 to 0.5 Variable Clock 1/4TCL = 5 MHz to min. max. min. max. Program Memory Characteristics ALE pulse width tLHLL CC 35 – 2TCL – 15 – ns Address setup to ALE tAVLL CC 10 – TCL – 15 – ns Address hold after ALE tLLAX CC 10 – TCL – 15 – ns ALE low to valid instr intLLIV SR – 55 – 4 TCL – 45 ns ALE to PSEN tLLPL CC 10 – TCL – 15 – ns PSEN pulse width tPLPH CC 60 – 3 TCL – 15 – ns PSEN to valid instr intPLIV SR – 25 – 3 TCL – 50 ns Input instruction hold after PSEN tPXIX SR 0 – 0 – ns Input instruction float after PSEN tPXIZ 1)SR – 20 – TCL – 5 ns Address valid after PSENtPXAV 1)CC 20 – TCL – 5 – ns Address to valid instr intAVIV SR – 65 – 5 TCL – 60 ns Address float to PSEN tAZPL CC – 5 – – 5 – ns

External Data Memory Characteristics RD pulse width tRLRH CC 120 – 6 TCL – 30 – ns WR pulse width tWLWH CC 120 – 6 TCL – 30 – ns Address hold after ALE tLLAX2 CC 35 – 2 TCL –15 – ns RD to valid data in tRLDV SR – 75 – 5 TCL – 50 ns Data hold after RD tRHDX SR 0 – 0 – ns Data float after RD tRHDZ SR – 38 – 2 TCL – 12 ns ALE to valid data in tLLDV SR – 150 – 8 TCL – 50 ns Address to valid data intAVDV SR – 150 – 9 TCL – 75 ns ALE to WR or RD tLLWL CC 60 90 3 TCL – 15 3 TCL + 15 ns Address valid to WR tAVWL CC 70 – 4 TCL – 30 – ns WR or RD high to ALE hightWHLH CC 10 40 TCL –15 TCL + 15 ns Data valid to WR transitiontQVWX CC 5 – TCL – 20 – ns Data setup before WR tQVWH CC 125 – 7 TCL – 50 – ns Data hold after WR tWHQX CC 5 – TCL – 20 – ns Address float after RD tRLAZ CC – 0 – 0 ns 1) Interfacing the C508 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. AC Characteristics (cont’d) (Operating conditions apply) C L for Port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Parameter Symbol Limit Values Unit 10-MHz clock Duty Cycle 0.5 to 0.5 Variable Clock 1/4TCL = 5 MHz to min. max. min. max.

Figure 34 Program Memory Read Cycle External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq. = 5 MHz to 10 MHz min. max. Oscillator period tOSC SR 100 200 ns High time t1 SR 50 2 TCL ns Low time t2 SR 50 2 TCL ns Rise time tR SR –1 0 n s Fall time tF SR – 10 ns MCT00096 ALE PSEN Port 2 LHLLt A8 - A15 A8 - A15 A0 - A7 Instr.IN A0 - A7Port 0 tAVLL PLPH t tLLPL tLLIV tPLIV tAZPL tLLAX tPXIZ tPXIX tAVIV tPXAV

Figure 35 Data Memory Read Cycle MCT00097 ALE PSEN Port 2 WHLHt Port 0 RD tLLDV tRLRHtLLWL tRLDV tAVLL tLLAX2 tRLAZ tAVWL tAVDV tRHDX tRHDZ A0 - A7 from Ri or DPL from PCL A0 - A7 Instr. INData IN A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

Figure 36 Data Memory Write Cycle Figure 37 External Clock Drive on XTAL1 MCT00098 ALE PSEN Port 2 WHLHt Port 0 WR tWLWHtLLWL tQVWX tAVLL tLLAX2 tQVWH tAVWL tWHQX A0 - A7 from Ri or DPL from PCL A0 - A7 Instr.INData OUT A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH MCT04105 tR tF tOSC

0.7 V DD

0.2 V DD - 0.1

AC Characteristics of Programming Mode (Operating conditions apply) Parameter Symbol Limit Values Unit min. max. PALE pulse width tPAW 35 –n s PMSEL setup to PALE rising edge tPMS 10 – ns Address setup to PALE, PROG, or PRD falling edge tPAS 10 – ns Address hold after PALE, PROG, or PRD falling edge tPAH 10 – ns Address, data setup to PROG or PRD tPCS 100 – ns Address, data hold after PROG or PRD tPCH 0–n s PMSEL setup to PROG or PRD tPMS 10 – ns PMSEL hold after PROG or PRD tPMH 10 – ns PROG pulse width tPWW 100 – µs PRD pulse width tPRW 100 – ns Address to valid data out tPAD –7 5 n s PRD to valid data out tPRD –2 0 n s Data hold after PRD tPDH 0–n s Data float after PRD tPDF –2 0 n s PROG high between two consecutive PROG low pulses tPWH1 1– µs PRD high between two consecutive PRD low pulses tPWH2 100 – ns XTAL clock period tCLKP 100 200 ns

Figure 38 Programming Code Byte - Write Cycle Timing tPAW tPMS PAHtPASt A8-A13 A0-A7 D0-D7 PCSt PWWt PCHt tPWH MCT03369 H, H PALE PMSEL1,0 Port 2 Port 0 PROG Note: PRD must be held high during a programming write cycle.

Figure 39 Verify Code Byte - Read Cycle Timing tPAW tPMS PAHtPASt A8-A13 A0-A7 PADt D0-D7 tPDH tPDFPRDt PCSt PRWt PCHt tPWH MCT03370 H, H PALE PMSEL1,0 Port 2 Port 0 PRD Note: PROG must be high during a programming read cycle.

Figure 42 ROM Verification Mode 1 ROM/OTP Verification Characteristics for C508-4R/C508-4E ROM Verification Mode 1 (C508-4R only) Parameter Symbol Limit Values Unit min. max. Address to valid data tAVQV – 10 TCL ns MCS04106 AddressP1.0-P1.7 P2.0-P2.6 Port 0 P2.7, PSEN = V SS ALE = V IH, EA = V IH2 RESET = V IH1 Inputs: Data OUT tAVQV P1.0 - P1.7 = A0 - A7 P2.0 - P2.6 = A8 - A14 P0.0 - P0.7 = D0 - D7 Address: Data:

Package Information

P-MQFP-64-1 (SMD) (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

0.25 17.02±0.25 ±0.05 +0.719.05 21.0 max 1±0.31.78 0.45±0.1 3364 Index Marking 3.0 min 0.5 min 5.65 max -0.55 +0.22 Does not include plastic or metal protrusions of 0.25 max per side 4.35 max GPD09257 P-SDIP-64-2 (SMD) (Plastic Shrink Dual In-Line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device

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