C505CA-4E

C505A SIEMENS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 76

Technical content

Addendum to C505/C505C User's Manual 09.97 C505A C505 CA 8-Bit CMOS Microcontroller http://www .siemens.de/ Semiconductor/

Edition 09.97 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73,

81541 München

© Siemens AG 97. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en- dangered.

1 Introduction

The C505A is an enhanced, upgraded version of the C505-2R eight bit microcontroller and incorporates more on-chip RAM, a 10-bit A/D Converter and 32K bytes of on-chip OTP memory. With a maximum external clock rate of 20 MHz, the C505A has an instruction cycle time of 300 ns. With the C505A-4E fast OTP programming cycles are achieved (1 byte in 100 µsec). Also several levels of OTP memory protection can be selected. The basic functionality of the C505A-4E as a microcontroller is identical to the C505A-L (romless part) functionality. Therefore, the programmable C505A-4E typically can be used for prototype system design. The C505A-4E basically operates with internal OTP and/or external program memory. The C505A- L is identical to the C505A-4E, except that it lacks the on-chip OTP memory. Therefore, in this documentation the term C505A refers to all versions within this specification unless otherwise noted. The C505CA-4E and C505CA-L, are identical to the C505A-4E and the C505A-L respectively, except that they have, in addition, the full CAN interface. The term C505A refers to all the above four versions within this documentation unless otherwise noted. Figure 1-1 shows the different functional units of the C505A and Figure 1-2 shows the simplified logic symbol of the C505A. Figure 1-1 C505A Functional Units Note: This specification describes only the improved functionality over C505/C505C. Please refer to the C505/C505C User’s Manual for further details. Oscillator Watchdog 10-bit ADC CPU 8-bit USART I/O I/O 8 digit. I/O I/O OTP 32K × 8 RAM 256 × 8 XRAM

1 K × 8

On-Chip Emulation Support Module Timer 2 Watchdog Timer 8 analog inputs / Full-CAN Controller 8 datapointers I/O (2-bit I/O port) Port 0 Port 1 Port 2 Port 4 Port 3 Enhancements over C505/C505C. C505CA only.

Listed below is a summary of the main features of the C505A family:

• Fully compatible to standard 8051 microcontroller
• Superset of the 8051 architecture with 8 datapointers
• Up to 20 MHz operating frequency – 375 ns instruction cycle time @ 16 MHz – 300 ns instruction cycle time @ 20 MHz (50 % duty cycle)
• 32K byte on-chip OTP memory – C505A-4E : programmable OTP versions – C505A-L : without on-chip program memory – alternatively up to 64 K bytes of external program memory
• 256 byte on-chip RAM
• 1 K byte on-chip XRAM
• Five ports: 32 + 2 digital I/O lines(Port 1 with mixed analog/digital I/O capability)
• Three 16-bit timers/counters – Timer 0 / 1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation
• Full CAN Module (C505CA only) – 256 register/data bytes located in external data memory area – 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz – internal CAN clock prescaler when input frequency is over 10 MHz
• Full duplex serial interface with programmable baudrate generator (USART)
• 10-bit A/D Converter with 8 multiplexed inputs – Built-in self calibration
• Twelve interrupt sources with four priority levels
• On-chip emulation support logic –Enhanced Hooks Technology TM 1)
• Programmable 15-bit Watchdog Timer
• Oscillator Watchdog
• Fast Power On Reset
• Power Saving Modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin
• P-MQFP-44 package
• Pin configuration is compatible to C501, C504, C511/C513-family, C505, C505C
• Temperature ranges: SAB-C505A versions TA = 0 to 70 °C SAF-C505A versions TA = – 40 to 85°C SAH-C505A versions TA = – 40 to 110°C (max. operating frequency: TBD) SAK-C505A versions TA = –40 to 125°C (max. operating frequency: 12 MHz with 50 % duty cycle) 1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens.

C505CA only. C505CA

1.1 Pin Configuration

This section shows the pin configuration of the C505A in the P-MQFP-44 package. Figure 1-3 Pin Configuration (Top View) P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P4.1 / RXDC P2.5 / A13 ALE P2.6 / A14 P2.7 / A15 PSEN P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 V CC XTAL1 XTAL2 P3.7 / RD P3.6 / WR V SS 32 31 30 29 28 27 26 25 24 23 123456 7 89 1 0 11 C505A P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 V AREF V AGND P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 P0.0 / AD0 P1.0 / AN0 / INT3 / CC0 P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2 RESET P3.0 / RxD P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P4.0 / TXDC C505CA This pin functionality is available in the C505CA only.

1.2 Pin Definitions and Functions

This section describes all external signals of the C505A with its function. Table 1-1 : Pin Definitions and Functions Symbol Pin Number I/O Function I/O Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs of the A/D converter. Port 1 pins that have 1’s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / INT3 / CC0 Analog input channel 0 interrupt 3 input / capture/compare channel 0 I/O P1.1 / AN1 / INT4 / CC1 Analog input channel 1/ interrupt 4 input / capture/compare channel 1 I/O P1.2 / AN2 / INT5 / CC2 Analog input channel 2 / interrupt 5 input / capture/compare channel 2 I/O P1.3 / AN3 / INT6 / CC3 Analog input channel 3 interrupt 6 input / capture/compare channel 4 I/O P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2 external reload / trigger input P1.6 / AN6 / CLKOUT Analog input channel 6 / system clock output P1.7 / AN7 / T2 Analog input channel 7 / counter 2 input *) I = Input O= Output

A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to V SS permits power-on reset using only an external capacitor to VCC . P3.0-P3.7 5, 7-13 I/O Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR ). The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory *) I = Input O= Output Table 1-1 : Pin Definitions and Functions (cont’d) Symbol Pin Number I/O Function

P4.0 P4.1 I/O I/O Port 4 is a 2-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to the secondary function RXDC must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows (C505CA only) : P4.0 / TXDC Transmitter output of CAN controller P4.1 / RXDC Receiver input of CAN controller XTAL2 14 O XTAL2 Output of the inverting oscillator amplifier. XTAL1 15 I XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of the etxernal clock signal of 50 % should be maintained. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed. *) I = Input O= Output Table 1-1 : Pin Definitions and Functions (cont’d) Symbol Pin Number I/O Function

P2.0-P2.7 18-25 I/O Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors. PSEN

26 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. ALE 27 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal OTP (EA =1) the ALE generation can be disabled by bit EALE in SFR SYSCON. ALE should not be driven during reset operation. *) I = Input O= Output Table 1-1 : Pin Definitions and Functions (cont’d) Symbol Pin Number I/O Function

EA 29 I External Access Enable When held at high level, instructions are fetched from the internal OTP memory when the PC is less than 8000H. When held at low level, the C505A/C505CA fetches all instructions from external program memory. EA should not be driven during reset operation. For the C505A-L and the C505CA-L this pin must be tied low. P0.0-P0.7 37-30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1’s. V AREF 38 – Reference voltage for the A/D converter. VAGND 39 – Reference ground for the A/D converter. VSS 16 – Ground (0V) VCC 17 – Power Supply (+5V) *) I = Input O= Output Table 1-1 : Pin Definitions and Functions (cont’d) Symbol Pin Number I/O Function

2 Memory Organization

The C505A CPU manipulates operands in the following four address spaces: – up to 64 Kbytes of program memory (32K on-chip OTP memory for C505A-4E) – up to 64 Kbytes of external data memory – 256 bytes of internal data memory – 1 Kbytes of internal XRAM data memory – 256 bytes CAN controller registers / data memory (C505CA only) – a 128 byte special function register area Figure 2-1 illustrates the memory address spaces of the C505A. Figure 2-1 C505A Memory Map Internal XRAM Int. CAN Contr. (256 Byte) (1 K Byte) not used FFFF H 8000H 7FFF H 0000H "Code Space" int. (EA = 1) ext. (EA = 0) "internal Data Space" indirect direct addr. 7FH 00H Internal RAM Special Function Regs. 80H FFH 80H FFH addr. ext. Internal RAM "Data Space" 0000H FC00 H FFFF H F7FF H F700H F6FF H Ext. Data Memory Alternatively Ext. Data Memory Internal “Data Space” F700H -F7FFH : Device CAN Area Unused Area Internal XRAM C505A - F700 H -FBFFH FC00 H -FFFFH C505CA F700 H -F7FFH F800H -FBFFH FC00 H −FFFF H see table below for detailed Data memory partitioning

2.1 Program Memory, "Code Space"

The C505A-4E has 32 Kbytes of on-chip OTP program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C505A-4E executes program code out of the OTP memory unless the program counter address exceeds 7FFFH . Address locations 8000H through FFFF H are then fetched from the external program memory. If the EA pin is held low, the C505A fetches all instructions from the external program memory.

2.2 Data Memory, "Data Space"

The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH , contain 128 directly addressable bit locations. The stack can be located anywhere in the internal RAM area, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal CAN controller (in C505CA only) and the internal

1 Kbyte XRAM are located in the external memory address area at addresses F700H to F7FFH and

FC00 H to FFFFH respectively. The CAN controller registers and internal XRAM can therefore be accessed using MOVX instructions with addresses pointing to the respective address areas.

2.3 General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks of eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage.

2.4 Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. One special function register of the C505A (PCON1) is located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“). In the C505CA, the registers and data locations of the CAN controller (CAN-SFRs) are located in the external data memory area at addresses F700H to F7FFH . This is compatible to the C505C and details about the access of these registers is described in the C505C User’s Manual. Special Function Register SYSCON (Address B1H ) Reset Value : XX100X01 B (C505CA only) Reset Value : XX100001B As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. bitaddressable. The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505A are listed in table 2-1 and table 2-2. In table 2-1 they are organized in groups which refer to the functional blocks of the C505A. The CAN-SFRs (applicable to the C505CA only) are also included in table 2-1. Table 2-2 illustrates the contents of the SFRs in numeric order of their addresses. Table 2-3 list the CAN-SFRs in numeric order of their addresses. Bit Function CSWO CAN Controller switch-off bit CPWD = 0 : CAN Controller is enabled (default after reset). CPWD = 1 : CAN Controller is switched off. This function is an enhancement over the C505C-2R. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP CMODB1H SYSCON Bit No. MSB LSB CSWO XMAP1–– XMAP0 The functions of the shaded bits are not described here. 1) This bit is available in the C505CA only.

Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP SYSCON VR0 4) VR1 4) VR2 4) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 E0H F0H 83H 82H 92H D0 H 81H B1H FC H FD H FE H 00H 00H 00H 00H XXXXX000 B 00H 07H XX100X01 B 3) 6) XX100101 B 3) 7) C5 H 05H A/D- Converter ADCON0 2) ADCON1 ADDATH ADDATL P1ANA 2) 4) A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter High Byte Data Register A/D Converter Low Byte Data Register Port 1 Analog Input Selection Register D8 H DC H D9 H DA H 90H 00X00000B 01XXX000 B 00H 00XXXXXX B FFH Interrupt System IEN0 IEN1 2) IP0 2) IP1 TCON 2) T2CON 2) SCON 2) IRCON Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register A8 H B8 H A9H B9H 88H C8 H 98H C0 H 00H 00H 00H XX000000 B 00H 00X00000B 00H 00H XRAM XPAGE SYSCON 2) Page Address Register for Extended on-chip XRAM and CAN Controller System Control Register 91H B1H 00H XX100X01 B 3) 6) XX100101 B 3 7) Ports P0 P1ANA 2) 4) Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 4 80H 90H 90H A0 H B0 H E8H 1) FFH FFH FFH FFH FFH XXXXXX11 B 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The content of this SFR varies with the actual step of the C505A (eg. 11 H for the first step) 6) C505A only 7) C505CA only

ADCON0 2) PCON 2) SBUF SCON SRELL SRELH A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte D8 H 87H 99H 98H AA H BA H 00X00000B 00H XX H 00H D9 H XXXXXX11 B Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Compare/ Capture Unit / Timer 2 CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON IEN0 IEN1 2) Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 C1 H C3 H C5 H C7 H C2 H C4 H C6 H CB H CA H CD H CC H C8 H A8 H B8 H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 00H 00H Watchdog WDTREL IEN0 2) IEN1 2) IP0 2) Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 86H A8 H B8 H A9H 00H 00H 00H 00H Power Save Modes PCON PCON1 4) Power Control Register Power Control Register 1 87H 88H 00H 0XX0XXXX B 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Table 2-1 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

(C505CA only) CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers : Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7 F700H F701H F702H F704H F705H F706H F707H F708H F709H F70A H F70B H F70C H F70D H F70E H F70FH F7n0H F7n1H F7n2H F7n3H F7n4H F7n5H F7n6H F7n7H F7n8H F7n9H F7nA H F7nB H F7nC H F7nD H F7nE H 01H XX H XX H UU H 0UUUUUUU B UU H UUU11111 B UU H UU H UU H UUUUU000 B UU H UU H UU H UUUUU000 B UU H UU H UU H UU H UU H UUUUU000 B UUUUUU00 B XX H XX H XX H XX H XX H XX H XX H XX H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The notation “n“ (n= 1 to F) in the message object address definition defines the number of the related message object. Table 2-1 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 86H WDTREL 00 H WDT PSEL 87H PCON 00 H SMOD PDS IDLS SD GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 3) PCON1 0XX0- XXXX B 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 2) P1 FFH T2 CLK- OUT T2EX .4 .3 INT5 INT4 .0 90H 3) P1ANA FFH EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 92H DPSEL XXXX- X000B 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI A0H A8H 2) IEN0 00H EA WDT ET2 ES ET1 EX1 ET0 EX0 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B1H SYSCON XX10- 0X01B – – EALE RMAP CMOD – XMAP1 XMAP0 B1H SYSCON XX10- 0001B – – EALE RMAP CMOD CSWO XMAP1 XMAP0 B8H 2) IEN1 3) 0000- 00X0B EXEN2 SWDT EX6 EX5 EX4 EX3 – EADC B8H 2) IEN1 4) 00H EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC B9H IP1 XX00- 0000B BA H SRELH XXXX- XX11 B C0 H IRCON 00H EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC C1 H CCEN 00 H COCA COCA COCA COCA COCA COCA COCA COCA C8 H T2CON 00X0- 0000B T2PS I3FR – T2R1 T2R0 T2CM T2I1 T2I0 D0 H PSW 00H CY AC F0 RS1 RS0 OV F1 P 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) C505A only 4) C505CA only Table 2-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

BD CLK – BSY ADM MX2 MX1 MX0 DA H ADDATL 00XX- XXXX B DC H ADCON1 01XX- X000B ADCL1 ADCL0 – – – MX2 MX1 MX0 E0H E8H 2) P4 3) XXXX- XX11 B E8H 2) P4 4) XXXX- XX11 B F0H FC H 5) 6) FD H 5) 6) FE H 5) 6) 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) C505A only 4) C505CA only 5) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 6) These are read-only registers 7) The content of this SFR varies with the actual of the step C505A (eg. 11 H for the first step) Table 2-2 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Contents of the CAN Registers in numeric order of their addresses (C505CA only) Addr. n=1-FH Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F700H CR 01 H TEST CCE 0 0 EIE SIE IE INIT F701H SR XX H BOFF EWRN – RXOK TXOK LEC2 LEC1 LEC0 F702H IR XX H INTID F704H BTR0 UU H SJW BRP F705H BTR1 0UUU. UUUU B

0 TSEG2 TSEG1

F707H GMS1 UUU1. 1111B I D 2 0 - 1 8 11111 F708H UGML0 UU H ID28-21 F709H UGML1 UU H ID20-13 F70A H LGML0 UU H ID12-5 F70B H LGML1 UUUU. U000 B I D 4 - 0 000 F70C H UMLM0 UU H ID28-21 F70D H UMLM1 UU H ID20-18 ID17-13 F70E H LMLM0 UU H ID12-5 F70FH LMLM1 UUUU. U000 B I D 4 - 0 000 F7n0H MCR0 UU H MSGVAL TXIE RXIE INTPND F7n1H MCR1 UU H RMTPND TXRQ MSGLST CPUUPD NEWDAT F7n2H UAR0 UU H ID28-21 F7n3H UAR1 UU H ID20-18 ID17-13 F7n4H LAR0 UU H ID12-5 F7n5H LAR1 UUUU. U000 B I D 4 - 0 000 F7n6H MCFG UUUU. UU00 B DLC DIR XTD 0 0 1) The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object. 2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation

1) The notation “n“ (n= 1 to F) in the address definition defines the number of the related message object. 2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation Table 2-3 Contents of the CAN Registers in numeric order of their addresses (cont’d) (C505CA only) Addr. n=1-FH Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

3 A/D Converter

The C505A includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mec hanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: – 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs – 10-bit resolution – Single or continuous conversion mode – Internal start-of-conversion trigger capability – Interrupt request generation after each conversion – Using successive approximation conversion technique via a capacitor array – Built-in hidden calibration of offset and linearity errors The externally applied reference voltage range has to be held on a fixed value within the specifications. The main functional blocks of the A/D converter are shown in figure 3-1.

3.1 A/D Converter Operation

An internal start of a single A/D conversion is triggered by a write-to-ADDATL instruction. The start procedure itself is independent of the value which is written to ADDATL. When single conversion m ode is selected (bit ADM=0) only one A/D conversion is performed. In continuous m ode (bit ADM=1) , after completion of an A/D conversion a new A/D conversion is triggered automatically until bit ADM is reset. The busy flag BSY (ADCON0.4) is automatically set when an A/D conversion is in progress. After com pletion of the conversion it is reset by hardware. This flag can be read only, a write has no effect. The interrupt request flag IADC (IRCON.0) is set when an A/D conversion is completed. The bits MX0 to MX2 in special function register ADCON0 and ADCON1 are used for selection of the analog input channel. The bits MX0 to MX2 are represented in both registers ADCON0 and ADCON1; however, these bits are present only once. Therefore, there are two methods of selecting an analog input channel : If a new channel is selected in ADCON1 the change is automatically done in the corresponding bits MX0 to MX2 in ADCON0 and vice versa. Port 1 is a dual purpose input/output port. These pins can be used either for digital I/O functions or as the analog inputs. If less than 8 analog inputs are required, the unused analog inputs at port 1 are free for digital I/O functions.

Block Diagram of the A/D Converter Shaded bit locations are not used in ADC -functions. Internal Bus M U X AD M MX2 MX 1 MX0 AD C ON0 (D8H ) BS Y– Port 1 ADDATH (D9H ) Single / Continuous Mode A / D Converter Start of conversion Write to ADDATL Internal Bus S& H f OSC VAR EF VAG ND BD CLK EA N 7 EAN 2 EAN 1 EAN 0EAN 6 EAN 5 EAN 4 EAN3 P1ANA (90H ) IEX4 IEX3 SWI IADC IRCON (C0 H ) IEX5IEX6EXF2 TF2 EX EN2 EX4 EX 3 EC AN EA D C IEN1 (B8H ) EX 5EX 6SWDT Clock ÷32, 16, 8, 4 Prescaler Conversion Clock fAD C MSB – MX2 MX 1 MX0 AD C ON1 (DC H ) ––AD C L1 AD C L0 Input Clock fIN ADDATL (DAH ) LSB

3.2 A/D Converter Registers

This section describes the bits/functions of all registers which are used by the A/D converter. Special Function Register ADDATH (Address D9H ) Reset Value : 00H Special Function Register ADDATL (Address DAH ) Reset Value : 00XXXXXXB The registers ADDATH and ADDATL hold the 10-bit conversion result in left justified data format. The most significant bit of the 10-bit conversion result is bit 7 of ADDATH. The least significant bit of the 10-bit conversion result is bit 6 of ADDATL. To get a 10-bit conversion result, both ADDAT registers must be read. If an 8-bit conversion result is required, only the reading of ADDATH is necessary. The data remains in ADDAT until it is overwritten by the next converted data. ADDAT can be read or written under software control. lf the A/D converter of the C505A is not used, register ADDATH can be used as an additional general purpose register. 76543210 D9 H ADDATH LSBDA H ADDATL Bit No. MSB LSB M SB .1 .0

Special Function Register ADCON0 (Address D8H ) Reset Value : 00H Special Function Register ADCON1 (Address DCH ) Reset Value : 01XXX000B The shaded bits are not used for A/D converter control. Bit Function – Reserved bits for future use BSY Busy flag This flag indicates whether a conversion is in progress (BSY = 1). The flag is cleared by hardware when the conversion is finished. ADM A/D conversion mode Whe n set, a continuous A/D conversion is selected. If cleared during a running A/D conversion, the conversion is stopped at its end. MX2 - MX0 A/D converter input channel select bits Bits MX2-0 can be written or read either in ADCON0 or ADCON1. The channel selection done by writing to ADCON 1(0) overwrites the selection in ADCON 0(1) when ADCON 1(0) is written after ADCON 0(1). The analog inputs are selected according the following table : 76543210 – BSY AD M M X2 M X1 M X0D8 H ADCON0 ADCL1 MX2 MX1 MX 0DC H AD CO N 1 Bit No. MSB LSB ADCL0 CL KBD –– – MX2 MX1 MX0 Selected Analog Input 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2

Note :Generally, before entering the power-down mod e, an A/D conversion in progress must be stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit or waiting for the A/D conversion interrupt. In continuous conversion mode, bit ADM must be cleared and the last A/D conversion m ust be terminated before entering the power-down mo de. A single A/D conversion is started by writing to SFR ADDATL with dummy data. A continuous conversion is started under the following conditions : – By setting bit ADM during a running single A/D conversion – By setting bit ADM when at least one A/D conversion has occurred after the last reset operation. – By writing ADDATL with dumm y data after bit ADM has been set before (if no A/D conversion has occurred after the last reset operation). When bit ADM is reset by software in continuous conversion mode, the just running A/D conversion is stopped after its end. ADCL1 ADCL0 A/D converter clock prescaler selection ADCL1 and ADCL0 select the prescaler ratio for the A/D conversion clock f ADC . Depending on the clock rate fOSC of the C505A, fADC must be adjusted in a way that the resulting conversion clock fADC is less than or equal to 2 MHz (see section 3.3). The prescaler ratio is selected according to the following table : Bit Function ADCL 1 ADCL0 Prescaler Ratio 0 0 0 1 1 0 1 1 divide by 4 divide by 8 (default after reset) divide by 16 divide by 32

The A/D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON. Special Function Register IEN1 (Address B8H ) Reset Value : 00H Special Function Register IRCON (Address C0H ) Reset Value : 00H The shaded bits are not used for A/D converter control. Bit Function EADC Enable A/D converter interrupt If EADC = 0, the A/D converter interrupt is disabled. SWI This bit can be set by software to generate an interrupt. The interrupt service routine is at 004BH . This bit is cleared when the interrupt is processed. This interrupt is enabled by setting bit IEN1.1(ECAN). C7 H C6 H C5 H C4 H C3 H C2 H C1 H C0 H IEX6 IEX5 IEX4 IEX3 SWI IADCC0 H IRC O NTF2EXF2 EXEN 2 SWDT EX6 EX 5B8H IEN1 Bit No. BF H M SB LSB EX4 EX3 EC AN EA D C BE H BD H BC H BB H BA H B9H B8H

3.3 A/D Converter Clock Selection

The ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC ) and the input clock fIN (=1/tIN). fADC is derived from the C505A system clock fOSC which is applied at the XTAL pins via the ADC clock prescaler as shown in figure 3-2. The input clock fIN is equal to fOSC The conversion fADC clock is limited to a maximum frequency of 2 MHz. Therefore, the AD C clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. The table in figure 3-2 shows the prescaler ratio which must be selected by ADCL1 and ADCL0 for typical system clock rates. Up to 8 MHz system clock the prescaler ratio 4 is selected. Using a system clock greater than 8 MHz and less than 16 MHz, the prescaler ratio of at least 8 must be selected. A prescaler ratio of at least 16 must be selected when using a system clock greater than 16 MHz. A prescaler ratio of 32 can used for any of the above frequency ranges. Figure 3-2 A/D Converter Clock Selection The duration of an A/D conversion is a multiple of the period of the f IN clock signal. The calculation of the A/D conversion time is shown in the next section. MCU System Clock Rate (f OSC ) fIN [MHz] Prescaler Ratio f A D C [MHz] ADCL1 ADCL0 2 MHz 2 ÷ 4 0.5 0 0 6 MHz 6 ÷ 4 1.5 0 0

8 MHz 8 ÷ 4 200

12 MHz 12 ÷ 8 1.5 0 1

16 MHz 16 ÷ 8 201

20 MHz 20 ÷ 16 1.25 1 0 f OSC Clock Prescaler ÷ 16 C onversion Clock ÷ 8 ÷ 4 MUX A / D Converter ADCL1 ADCL0 fADC max = 2 MHzCondition : fADC ÷ 32 fIN Input Clock fIN = 1 CLPfOSC =

3.4 A/D Conversion Timing

An A/D conversion is started by writing into the SFR ADDATL with dummy data. A write to SFR ADDAT L will start a new conversion even if a conversion is currently in progress. The conversion begins with the next machine cycle, and the BSY flag in SFR ADCON0 will be set. The A/D conversion procedure is divided into three parts : – Sam ple phase (tS), used for sampling the analog input voltage. – Conversion phase (tCO ), used for the real A/D conversion (includes calibration). – Write result phase (tWR ), used for writing the conversion result into the ADDAT registers. The total A/D conversion time is defined by tADCC which is the sum of the two phase times tS and tCO . The duration of the three phases of an A/D conversion is specified by their corresponding timing parameter as shown in figure 3-3. Figure 3-3 A/D Conversion Timing Sample Time tS : During this time the internal capacitor array is connected to the selected analog input channel and is loaded with the analog voltage to be converted. The analog voltage is internally fed to a voltage comparator. With beginning of the sample phase the BSY bit in SFR ADCON0 is set. Sample Phase C onversion Phase Start of an AD conversion BSY Bit tS tCO tWR R esult is written into ADDAT tADCC A/D Conversion Time Cycle Time Write Result Phase Prescaler Ratio (=PS) t S tCO t A DCC 32 64 x tIN 320 x tIN 384 x tIN 16 32 x tIN 160 x tIN 192 x tIN 8 16 x tIN 8 0 x tIN 9 6 x tIN 4 8 x tIN 4 0 x tIN 4 8 x tIN tADCC = tS + tCO t WR = t IN PS = Prescaler value

The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the beginning of the write result cycle. If continuous conversion is selected, BSY is again set with the beginning of the machine cycle which follows the write result cycle. The interrupt flag IADC is set at the end of the A/D conversion. If the A/D converter interrupt is enabled and the A/D converter interrupt is prioritized to be serviced immediately, the first instruction of the interrupt service routine will be executed in the third machine cycle which follows the write result cycle. IADC must be reset by software. De pending on the application, typically there are three methods to handle the A/D conversion in the C5 05A. – Software delay The machine cycles of the A/D conversion are counted and the program executes a software delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. This is the fastest method to get the result of an A/D conversion. – Polling BSY bit The BSY bit is polled and the program waits until BSY=0 . Attention : a polling JB instruction which is two machine cycles long, possibly may not recognize the BSY=0 condition during the write result cycle in the continuous conversion mode. – A/D conversion interrupt After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the A/D conversion is read in the interrupt service routine. If other C5 05A interrupts are enabled, the interrupt latency must be regarded. Therefore, this software method is the slowest method to get the result of an A/D conversion. De pending on the oscillator frequency of the C505A and the selected divider ratio of the conversion clock prescaler the total time of an A/D conversion is calculated according figure 3-3 and table 3- 1. Figure 3-5 on the next page shows the minimum A/D conversion time in relation to the oscillator frequency fOSC . The minimum conversion time is 6 µs and can be achieved at fOSC of 8 or 16 MHz (or whenever fAD C = 2 MHz). Note : The prescaler ratios in table 3-1 are minimum values. Table 4-1 A/D Conversion Time for Dedicated System Clock Rates fOSC [MHz] Prescaler Ratio PS fA D C [MHz] Samp le Time tS [µs] Total Conversion Time t A D CC [µs] 2 MHz ÷ 4 0.5 4 24 6 MHz ÷ 4 1.5 1.33 8

8 MHz ÷ 4 2 1 6

12 MHz ÷ 8 1.5 1.33 8

16 MHz ÷ 8 2 1 6

20 MHz ÷ 16 1.25 1.6 9.6

Minimum A/D Convers ion Time in Relation to System Clock [µs] t ADCC min = 6 µs ÷ 4 ÷ 16 tADCC 4 12 16 18 fO SC [MHz]8 14 1062 20 ÷ 8

3.5 A/D Converter Calibration

The C505A A/D converter includes hidden internal calibration mechanisms which assure a safe functionality of the A/D converter according to the DC characteristics. The A/D converter calibration is implemented in a way that a user program which executes A/D conversions is not affected by its operation. Further, the user program has no control over the calibration m echanism. The calibration itself executes two basic functions : – Offset calibration : correction of offset errors of comparator and the capacitor network – Linearity calibration : correction of the binary weighted capacitor network The A/D converter calibration operates in two phases : calibration after a reset operation and calibration at each A/D conversion. The calibration phases are controlled by a state machine in the A/D converter. This state machine executes the calibration phases and stores the calibration results dynamically in a small calibration RAM. After a reset operation the A/D calibration is automatically started. This reset calibration phase which takes 3328 fADC clocks, alternating offset and linearity calibration is executed. Therefore, at

8 MH z oscillator frequency and with the default after reset prescaler value of 4, a reset calibration

time of approx. 1.66 ms is reached. For achieving a proper reset calibration, the fADC prescaler value must satisfy the condition fADC max ≤ 2 MHz. If this condition is not met at a specific oscillator frequency with the default prescaler value after reset, the fADC prescaler must be adjusted immediately after reset by setting bits ADCL1 and ADCL0 in SFR ADCON1 to a suitable value. It is also recomm ended to have the proper voltages, as specified in the DC specifications, applied at the VAREF and VAR EF pins before the reset calibration has started. After the reset calibration phase the A/D converter is calibrated according to its DC characteristics. Nevertheless, during the reset calibration phase single or continuous A/D can be executed. In this case it must be regarded that the reset calibration is interrupted and continued after the end of the A/D conversion. Therefore, interrupting the reset calibration phase by A/D conversions extends the total reset calibration time. If the specified total unadjusted error (TUE) has to be valid for an A/D conversion, it is recommend ed to start the first A/D conversions after reset when the reset calibration phase is finished. Depending on the oscillator frequency used, the reset calibration phase can be possibly shortened by setting ADCL1 and ADC L0 (prescaler value) to its final value immediately after reset. After the reset calibration, a second calibration mechanism is initiated. This calibration is coupled to each A/D conversion. With this second calibration mech anism alternatively offset and linearity calibration values, stored in the calibration RAM, are always checked when an A/D conversion is executed and corrected if required.

3.5.1 A/D Converter Analog Input Selection

The analog inputs are located at port 1. The corresponding pins have a port structure, which allows to use them either as digital I/O pins or as analog inputs (see section 6.1.3.2). The analog input function of these digital/analog port lines are selected via the register P1ANA. This register lies in the mapped SFR area and can be accessed when bit RMAP in SFR SYSCON is set when writing to its address (90H ). If a specific bit location of P1ANA is set, the corresponding port line is configured as a digital input. With a 0 in the bit location the port line operates as analog port. Special Function Registers P1ANA (Address 90H ) Reset Value : FFH Bit Function EAN7 - EAN0 Enable analog port 1 inputs If EAN x (x = 7-0) is cleared, port pin P1.x is enabled for operation as an analog input. If EANx is set, port pin P1.x is enabled for digital I/O function (default after reset). 76543210 90H P1ANA Bit No. MSB LSB EAN7 EA N 6 EA N 5 EA N 4 EAN3 EAN2 EAN1 EAN0

4 OTP Memory Operation

The C505A-4E is the OTP version in the C505A microcontroller with a 32K byte one-time programmable (OTP) program memory. With the C505A-4E fast programming cycles are achieved (1 byte in 100 µsec). Also several levels of OTP mem ory protection can be selected. The basic functionality of the C505A-4 E as microcontroller is identical to the C505A-L (romless part) functionality.

4.1 Programming Conf iguration

During normal program execution the C505A-4E behaves like the C505A-L. For programming the device, the C505A-4E must be put into the programming mod e. This, typically, is done not in-system but in a special programming hardware. In the programming mode the C505A-4E operates as a slave device similar as an EPROM st andalone memory device and must be controlled with address/ data information, control lines, and an external 11.5 V programming voltage. In the programmi ng m ode port 0 provides the bidirectional data lines and port 2 is used for the multiplexed address inputs. The upper address information at port 2 is latched with the signal PALE. For basic programming mode selection the inputs RESET, PSEN , EA/VPP , ALE and PMSEL1/0 and P SEL are used. Further, the inputs PMSEL1,0 are required to select the access types (e.g. and a clock signal at the XTAL pins must be applied to the C505A-4E. The 11.5 V external programming voltage is input through the EA /VPP pin. Figure 4-1 shows the pins of the C505A-4E which are required for controlling of the OTP programming mode. Figure 4-1 Programming Mode Configuration Port 0 P0.0-7 V CC V SS C505A-4E C505CA-4E PROG P2.0-7 Port 2 EA / V PP PMSEL0 PSEL RE SET PSEN PMSEL1 PRD PALE XTAL1 XTAL2

4.2 Pin Configuration

Figure 4-2 shows the detailed pin configuration of the C505A-4E in programming mode. Figure 4-2 OTP Programmin g Mode Pin Configuration (Top View) D4 EA / V PP N.C. A5 / A13 PR O G A6 / A14 PS EN A4 / A12 A3 / A11 A2 / A10 A1 / A9 A0 / A8 V CC XTAL1 XTAL2 N.C. N.C. V SS 32 31 30 29 28 27 26 25 24 23 12345 6 7 8 9 10 11 C505A-4E N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. RE SET PM SE L0 PM SE L1 PS EL PR D PA LE N.C. N.C. C505CA-4E

4.3 Pin Definitions

The following figure 4-1 contains the functional description of all C505A-4E pins which are required for OTP memory programming Table 4-1 Pin Definitions and Functions of the C505A-4E in Programming Mode Symbol Pin Numbe r I/O *) Function P-MQFP-44 RESET 4 I Reset This input must be at static “1“ (active) level during the whole programming mode. PM SEL0 PM SEL1 I I Programmin g mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1, 0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PSEL

8 I Basic programming mode select

This input is used for the basic programming mode selection and must be switched according figure 4-3. PR D 9 I Programmin g mode read strobe This input is used for read access control for OTP memory read, version byte read, and lock bit read operations. PALE 10 I Programmin g address latch enable PA LE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1,0 is changed. XTAL2 14 O XTAL2 Ou tput of the inverting oscillator amplifier. XTAL1 15 I XTAL1 Input to the oscillator amplifier. *) I = Input O = Output PMSEL1 PMSEL0 Access Mode 0 0 R eserved 0 1 Re ad signature bytes 1 0 Program/read lock bits 1 1 Program/read OTP memory byte

VSS 16 – Circuit ground potential must be applied in programming mode. VCC 17 – Power supply terminal must be applied in programming mode. P2.0-7 18-25 I Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. PSEN

26 I Program store enable

This input must be at static “0“ level during the whole programming mode. PR OG 27 I Programmin g mode write strobe This input is used in programming mode as a write strobe for OTP m emory program, and lock bit write operations During basic programmi ng mode selection a low level must be applied to PROG . EA /VPP 29 – Programming voltage This pin must be at 11.5 V (V PP ) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at VIHx high level. This pin is also used for basic programming mode selection. At basic programmi ng mode selection a low level must be applied to EA/VPP . P0.7-0 30-37 I/O Data lines 0-7 During programming mode, data bytes are transferred via the bidirectional D7-0 lines which are located at port 0. 28, 38-44 – Not Connected These pins should not be connected in programming mode. *) I = Input O = Output Table 4-1 Pin Definitions and Functions of the C505A-4E in Programming Mod e (cont’d) Symbol Pin Numbe r I/O *) Function P-MQFP-44

4.4 Programming Mode Selection

The selection for the OTP programming mode can be separated into two different parts : – Basic programming mode selection – Access mode selection With the basic programming mode selection the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic. Further, after selection of the basic programming mode, OTP memory accesses are executed by using one of the access modes. These access modes are OTP memory byte program/read, version byte read, and program/read lock byte operations.

4.4.1 Basic Programming Mod e Selection

The basic programming mode selection scheme is shown in figure 4-3. Figure 4-3 Basic Programming Mode Selection R ESET PSEN PROG EA /VPP “1“ “0“ PSEL “0“ VCC C lock (XTAL1/XTAL2) stable PRD PALE “1“ “0“ R eady for access mode selectionDuring this period signals are not actively driven 0V VIH 2 VPP PMSEL1,0 0,1

The basic programming mode is selected by executing the following steps : – With a stable Vcc a clock signal is applied to the XTAL pins; the RESE T pin is set to “1“ level and the PSEN pin is set to “0“ level. – PR O G , PALE, PMSEL1 and EA/VPP are set to “0“ level; PRD, PSEL, and PMSEL0 are set to “1“ level. – PSEL is switched from “1“ to “0“ level and thereafter PROG is switched to “1“ level. – PMSEL1, 0 can now be changed; after EA /VPP has been set to VIHx high level or to VPP the OTP memory is ready for access. The pins RESET and PSEN must stay at “1“ respectively “0“ static signal level during the whole programming mode. With a falling edge of PSEL the logic state of PROG and EA/VPP is internally latched. These two signals are now used as programming write pulse signal (PROG) and as programming voltage input pin VPP . After the falling edge of PSEL, PSEL must stay at “0“ state during all programming operations. Note:If protection level 1 to 3 has been programmed (see section 4.6) and the programming mode has been left, it is no more possible to enter the programming mode !

4.4.2 OTP Memory Access Mode Selection

When the C505A-4E has been put into the programming mod e using the basic programming mode selection, several access m odes of the OTP mem ory programming interface are available. The conditions for the different control signals of these access modes are listed in table 4-2. The access modes from the table above are basically selected by setting the two PMSEL1,0 lines to the required logic level. The PROG and PRD signal are the write and read strobe signal. Data is transferred via port 0 and addresses are applied to port 2. The following sections describes the details of the different access modes. Table 4-2 Ac cess Modes Selection Ac cess Mode EA VPP PR OG PRD PMSEL Address (Port 2) Data (Port 0)10 Program OTP memory byte VPP H H H A0-7 A8-14 D0-7 Read OTP memory byte VIH x H Program OTP lock bits VPP HHL – D 1,D 0 see table 4-3Re ad OTP lock bits VIH x H R ead O TP version byte VIH x H L H Byte addr. of version byte D0-7

4.5 Program / Read OTP Memory Bytes

The program/read OTP memory byte access mode is defined by PMSEL1,0 = 1,1. It is initiated wh en the PMSEL 1,0 = 1,1 is valid at the rising edge of PALE. With the falling edge of PALE the upper addresses A8-A14 of the 15-bit OTP memory address are latched. After A8-A14 has been latched, A0-A7 is put on the address bus (port 2). A0-A7 must be stable when PROG is low or PRD is low. If subsequent OTP address locations are accessed with constant address information at the high address lines A8-14, A8-A14 must only be latched once (page address mechanism). Figure 4-4 shows a typical basic OTP memory programming cycle with a following OTP memory read operation. In this example A0-A14 of the read operation are identical to A8-A14 of the preceeding programmi ng operation. Figure 4-4 Programming / Verify OTP Memory Access Waveform If the address lines A8-A14 m ust be updated, PALE must be activated for the latching of the new A8- A14 value. Control, address, and data information must only be switched when the PROG and PRD signals are at high level. The PAL E high pulse must always be executed if a different access mode has been used prior to the actual access mode. PR OG PALE Port 0 A8- PMSEL1,0 1, 1 D0-D7 Port 2 A0-A7A14 PRD D0-D7 min. 100 µs min. 100 ns

4.6 Lock Bits Programming / Read

The C505A-4E has tw o programmable lock bits which, wh en programmed according table 4-3, provide four levels of protection for the on-chip OTP code memory. Note : A 1 means that the lock bit is unprogrammed . 0 means that lock bit is programmed. For a OTP verify operation at protection level 1, the C505A-4E must be put into the OTP verification mode. If a device is programmed with protection level 2 or 3, it is no longer possible to verify the OTP content of a customer rejected (FAR) OTP device. When a protection level has been activated by programming of the lock bits, the basic programmi ng mode must be left for activation of the protection mechanisms. This means, after the activation of a protection level further OTP program/verify operations are still possible if the basic programmi ng mode is maintained. The state of the lock bits can always be read if protection level 0 is selected. If protection level 1 to 3 has been programmed and the programming mod e has been left, it is not possible to re-enter the programming mode. In this case, the lock bits cannot be read anymore. Figure 4-6 shows the waveform of a lock bit write/read access. For a simple drawing, the PROG pulse is shortened. In reality, for lock bit programming, a 100µs PROG low pulse must be applied. Table 4-3 Lock Bit Protection Types Lock Bits at D1,D0 Protection Level Protection Type D1 D 0 1 1 Level 0 The OTP lock feature is disabled. During normal operation of the C505A-4E, the state of the EA pin is not latched on reset. 1 0 Level 1 During normal operation of the C505A-4E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible according to OTP verification mode. Further programmi ng of the OTP memory is disabled (reprogramming security). 0 1 Level 2 Sam e as level 1, but also OTP memory read operation using OTP verification mode is disabled. 0 0 Level 3 Sam e as level 2; but additionally external code execution by setting EA=low during normal operation of the C505A-4E is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the OTP memory boundary), is still possible.

Write/Read Lock Bit W aveform PROG PMSEL1,0 1, 0 PR D Port 0 (D 1,D 0) 1,0 1,0 PALE The exam ple shows the programming and reading of a protection level 1.

4.6.1 Access of Version Bytes

The C505A-4E and C505CA-4E provide three version bytes at address locations FC H , FDH , and FE H . The information stored in the version bytes, is defined by the mask of each microcontroller step, Therefore, the version bytes can be read but not written. The three Version Re gisters hold information as manufacturer code, device type, and stepping code. For reading of the version bytes the control lines must be used according table 4-2 and figure 4-7. The address of the version byte must be applied at the port 1 address lines. PALE must not be activated. Figure 4-7 Read Version Register(s) Waveform Version bytes are typically used by programming systems for adapting the programming firmware to specific device characteristics such as OTP size etc. Note:The 3 version bytes are implemented in a way that they can be also be read during normal program execution mode as a mapped register with bit RMAP in SFR SYSCON set. The addresses of the version bytes in normal mode and programm ing mode are identical and therefore they are located in the SFR address range. The steppings of the C505A versions will contain the following version byte information : Note: Future steppings of C505A would have a different version byte 2 content. Stepping Version Byte 0 = VR0 (mapped addr. FCH ) Version Byte 1 = VR1 (mapped addr. FDH ) Version Byte 2 = VR2 (mapped addr. FEH ) ES-AA Steps of C 505A-4E and C505CA-4E C5 H 05H 11H PR OG PM SEL1 ,0 0, 1 Port 2 PRD FC FD FE VR 0 VR 1Port 0 VR 2 PALE

4.7 OTP Verification Mode

The OT P verification mode as shown in figure 4-8 is used to verify the contents of the OTP wh en the protection level 1 has been set. The detailed timing characteristics of the OTP verification mode are shown in the AC specifications (chapter 5). Figure 4-8 OTP Verification Mode OTP verification mode is selected if the inputs PSEN , EA, and ALE are put to the specified logic levels. With RESET going inactive, the OT P verification mode sequence is started. The C505A-4E outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data bytes at port 0 are assigned to the OTP addresses in the following way : 1. Data Byte = content of OTP address 0000H 2. Data Byte = content of OTP address 0001H 3. Data Byte = content of OTP address 0002H 16. Data Byte= content of OTP address 000FH The C505A-4E does not output any address information during the OTP verification mode. The first data byte to be verified is always the byte which is assigned to the OTP address 0000H and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse the OTP address pointer is internally incremented and the expected data byte for the next OTP address must be delivered externally. Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the OTP content of the actual address. If a verify error is detected, the error condition Inputs : ALE = VSS PSEN = VIH, EA = VIH 2 RESET = R ESET ALE Port 0 P3.5 Da ta for Data for Low : Verify Error High : Verify ok Addr. X·16 D ata for Ad. X·16 +1Addr. 0 Data for Addr. 1 D ata for Ad. X·16 -1 1. ALE pulse after reset Latch Latch Latch Latch

6 CLP

3 CLP

5 Device Specifications

5.1 Absolute Maximum Ratings

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS ) the Voltage on VCC pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings.

5.2 DC Characteristics

VCC = 5V +10%, -15%; VSS =0V TA =0 t o 7 0°C for the SAB- versions TA = -40 to 85°C for the SAF- versions TA = -40 to 110°C for the SAH- versions TA = -40 to 125°C for the SAK- versions Notes see next page Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltages all except EA, RESET EA pin RESET pin VIL VIL1 VIL2 –0 . 5 –0 . 5 –0 . 5 0.2 VCC - 0.1 0.2 VCC - 0.3 0.2 VCC + 0.1 V V V Input high voltages all except XTAL1, RESET XTAL1 pin RESET pin VIH VIH1 VIH2 0.2VCC +0 . 9 0.7VCC 0.6VCC VCC + 0.5 VCC + 0.5 VCC + 0.5 V V V Output low voltages Ports 1, 2, 3, 4 Port 0, ALE, PSEN VOL VOL1 0.45 0.45 V V IOL = 1.6 mA 1) IOL = 3.2 mA 1) Output high voltages Ports 1, 2, 3, 4 Port 0 in external bus mode, ALE, PSEN VOH VOH2 2.4 0.9 VCC 2.4 0.9 VCC V V V V IOH =–8 0 µA IOH =–1 0 µA IOH = – 800µA IOH =–8 0 µA 2) Logic 0 input current Ports 1, 2, 3, 4 IIL –1 0 –7 0 µA VIN =0 . 4 5V Logical 0-to-1 transition current Ports 1, 2, 3, 4 ITL – 65 – 650 µA VIN =2V Input leakage current Port 0, AN0-7 (Port 1), EA ILI – ± 1 µA0 . 4 5 <VIN < VCC Pin capacitance C IO –1 0 p F fc =1M H z , TA =2 5°C Overload current IOV – ± 5m A 3) 4) Programming voltage VPP 10.9 12.1 V 11.5 V ± 5% 5) Supply current at EA/VCC 30 mA 5)

Notes : 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address lines are stabilizing. 3) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 4) Not 100% tested, guaranteed by design characterization. 5) Only valid in porgramming mode. 6) ICC (active mode) is measured with: XTAL1 driven with tR /tF = 5 ns, 50% duty cycle , VIL= VSS +0 . 5V , VIH = VCC – 0.5 V; XTAL2 = N.C.; EA = Port0 = RESET =VCC ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approx. 1 mA) 7) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR /tF = 5 ns, 50% duty cycle, VIL= VSS +0 . 5V , VIH = VCC – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 =VCC ; all other pins are disconnected; 8) ICC (active mode with slow-down mode) is measured : TBD 9) ICC (idle mode with slow-down mode) is measured : TBD 10)IPD (power-down mode) is measured under following conditions: EA =P o r t 0=VCC ; RESET =VSS ; XTAL2 = N.C.; XTAL1 =VCC ; VAGND = VSS ; VAREF = VCC ; all other pins are disconnected. 11) The typical ICC values are periodically measured at TA = +25 °C but not 100% tested. 12) The maximum ICC values are measured under worst case conditions (TA = 0 °C or -40 °C and VCC =5 . 5V ) Parameter Symbol Limit Values Unit Test Condition typ. 11) max.12) C505A Active Mode 12 MHz

20 MHz

12 MHz

Power down current IPD TBD 60 µA VCC = 2..5.5 V 10)

C505A : Power Supply Current Calculation Formulas Note : fosc is the oscillator frequency in MHz. ICC values are given in mA. Parameter Symbol Formula Active mode ICC typ ICC max TBD TBD Idle mode ICC typ ICC max TBD TBD Active mode with slow-down enabled ICC typ ICC max TBD TBD Idle mode with slow-down enabled ICC typ ICC max TBD TBD ICC [mA] ICC max ICC typ fOSC [MHz]12842 0 16 TBD C505A

5.3 A/D Converter Characteristics

VCC =5V + 10%, – 15%; VSS =0 V TA =0 t o 7 0°C for the SAB-C505A versions TA = – 40 to 85°C for the SAF-C505A versions TA = – 40 to 110°C for the SAH-C505A versions TA = – 40 to 125°C for the SAK-C505A versions 4 V ≤ VAREF ≤ VCC + 0.1 V ; VSS – 0.1 V ≤ VAGND ≤ V ss + 0.2 V Notes see next page. Clock calculation table : Further timing conditions : tADC min = 500 ns tIN = 1 / fOSC = tCLP Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage VAIN VAGND VAREF V 1) Sample time tS – 64 x tIN 32 x tIN 16 x tIN 8 x tIN ns Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 4 2) Conversion cycle time tADCC – 384 x tIN 192 x tIN 96 x tIN 48 x tIN ns Prescaler ÷ 32 Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 4 3) Total unadjusted error TUE – ± 2L S B V SS +0.5V ≤ VAIN ≤ VCC -0.5V 4) – ± 4L S B V SS < VAIN < VCC +0.5V VCC - 0.5 V < VAIN < VCC 4) Internal resistance of reference voltage source RAREF – tADC / 250 - 0.25 kΩ tADC in [ns] 5) 6) Internal resistance of analog source RASRC – tS / 500 - 0.25 kΩ tS in [ns] 2) 6) ADC input capacitance C AIN –5 0p F 6) Clock Prescaler Ratio ADCL1, 0 t ADC t S t ADCC ÷ 32 1 1 32 x t IN 64 x t IN 384 x t IN ÷ 16 1 0 16 x t IN 32 x t IN 192 x t IN ÷ 8 0 1 8 x t IN 16 x t IN 96 x tIN ÷ 4 0 0 4 x t IN 8 x tIN 48 x tIN

Notes: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH , respectively. 2) During the sample time the input capacitance C AIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization.

5.4 AC Characteristics (12 MHz, 0.5 Duty Cycle) VCC = 5V +10%, -15%; VSS =0V TA =0 t o 7 0°C for the SAB-C505A versions TA = -40 to 85°C for the SAF-C505A versions TA = -40 to 110°C for the SAH-C505A versions TA = -40 to 125°C for the SAK-C505A versions (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C505A to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit

12 MHz clock

0.5 Duty Cycle

1/CLP = 2 MHz to 12 MHz min. max. min. max. ALE pulse width tLHLL 43 – CLP - 40 – ns Address setup to ALE tAVLL 17 – CLP/2 - 25 – ns Address hold after ALE tLLAX 17 – CLP/2 - 25 – ns ALE to valid instruction in tLLIV – 80 – 2 CLP - 87 ns ALE to PSEN tLLPL 22 – CLP/2 - 20 – ns PSEN pulse width tPLPH 95 – 3/2 CLP - 30 –n s PSEN to valid instruction intPLIV – 60 – 3/2 CLP - 65 ns Input instruction hold after PSENtPXIX 0–0 – n s Input instruction float after PSENtPXIZ *) – 32 – CLP/2 - 10 ns Address valid after PSEN tPXAV *) 37 – CLP/2 - 5 – ns Address to valid instruction intAVIV – 148 – 5/2 CLP - 60 ns Address float to PSEN tAZPL 0–0 – n s

AC Characteristics (12 MHz, 0.5 Duty Cycle, cont’d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 1/CLP = 2 MHz to 12 MHz min. max. min. max. RD pulse width tRLRH 180 – 3 CLP - 70 – ns WR pulse width tWLWH 180 – 3 CLP - 70 – ns Address hold after ALE tLLAX2 56 – CLP - 27 – ns RD to valid data in tRLDV – 118 – 5/2 CLP- 90 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ –6 3 – C L P - 2 0 n s ALE to valid data in tLLDV – 200 – 4 CLP - 133 ns Address to valid data in tAVDV – 220 – 9/2 CLP - 155 ns ALE to WR or RD tLLWL 75 175 3/2 CLP - 50 3/2 CLP + 50 ns Address valid to WR tAVWL 70 – 2 CLP - 97 – ns WR or RD high to ALE high tWHLH 17 67 CLP/2 - 25 CLP/2 + 25 ns Data valid to WR transition tQVWX 5–C L P / 2 - 3 7 – n s Data setup before WR tQVWH 170 – 7/2 CLP - 122 – ns Data hold after WR tWHQX 15 – CLP/2 - 27 – ns Address float after RD tRLAZ – 0 –0n s External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq. = 2 MHz to 12 MHz min. max. Oscillator period CLP 83.3 500 ns High time TCL H 20 CLP-TCL L ns Low time TCL L 20 CLP-TCL H ns Rise time tR –1 2 n s Fall time tF –1 2 n s Oscillator duty cycle DC 0.5 0.5 –

5.5 AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) VCC = 5V +10%, -15%; VSS =0V TA =0 t o 7 0°C for the SAB-C505A versions TA = -40 to 85°C for the SAF-C505A versions (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C505A to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit 16-MHz clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP= 2 MHz to 16 MHz min. max. min. max. ALE pulse width tLHLL 48 – CLP - 15 – ns Address setup to ALE tAVLL 10 – TCL Hmin -15 – ns Address hold after ALE tLLAX 10 – TCL Hmin -15 – ns ALE to valid instruction in tLLIV – 75 – 2 CLP - 50 ns ALE to PSEN tLLPL 10 – TCL Lmin -15 – ns PSEN pulse width tPLPH 73 – CLP+ TCL Hmin -15 –n s PSEN to valid instruction in tPLIV –3 8 – C L P + TCL Hmin- 50 ns Input instruction hold after PSENtPXIX 0–0 – n s Input instruction float after PSENtPXIZ *) –1 5 – T C L Lmin -10 ns Address valid after PSEN tPXAV *) 20 – TCL Lmin - 5 – ns Address to valid instruction intAVIV – 95 – 2 CLP + TCL Hmin -55 ns Address float to PSEN tAZPL -5 – -5 – ns

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 16-MHz clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP= 2 MHz to 16 MHz min. max. min. max. RD pulse width tRLRH 158 – 3 CLP - 30 – ns WR pulse width tWLWH 158 – 3 CLP - 30 – ns Address hold after ALE tLLAX2 48 – CLP - 15 – ns RD to valid data in tRLDV – 100 – 2 CLP+ TCL Hmin - 50 ns Data hold after RD tRHDX 0–0 – n s Data float after RD tRHDZ – 51 – CLP - 12 ns ALE to valid data in tLLDV – 200 – 4 CLP - 50 ns Address to valid data in tAVDV – 200 – 4 CLP + TCL Hmin -75 ns ALE to WR or RD tLLWL 73 103 CLP + TCL Lmin - 15 CLP+ TCL Lmin+ 15 ns Address valid to WR tAVWL 95 – 2 CLP - 30 – ns WR or RD high to ALE high tWHLH 10 40 TCL Hmin - 15 TCL Hmin + 15 ns Data valid to WR transition tQVWX 5–T C L Lmin - 20 – ns Data setup before WR tQVWH 163 – 3 CLP + TCL Lmin - 50 –n s Data hold after WR tWHQX 5–T C L Hmin - 20 – ns Address float after RD tRLAZ –0– 0 n s

AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont’d) Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. External Clock Drive Characteristics Parameter Symbol CPU Clock = 16 MHz Duty Cycle 0.4 to 0.6 Variable CPU Clock 1/CLP = 2 to 16 MHz Unit min. max. min. max. Oscillator period CLP 62.5 62.5 62.5 500 ns High time TCL H 25 – 25 CLP - TCL L ns Low time TCL L 25 – 25 CLP - TCL H ns Rise time tR – 10 – 10 ns Fall time tF – 10 – 10 ns Oscillator duty cycle DC 0.4 0.6 25 / CLP 1 - 25 / CLP – Clock cycle TCL 25 37.5 CLP * DC min CLP * DCmax ns

5.6 AC Characteristics (20 MHz, 0.5 Duty Cycle) VCC = 5V +10%, -15%; VSS =0V TA =0 t o 7 0°C for the SAB-C505A versions TA = -40 to 85°C for the SAF-C505A versions (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C505A to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit

20 MHz clock

1/CLP = 2 MHz to 20 MHz min. max. min. max. ALE pulse width tLHLL 35 – CLP - 15 – ns Address setup to ALE tAVLL 10 – CLP/2 - 15 – ns Address hold after ALE tLLAX 10 – CLP/2 - 15 – ns ALE to valid instruction in tLLIV – 55 – 2 CLP - 45 ns ALE to PSEN tLLPL 10 – CLP/2 - 15 – ns PSEN pulse width tPLPH 60 – 3/2 CLP - 15 –n s PSEN to valid instruction intPLIV – 25 – 3/2 CLP - 50 ns Input instruction hold after PSENtPXIX 0–0 – n s Input instruction float after PSENtPXIZ *) – 20 – CLP/2 - 5 ns Address valid after PSEN tPXAV *) 20 – CLP/2 - 5 – ns Address to valid instruction intAVIV – 65 – 5/2 CLP - 60 ns Address float to PSEN tAZPL - 5 – - 5 – ns

AC Characteristics (20 MHz, 0.5 Duty Cycle, cont’d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 1/CLP = 2 MHz to 20 MHz min. max. min. max. RD pulse width tRLRH 120 – 3 CLP - 30 – ns WR pulse width tWLWH 120 – 3 CLP - 30 – ns Address hold after ALE tLLAX2 35 – CLP - 15 – ns RD to valid data in tRLDV – 75 – 5/2 CLP- 50 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ –3 8 – C L P - 1 2 n s ALE to valid data in tLLDV – 150 – 4 CLP - 50 ns Address to valid data in tAVDV – 150 – 9/2 CLP - 75 ns ALE to WR or RD tLLWL 60 90 3/2 CLP - 15 3/2 CLP + 15 ns Address valid to WR tAVWL 70 – 2 CLP - 30 – ns WR or RD high to ALE high tWHLH 10 40 CLP/2 - 15 CLP/2 + 15 ns Data valid to WR transition tQVWX 5–C L P / 2 - 2 0 – n s Data setup before WR tQVWH 125 – 7/2 CLP - 50 – ns Data hold after WR tWHQX 5–C L P / 2 - 2 0 – n s Address float after RD tRLAZ – 0 –0n s External Clock Drive Characteristics Parameter Symbol Limit Values Unit Variable Clock Freq. = 2 MHz to 20 MHz min. max. Oscillator period CLP 50 500 ns High time TCL H 15 CLP-TCL L ns Low time TCL L 15 CLP-TCL H ns Rise time tR –1 0 n s Fall time tF –1 0 n s Oscillator duty cycle DC 0.5 0.5 –

External Clock Drive on XTAL1 TCL H TCL L CLP tR tF 0.2V CC

0.7 CCV

• 0.1 MCT03310

5.7 OTP Memory Characteristics

5.7.1 Programming Mode Timing Characteristics

VCC = 5 V ± 10 %; VPP = 11.5 V ± 5% ; TA = 25 °C ± 10 °C Parameter Symbol Limit Values Unit min. max. PALE pulse width tPAW 35 – ns PMSEL setup to PALE rising edge tPMS 10 – Address setup to PALE, PROG, or PRD falling edge tPAS 10 – ns Address hold after PALE, PROG, or PRD falling edge tPAH 10 – ns Address, data setup to PROG or PRD tPCS 100 – ns Address, data hold after PROG or PRD tPCH 0–n s PMSEL setup to PROG or PRD tPMS 10 – ns PMSEL hold after PROG or PRD tPMH 10 – ns PROG pulse width tPWW 100 – µs PRD pulse width tPRW 100 – ns Address to valid data out tPAD –7 5 n s PRD to valid data out tPRD –2 0 n s Data hold after PRD tPDH 0–n s Data float after PRD tPDF –2 0 n s PROG high between two consecutive PROG low pulses tPWH1 1– µs PRD high between two consecutive PRD low pulses tPWH2 100 ns XTAL clock period tCLKP 83.3 500 ns

Programming Code Byte - Write Cycle Timing tPAW tPAS PALE Port 2 A0-7 Port 0 PMSEL1,0 D0-7 PROG tPAH tPCS A8-14 tPCH tPWH tPWW Notes : PRD must be high during a programming write cycle tPMS H, H

Verify Code Byte - Read Cycle Timing tPAS Port 0 D0-7 PRD tPAH tPCS tPRW Notes : PROG must be high during a programming read cycle tPCH tPDH tPRD tPDF PALE PMSEL1,0 tPMS tPAW Port 2 A0-7A8-14 H, H tPAD tPWH

Version Registers - Read Timing PRD Note : PALE should be low during a lock bit read/write cycle PMSEL1,0 H, L Port 0 D0, D1 D0, D1 H, L PROG tPCS tPMS tPWW tPMH tPCH tPMS tPRD tPRW tPMH tPDH tPDF D0-7 L, H e.g. FDH Note : PROG must be high during a programming read cycle tPMS tPRD tPRW tPCS tPMH tPDH tPDF tPCH PRD PMSEL1,0 Port 2 Port 0

5.7.2 OTP Verification Mode Characteristics

Note: This mode cannot be entered into if OTP protection levels of 1 to 3 are programmed. Parameter Symbol Limit Values Unit min. typ max. ALE pulse width tAWD –C L P –n s ALE period tACY –6 C L P –n s Data valid after ALE tDVA ––2 C L P n s Data stable after ALE tDSA 4 CLP – – ns P3.5 setup to ALE low tAS –T C L H –n s Oscillator frequency 1/ CLP 4–6M H z

AC Testing: Input, Output Waveforms AC Testing : Float Waveforms Recommended Oscillator Circuits for Crystal Oscillator AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’. For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH /VOL level occurs. XTAL2 XTAL1 External Oscillator Signal Crystal Mode : C = 20 pF ± 10 pF (incl. stray capacitance) Crystal Oscillator Mode Driving from External Source XTAL1 XTAL2N.C. C MHz 2 - 20 C

5.8 Package Information

Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Plastic Package, P-MQFP-44-2 (SMD) (Plastic Metric Quad Flat Pack) GPM 05622 Dimensions in mm

6 Index

Note: Bold page numbers refer to the main definition part of SFRs or SFR bits. A AC Testing B C D E

F G I L M N

O OTP Protection P Pin Definitions and functions (Normal Mode) 1-5–1-9 Pin Definitions and functions (OTP Mode) 4-3–4-4 R S CAN registers - address ordered 2-10–2-11 T Timings

U V W X