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User's Manual 08.97 C505 C505 C 8-Bit CMOS Microcontroller http://www .siemens.de/ Semiconductor/
This edition was realized using the software system FrameMaker â Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73,
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Siemens AG 1997, All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en- dangered. C505 User’s Manual Revision History : 1997-08-01 Previous Releases : Original Version Page (previous version) Page (new version) Subjects (changes since last revision)
Semiconductor Group I-1 1997-08-01 Table of Contents Page General Information C505 / C505C
4.2 PSEN
Semiconductor Group I-2 1997-08-01 Table of Contents Page General Information C505 / C505C
Semiconductor Group I-3 1997-08-01 Table of Contents Page General Information C505 / C505C
Semiconductor Group I-4 1997-08-01 Table of Contents Page General Information C505 / C505C
Semiconductor Group 1-1 1997-08-01 Introduction C505 / C505C
1 Introduction
The C505 microcontroller is a member of the Siemens C500 family of 8-bit microcontrollers. The C505 is fully compatible to the standard 8051 microcontroller. Additionally the C505 provides extended power save provisions, on-chip RAM, 16K of on-chip program memory, and RFI related improvements. The C505 does not have an internal clock prescaler and with a maximum external clock rate of 20 MHz it achieves a 300 ns instruction cycle time. The C505-2R operates with internal and/or external program memory. The C505-L is identical to the C505-2R, except that it lacks the on-chip porgram memory. The C505C-2R and C505C-L, are identical to the C505-2R and the C505-L respectively, except that they have, in addition, the full CAN interface. Therefore, the term C505 refers to all the above four versions within this documentation unless otherwise noted. Figure 1-1 shows the different functional units of the C505 and Figure 1-2 shows the simplified logic symbol of the C505. Figure 1-1 C505 Functional Units I / O
8 Analog Inputs /
8 Digit. I / O I / O I / O I / O (2-Bit I / O Port) Support Module Watchdog Timer Timer 2 8-Bit ADC T 0 T 1 Oscillator Watchdog Controller Full-CAN CPU
8 Datapointers
Semiconductor Group 1-2 1997-08-01 Listed below is a summary of the main features of the C505 family: Fully compatible to standard 8051 microcontroller Superset of the 8051 architecture with 8 datapointers Up to 20 MHz operating frequency – 375 ns instruction cycle time @ 16 MHz – 300 ns instruction cycle time @ 20 MHz (50 % duty cycle) 16K byte on-chip ROM (C505-2R and C505C-2R only) – Optional ROM protection available 256 byte on-chip RAM 256 byte on-chip XRAM Five ports: 32 + 2 digital I/O lines(Port 1 with mixed analog/digital I/O capability) Three 16-bit timers/counters – Timer 0 / 1 (C501 compatible) – Timer 2 with 4 channels for 16-bit capture/compare operation Full CAN Module (C505C only) – 256 register/data bytes located in external data memory area – 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz – internal CAN clock prescaler when input frequency is over 10 MHz Full duplex serial interface with programmable baudrate generator (USART) 8-bit A/D Converter Twelve interrupt sources with four priority levels On-chip emulation support logic (Enhanced Hooks) Programmable 15-bit Watchdog Timer Oscillator Watchdog Fast Power On Reset Power Saving Modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake up capability through INT0 or P4.1 pin P-MQFP-44 package Pin configuration is compatible to C501, C504, C511/C513-family Temperature ranges: SAB-C505 T A = 0 to 70 C SAF-C505 T A = – 40 to 85 C SAH-C505 T A = – 40 to 110 C (max. operating frequency: TBD) SAK-C505 T A = – 40 to 125 C (max. operating frequency: 8 MHz)
Semiconductor Group 1-3 1997-08-01 Introduction C505 / C505C Figure 1-2 Logic Symbol AGND AREF V V EA PSEN RESET ALE XTAL2 XTAL1 2-Bit Digital I / O 8-Bit Digital I / O 8-Bit Digital I / O Port 4Port 3Port Port 8-Bit Digital I / O / 8-Bit Digital I / O 1Port 0Port V SSV CC C505 MCL03284 RXDC TXDC C505C only 8-Bit Analog Inputs
Semiconductor Group 1-4 1997-08-01
1.1 Pin Configuration
This section shows the pin configuration of the C505 in the P-MQFP-44 package. Figure 1-3 Pin Configuration (top view) EA P4.1 / RXDC P0.6 / AD6 P0.7 / AD7 P0.5 / AD5 P2.6 / A14 P2.5 / A13 PSEN P2.7 / A15 ALE P2.4 / A12 P2.3 / A11 XTAL2 XTAL1 P4.0 / TXDC P1.7 / AN7 / T2 P3.2 / INT0 P3.3 / INT1 RESET P1.6 / AN6 / CLKOUT P1.5 / AN5 / T2EX 1116 MCP03285 P2.2 / A10 P2.1 / A9 V V CC SS P2.0 / A8 33 31 30 29 28 27 26 25 24 2332 P0.4 / AD4 P3.0 / RxD P3.4 / T0 P3.5 / T1 P3.1 / TxD P1.4 / AN4 V V AREF AGND 2345 78 1 0 9 P1.1 / AN1 / INT4 / CC1 P1.0 / AN0 / INT3 / CCO P1.3 / AN3 / INT6 / CC3 P1.2 / AN2 / INT5 / CC2 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 P3.7 / RD P3.6 / WR C505
Semiconductor Group 1-5 1997-08-01 Introduction C505 / C505C
1.2 Pin Definitions and Functions
This section describes all external signals of the C505 with its function. Table 1-1 Pin Definitions and Functions Symbol Pin Number I/O*) Function I/O Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs of the A/D converter. Port 1 pins that have 1’s written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( I IL , in the DC characteristics) because of the internal pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / INT3 / CC0 Analog input channel 0 Interrupt 3 input / capture/compare channel 0 I/O P1.1 / AN1 / INT4 / CC1 Analog input channel 1/ Interrupt 4 input / capture/compare channel 1 I/O P1.2 / AN2 / INT5 / CC2 Analog input channel 2 / Interrupt 5 input / capture/compare channel 2 I/O P1.3 / AN3 / INT6 / CC3 Analog input channel 3 Interrupt 6 input / capture/compare channel 4 I/O P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2 external reload / trigger input P1.6 / AN6 / CLKOUT Analog input channel 6 / System clock output P1.7 / AN7 / T2 Analog input channel 7 / Counter 2 input Port 1 is used for the low-order address byte during program verification of the C505-2R. *) I = Input O= Output
Semiconductor Group 1-6 1997-08-01 RESET 4 I RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to V SS permits power-on reset using only an external capacitor to V CC P3.0-P3.7 5, 7-13 I/O Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current ( I IL , in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR ). The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory *) I = Input O= Output Table 1-1 Pin Definitions and Functions Symbol Pin Number I/O*) Function
Semiconductor Group 1-7 1997-08-01 Introduction C505 / C505C P4.0 P4.1 I/O I/O Port 4 is a 2-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current ( I IL , in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to the secondary function RXDC must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows (C505C only): P4.0 / TXDC Transmitter output of CAN controller P4.1 / RXDC Receiver input of CAN controller XTAL2 14 O XTAL2 Output of the inverting oscillator amplifier. XTAL1 15 I XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50 % should be maintained. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed. *) I = Input O= Output Table 1-1 Pin Definitions and Functions Symbol Pin Number I/O*) Function
Semiconductor Group 1-8 1997-08-01 P2.0-P2.7 18-25 I/O Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors. PSEN
26 O The Program Store Enable
output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. ALE 27 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periodes except during an external data memory access. When instructions are executed from internal ROM (EA =1) the ALE generation can be disabled by bit EALE in SFR SYSCON. This pin should not be driven during reset operation. *) I = Input O= Output Table 1-1 Pin Definitions and Functions Symbol Pin Number I/O*) Function
Semiconductor Group 1-9 1997-08-01 Introduction C505 / C505C EA 29 I External Access Enable When held at high level, instructions are fetched from the internal ROM when the PC is less than 4000 H . When held at low level, the C505 fetches all instructions from external program memory. This pin should not be driven during reset operation. For the C505-L and the C505C-L this pin must be tied low. P0.0-P0.7 37-30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1’s. Port 0 also outputs the code bytes during program verification in the C505C-2R. External pullup resistors are required during program verification. V AREF 38 – Reference voltage for the A/D converter. VAGND 39 – Reference ground for the A/D converter. VSS 16 – Ground (0V) VCC 17 – Power Supply (+ 5 V) *) I = Input O= Output Table 1-1 Pin Definitions and Functions Symbol Pin Number I/O*) Function
Semiconductor Group 2-1 1997-08-01
2 Fundamental Structure
The C505 is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining all architectural and operational characteristics of the C501, the C505 incorporates a CPU with 8 datapointers, an 8-bit A/D converter, a 4-channel capture/compare unit, a Full-CAN controller unit (C505C only), an XRAM data memory as well as some enhancements in the Fail Save Mechanism Unit. Figure 2-1 shows a block diagram of the C505.
Semiconductor Group 2-2 1997-08-01 Fundamental Structure C505 / C505C Figure 2-1 Block Diagram of the C505 Watchdog Oscillator Port 4 Port 3 Port 2 Port 1 8-Bit Digit. I / O Port 0 XRAM RAM ROM Programmable Watchdog Timer USART Generator Interrupt Unit 8-Bit A / D Converter Emulation Support Logic Port 0 Port 1 Port 2 Port 3 Port 4 OSC & Timing S & H XTAL1 XTAL2 RESET ALE PSEN EA V AREF AGNDV 8-Bit Digit. I / O 8-Bit Digit. I / O 8-Bit Digit. I / O 2-Bit Digit. I / O MCB03286
256 Byte
Reg. / Data MUX CCV SSV C505 C505C only
Semiconductor Group 2-3 1997-08-01
2.1 CPU
The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three- byte instructions. With a 16 MHz external clock, 58% of the instructions execute in 375 ns (20 MHz : 300 ns). The CPU (Central Processing Unit) of the C505 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, substract, multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations as set, clear, complement, jump- if-set, jump-if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence. Additionally to the CPU functionality of the C501/8051 standard microcontroller, the C505 contains 8 datapointers. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. Accumulator ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU.
Semiconductor Group 2-4 1997-08-01 Fundamental Structure C505 / C505C Special Function Register PSW (Address D0H ) Reset Value : 00 H B Register The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register. Stack Pointer The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin a location = 08H above register bank zero. The SP can be read or written under software control. Bit Function CY Carry Flag Used by arithmetic instructions. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instructions. F1 General Purpose Flag P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 PD0 H PSW D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH
Semiconductor Group 2-5 1997-08-01
2.2 CPU Timing
The C505 has no clock prescaler. Therefore, a machine cycle of the C505 consists of 6 states (6 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL1 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. If it is a two-byte instruction, the second reading takes place during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most C505 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figure 2-2 (c) and (d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.
Semiconductor Group 2-6 1997-08-01 Fundamental Structure C505 / C505C Figure 2-2 Fetch Execute Sequence P1 P2 P1 P2 P1 P2 P1 P2 S3 S4 P1 P2 P1 P2 S5 S6 P1 P2 P1 P2 S1 S2 P1 P2 P1 P2 S3 S4 P1 P2 P1 P2 S5 S6 OSC (XTAL2) ALE Read Opcode Read Next Opcode (Discard) S1 S2 S3 S4 S5 S6 (a) 1-Byte, 1-Cycle Instruction, e. g. INC A Opcode Again Read Next (b) 2-Byte, 1-Cycle Instruction, e. g. ADD A #DATA Read Opcode S1 S2 Byte Read 2nd S4S3 S5 S6 Opcode Read Next S6S5S3 S4S2S1 Opcode Read Read Next Opcode (Discard) S1 S2 S4S3 S5 S6 Read Next Opcode Again (c) 1-Byte, 2-Cycle Instruction, e. g. INC DPTR (d) MOVX (1-Byte, 2-Cycle) S4S1 S2 S3 S5 S6 S1 S3S2 S4 S5 S6 Read Opcode (MOVX) (Discard) Opcode Read Next No Fetch No ALE No Fetch Read Next Opcode Again ADDR DATA Access of External Memory MCD03287
Semiconductor Group 3-1 1997-08-01
3 Memory Organization
The C505 CPU manipulates operands in the following four address spaces: – up to 64 Kbytes of program memory (16K on-chip program memory for C505-2R) – up to 64 Kbytes of external data memory – 256 bytes of internal data memory – 256 bytes of internal XRAM data memory – 256 bytes CAN controller registers / data memory (C505C only) – a 128 byte special function register area Figure 3-1 illustrates the memory address spaces of the C505. Figure 3-1 C505 Memory Map Ext. Int. (EA = 1) Ext. Data Memory Int. CAN Contr. (256 Byte) (EA = 0) Ext. FFFF H 4000 H 3FFF H 0000H Data Memory Ext. F7FF H F700 H F6FF H
0000 H 00 H
Regs. Function Special RAM Internal RAM Internal H80 HFFAddr. Indirect Addr. Direct Alternatively "Code Space" "Data Space" "internal Data Space" MCD03288 XRAM (256 KByte) Internal Not used FF00 H FFFF H C505C only 80 H FF H
Semiconductor Group 3-2 1997-08-01 Memory Organization C505 / C505C
3.1 Program Memory, "Code Space"
The C505-2R has 16 Kbytes of read-only program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C505-2R executes program code out of the internal ROM unless the program counter address exceeds 3FFFH . Address locations 4000H through FFFFH are then fetched from the external program memory. If the EA pin is held low, the C505 fetches all instructions from the external program memory.
3.2 Data Memory, "Data Space"
The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks : the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH , contain 128 directly addressable bit locations. The stack can be located anywhere in the internal RAM area, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions that use a 16-bit or an 8-bit address. The internal CAN controller (C505C only) and the internal XRAM are located in the external memory address area at addresses F700H to F7FFH and FF00H to FFFFH respectively. The CAN controller registers and internal XRAM can therefore be accessed using MOVX instructions with addresses pointing to the respective address areas.
3.3 General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks of eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in chapter 2). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction op code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage.
Semiconductor Group 3-3 1997-08-01
3.4 XRAM Operation
The XRAM in the C505 is a memory area that is logically located at the upper end of the external data memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM.
3.4.1 XRAM/CAN Controller Access Control
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to XRAM and the CAN controller. XMAP0 is a general access enable/disable control bit and XMAP1 controls the external signal generation during XRAM/CAN controller accesses. CAN controller accesses are applicable only in the case of the C505C versions. Special Function Register SYSCON (Address B1H ) Reset Value : XX100X01 B When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM and CAN Controller RD and WR become active and port 0 and 2 drive the actual address/data information which is read/written from/to XRAM or CAN controller. This feature allows to check the internal data transfers to XRAM and CAN controller. When port 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set. Otherwise the I/O function of the port 0 and port 2 lines is interrupted. Bit Function XMAP1 XRAM/CAN controller visible access control Control bit for RD /WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0 : The signals RD and WR are not activated during accesses to the XRAM/CAN Controller XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally. XMAP0 Global XRAM/CAN controller access enable/disable control XMAP0 = 0 : The access to XRAM and CAN controller is enabled. XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default after reset!). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP CMODB1H SYSCON Bit No. MSB LSB – XMAP1–– XMAP0 The functions of the shaded bits are not described here.
Semiconductor Group 3-4 1997-08-01 Memory Organization C505 / C505C After a reset operation, bit XMAP0 is set. This means that the accesses to XRAM and CAN controller are generally disabled. In this case, all accesses using MOVX instructions within the address range of F700H to FFFFH generate external data memory bus cycles. When XMAP0 is cleared, the access to XRAM and CAN controller is enabled and all accesses using MOVX instructions with an address in the range of F700H to F7FFH will access the CAN controller and FF00H to FFFFH will access the internal XRAM. Internal accesses (XMAP0=0) in the address range gap from F800H to FEFFH for the C505C (as shown in figure 3-1) will have undefined data. In the case of the pure C505 microcontroller (without CAN controller), internal accesses in the address range of F700H to FEFFH will have undefined data Bit XMAP0 is hardware protected. If it is cleared once (XRAM and CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. This hardware protection mechanism is done by an asymmetric latch at XMAP0 bit. An unintentional disabling of XRAM and CAN controller could be dangerous since indeterminate values could be read from the external bus. To avoid this the XMAP0 bit is forced to '1' only by a reset operation. Additionally, during reset an internal capacitor is charged. So the reset state is a disabled XRAM and CAN controller. Because of the charge time of the capacitor, XMAP0 bit once written to '0' (that is, discharging the capacitor) cannot be set to '1' again by software. On the other hand any distortion (software hang up, noise,...) is not able to charge this capacitor, too. That is, the stable status is XRAM and CAN controller enabled. The clear instruction for the XMAP0 bit should be integrated in the program initialization routine before XRAM or CAN controller is used. In extremely noisy systems the user may have redundant clear instructions. Note: The CAN controller peripheral exists in the C505C only.
Semiconductor Group 3-5 1997-08-01
3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)
The XRAM and CAN controller can be accessed by two read/write instructions, which use the 16-bit DPTR for indirect addressing. These instructions are : – MOVX A, @DPTR (Read) – MOVX @DPTR, A (Write) For accessing the XRAM, the effective address stored in DPTR must be in the range of FF00H to FFFF H . For accessing the CAN controller, the effective address stored in DPTR must be in the range of F700H to F7FFH .
3.4.3 Accesses to XRAM using the Registers R0/R1 (8-bit Addressing Mode)
The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8-bit address (indirect addressing with registers R0 or R1). The instructions are: MOVX A, @Ri (Read) MOVX @Ri, A (Write) Aspecial page register is implemented in the C505 to provide the possibility of accessing the XRAM or CAN controller also with the MOVX @Ri instructions, i.e. XPAGE serves the same function for the XRAM and CAN controller as Port 2 for external data memory. Special Function Register XPAGE (Address 91H ) Reset Value : 00 H Figures 3-2 to 3-4 show the dependencies of XPAGE- and Port 2 - addressing in order to explain the differences in accessing XRAM/CAN controller, ext. RAM or what is to do when Port 2 is used as an I/O-port. Bit Function XPAGE.7-0 XRAM/CAN controller high address XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX instructions are used to access internal XRAM or CAN controller. XPAGE 76543210 .5 .4 .391H Bit No. MSB LSB
Semiconductor Group 3-6 1997-08-01 Memory Organization C505 / C505C Figure 3-2 Write Page Address to Port 2 “MOV P2,pageaddress“ will write the page address to port 2 and the XPAGE-Register. When external RAM is to be accessed in the XRAM/CAN controller address range, the XRAM/CAN controller has to be disabled. When additional external RAM is to be addressed in an address range < F700H , the XRAM/CAN controller may remain enabled and there is no need to overwrite XPAGE by a second move. MCS02761 XRAM CAN-Controller Port 0 Port 2 Write to Page Address Address/Data XPAGE Port 2
Semiconductor Group 3-7 1997-08-01 Figure 3-3 Write Page Address to XPAGE “MOV XPAGE,pageaddress“ will write the page address only to the XPAGE register. Port 2 is available for addresses or I/O data. MCS02762 XRAM CAN-Controller Port 0 XPAGE Write to Port 2 I/O Data Address/Data Address/ XPAGE
Semiconductor Group 3-8 1997-08-01 Memory Organization C505 / C505C Figure 3-4 Use of Port 2 as I/O Port At a write to port 2, the XRAM/CAN controller address in XPAGE register will be overwritten because of the concurrent write to port 2 and XPAGE register. So, whenever XRAM is used and the XRAM address differs from the byte written to port 2 latch it is absolutely necessary to rewrite XPAGE with the page address. Example : I/O data at port 2 shall be AAH . A byte shall be fetched from XRAM at address FF30H . MOV R0, #30H ; MOV P2, #0AAH ; P2 shows AAH and XPAGE contains AAH MOV XPAGE, #0FFH ; P2 still shows AAH but XRAM is addressed MOVX A, @R0 ; the contents of XRAM at FF30H is moved to accumulator MCS02763 XRAM CAN-Controller Port 0 I/O Data to Port 2 Write I/O Data Address/Data XPAGE Port 2
Semiconductor Group 3-9 1997-08-01 The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM/CAN Controller address range, an external access is performed. For the C505 the content of XPAGE must be F7H FFH in order to use the XRAM/CAN Controller. The software has to distinguish two cases, if the MOVX @Ri instructions with paging shall be used : a) Access to XRAM/CAN Contr. :The upper address byte must be written to XPAGE or P2; both writes select the XRAM/CAN controller address range. b) Access to external memory : The upper address byte must be written to P2; XPAGE will be automatically loaded with the same address in order to deselect the XRAM.
3.4.4 Reset Operation of the XRAM
The contents of the XRAM are not affected by a reset. After power-up the contents are undefined, while they remain unchanged during and after a reset as long as the power supply is not turned off. If a reset occurs during a write operation to XRAM, the content of a XRAM memory location depends on the cycle in which the active reset signal is detected (MOVX is a 2-cycle instruction): Reset during 1st cycle : The new value will not be written to XRAM. The old value is not affected. Reset during 2nd cycle : The old value in XRAM is overwritten by the new value.
3.4.5 Behaviour of Port 0 and Port 2
The behaviour of port 0 and port 2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA . The table 3-1 lists the various operating conditions. It shows the following characteristics: a) Use of P0 and P2 pins during the MOVX access. Bus:The pins work as external address/data bus. If (internal) XRAM/CAN controller is accessed, the data written to the XRAM/CAN controller can be seen on the bus in debug mode. I/0:The pins work as Input/Output lines under control of their latch. b) Activation of the RD and WR pin during the access. c) Use of internal (XRAM/CAN controller) or external XDATA memory. The shaded areas describe the standard operation as each C5xx device without on-chip XRAM/ CAN controller behaves.
Semiconductor Group 3-10 1997-08-01 Memory Organization C505 / C505C Table 3-1 - Behaviour of P0/P2 and RD/WR During MOVX Accesses EA = 0 EA = 1 XMAP1, XMAP0 XMAP1, XMAP0 00 10 X1 00 10 X1 MOVX @DPTR DPTR XRAM/CAN address range a)P0/P2fi Bus b)RD/WR active c)ext.memory is used a)P0/P2fi Bus b)RD/WR active c)ext.memory is used a)P0/P2fi Bus b)RD/WR active c)ext.memory is used a)P0/P2fi Bus b)RD/WR active c)ext.memory is used a)P0/P2fi Bus b)RD/WR active c)ext.memory is used a)P0/P2fi Bus b)RD/WR active c)ext.memory is used DPTR XRAM/CAN address range a)P0/P2 fi Bus (RD/WR -Data) b)RD/WR inactive c)XRAM/CAN is used a)P0/P2 fi Bus (RD/WR -Data) b)RD/WR active c)XRAM/CAN is used a)P0/P2fi Bus b)RD/WR active c) ext.memory is used a)P0/P2fi I/O b)RD/WR inactive c)XRAM/CAN is used a)P0/P2 fi Bus (RD/WR -Data) b)RD/WR active c)XRAM/CAN is used a)P0/P2fi Bus b)RD/WR active c) ext.memory is used MOVX @ Ri XPAGE XRAM/CAN addr.page range a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used XPAGE XRAM/CAN addr.page range a)P0 fi Bus (RD/WR -Data) P2fi I/O b)RD/WR inactive c)XRAM/CAN is used a)P0 fi Bus (RD/WR -Data) P2fi I/O b)RD/WR active c)XRAM/CAN is used a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used a)P0/P2fi I/O b)RD/WR inactive c)XRAM/CAN is used a)P0 fi Bus (RD/WR -Data) P2fi I/O b)RD/WR active c)XRAM/CAN is used a)P0fi Bus P2fi I/O b)RD/WR active c)ext.memory is used modes compatible to 8051/C501 family
Semiconductor Group 3-11 1997-08-01
3.5 Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. One special function register of the C505 (PCON1) is located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“). The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data memory area at addresses F700H to F7FFH . Details about the access of these registers is described in section 3.4.1 of this chapter. Special Function Register SYSCON (Address B1H ) Reset Value : XX100X01 B As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. bitaddressable. The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505 are listed in table 3-2 and table 3-3. In table 3-2 they are organized in groups which refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C only) are also included in table 3-2. Table 3-3 illustrates the contents of the SFRs in numeric order of their addresses. Table 3-4 list the CAN-SFRs in numeric order of their addresses. . Bit Function RMAP Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP CMODB1H SYSCON Bit No. MSB LSB – XMAP1–– XMAP0 The functions of the shaded bits are not described here.
Semiconductor Group 3-12 1997-08-01 Memory Organization C505 / C505C Table 3-2 Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL DPSEL PSW SP SYSCON VR0 4) VR1 4) VR2 4) Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 E0H F0H 83H 82H 92H D0 H 81H B1H FC H FD H FE H 00H 00H 00H 00H XXXXX000 B 00H 07H XX100X01 B C5 H 05H A/D- Converter ADCON0 2) ADCON1 ADDAT ADST P1ANA A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register A/D Converter Start Register Port 1 Analog Input Selection Register D8 H DC H D9 H DA H 90H 00X00000B 01XXX000 B 00H XX H FFH Interrupt System IEN0 2) IEN1 2) IP0 2) IP1 TCON 2) T2CON 2) SCON 2) IRCON Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register A8 H B8 H A9H B9H 88H C8 H 98H C0 H 00H 00H 00H XX000000 B 00H 00X00000B 00H 00H XRAM XPAGE SYSCON 2) Page Address Register for Extended on-chip XRAM and CAN Controller System Control Register 91H B1H 00H XX100X01 B Ports P0 P1ANA Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 4 80H 90H 90H 1) 4) A0 H B0 H E8H 1) FFH FFH FFH FFH FFH XXXXXX11 B 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The content of this SFR varies with the actual step of the C505 (eg. 01 H for the first step)
Semiconductor Group 3-13 1997-08-01 Serial Channel ADCON0 2) PCON 2) SBUF SCON SRELL SRELH A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte D8 H 87H 99H 98H AA H BA H 00X00000B 00H XX H 00H D9 H XXXXXX11 B Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Compare/ Capture Unit / Timer 2 CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON IEN0 IEN1 2) Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 C1 H C3 H C5 H C7 H C2 H C4 H C6 H CB H CA H CD H CC H C8 H A8 H B8 H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 00H 00H Watchdog WDTREL IEN0 2) IEN1 2) IP0 2) Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 86H A8 H B8 H A9H 00H 00H 00H 00H Power Save Modes PCON PCON1 4) Power Control Register Power Control Register 1 87H 88H 00H 0XX0XXXX B 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset
Semiconductor Group 3-14 1997-08-01 Memory Organization C505 / C505C CAN Controller (C505C) CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers : Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7 F700H F701H F702H F704H F705H F706H F707H F708H F709H F70A H F70B H F70C H F70D H F70E H F70FH F7n0H F7n1H F7n2H F7n3H F7n4H F7n5H F7n6H F7n7H F7n8H F7n9H F7nA H F7nB H F7nC H F7nD H F7nE H 01H XX H XX H UU H 0UUUUUUU B UU H UUU11111 B UU H UU H UU H UUUUU000 B UU H UU H UU H UUUUU000 B UU H UU H UU H UU H UU H UUUUU000 B UUUUUU00 B XX H XX H XX H XX H XX H XX H XX H XX H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The notation “n” (n= 1 to F) in the message object address definition defines the number of the related message object. Table 3-2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset
Semiconductor Group 3-15 1997-08-01 Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 86H WDTREL 00 H WDT PSEL 87H PCON 00 H SMOD PDS IDLS SD GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 3) PCON1 0XX0- XXXX B 89H TMOD 00 H GATE C/T M1 M0 GATE C/T M1 M0 90H 2) P1 FFH T2 CLK- OUT T2EX .4 .3 INT5 INT4 .0 90H 3) P1ANA FFH EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 92H DPSEL XXXX- X000B 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI A0H A8H 2) IEN0 00H EA WDT ET2 ES ET1 EX1 ET0 EX0 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group 3-16 1997-08-01 Memory Organization C505 / C505C B0H 2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD B1H SYSCON XX10- 0X01B – – EALE RMAP CMOD – XMAP1 XMAP0 B8H 2) IEN1 00H EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC B9H IP1 XX00- 0000B BA H SRELH XXXX- XX11 B C0 H 2) IRCON 00H EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC C1 H CCEN 00 H COCA COCAL COCA COCAL COCA COCAL COCA COCAL C8 H 2) T2CON 00X0- 0000B T2PS I3FR – T2R1 T2R0 T2CM T2I1 T2I0 D0 H 2) PSW 00H CY AC F0 RS1 RS0 OV F1 P D8 H 2) ADCON0 00X0- 0000B BD CLK – BSY ADM MX2 MX1 MX0 DA H ADST XXXX- XXXX B 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Semiconductor Group 3-17 1997-08-01 DC H ADCON1 01XX- X000B ADCL1 ADCL0 – – – MX2 MX1 MX0 E0H E8H 2) P4 XXXX- XX11 B F0H FC H 3)4) VR0 C5 H 11000101 FD H 3)4) VR1 05 H 00000101 FE H 1) X means that the value is undefined and the location is reserved. 2) Bit-addressable special function registers. 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers. 5) The content of this SFR varies with the actual of the step C505 (eg. 01 H for the first step). Table 3-3 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Semiconductor Group 3-18 1997-08-01 Memory Organization C505 / C505C Table 3-4 Contents of the CAN Registers in numeric order of their addresses (C505C only) Addr. n=1-FH Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F700H CR 01 H TEST CCE 0 0 EIE SIE IE INIT F701H SR XX H BOFF EWRN – RXOK TXOK LEC2 LEC1 LEC0 F702H IR XX H INTID F704H BTR0 UU H SJW BRP F705H BTR1 0UUU. UUUU B
0 TSEG2 TSEG1
F707H GMS1 UUU1. 1111B ID20-18 11111 F708H UGML0 UU H ID28-21 F709H UGML1 UU H ID20-13 F70A H LGML0 UU H ID12-5 F70B H LGML1 UUUU. U000 B ID4-0 0 0 0 F70C H UMLM0 UU H ID28-21 F70D H UMLM1 UU H ID20-18 ID17-13 F70E H LMLM0 UU H ID12-5 F70FH LMLM1 UUUU. U000 B ID4-0 0 0 0 F7n0H MCR0 UU H MSGVAL TXIE RXIE INTPND F7n1H MCR1 UU H RMTPND TXRQ MSGLST CPUUPD NEWDAT F7n2H UAR0 UU H ID28-21 F7n3H UAR1 UU H ID20-18 ID17-13 F7n4H LAR0 UU H ID12-5 F7n5H LAR1 UUUU. U000 B ID4-0 0 0 0 F7n6H MCFG UUUU. UU00 B DLC DIR XTD 0 0 1) The notation “n” (n= 1 to F) in the address definition defines the number of the related message object. 2) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation.
Semiconductor Group 3-19 1997-08-01 1) The notation “n” (n= 1 to F) in the address definition defines the number of the related message object. 2) “X” means that the value is undefined and the location is reserved. “U” means that the value is unchanged by a reset operation. “U” values are undefined (as “X”) after a power-on reset operation. Table 3-4 Contents of the CAN Registers in numeric order of their addresses (cont’d) (C505C only) Addr. n=1-FH Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Semiconductor Group 4-1 1997-08-01 External Bus Interface C505 / C505C
4 External Bus Interface
The C505 allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture with one exception : if the C505 is used in systems with no external memory the generation of the ALE signal can be suppressed. Resetting bit EALE in SFR SYSCON register, the ALE signal will be gated off. This feature reduces RFI emissions of the system.
4.1 Accessing External Memory
It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described. Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri).
4.1.1 Role of P0 and P2 as Data/Address Bus
When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. If an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. It should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods.
Semiconductor Group 4-2 1997-08-01 Figure 4-1 External Program Memory Execution PCL OUT PCH OUT One Machine Cycle One Machine Cycle OUT PCH IN INST (A) without MOVX PCL OUT valid PCL OUT valid PCL OUT valid PCL OUT valid ALE PSEN RD RD PSEN ALE valid PCL OUT valid PCL OUT MOVX with (B) IN DATA IN INSTINST IN DPH OUT OR P2 OUT One Machine CycleOne Machine Cycle S6S5S4S3S2S1S6S5S4S3S2S1 MCD02575 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 OUT PCH PCH OUTOUT PCH PCH OUT OUT PCHPCH OUT P0 INST IN PCL OUT IN INST OUT PCL INST IN PCL OUT IN INST P0 PCL OUT DPL or Ri valid PCL OUT INST IN
Semiconductor Group 4-3 1997-08-01 External Bus Interface C505 / C505C
4.1.2 Timing
The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN , RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe.
4.1.3 External Program Memory Access
The external program memory is accessed under two conditions: - whenever signal EA is active (low); or - whenever the program counter (PC) content is greater than 3FFFH When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and must not be used for general-purpose I/O. The content of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). , Program Store Enable The read strobe for external program memory fetches is PSEN. It is not activated for internal program memory fetches. When the CPU is accessing external program memory, PSEN is activated twice every instruction cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 6 oscillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN , takes 3 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 4-1 a) and b).
4.3 Overlapping External Data and Program Memory Spaces
In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C505 the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.
Semiconductor Group 4-4 1997-08-01
4.4 ALE, Address Latch Enable
The C505 allows to switch off the ALE output signal. If the internal ROM is used (EA=1 and PC £ 3FFF H ) and ALE is switched off by EALE=0, then, ALE will only go active during external data memory accesses (MOVX instructions). If EA=0, the ALE generation is always enabled and the bit EALE has no effect. After a hardware reset the ALE generation is enabled. Special Function Register SYSCON (Address B1H ) Reset Value : XX100X01 B Bit Function EALE Enable ALE output EALE = 0 : ALE generation is disabled; disables ALE signal generation during internal code memory accesses (EA=1). With EA=1, ALE is automatically generated at MOVX instructions. EALE = 1 : ALE generation is enabled If EA =0, the ALE generation is always enabled and the bit EALE has no effect on the ALE generation. – Reserved bits for future use. Read by CPU returns undefined values. 76543210 EALE RMAP CMODB1H SYSCON Bit No. MSB LSB – XMAP1–– XMAP0 The shaded bits are not described in this section.
Semiconductor Group 4-5 1997-08-01 External Bus Interface C505 / C505C
4.5 Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each C500 production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks Technology TM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. Figure 4-2 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1) “Enhanced Hooks Technology” is a trademark and patent of MetaLink Corporation licenced to Siemens. MCS02647 SYSCON PCON TCON RESET EA PSEN ALE Port 0 Port 2 I/O Ports Optional Port 3 Port 1 C500 MCU Interface Circuit Enhanced Hooks RPort 0RPort 2 RTCON RPCON RSYSCON TEA TALE TPSEN EH-IC Target System Interface ICE-System Interface to Emulation Hardware
Semiconductor Group 4-6 1997-08-01
4.6 Eight Datapointers for Faster External Bus Access
4.6.1 The Importance of Additional Datapointers
The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this datapointer and an increment instruction, any other pointer handling is to be handled bytewise. For complex applications with peripherals located in the external data memory space (e.g. CAN controller) or extended data storage capacity this turned out to be a "bottle neck" for the 8051’s communication to the external world. Especially programming in high-level languages (PLM51, C51, PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages.
4.6.2 How the eight Datapointers of the C505 are realized
Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility to the 8051 instruction set. This instruction set, however, allows the handling of only one single 16- bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the C505 contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user’s program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the C505 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment. Figure 4-3 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx. Special Function Register DPSEL (Address 92H ) Reset Value : XXXXX000 B Bit Function DPSEL.2-0 Data pointer select bits DPSEL.2-0 defines the number of the actual active data pointer.DPTR0-7. DPSEL 76543210 –––92H Bit No. MSB LSB .2 .1–– . 0
Semiconductor Group 4-7 1997-08-01 External Bus Interface C505 / C505C Figure 4-3 Accessing of External Data Memory via Multiple Datapointers
4.6.3 Advantages of Multiple Datapointers
Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte by byte. This not only takes more time, it also requires additional space in the internal RAM.
4.6.4 Application Example and Performance Analysis
The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: 1FFF H Start address of table in external RAM: 2FA0H DPH(83 ) DPL(82 ) DPTR0 DPTR7 .0.1.2----- DPSEL(92 ) DPSEL Selected Data- pointer.2 .1 .0 DPTR 0000 0 0 1 DPTR 1 0 1 0 DPTR 2 0 1 1 DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 1 1 0 DPTR 6 1 1 1 DPTR 7 MCD00779 External Data Memory H HH
Semiconductor Group 4-8 1997-08-01 Example 1 : Using only One Datapointer (Code for a C501) Initialization Routine MOV LOW(SRC_PTR), #0FFH ;Initialize shadow_variables with source_pointer MOV HIGH(SRC_PTR), #1FH MOV LOW(DES_PTR), #0A0H ;Initialize shadow_variables with destination_pointer MOV HIGH(DES_PTR), #2FH Table Look-up Routine under Real Time Conditions ; Number of cycles PUSH DPL ;Save old datapointer 2 PUSH DPH ; 2 MOV DPL, LOW(SRC_PTR) ;Load Source Pointer 2 MOV DPH, HIGH(SRC_PTR) ; 2 ;INC DPTR Increment and check for end of table (execution time ;CJNE … not relevant for this consideration) – MOVC A,@DPTR ;Fetch source data byte from ROM table 2 MOV LOW(SRC_PTR), DPL ;Save source_pointer and 2 MOV HIGH(SRC_PTR), DPH ;load destination_pointer 2 MOV DPL, LOW(DES_PTR) ; 2 MOV DPH, HIGH(DES_PTR) ; 2 INC DPTR ;Increment destination_pointer ;(ex. time not relevant) – MOVX @DPTR, A ;Transfer byte to destination address 2 MOV LOW(DES_PTR), DPL ;Save destination_pointer 2 MOV HIGH(DES_PTR),DPH ; 2 POP DPH ;Restore old datapointer 2 POP DPL ; 2 ; Total execution time (machine cycles) : 28
Semiconductor Group 4-9 1997-08-01 External Bus Interface C505 / C505C Example 2 : Using Two Datapointers (Code for a C505) Initialization Routine MOV DPSEL, #06H ;Initialize DPTR6 with source pointer MOV DPTR, #1FFFH MOV DPSEL, #07H ;Initialize DPTR7 with destination pointer MOV DPTR, #2FA0H Table Look-up Routine under Real Time Conditions ; Number of cycles PUSH DPSEL ;Save old source pointer 2 MOV DPSEL, #06H ;Load source pointer 2 ;INC DPTR Increment and check for end of table (execution time ;CJNE … not relevant for this consideration) – MOVC A,@DPTR ;Fetch source data byte from ROM table 2 MOV DPSEL, #07H ;Save source_pointer and ;load destination_pointer 2 MOVX @DPTR, A ;Transfer byte to destination address 2 POP DPSEL ;Save destination pointer and ;restore old datapointer 2 ; Total execution time (machine cycles) : 12 The above example shows that utilization of the C505’s multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that a C505 program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use.
Semiconductor Group 4-10 1997-08-01
4.7 ROM Protection for the C505
The C505-2R allows to protect the contents of the internal ROM against unauthorized read out. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C505-2R version has to define whether ROM protection has to be selected or not. The C505-2R devices, which operate from internal ROM, are always checked for correct ROM contents during production test. Therefore, unprotected as well as protected ROMs must provide a procedure to verify the ROM contents. In ROM verification mode 1, which is used to verify unprotected ROMs, a ROM address is applied externally to the C505-2R and the ROM data byte is output at port 0. ROM verification mode 2, which is used to verify ROM protected devices, operates different : ROM addresses are generated internally and the expected data bytes must be applied externally to the device (by the manufacturer or by the customer) and are compared internally with the data bytes from the ROM. After 16 byte verify operations the state of the P3.5 pin shows whether the last 16 bytes have been verified correctly. This mechanism provides a very high security of ROM protection. Only the owner of the ROM code and the manufacturer who know the contents of the ROM can read out and verify it with less effort. The behaviour of the move code instruction, when the code is executed from the external ROM, is in such a way that accessing a code byte from a protected on-chip ROM address is not possible. In this case the byte accessed will be invalid.
4.7.1 Unprotected ROM Mode
If the ROM is unprotected, the ROM verification mode 1 as shown in figure 4-4 is used to read out the contents of the ROM. The AC timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 10). Figure 4-4 ROM Verification Mode 1 ROM verification mode 1 is selected if the inputs PSEN , ALE, EA, and RESET are put to the specified logic level. Then the 14-bit address of the internal ROM byte to be read is applied to the port 1 and port 2 lines. After a delay time, port 0 outputs the content of the addressed ROM cell. In ROM verification mode 1, the C505 must be provided with a system clock at the XTAL pins and pullup resistors on the port 0 lines. MCD02626 Inputs : PSEN, P2.6, P2.7 =SSV ALE, EA =VIH RESET = VIH1 Address Data OUT P1.0 - P1.7 P2.0 - P2.5 Port 0
Semiconductor Group 4-11 1997-08-01 External Bus Interface C505 / C505C
4.7.2 Protected ROM Mode
If the ROM is protected, the ROM verification mode 2 as shown in figure 4-5 is used to verify the contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in the AC specifications (chapter 10). Figure 4-5 ROM Verification Mode 2 ROM verification mode 2 is selected if the inputs PSEN , EA, and ALE are put to the specified logic levels. With RESET going inactive, the ROM verification mode 2 sequence is started. The C505 outputs an ALE signal with a period of 3 CLP and expects data bytes at port 0. The data bytes at port 0 are assigned to the ROM addresses in the following way : 1. Data Byte = content of internal ROM address 0000H 2. Data Byte = content of internal ROM address 0001H 3. Data Byte = content of internal ROM address 0002H 16. Data Byte= content of internal ROM address 000FH The C505-2R does not output any address information during the ROM verification mode 2. The first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse the ROM address pointer is internally incremented and the expected data byte for the next ROM address must be delivered externally. Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared internally with the ROM content of the actual address. If an verify error is detected, the error RESET ALE Port 0 P3.5
6 CLP
3 CLP
Data for Addr. 0 Data for Addr. X 16Data for Addr. X 16 + 1 Data for Ad. X 16 - 1 Data for Addr. 1 Inputs : ALE = PSEN, EA = RESET = V SS V IH MCT03289 1. ALE pulse after reset Low: Verify Error High: Verify ok
Semiconductor Group 4-13 1997-08-01 External Bus Interface C505 / C505C
4.8 Version Registers
Version registers are typically used for adapting the programming firmware to specific device characteristics such as ROM / OTP size etc. Three version registers are implemented in the C505. They can be read during normal program execution mode as mapped SFRs when the bit RMAP in SFR SYSCON is set. The first step of the C505 will contain the following information in the version registers. Version register 2 will be incremented with each new step of the C505. Contents of Version registers Name Address C505-2R Version Register 0 FC H C5 H Version Register 1 FD H 05H Version Register 2 FE H 01H
Semiconductor Group 5-1 1997-08-01
5 System Reset
5.1 Hardware Reset Operation
The hardware reset function incorporated in the C505 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode is to be terminated. Additional to the hardware reset, which is applied externally to the C505, there are two internal reset sources, the watchdog timer and the oscillator watchdog. This chapter deals only with the external hardware reset. The reset input is an active high input. An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle and is repeated every cycle until RESET goes low again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic power-up reset can be obtained, when VCC is applied, by connecting the reset pin to VCC via a capacitor. After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset.
Semiconductor Group 5-2 1997-08-01 System Reset C505 / C505C The time required for a reset operation is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is typically met using a capacitor of 4.7 to 10 mF. The same considerations apply if the reset signal is generated externally (figure 5-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. Figure 5-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H . After reset is internally accomplished the port latches of ports 0 to 4 default in FFH . This leaves port 0 floating, since it is an open drain port when not used as data/address bus. All other I/O port lines (ports 1,3 and 4) output a one (1). Port 2 lines output a zero (or one) after reset, if the EA is held low (or high). The internal SFRs are set to their initial states as defined in table 3-2. The contents of the internal RAM and XRAM of the C505 are not affected by a reset. After power- up the contents are undefined, while it remains unchanged during a reset if the power supply is not turned off. C505 RESET MCS03291 C505 C505 VCC CCV RESET RESET
Semiconductor Group 5-3 1997-08-01
5.2 Fast Internal Reset after Power-On
The C505 uses the oscillator watchdog unit for a fast internal reset procedure after power-on. Figure 5-1 shows the power-on sequence under control of the oscillator watchdog. Normally the devices of the 8051 family do not enter their default reset states before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 10 ms). During this time period the pins have an undefined state which could have severe effects especially to actuators connected to port pins. In the C505 the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). In the following the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is detected the watchdog uses the RC oscillator output as clock source for the chip rather than the on-chip oscillator's output. This allows correct resetting of the part and brings also all ports to the defined state (see figure 5-2). Under worst case conditions (fast VCC rise time - e.g. 1ms, measured from VCC = 4.25 V up to stable port condition), the delay between power-on and the correct port reset state is : – Typ.: 18 ms – Max.: 34 ms The RC oscillator will already run at a VCC below 4.25V (lower specification limit). Therefore, at slower VCC rise times the delay time will be less than the two values given above. After the on-chip oscillator has finally started, the oscillator watchdog detects the correct function; then the watchdog still holds the reset active for a time period of max. 768 cycles of the RC oscillator clock in order to allow the oscillation of the on-chip oscillator to stabilize (figure 5-2, II). Subsequently the clock is supplied by the on-chip oscillator and the oscillator watchdog's reset request is released (figure 5-2, III). However, an externally applied reset still remains active (figure 5-2, IV) and the device does not start program execution (figure 5-2, V) before the external reset is also released. Although the oscillator watchdog provides a fast internal reset it is additionally necessary to apply the external reset signal when powering up. The reasons are as follows: – Termination of Software Power-Down Mode – Reset of the status flag OWDS that is set by the oscillator watchdog during the power up sequence. Using a crystal or ceramic resonator for clock generation, the external reset signal must be held active at least until the on-chip oscillator has started and the internal watchdog reset phase is completed (after phase III in figure 5-2). When an external clock generator is used, phase II is very short. Therefore, an external reset time of typically 1 ms is sufficent in most applications. Generally, for reset time generation at power-on an external capacitor can be applied to the RESET pin.
Semiconductor Group 5-4 1997-08-01 System Reset C505 / C505C Figure 5-2 Power-On Reset of the C505 MCD02627 I II III IV V Power On; undef.Ports typ. 18 max. 34 µ s µ s Clock from RC-Oscillator; RESET at Ports On-Chip Osc. starts; Sequence Final RESET by Osc.-WD; (max. 768 RC in RESET Port remains because of active ext. Execution Start of Program RESETUndef.Ports On-Chip Osc. RC Osc.V RESET CC RESET Signal Clock Cycles)
Semiconductor Group 5-5 1997-08-01
5.3 Hardware Reset Timing
This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (high level) the internal reset procedure is started. It needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is also performed if there is no clock available at the device. (This is done by the oscillator watchdog, which provides an auxiliary clock for performing a perfect reset without clock at the XTAL1 and XTAL2 pins). The RESET signal must be active for at least one machine cycle; after this time the C505 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 5-3 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles. Figure 5-3 CPU Timing after Reset MCT02092 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 P1 P2 PCL OUT PCH OUT PCH OUT One Machine Cycle RESET ALE Inst. in OUT PCL
Semiconductor Group 5-6 1997-08-01 System Reset C505 / C505C
5.4 Oscillator and Clock Circuit
XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 5-4 shows the recommended oscillator circuit. Figure 5-4 Recommended Oscillator Circuit In this application the on-chip oscillator is used as a crystal-controlled, positive-reactance oscillator (a more detailed schematic is given in figure 5-5). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are non-critical. In this circuit 20 pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors. MCS03292 C 2 - 20 MHz XTAL1 XTAL2 C = 20 pF 10 pF for crystal operation C505 C
Semiconductor Group 5-8 1997-08-01 System Reset C505 / C505C
5.5 System Clock Output
For peripheral devices requiring a system clock, the C505 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON0), a clock signal with 1/6 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin must be programmed to a one (1), which is also the default after reset. Special Function Register ADCON0 (Address D8H ) Reset Value : 00X000000 B The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing diagram of the system clock output is shown in figure 5-7. Note : During slow-down operation the frequency of the CLKOUT signal is divided by 32. Bit Function CLK Clockout enable bit When set, pin P1.6/CLKOUT outputs the system clock which is 1/6 of the oscillator frequency. – Reserved bits for future use. Read by CPU returns undefined values. BD CLK – BSYD8 H ADCON0 Bit No. DF H DE H DD H DC H DB H DA H D9 H D8 H MSB LSB ADM MX2 MX1 MX0 The shaded bits are not used for clock output control.
Semiconductor Group 5-9 1997-08-01 Figure 5-7 Timing Diagram - System Clock Output MCT01858 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 ALE PSEN RD,WR CLKOUT
Semiconductor Group 6-1 1997-08-01 On-Chip Peripheral Components C505 / C505C
6 On-Chip Peripheral Components
This chapter gives detailed information about all on-chip peripherals of the C505 except for the integrated interrupt controller, which is described separately in chapter 7.
6.1 Parallel I/O
The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET . Port 4 is 2-bit I/O port with CAN controller specific alternate functions. This port has no available bits at bit positions 2-7.
6.1.1 Port Structures
The C505 generally allows digital I/O on 34 lines grouped into 4 bidirectional 8-bit ports and one 2-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0-P4 are performed via their corresponding special function registers. Depending on the specific ports, multiple functions are assigned to the port pins. Therefore, the parallel I/O ports of the C505 can be grouped into three different types which are listed in table 6-1. Type A and B port pins are standard C501 compatible I/O port lines, which can be used for digital I/O. The type A ports (port 0 and port 2) are also designed for accessing external data or program memory. Type B port lines are located at port 3 and port 4 to provide alternate functions for the serial interface and CAN controller I/O lines respectively, or are used as control outputs during external data memory accesses. The C505 provides eight analog input lines which are realized as mixed digital/analog inputs (type C). The 8 analog inputs, AN0-AN7, are located at the port 1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. The analog function of the specific port 1 pins are enabled by bits in the SFRs P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog input. Note : P1ANA is a mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set. Table 6-1 C505 Port Structure Types Type Description A Standard digital I/O ports which can also be used for external address/data bus. B Standard multifunctional digital I/O port lines C Mixed digital/analog I/O port lines with programmable analog input function
On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-2 1997-08-01 As already mentioned, port 1, 3 and 4 are provided for multiple alternate functions. These functions are listed in table 6-2: Prior to the description of the port type, specific port configurations the general port structure is described in the next section. Table 6-2 Alternate Functions of Port 1, 3 and 4 Port Second / third Function Port Type Function P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 AN0 / INT3 CC0 AN1 / INT4 / CC1 AN2 / INT5 / CC2 AN3 / INT6 / CC3 AN4 AN5 / T2EX AN6 / CLKOUT AN7 / T2 RxD TxD INT0 INT1 WR RD TXDC RXDC C C C C C C C C B B B B B B B B B B Analog input channel 0 / External Interrupt 3 input / Capture/compare 0 input/output Analog input channel 1 / External Interrupt 4 input / Capture/compare 1 input/output Analog input channel 2 / External Interrupt 5 input / Capture/compare 2 input/output Analog input channel 3 / External Interrupt 6 input / Capture/compare 3 input/output Analog input channel 4 Analog input channel 5 / Timer 2 external reload/trigger input Analog input channel 6 / System clock output Analog input channel 7 / Timer 2 external count input Serial port’s receiver data input (asynchronous) or data input/ output (synchronous) Serial port’s transmitter data output (asynchronous) or data clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external counter input Timer 1 external counter input External data memory write strobe External data memory read strobe CAN controller transmit output (C505C only) CAN controller receive input (C505C only)
Semiconductor Group 6-3 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.1.2 Standard I/O Port Circuitry
Figure 6-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the five I/O-ports. The bit latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read-latch" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the corresponding port SFR P0 to P4) activate the "read-latch" signal, while others activate the "read-pin" signal. Figure 6-1 Basic Structure of a Port Circuitry MCS01822 D CLK Port Latch Q Q Port Read Latch to Latch Read Pin Write Int. Bus Port Driver Circuit Pin
On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-4 1997-08-01 The output drivers of Port 1 to 4 have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-2: Q =0), which turns off the output driver FET n1. Then, for ports 1 to 4 the pin is pulled high by the internal pullups, but can be pulled low by an external source. When externally pulled low the port pins source current ( IIL or ITL). For this reason these ports are called "quasi-bidirectional". Figure 6-2 Basic Output Driver Circuit of Ports 1 to 4 MCS01823 D CLK Bit Latch Q Q Internal Pull Up Arrangement Pin Read Latch to Latch Read Pin Write VCC Int. Bus
Semiconductor Group 6-5 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.1.2.1 Port 0 Circuitry
Port 0, in contrast to ports 1 to 4, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-3) is used only when the port is emitting 1’s during the external memory accesses. Otherwise, the pullup is always off. Consequently, P0 lines that are used as output port lines are open drain lines. Writing a "1" to the port latch leaves both output FETs off and the pin floats. In that condition it can be used as high-impedance input. If port 0 is configured as general I/O port and has to emit logic high-level (1), external pullups are required. Figure 6-3 Port 0 Circuitry MCS02434 D CLK Bit Latch Control Addr./Data MUX Pin Read Latch Bus Latch Read Pin Write to VCC Int. Port=1 Q Q
On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-6 1997-08-01
6.1.2.2 Port 1, Port 3 and Port 4 Circuitry
The pins of ports 1, 3 and 4 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-2. Figure 6-4 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1); otherwise the pulldown FET is on and the port pin is stuck at 0. After reset all port latches contain ones (1). Figure 6-4 Ports 1, 3 and 4 The alternate functions of Port 4 pins are available for the C505C only. MCS01827 D CLK Bit Latch Q Q Internal Pull Up Arrangement Pin Read Latch to Latch Read Pin Write VCC Int. Bus Alternate Output Function Alternate Input Function
Semiconductor Group 6-7 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.1.2.3 Port 2 Circuitry
As shown in figure 6-3 and below in figure 6-5, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally. The switching is done by an internal control signal dependent on the input level at the EA pin and/or the contents of the program counter. If the ports are configured as an address/data bus, the port latches are disconnected from the driver circuit. During this time, the P0/P2 SFR remains unchanged. Being an address/data bus, port 0 uses a pullup FET as shown in figure 6-3. When a 16-bit address is used, port 2 uses the additional strong pullups p1 (figure 6-5a) to emit 1’s for the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port activity. Figure 6-5 Port 2 Circuitry If no external bus cycles are generated using data or code memory accesses, port 0 can be used for I/O functions. MCS03228 D CLK Bit Latch ControlAddr. MUX Pin Read Latch Latch Read Pin Write to VCC Int. Bus Port Q Q Internal Pull Up Arrangement
On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-8 1997-08-01 Figure 6-5a Port 2 Pull-up Arrangement Port 2 in I/O function works similar to the Type B port driver circuitry (section 6.1.3.1) whereas in address output function it works similar to Port 0 circuitry. MCS03229 = 1= 1 VCC Port Pin SSV Input Data (Read Pin) Delay p1 p2 p3 n1= 1 MUX Addr. Control Q
1 State
Semiconductor Group 6-9 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.1.3 Detailed Output Driver Circuitry
In fact, the pullups mentioned before and included in figure 6-2, 6-4 and 6-5 are pullup arrangements. The differences of the port types available in the C505 are described in the next sections.
6.1.3.1 Type B Port Driver Circuitry
Figure 6-6 shows the output driver circuit of the type B multifunctional digital I/O port lines. The basic circuitry of these ports is shown in figure 6-4. The pullup arrangement of type B port lines has one n-channel pulldown FET and three pullup FETs: Figure 6-6 Driver Circuit of Type B Port Pins – The pulldown FET n1 is of n-channel type. It is a very strong driver transistor which is capable of sinking high currents ( IOL ); it is only activated if a "0" is programmed to the port pin. A short circuit to VCC must be avoided if the transistor is turned on, since the high current might destroy the FET. This also means that no “0“ must be programmed into the latch of a pin that is used as input. – The pullup FET p1 is of p-channel type. It is activated for two oscillator periods (S1P1 and S1P2) if a 0-to-1 transition is programmed to the port pin, i.e. a "1" is programmed to the port latch which contained a "0". The extra pullup can drive a similar current as the pulldown FET n1. This provides a fast transition of the logic levels at the pin. – The pullup FET p2 is of p-channel type. It is always activated when a "1" is in the port latch, thus providing the logic high output level. This pullup FET sources a much lower current than p1; therefore the pin may also be tied to ground, e.g. when used as input with logic low input level. MCS03230 =1=1 VCC Port Pin SSV Q Input Data (Read Pin) p1 p2 p3 Delay = 1 State
On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-10 1997-08-01 – The pullup FET p3 is of p-channel type. It is only activated if the voltage at the port pin is higher than approximately 1.0 to 1.5 V. This provides an additional pullup current if a logic high level shall be output at the pin (and the voltage is not forced lower than approximately 1.0 to 1.5 V). However, this transistor is turned off if the pin is driven to a logic low level, e.g when used as input. In this configuration only the weak pullup FET p2 is active, which sources the current IIL . If, in addition, the pullup FET p3 is activated, a higher current can be sourced (ITL). Thus, an additional power consumption can be avoided if port pins are used as inputs with a low level applied. However, the driving capability is stronger if a logic high level is output. The described activating and deactivating of the four different transistors translates into four states the pins can be: – input low state (IL), p2 active only – input high state (IH) = steady output high state (SOH) p2 and p3 active – forced output high state (FOH), p1, p2 and p3 active – output low state (OL), n1 active If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state. If the latch is loaded with "0", the pin will be in OL state. If the latch holds a "0" and is loaded with "1", the pin will enter FOH state for two cycles and then switch to SOH state. If the latch holds a "1" and is reloaded with a "1" no state change will occur. At the beginning of power-on reset the pins will be in IL state (latch is set to "1", voltage level on pin is below of the trip point of p3). Depending on the voltage level and load applied to the pin, it will remain in this state or will switch to IH (=SOH) state. If it is used as output, the weak pull-up p2 will pull the voltage level at the pin above p3’s trip point after some time and p3 will turn on and provide a strong "1". Note, however, that if the load exceeds the drive capability of p2 ( IIL), the pin might remain in the IL state and provide a week "1" until the first 0-to-1 transition on the latch occurs. Until this the output level might stay below the trip point of the external circuitry. The same is true if a pin is used as bidirectional line and the external circuitry is switched from output to input when the pin is held at "0" and the load then exceeds the p2 drive capabilities. If the load exceeds IIL the pin can be forced to "1" by writing a "0" followed by a "1" to the port pin.
Semiconductor Group 6-11 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.1.3.2 Type C Port Driver Circuitry
Figure 6-7 shows the port driver circuit of the type C mixed digital/analog I/O port 1 lines of the C505. The analog function is selected by the bits in the SFR P1ANA. When analog function is selected, all output driver transistors (p1, p2, p3 and n1) are switched off. Figure 6-7 Driver Circuit of Type C Port Pins =1 =1 Input Data (Read Pin) >1=1 Port Pin Delay = 1 State Q Enable Analog Input (Bits of SFR P1ANA) to A / D Converter p1 p2 p3 V SS MCT03295 CCV
On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-12 1997-08-01
6.1.4 Port Timing
When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1). Consequently, the new value in the port latch will not appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle. When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 6-8 illustrates this port timing. It must be noted that this mechanism of sampling once per machine cycle is also used if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is detected when the sampled value differs from the value that was sampled the cycle before. Therefore, there must be met certain reqirements on the pulse length of signals in order to avoid signal "edges" not being detected. The minimum time period of high and low level is one machine cycle, which guarantees that this logic level is noticed by the port at least once. Figure 6-8 Port Timing MCT03231 P1 P2 S4 S5 P2P1 P2P1 P2P1 P2P1 P2P1 XTAL2 Input sampled: e.g. MOV A, P1 Old Data New DataPort P1 active for 1 State (driver transistor)
Semiconductor Group 6-13 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.1.5 Port Loading and Interfacing
The output buffers of ports 1 to 4 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be be looked up in the DC characteristics in the Data Sheet of the C505 or in chapter 10 of this User’s Manual. The corresponding parameters are VOL and VOH . The same applies to port 0 output buffers. They do, however, require external pullups to drive floating inputs, except when being used as the address/data bus. When used as inputs it must be noted that the ports 1 to 4 are not floating but have internal pullup transistors. The driving devices must be capable of sinking a sufficient current if a logic low level shall be applied to the port pin (the parameters ITL and IIL in the DC characteristics specify these currents). Port 0 as well as port 1 programmed to analog input function, however, have floating inputs when used for digital input.
On-Chip Peripheral Components C505 / C505C Semiconductor Group 6-14 1997-08-01
6.1.6 Read-Modify-Write Feature of Ports 0 to 4
Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-3. If the destination is a port or a port pin, these instructions read the latch rather than the pin. Note that all other instructions which can be used to read a port, exclusively read the port pin. In any case, reading from latch or pin, resp., is performed by reading the SFR P0, P2 and P3; for example, "MOV A, P3" reads the value from port 3 pins, while "ANL P3, #0AAH" reads from the latch, modifies the value and writes it back to the latch. It is not obvious that the last three instructions in table 6-3 are read-modify-write instructions, but they are. The reason is that they read the port byte, all 8 bits, modify the addressed bit, then write the complete byte back to the latch. The reason why read-modify-write instructions are directed to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "1" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the a port bit by a SETB or CLR instruction, another bit in this port with the above mentioned configuration might be changed if the value read from the pin were written back to th latch. However, reading the latch rather than the pin will return the correct value of "1". Table 6-3 "Read-Modify-Write"-Instructions Instruction Function ANL Logic AND; e.g. ANL P1, A ORL Logic OR; e.g. ORL P2, A XRL Logic exclusive OR; e.g. XRL P3, A JBC Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL CPL Complement bit; e.g. CPL P3.0 INC Increment byte; e.g. INC P4 DEC Decrement byte; e.g. DEC P5 DJNZ Decrement and jump if not zero; e.g. DJNZ P3, LABEL MOV Px.y,C Move carry bit to bit y of port x CLR Px.y Clear bit y of port x SETB Px.y Set bit y of port x
Semiconductor Group 6-15 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2 Timers/Counters
The C505 contains three 16-bit timers/counters, timer 0, 1, and 2, which are useful in many applications for timing and counting. In "timer" function, the timer register is incremented every machine cycle. Thus one can think of it as counting machine cycles. Since a machine cycle consists of 6 oscillator periods, the counter rate is 1/6 of the oscillator frequency. In "counter" function, the timer register is incremented in response to a 1-to-0 transition (falling edge) at its corresponding external input pin, T0, T1, or T2 (alternate functions of P3.4, P3.5 and P1.7 resp.). In this function the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) to recognize a 1- to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle.
6.2.1 Timer/Counter 0 and 1
Timer / counter 0 and 1 of the C505 are fully compatible with timer / counter 0 and 1 of the C501 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; Timer/ counter 1 in this mode holds its count. The effect is the same as setting TR1 = 0. External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. Each timer consists of two 8-bit registers (TH0 and TL0 for timer/counter 0, TH1 and TL1 for timer/ counter 1) which may be combined to one timer configuration depending on the mode that is established. The functions of the timers are controlled by two special function registers TCON and TMOD. In the following descriptions the symbols TH0 and TL0 are used to specify the high-byte and the low-byte of timer 0 (TH1 and TL1 for timer 1, respectively). The operating modes are described and shown for timer 0. If not explicity noted, this applies also to timer 1.
Semiconductor Group 6-16 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.1.1 Timer/Counter 0 and 1 Registers
Totally six special function registers control the timer/counter 0 and 1 operation : – TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers Special Function Register TL0 (Address 8AH ) Reset Value : 00 H Special Function Register TH0 (Address 8CH ) Reset Value : 00 H Special Function Register TL1 (Address 8BH ) Reset Value : 00 H Special Function Register TH1 (Address 8DH ) Reset Value : 00 H Bit Function TLx.7-0 x=0-1 Timer/counter 0/1 low register THx.7-0 x=0-1 Timer/counter 0/1 high register .7 .6 .5 .48AH TL0 Bit No. 76543210 MSB LSB .3 .2 .1 .0 Operating Mode Description 0 "TLx" holds the 5-bit prescaler value. 1 "TLx" holds the lower 8-bit part of the 16-bit timer/counter value. 2 "TLx" holds the 8-bit timer/counter value. 3 TL0 holds the 8-bit timer/counter value; TL1 is not used. Operating Mode Description 0 "THx" holds the 8-bit timer/counter value. 1 "THx" holds the higher 8-bit part of the 16-bit timer/counter valu e 2 "THx" holds the 8-bit reload value. 3 TH0 holds the 8-bit timer value; TH1 is not used.
Semiconductor Group 6-17 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register TCON (Address 88H ) Reset Value : 00 H Bit Function TR0 Timer 0 run control bit Set/cleared by software to turn timer/counter 0 ON/OFF. TF0 Timer 0 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR1 Timer 1 run control bit Set/cleared by software to turn timer/counter 1 ON/OFF. TF1 Timer 1 overflow flag Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. 8FH 8EH 8D H 8C H 8BH 8AH 89H 88H TF1 TR1 TF0 TR088H TCON Bit No. 76543210 MSB LSB IE1 IT1 IE0 IT0 The shaded bits are not used for controlling timer/counter 0 and 1.
Semiconductor Group 6-18 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register TMOD (Address 89H ) Reset Value : 00 H Bit Function GATE Gating control When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx" control bit is set. When cleared timer "x" is enabled whenever "TRx" control bit is set. C/T Counter or timer select bit Set for counter operation (input from "Tx" input pin). Cleared for timer operation (input from internal system clock). Mode select bits Gate C/T M1 M089H TMOD Bit No. 76543210 MSB LSB Gate C/T M1 M0 Timer 1 Control Timer 0 Control M1 M0 Function 0 0 8-bit timer/counter: "THx" operates as 8-bit timer/counter "TLx" serves as 5-bit prescaler 0 1 16-bit timer/counter. "THx" and "TLx" are cascaded; there is no prescaler 1 0 8-bit auto-reload timer/counter. "THx" holds a value which is to be reloaded into "TLx" each time it overflows 1 1 Timer 0 : TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only controlled by timer 1 control bits. Timer 1 : Timer/counter 1 stops
Semiconductor Group 6-19 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.1.2 Mode 0
Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by- 32 prescaler. Figure 6-9 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1 (setting Gate = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements). TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR0, TF0, TH0, TL0 and INT0 for the corresponding timer 1 signals in figure 6-9. There are two different gate bits, one for timer 1 (TMOD.7) and one for timer 0 (TMOD.3). Figure 6-9 Timer/Counter 0, Mode 0: 13-Bit Timer/Counter MCS02726 C/T = 0 TL0 TH0 TF0 C/T = 1 Control Interrupt = 1 TR0 P3.4/T0 Gate P3.2/INT0 Bits)(5 (8 Bits) OSC ÷ 6
Semiconductor Group 6-20 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.1.3 Mode 1
Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-10. Figure 6-10 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter MCS02727 C/T = 0 TL0 TH0 TF0 C/T = 1 Control Interrupt = 1 TR0 P3.4/T0 Gate P3.2/INT0 Bits)(8 (8 Bits) OSC ÷ 6
Semiconductor Group 6-21 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.1.4 Mode 2
Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-11. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. Figure 6-11 Timer/Counter 0,1, Mode 2: 8-Bit Timer/Counter with Auto-Reload MCS02728 C/T = 0 TL0 TF0 C/T = 1 Control Interrupt = 1 TR0 P3.4/T0 Gate P3.2/INT0 TH0 Reload Bits)(8 (8 Bits) ÷ 6OSC
Semiconductor Group 6-22 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.1.5 Mode 3
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate counters. The logic for mode 3 on timer 0 is shown in figure 6-12. TL0 uses the timer 0 control bits: C/T , Gate, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial channel as a baud rate generator, or in fact, in any application not requiring an interrupt from timer 1 itself. Figure 6-12 Timer/Counter 0, Mode 3: Two 8-Bit Timers/Counters MCS02729 C/T = 0 TL0 TF0 C/T = 1 Control Interrupt = 1 TR0 P3.4/T0 Gate P3.2/INT0 TH0 InterruptTF1 TR1 Timer Clock Bits)(8 (8 Bits) ÷ 6OSC fOSC /6
Semiconductor Group 6-23 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.2 Timer/Counter 2 with Additional Compare/Capture/Reload
The timer 2 with additional compare/capture/reload features is one of the most powerful peripheral units of the C505. lt can be used for all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. Timer 2 is designed to support various automotive control applications as well as industrial applications (frequency generation, digital-to-analog conversion, process control ...). Please note that the functionality of this timer is not equivalent to timer 2 of the C501. The C505 timer 2 in combination with the compare/capture/reload registers allows the following operating modes: – Compare : up to 4 PWM output signals with 65535 steps at maximum, and 300 ns resolution – Capture : up to 4 high speed capture inputs with 300 ns resolution – Reload : modulation of timer 2 cycle time The block diagram in figure 6-13 shows the general configuration of timer 2 with the additional compare/capture/reload registers. The I/O pins which can be used for timer 2 control are located as multifunctional port functions at port 1 (see table 6-4). Table 6-4 Alternate Port Functions of Timer 2 Pin Symbol Function P1.0 / AN0 / INT3 / CC0 Compare output / capture input for CRC register P1.1 / AN1 / INT4 / CC1 Compare output / capture input for CC register 1 P1.2 / AN2 / INT5 / CC2 Compare output / capture input for CC register 2 P1.3 / AN3 / INT6 / CC3 Compare output / capture input for CC register 3 P1.5 / AN5 / T2EX External reload trigger input P1.7 / AN7 / T2 External count or gate input to timer 2
Semiconductor Group 6-24 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-13 Timer 2 Block Diagram MCB02730 Comparator CCL3/CCH3 Capture Input/ Output Control P1.0/ INT3/ CC0 CC1 INT4/ P1.1/CC2 INT5/ P1.2/ CC3 INT6/ P1.2/ CCL2/CCH2 Comparator CCL1/CCH1 Comparator CRCL/CRCH Comparator Bit16 16 Bit 16 Bit 16 Bit OSC ÷12 fOSC T2PS Sync.P1.7/ T2EX P1.5/ Sync. T2I1 T2I0 Timer 2 TH2TL2 TF2 Reload EXEN2 Reload 1EXF2 Interrupt Request Compare
Semiconductor Group 6-25 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.2.1 Timer 2 Registers
This chapter describes all timer 2 related special function registers of timer 2. The interrupt related SFRs are also included in this section. Table 6-5 summarizes all timer 2 SFRs. Table 6-5 Special Function Registers of the Timer 2 Unit Symbol Description Address T2CON TL2 TH2 CCEN CRCL CRCH CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 IEN0 IEN1 IRCON Timer 2 control register Timer 2, low byte Timer 2, high byte Compare / capture enable register Compare / reload / capture register, low byte Compare / reload / capture register, high byte Compare / capture register 1, low byte Compare / capture register 1, high byte Compare / capture register 2, low byte Compare / capture register 2, high byte Compare / capture register 3, low byte Compare / capture register 3, high byte Interrupt enable register 0 Interrupt enable register 1 Interrupt control register C8 H CC H CD H C1 H CA H CB H C2 H C3 H C4 H C5 H C6 H C7 H A8H B8H C0 H
Semiconductor Group 6-26 1997-08-01 On-Chip Peripheral Components C505 / C505C The T2CON timer 2 control register is a bit-addressable register which controls the timer 2 function and the compare mode of registers CRC, CC1 to CC3. Special Function Register T2CON (Address C8H ) Reset Value : 00X00000 B Bit Function T2PS Prescaler select bit When set, timer 2 is clocked in the “timer“ or “gated timer“ function with 1/12 of the oscillator frequency. When cleared, timer 2 is clocked with 1/6 of the oscillator frequency. T2PS must be 0 for the counter operation of timer 2. I3FR External interrupt 3 falling / rising edge flag Used for capture function in combination with register CRC. If set, a capture to register CRC (if enabled) will occur on a positive transition at pin P1.0/AN0/INT3 CC0 T2R1 T2R0 Timer 2 reload mode selection T2CM Compare mode bit for registers CRC, CC1 through CC3 When set, compare mode 1 is selected. T2CM = 0 selects compare mode 0. T2I1 T2I0 Timer 2 input selection CF H CE H CD H CC H CB H CA H C9 H C8 H T2PS I3FR – T2R1C8 H T2CON Bit No. 76543210 MSB LSB T2R0 T2CM T2I1 T2I0 The shaded bits are not used for controlling timer/counter 2. T2R1 T2R0 Function
0 X Reload disabled
1 0 Mode 0 : auto-reload upon timer 2 overflow (TF2) 1 1 Mode 1 : reload on falling edge at pin P1.5 / AN5 / T2EX T2I1 T2I0 Function 0 0 No input selected, timer 2 stops 0 1 Timer function : input frequency = f osc/6 (T2PS = 0) or fosc/12 (T2PS = 1) 1 0 Counter function : external input signal at pin P1.7 / AN7 / T2 1 1 Gated timer function : input controlled by pin P1.7 / AN7 / T2
Semiconductor Group 6-27 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register TL2 (Address CCH ) Reset Value : 00 H Special Function Register TH2 (Address CDH ) Reset Value : 00 H Special Function Register CRCL (Address CAH ) Reset Value : 00 H Special Function Register CRCH (Address CBH ) Reset Value : 00 H Bit Function TL2.7-0 Timer 2 value low byte The TL2 register holds the 8-bit low part of the 16-bit timer 2 count value. TH2.7-0 Timer 2 value high byte The TH2 register holds the 8-bit high part of the 16-bit timer 2 count value. CRCL.7-0 Reload register low byte CRCL is the 8-bit low byte of the 16-bit reload register of timer 2. It is also used for compare/capture functions. CRCH.7-0 Reload register high byte CRCH is the 8-bit high byte of the 16-bit reload register of timer 2. It is also used for compare/capture functions. .7 .6 .5 .4CC H TL2 Bit No. 76543210 MSB LSB .3 .2 .1 LSB
Semiconductor Group 6-28 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register IEN0 (Address A8H ) Reset Value : 00 H Special Function Register IEN1 (Address B8H ) Reset Value : 00 H Special Function Register IRCON (Address C0H ) Reset Value : 00 H Bit Function ET2 Timer 2 overflow / external reload interrupt enable. If ET2 = 0, the timer 2 interrupt is disabled. If ET2 = 1, the timer 2 interrupt is enabled. EXEN2 Timer 2 external reload interrupt enable If EXEN2 = 0, the timer 2 external reload interrupt is disabled. If EXEN2 = 1, the timer 2 external reload interrupt is enabled. The external reload function is not affected by EXEN2. EXF2 Timer 2 external reload flag EXF2 is set when a reload is caused by a falling edge on pin T2EX while EXEN2 = 1. If ET2 in IEN0 is set (timer 2 interrupt enabled), EXF2 = 1 will cause an interrupt. EXF2 can be used as an additional external interrupt when the reload function is not used. EXF2 must be cleared by software. TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software. If the timer 2 interrupt is enabled, TF2 = 1 will cause an interrupt. EXF2 TF2 IEX6 IEX5C0 H IRCON Bit No. C7 H IEX4 IEX3 SWI IADC C6 H C5 H C4 H C3 H C2 H C1 H C0 H The shaded bits are not used in timer/counter 2 interrupt control. EAL WDT ET2 ESA8H IEN0 Bit No. AF H MSB LSB ET1 EX1 ET0 EX0 AE H AD H AC H AB H AA H A9H A8H EXEN2 SWDT EX6 EX5B8H IEN1 Bit No. BF H EX4 EX3 ECAN EADC BE H BD H BC H BB H BA H B9H B8H
Semiconductor Group 6-29 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register CCEN (Address C1H ) Reset Value : 00 H Bit Function COCAH3 COCAL3 Compare/capture mode for CC register 3 COCAH2 COCAL2 Compare/capture mode for CC register 2 COCAH1 COCAL1 Compare/capture mode for CC register 1 COCAH0 COCAL0 Compare/capture mode for CRC register COCAH3 COCAL3 COCAH2 COCAL2C1 H CCEN Bit No. 76543210 MSB LSB COCAH1 COCAL1 COCAH0 COCAL0 COCAH3 COCAL3 Function 0 0 Compare/capture disabled 0 1 Capture on rising edge at pin P1.3 / AN3 / INT6 / CC3 1 0 Compare enabled 1 1 Capture on write operation into register CCL3 COCAH2 COCAL2 Function 0 0 Compare/capture disabled 0 1 Capture on rising edge at pin P1.2 / AN2 / INT5 / CC2 1 0 Compare enabled 1 1 Capture on write operation into register CCL2 COCAH1 COCAL1 Function 0 0 Compare/capture disabled 0 1 Capture on rising edge at pin P1.1 / AN1 / INT4 / CC1 1 0 Compare enabled 1 1 Capture on write operation into register CCL1 COCAH0 COCAL0 Function 0 0 Compare/capture disabled 0 1 Capture on falling/rising edge at pin P1.0 / AN0 / INT3 CC0 1 0 Compare enabled 1 1 Capture on write operation into register CRCL
Semiconductor Group 6-30 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.2.2 Timer 2 Operation
The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. The detailed operation is described below. Timer Mode In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. Thus, the 16-bit timer register (consisting of TH2 and TL2) is either incremented in every machine cycle or in every second machine cycle. The prescaler is selected by bit T2PS in special function register T2CON. lf T2PS is cleared, the input frequency is 1/6 of the oscillator frequency. if T2PS is set, the 2:1 prescaler gates 1/12 of the oscillator frequency to the timer. Gated Timer Mode In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The external gate signal is sampled once every machine cycle. Event Counter Mode In the counter function, the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. When the sampled inputs show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the timer register in the cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. Note: The prescaler must be off for proper counter operation of timer 2, i.e. T2PS must be 0. In either case, no matter whether timer 2 is configured as timer, event counter, or gated timer, a rolling-over of the count from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. lf TF2 is used to generate a timer overflow interrupt, the request flag must be cleared by the interrupt service routine as it could be necessary to check whether it was the TF2 flag or the external reload request flag EXF2 which requested the interrupt. Both request flags cause the program to branch to the same vector address.
Semiconductor Group 6-31 1997-08-01 On-Chip Peripheral Components C505 / C505C Reload of Timer 2 The reload mode for timer 2 is selected by bits T2R0 and T2R1 in SFR T2CON. Figure 6-14 shows the configuration of timer 2 in reload mode. Mode 0 : When timer 2 rolls over from all l’s to all 0’s, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC registers, which are preset by software. The reload will happen in the same machine cycle in which TF2 is set, thus overwriting the count value 0000H . Mode 1 : A 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/AN5/T2EX. In addition, this transition will set flag EXF2, if bit EXEN2 in SFR IEN1 is set. lf the timer 2 interrupt is enabled, setting EXF2 will generate an interrupt. The external input pin T2EX is sampled in every machine cycle. When the sampling shows a high in one cycle and a low in the next cycle, a transition will be recognized. The reload of timer 2 registers will then take place in the cycle following the one in which the transition was detected. Figure 6-14 Timer 2 in Reload Mode MCS01903 Mode 1 EXF2 0Mode EXEN2 TF2CRCHCRCL Reload TH2TL2Input Clock Timer Interrupt Request T2EX P1.5 2<_
Semiconductor Group 6-32 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.2.3 Compare Function of Registers CRC, CC1 to CC3
The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a compare/capture register is compared with the contents of the timer register. lf the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin, and an interrupt is requested. The contents of a compare register can be regarded as ’time stamp’ at which a dedicated output reacts in a predefined way (either with a positive or negative transition). Variation of this ’time stamp’ somehow changes the wave of a rectangular output signal at a port pin. This may - as a variation of the duty cycle of a periodic signal - be used for pulse width modulation as well as for a continually controlled generation of any kind of square wave forms. Two compare modes are implemented to cover a wide range of possible applications. The compare modes 0 and 1 are selected by bit T2CM in special function register T2CON. In both compare modes, the new value arrives at the port pin 1 within the same machine cycle in which the internal compare signal is activated. The four registers CRC, CC1 to CC3 are multifunctional as they additonally provide a capture, compare or reload capability (CRC register only). A general selection of the function is done in register CCEN. Please note that the compare interrupt CC0 can be programmed to be negative or positive transition activated. The internal compare signal (not the output signal at the port pin!) is active as long as the timer 2 contents is equal to the one of the appropriate compare registers, and it has a rising and a falling edge. Thus, when using the CRC register, it can be selected whether an interrupt should be caused when the compare signal goes active or inactive, depending on bit I3FR in T2CON. For the CC registers 1 to 3 an interrupt is always requested when the compare signal goes active (see figure 6-16).
6.2.2.3.1 Compare Mode 0
In mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only, and not by the user. Writing to the port will have no effect. Figure 6-15 shows a functional diagram of a port latch in compare mode 0. The port latch is directly controlled by the two signals timer overflow and compare. The input line from the internal bus and the write-to-latch line are disconnected when compare mode 0 is enabled. Compare mode 0 is ideal for generating pulse width modulated output signals, which in turn can be used for digital-to-analog conversion via a filter network or by the controlled device itself (e.g. the inductance of a DC or AC motor). Mode 0 may also be used for providing output clocks with initially defined period and duty cycle. This is the mode which needs the least CPU time. Once set up, the output goes on oscillating without any CPU intervention. Figure 6-16 and 6-17 illustrate the function of compare mode 0.
Semiconductor Group 6-33 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-15 Port Latch in Compare Mode 0 Figure 6-16 Timer 2 with Registers CCx in Compare Mode 0 MCS02661 Latch Port Q QCLK D Port Pin Read Pin CCV Read Latch Port Circuit Internal Bus Latch Write to Compare Reg. Compare Register Circuit Comparator Timer Register Timer Circuit Compare Match S R Overflow Timer
16 Bit
P1.0/ Compare Signal Overflow Interrupt Set Latch Reset Latch TL2 Timer 2 TH2 Comparator Shaded Function Interrupt 16-Bit Compare Register CCx P1.3/ INT6/ CC3 Q R SS R Q SR Q SR Q CC2 INT5/ P1.2/ P1.1/ INT4/ CC1 16-Bit I3FR
Semiconductor Group 6-34 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-17 Function of Compare Mode 0
6.2.2.3.2 Modulation Range in Compare Mode 0
Generally it can be said that for every PWM generation in compare mode 0 with n-bit wide compare registers there are 2n different settings for the duty cycle. Starting with a constant low level (0% duty cycle) as the first setting, the maximum possible duty cycle would then be : (1 - 1/2n) x 100% This means that a variation of the duty cycle from 0% to real 100% can never be reached if the compare register and timer register have the same length. There is always a spike which is as long as the timer clock period. This “spike“ may either appear when the compare register is set to the reload value (limiting the lower end of the modulation range) or it may occur at the end of a timer period. In a timer 2/CCx register configuration in compare mode 0 this spike is divided into two halves: one at the beginning when the contents of the compare register is equal to the reload value of the timer; the other half when the compare register is equal to the maximum value of the timer register (here: FFFFH ). Please refer to figure 6-18 where the maximum and minimum duty cycle of a compare output signal are illustrated. Timer 2 is incremented with the machine clock (fosc/6), thus at 20-MHz operational frequency, these spikes are both approx. 150 ns long. MCT01906 Timer Count = FFFF Timer Count = Compare ValueContents of Timer 2 Timer Count = Reload Value Interrupt can be generated on overflow Compare Output (P1.x/CCx) Interrupt can be generated on compare-match H
Semiconductor Group 6-35 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-18 Modulation Range of a PWM Signal, generated with a Timer 2/CCx Register Combination in Compare Mode 0* The following example shows how to calculate the modulation range for a PWM signal. To calculate with reasonable numbers, a reduction of the resolution to 8-bit is used. Otherwise (for the maximum resolution of 16-bit) the modulation range would be so severely limited that it would be negligible. Example: Timer 2 in auto-reload mode; contents of reload register CRC = FF00H Restriction of modulation range = 1 / (256 x 2) x 100% = 0.195% This leads to a variation of the duty cycle from 0.195% to 99.805% for a timer 2/CCx register configuration when 8 of 16 bits are used. MCT01907 H L P1.x CCHx/CCLx = 0000 or = CRCH/CRCL (maximum duty cycle) P1.x L H CCHx/CCLx = FFFF (minimum duty cycle) Appr. 1/2 Machine Cycle Appr. 1/2 Machine Cycle H H
Semiconductor Group 6-36 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.2.3.3 Compare Mode 1
In compare mode 1, the software adaptively determines the transition of the output signal. lt is commonly used when output signals are not related to a constant signal period (as in a standard PWM Generation) but must be controlled very precisely with high resolution and without jitter. In compare mode 1, both transitions of a signal can be controlled. Compare outputs in this mode can be regarded as high speed outputs which are independent of the CPU activity. lf compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, one can choose whether the output signal is to make a new transition (1-to-0 or 0-to-1, depending on the actual pinlevel) or should keep its old value at the time the timer 2 count matches the stored compare value. Figure 6-19 and figure 6-20 show functional diagrams of the timer/compare register/port latch configuration in compare mode 1. In this function, the port latch consists of two separate latches. The upper latch (which acts as a “shadow latch“) can be written under software control, but its value will only be transferred to the output latch (and thus to the port pin) in response to a compare match. Note that the double latch structure is transparent as long as the internal compare signal is active. While the compare signal is active, a write operation to the port will then change both latches. This may become important when driving timer 2 with a slow external clock. In this case the compare signal could be active for many machine cycles in which the CPU could unintentionally change the contents of the port latch. A read-modify-write instruction will read the user-controlled „shadow latch“ and write the modified value back to this “shadow-latch“. A standard read instruction will - as usual - read the pin of the corresponding compare output.
Semiconductor Group 6-37 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-19 Port Latch in Compare Mode 1 Figure 6-20 Timer 2 with Registers CCx in Compare Mode 1 (CCx stands for CRC, CC1 to CC3, IEXx stands for IEX3 to IEX6) MCS02662 Latch Port Q QCLK D Read Pin CCV D CLK Q Shadow Latch Read Latch Port Circuit Internal Bus Latch Write to Compare Reg. Compare Register Circuit Comparator Timer Register Timer Circuit Compare Match Pin Port16 Bit P1.7 CC0 INT3/ P1.0/ Compare Signal Overflow Interrupt Output Latch Shadow Latch Port Latch Circuit TL2 Timer TH2 Comparator Shaded Function Interrupt P1.3/ INT6/ CC3 I3FR
Semiconductor Group 6-38 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.2.4 Using Interrupts in Combination with the Compare Function
The compare service of registers CRC, CC1, CC2 and CC3 are assigned to alternate output functions at port pins P1.0 to P1.3. Another option of these pins is that they can be used as external interrupt inputs. However, when using the port lines as compare outputs then the input line from the port pin to the interrupt system is disconnected (but the pin’s level can still be read under software control). Thus, a change of the pin’s level will not cause a setting of the corresponding interrupt flag. In this case, the interrupt input is directly connected to the (internal) compare signal thus providing a compare interrupt. The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next “compare match“. The principle is, that the internal compare signal (generated at a match between timer count and register contents) not only manipulates the compare output but also sets the corresponding interrupt request flag. Thus, the current task of the CPU is interrupted - of course provided the priority of the compare interrupt is higher than the present task priority - and the corresponding interrupt service routine is called. This service routine then sets up all the necessary parameters for the next compare event. Advantages when using compare interrupts Firstly, there is no danger of unintentional overwriting a compare register before a match has been reached. This could happen when the CPU writes to the compare register without knowing about the actual timer 2 count. Secondly, and this is the most interesting advantage of the compare feature, the output pin is exclusively controlled by hardware therefore completely independent from any service delay which in real time applications could be disastrous. The compare interrupt in turn is not sensitive to such delays since it loads the parameters for the next event. This in turn is supposed to happen after a suff icient space of time. Please note the following special case where a program using compare interrupts could show a “surprising“ behavior: The configuration has already been mentioned in the description of compare mode 1. The fact that the compare interrupts are transition activated becomes important when driving timer 2 with a slow external clock. In this case it should be carefully considered that the compare signal is active as long as the timer 2 count is equal to the contents of the corresponding compare register, and that the compare signal has a rising and a falling edge. Furthermore, the “shadow latches“ used in compare mode 1 are transparent while the compare signal is active. Thus, with a slow input clock for timer 2, the comparator signal is active for a long time (= high number of machine cycles) and therefore a fast interrupt controlled reload of the compare register could not only change the “shadow latch“ - as probably intended - but also the output buffer. When using the CRC, you can select whether an interrupt should be generated when the compare signal goes active or inactive, depending on the status of bit I3FR in T2CON. Initializing the interrupt to be negative transition triggered is advisable in the above case. Then the compare signal is already inactive and any write access to the port latch just changes the contents of the “shadow-latch“. Please note that for CC1 to CC3 registers an interrupt is always requested when the compare signal goes active.
Semiconductor Group 6-39 1997-08-01 On-Chip Peripheral Components C505 / C505C The second configuration which should be noted is when compare function is combined with negative transition activated interrupts. lf the port latch of port P1.0 contains a 1, the interrupt request flags IEX3 will immediately be set after enabling the compare mode for the CRC register. The reason is that first the external interrupt input is controlled by the pin’s level. When the compare option is enabled the interrupt logic input is switched to the internal compare signal, which carries a low level when no true comparison is detected. So the interrupt logic sees a 1-to-0 edge and sets the interrupt request flag. An unintentional generation of an interrupt during compare initialization can be prevented lf the request flag is cleared by software after the compare is activated and before the external interrupt is enabled.
Semiconductor Group 6-40 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.2.2.5 Capture Function
Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this function. In mode 0, an external event latches the timer 2 contents to a dedicated capture register. In mode 1, a capture will occur upon writing to the low order byte of the dedicated 16-bit capture register. This mode is provided to allow the software to read the timer 2 contents “on-the-fly“. In mode 0, the external event causing a capture is : – for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1 – for the CRC register: a positive or negative transition at the corresponding pin, depending on the status of the bit I3FR in SFR T2CON. lf the edge flag is cleared, a capture occurs in response to a negative transition; lf the edge flag is set a capture occurs in response to a positive transition at pin P1.0 / INT3 / CC0. In both cases the appropriate port 1 pin is used as input and the port latch must be programmed to contain a one (1). The external input is sampled in every machine cycle. When the sampled input shows a low (high) level in one cycle and a high (low) in the next cycle, a transition is recognized. The timer 2 contents is latched to the appropriate capture register in the cycle following the one in which the transition was identified. In mode 0 a transition at the external capture inputs of registers CC1 to CC3 will also set the corresponding external interrupt request flags IEX3 to IEX6. lf the interrupts are enabled, an external capture signal will cause the CPU to vector to the appropriate interrupt service routine. In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The value written to the dedicated capture register is irrelevant for this function. The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction. In this mode no interrupt request will be generated. Figure 6-21 illustrates the operation of the CRC register, while Figure 6-21a shows the operation of the compare/ capture registers 1 to 3. The two capture modes can be established individually for each capture register by bits in SFR CCEN (compare/capture enable register). That means, in contrast to the compare modes, it is possible to simultaneously select mode 0 for one capture register and mode 1 for another register.
Semiconductor Group 6-41 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-21 Timer 2 - Capture with Register CRC MCS01909 Mode 1 IEX3 0Mode TF2 CRCHCRCL Capture TH2TL2Input Clock External Interrupt Request Timer 2 Interrupt Request CON.6 CRCL" "Write to CC0 3/P1.0/INT
Semiconductor Group 6-42 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-21a Timer 2 - Capture with Registers CC1 to CC3 MCS01910 Mode 1 IEX4 0Mode TF2 CCH1CCL1 Capture TH2TL2Input Clock External Interrupt 4 Request Timer 2 Interrupt Request CCL1" "Write to CC1 4/P1.1/INT
Semiconductor Group 6-43 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3 Serial Interface
The serial port of the C505 is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn’t been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in 4 modes (one synchronous mode, three asynchronous modes). The baud rate clock for the serial port is derived from the oscillator frequency (mode 0, 2) or generated either by timer 1 or by a dedicated baud rate generator (mode 1, 3). Mode 0, Shift Register (Synchronous) Mode: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 data bits are transmitted/ received: (LSB first). The baud rate is fixed at 1/6 of the oscillator frequency. (See section 6.3.4 for more detailed information) Mode 1, 8-Bit USART, Variable Baud Rate: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in special function register SCON. The baud rate is variable. (See section 6.3.5 for more detailed information) Mode 2, 9-Bit USART, Fixed Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in SCON) can be assigned to the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/16 or 1/32 of the oscillator frequency. (See section 6.3.6 for more detailed information) Mode 3, 9-Bit USART, Variable Baud Rate: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable. (See section 6.3.6 for more detailed information) In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incomming start bit if REN = 1. The serial interface also provides interrupt requests when transmission or reception of a frames have been completed. The corresponding interrupt request flags are TI or RI, resp. See chapter 7 of this user manual for more details about the interrupt structure. The interrupt request flags TI and RI can also be used for polling the serial interface, if the serial interrupt is not to be used (i.e. serial interrupt not enabled).
Semiconductor Group 6-44 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3.1 Multiprocessor Communication
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows. When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is beeing addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the incoming data bytes. SM2 has no effect in mode 0. SM2 can be used in mode 1 to check the validity of the stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
6.3.2 Serial Port Registers
The serial port control and status register is the special function register SCON. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). SBUF is the receive and transmit buffer of serial interface. Writing to SBUF loads the transmit register and initiates transmission. Reading out SBUF accesses a physically separate receive register.
Semiconductor Group 6-45 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register SCON (Address 98H ) Reset Value : 00 H Special Function Register SBUF (Address 99H ) Reset Value : XX H Bit Function SM0 SM1 Serial port 0 operating mode selection bits SM2 Enable serial port multiprocessor communication in modes 2 and 3 In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. REN Enable receiver of serial port Enables serial reception. Set by software to enable serial reception. Cleared by software to disable serial reception. TB8 Serial port transmitter bit 9 TB8 is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. RB8 Serial port receiver bit 9 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. TI Serial port transmitter interrupt flag TI is set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. TI must be cleared by software. RI Serial port receiver interrupt flag RI is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (exception see SM2). RI must be cleared by software. 9FH 9EH 9D H 9C H 9BH 9AH 99H 98H SM0 SM1 SM2 REN98H SCON Bit No. MSB LSB TB8 RB8 TI RI 99H SBUF 76543210 Serial Interface Buffer Register SM0 SM1 Selected operating mode 0 0 Serial mode 0 : Shift register, fixed baud rate (fOSC /6) 0 1 Serial mode 1 : 8-bit UART, variable baud rate 1 0 Serial mode 2 : 9-bit UART, fixed baud rate ( fOSC /16 or fOSC /32) 1 1 Serial mode 3 : 9-bit UART, variable baud rate
Semiconductor Group 6-46 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3.3 Baud Rate Generation
There are several possibilities to generate the baud rate clock for the serial port depending on the mode in which it is operating. For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. The serial interface requires a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators have to provide a "baud rate clock" to the serial interface which - there divided by 16 - results in the actual "baud rate". However, all formulas given in the following section already include the factor and calculate the final baud rate. Further, the abrevation f OSC refers to the external clock frequency (oscillator or external input clock operation). The baud rate of the serial port is controlled by two bits which are located in the special function registers as shown below. Special Function Register ADCON0 (Address D8H ) Reset Value : 00X00000 B Special Function Register PCON (Address 87H ) Reset Value : 00 H Figure 6-22 shows the configuration for the baud rate generation of the serial port. Bit Function BD Baud rate generator enable When set, the baud rate of serial interface is derived from the dedicated baud rate generator. When cleared (default after reset), baud rate is derived from the timer 1 overflow rate. SMOD Double baud rate When set, the baud rate of serial interface in modes 1, 2, 3 is doubled. After reset this bit is cleared. – Reserved bits for future use. Read by CPU returns undefined values. SMOD PDS IDLS SD87H PCON Bit No. MSB LSB GF1 GF0 PDE IDLE 76543210 BD CLK – BSYD8 H ADCON0ADM MX2 MX1 MX0 DF H DE H DD H DC H DB H DA H D9 H D8 H The shaded bits are not used for controlling the baud rate.
Semiconductor Group 6-47 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-22 Baud Rate Generation for the Serial Port Depending on the programmed operating mode different paths are selected for the baud rate clock generation. Figure 6-22 shows the dependencies of the serial port baud rate clock generation on the two control bits and from the mode which is selected in the special function register SCON.
6.3.3.1 Baud Rate in Mode 0
The baud rate in mode 0 is fixed to :
6.3.3.2 Baud Rate in Mode 2
The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON. If SMOD = 0 (which is the value after reset), the baud rate is 1/32 of the oscillator frequency. If SMOD = 1, the baud rate is 1/16 of the oscillator frequency. MCS02733 Rate fOSC (SMOD) Baud Clock PCON.7 (SM0/ SM1) SCON.7 SCON.6 Only one mode can be selected ADCON0.7 (BD) Baud Rate Generator (SRELH SRELL) Timer 1 Mode 2 Mode 0 Note: The switch configuration shows the reset state. Mode 3 Mode 1 Overflow Mode 0 baud rate =oscillator frequency Mode 2 baud rate = oscillator frequency
2 SMOD
x
Semiconductor Group 6-48 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3.3.3 Baud Rate in Mode 1 and 3
In these modes the baud rate is variable and can be generated alternatively by a baud rate generator or by timer 1.
6.3.3.3.1 Using the Internal Baud Rate Generator
In modes 1 and 3, the C505 can use an internal baud rate generator for the serial port. To enable this feature, bit BD (bit 7 of special function register ADCON0) must be set. Bit SMOD (PCON.7) controls a divide-by-2 circuit which affect the input and output clock signal of the baud rate generator. After reset the divide-by-2 circuit is active and the resulting overflow output clock will be divided by 2. The input clock of the baud rate generator is f OSC . Figure 6-23 Serial Port Input Clock when using the Baud Rate Generator The baud rate generator consists of a free running upward counting 10-bit timer. On overflow of this timer (next count step after counter value 3FFH ) there is an automatic 10-bit reload from the registers SRELL and SRELH. The lower 8 bits of the timer are reloaded from SRELL, while the upper two bits are reloaded from bit 0 and 1 of register SRELH. The baud rate timer is reloaded by writing to SRELL. MCS02734 fOSC (SMOD) PCON.7 1÷ 2 SRELH SRELL.1 .0 Baud Rate Generator Input Clock Overflow Note : The switch configuration shows the reset state.
10 Bit Timer
Semiconductor Group 6-49 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register SRELH (Address BAH ) Reset Value : XXXXXX11 B Special Function Register SRELL (Address AAH ) Reset Value : D9 H After reset SRELH and SRELL have a reload value of 3D9H . With this reload value the baud rate generator has an overflow rate of input clock / 39. With a 6 MHz oscillator frequency, the commonly used baud rates 4800 baud (SMOD = 0) and 9600 baud (SMOD = 1) are available (with 0.16 % deviation). With the baud rate generator as clock source for the serial port in mode 1 and 3, the baud rate of can be determined as follows: Bit Function SRELH.0-1 Baudrate generator reload high value Upper two bits of the baudrate timer reload value. SRELL.0-7 Baudrate generator reload low value Lower 8 bits of the baudrate timer reload value. – Reserved bits for future use. Read by CPU returns undefined values. AA H SRELL Bit No. MSB LSB LSB BA H SRELHMSB 76543210 The shaded bits are not used for reload operation. Mode 1, 3 baud rate = 32 x (baud rate generator overflow rate) 2SMOD x oscillator frequency Baud rate generator overflow rate = 210 – SREL with SREL = SRELH.1 – 0, SRELL.7 – 0
Semiconductor Group 6-50 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3.3.3.2 Using Timer 1 to Generate Baud Rates
In mode 1 and 3 of the serial port also timer 1 can be used for generating baud rates. Then the baud rate is determined by the timer 1 overflow rate and the value of SMOD as follows: The timer 1 interrupt is usually disabled in this application. Timer 1 itself can be configured for either "timer" or "counter" operation, and in any of its operating modes. In most typical applications, it is configured for "timer" operation in the auto-reload mode (high nibble of TMOD = 0010B). In this case the baud rate is given by the formula: Very low baud rates can be achieved with timer 1 if leaving the timer 1 interrupt enabled, configuring the timer to run as 16-bit timer (high nibble of TMOD = 0001B), and using the timer 1 interrupt for a 16-bit software reload. Mode 1, 3 baud rate = (timer 1 overflow rate)32 SMOD x Mode 1, 3 baud rate = 32 x 6 x (256 – (TH1)) 2SMOD x oscillator frequency
Semiconductor Group 6-51 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3.4 Details about Mode 0
Serial data enters and exists through RxD. TxD outputs the shift clock. 8 data bits are transmitted/ received: (LSB first). The baud rate is fixed at fOSC /6. Figure 6-24 shows a simplified functional diagram of the serial port in mode 0. The associated timing is illustrated in figure 6-25. Transmission is initiated by any instruction that uses SBUF as a destination register. The "Write-to- SBUF" signal at S6P2 also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "Write-to-SBUF", and activation of SEND. SEND enables the output of the shift register to the alternate output function line of P3.0, and also enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1 and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register are shifted to the right one position. As data bits shift out to the right, zeroes come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the MSB, and all positions to the left of that contain zeroes. This condition flags the TX control block to do one last shift and then deactivate SEND and set TI. Both of these actions occur at S1P1 of the 10th machine cycle after "Write-to-SBUF". Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 of the next machine cycle, the RX control unit writes the bits 1111 1110 to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bit comes in from the right, 1s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set.
Semiconductor Group 6-52 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-24 Serial Interface, Mode 0, Functional Diagram MCS02101 Internal Bus SBUF Zero Detector D S CLK Q Shift Send TX Control Start TX Clock TI RX Control Start RI Receive Shift Serial Port Interrupt Input Shift Register SBUF Internal Bus Write to SBUF ShiftLoad SBUF Read SBUF RXD P3.0 Alt. Output Function Function Output P3.1 Alt. TXD Shift Clock REN RI RX Clock Function Input P3.0 Alt. RXD 01 111111 Shift Baud Rate Clock
Semiconductor Group 6-53 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-25 Serial Interface, Mode 0, Timing Diagram S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S D0 D1 D2 D3 D4 D5 D6 D7 ALE Write to SBUF Send Shift RXD (Data Out) S6P2 TXD (Shift Clock) S3P1 S6P1 Write to SCON (Clear RI) Shift Receive RI RXD (Data In) TXD (Shift Clock) D0 D1 D2 D3 D4 D5 D6 D7 S5P TI MCT02102 ReceiveTransmit
Semiconductor Group 6-54 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3.5 Details about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The baud rate is determined either by the timer 1 overflow rate or by the internal baud rate generator. Figure 6-26 shows a simplified functional diagram of the serial port in mode 1. The associated timings for transmit/receive are illustrated in figure 6-27. Transmission is initiated by an instruction that uses SBUF as a destination register. The "Write-to- SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission starts at the next rollover in the divide- by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "Write- to-SBUF" signal). The transmission begins with activation of SEND , which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeroes are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeroes. This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after "Write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide- by-16 counter is immediately reset, and 1FFH is written into the input shift register, and reception of the rest of the frame will proceed. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for the noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is to provide rejection or false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register, (which in mode 1 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1) RI = 0, and 2) either SM2 = 0, or the received stop bit = 1 If one of these two condtions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bit goes into SBUF, and RI is activated. At this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD.
Semiconductor Group 6-55 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-26 Serial Interface, Mode 1, Functional Diagram MCS02103 Internal Bus SBUF Zero Detector D S CLK Q Data Send 1-to-0 Transition Detector TX Control ShiftStart TX Clock RX ControlStart Load Shift SBUF Sample Bit Detector (9Bits) Input Shift Register 1FF SBUF Internal Bus Write to SBUF TXD Baud Rate Clock RXD Shift Load SBUF Read SBUF ÷ 16 ÷ 16 RX Interrupt Port Serial 1 TI RI H
Semiconductor Group 6-56 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-27 Serial Interface, Mode 1, Timing Diagram MCT02104 to SBUF D7 Stop BitD6D5D4D3D2D1D0Start Bit TI TXD Shift Data S1P1 Send D0Start Bit D1 D2 D3 D4 D5 D6 D7 Stop Bit ÷ 16 Reset Receive Transmit Write TX Clock Clock RX RXD Sample Times Bit Detector Shift RI
Semiconductor Group 6-57 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.3.6 Details about Modes 2 and 3
Eleven bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB8) can be assigned the value of 0 or 1. On reception, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 the oscillator frequency in mode 2 (When bit SMOD in SFR PCON (87 H ) is set, the baud rate is fOSC /16). In mode 3 the baud rate clock is generated by timer 1, which is incremented by a rate of fOSC /6 or by the internal baud rate generator. Figure 6-28 shows a functional diagram of the serial port in modes 2 and 3. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. The associated timings for transmit/receive are illustrated in figure 6-29. Transmission is initiated by any instruction that uses SBUF as a destination register. The "Write-to- SBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission starts at the next rollover in the divide- by-16 counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the "Write- to-SBUF" signal.) The transmission begins with activation of SEND, which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeroes are clocked in. Thus, as data bits shift out to the right, zeroes are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain zeroes. This condition flags the TX control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "Write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide- by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bit come from the right, 1s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the RX control block to do one last shift, load SBUF and RB8, and to set RI. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) RI = 0, and 2) Either SM2 = 0 or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bit goes into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8 or RI.
Semiconductor Group 6-58 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-28 Serial Interface, Mode 2 and 3, Functional Diagram MCS02105 Internal Bus TB8 SBUF Zero Detector D S CLK Q Data Send 1-to-0 Transition Detector ÷ 16 TX Control ShiftStart TX Clock TI RX ControlStart RI Load Shift SBUF RX Clock Serial Port Interrupt Sample Bit Detector (9Bits) Input Shift Register 1FF SBUF Internal Bus Write to SBUF TXD Baud Rate Clock RXD Shift Load SBUF Read SBUF ÷ 16 Stop Bit Generation
Semiconductor Group 6-59 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-29 Serial Interface, Mode 2 and 3, Timing Diagram MCT02587 Write to SBUF TX Clock D7 TB8 Stop BitD6D5D4D3D2D1D0Start Bit Stop Bit Gen. TI TXD Shift Data Mode 2 : S6P1 Send RX Clock RX D0Start Bit D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Bit Detector Sample Times Shift RI ÷ 16 Reset Receive Transmit Mode 3 : S1P1
Semiconductor Group 6-60 1997-08-01 On-Chip Peripheral Components C505C Only
6.4 The On-Chip CAN Controller
The Controller Area Network (CAN) bus with its associated protocol allows communication between a number of stations which are connected to this bus with high efficiency. Efficiency in this context means: – Transfer speed (data rates of up to 1 Mbit/sec can be achieved) – Data integrity (the CAN protocol provides several means for error checking) – Host processor unloading (the controller here handles most of the tasks autonomously) – Flexible and powerful message passing (the extended CAN protocol is supported) Note: The CAN interface is a part of the C505C derivatives only. The CAN interface which is integrated in the C505C is functionally fully compatible with the CAN module which is available in the 8-bit microcontroller C515C and in the 16-bit microcontroller C167CR. The CAN module of the C167CR has been adapted with its internal bus interface, clock generation logic, register access control logic, and interrupt function to the requirements of the 8-bit C500 microcontroller architecture. Generally, the CAN interface is made of two major blocks : – The CAN controller – The internal bus interface The CAN controller is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15). This includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc. In order to implement the physical layer, external components have to be connected to the C505C. The internal bus interface connects the on-chip CAN controller to the internal bus of the microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256 byte wide address range of the external data memory area (F700H to F7FFH ) and can be accessed using MOVX instructions.
Semiconductor Group 6-61 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.1 Basic CAN Controller Functions
The on-chip CAN controller combines several functional blocks (see figure 6-30) that work in parallel and contribute to the controller’s performance. These units and the functions they provide are described below. The CAN controller provides storage for up to 15 message objects of maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of control and status bits. Each object can be configured with its direction as either transmit or receive, except the last message which is only a receive buffer with a special mask register. An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier (taking into account the respective global mask register) is received over the CAN bus. By requesting the transmission of a message with the direction set as receive, a remote frame can be sent to request that the appropriate object be sent by some other node. Each object has separate transmit and receive interrupts and status bits, allowing the microcontroller full flexibility in detecting when a remote/data frame has been sent or received. For general purpose two masks for acceptance filtering can be programmed, one for identifiers of 11 bits and one for identifiers of 29 bits. However the microcontroller must configure bit XTD (Normal or Extended Frame Identifier) in the message configuration register for each valid message to determine whether a standard or extended frame will be accepted. The last message object has its own programmable mask for acceptance filtering, allowing a large number of infrequent objects to be handled by the system. The object layer architecture of the CAN controller is designed to be as regular and orthogonal as possible. This makes it easy to use and small for implementation. The message storage is implemented in an intelligent memory which can be addressed by the CAN controller and the microcontroller interface. The content of various bit fields in the object are used to perform the functions of acceptance filtering, transmit search, interrupt search and transfer completion. It can be filled with up to 15 messages of 8 bytes data. The CAN controller offers significantly improved status information over earlier versions, enabling a much easier diagnosis of the state of the network.
Semiconductor Group 6-62 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-30 CAN Controller Block Diagram MCB02736 Bit Timing Logic Timing Generator BTL-Configuration CRC Gen./Check TX/RX Shift Register TXDC RXDC Intelligent Interrupt Register Memory Processor Register Status Stream Bit Error Logic Management Messages Handlers Control Status + to internal Bus Clocks Control Messages (to all)
Semiconductor Group 6-63 1997-08-01 On-Chip Peripheral Components C505C Only TX/RX Shift Register The Transmit / Receive Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory. Bit Stream Processor (BSP) The Bit Stream Processor is a sequencer controlling the sequential data stream between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the processes of reception, arbitration, transmission, and error signalling are performed according to the CAN protocol. Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP. Cyclic Redundancy Check Register (CRC) This register generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages. This is done by dividing the data stream by the code generator polynomial. Error Management Logic (EML) The Error Management Logic is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit Stream Processor. According to the values of the error counters, the CAN controller is set into the states error active, error passive and busoff. The CAN controller is error active, if both error counters are below the error passive limit of 128. It is error passive, if at least one of the error counters equals or exceeds 128. It goes busoff, if the Transmit Error Counter equals or exceeds the busoff limit of 256. The device remains in this state, until the busoff recovery sequence is finished. Additionally, there is the bit EWRN in the Status Register, which is set, if at least one of the error counters equals or exceeds the error warning limit of 96. EWRN is reset, if both error counters are less than the error warning limit. Bit Timing Logic (BTL) This block monitors the busline input RXDC and handles the busline related bit timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant busline transition at Start of Frame (hard synchronization) and on any further recessive to dominant busline transition, if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time. The programming of the BTL depends on the baudrate and on external physical delay times.
Semiconductor Group 6-64 1997-08-01 On-Chip Peripheral Components C505C Only Intelligent Memory The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of control and status bits. After the initial configuration, the Intelligent Memory can handle the reception and transmission of data without further microcontroller actions. Organization of Registers and Message Objects All registers and message objects of the CAN controller are located in the CAN address area of 256 bytes, which is mapped into the external data memory area of the C505C.
Semiconductor Group 6-65 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.2 CAN Register Description
Each CAN register is described with its bit symbols, address, reset value, and a functional description of each bit or bitfield. Also the access type is indicated for each bit or bitfield : r : for read access w : for write access rw : for read and write access After reset the CAN registers either contain a defined reset value, keep their previous contents (UUH ), or are undefined (XXH ). Locations that are unchanged (UUH ) after reset, of course are undefined (XXH ) after a power-on reset operation. The reset values are defined either in hex (with index H ) or binary (with index B) expressions. The notation “n“ in the address definition of the message object registers defines the number of the related message object (n=1-15).
6.4.2.1 General Registers
The general registers of the CAN controller are located at the external data memory location F700H to F70FH . The registers of this general register block is shown in figure 6-31. The address mapping of the 16 registers/bytes of a message object is shown in figure 6-32.
Semiconductor Group 6-66 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-31 CAN Module Address Map MCD02737 Message Register High Lower Mask of Last Lower Mask of Last Message Register Low Upper Mask of Last Message Register High Upper Mask of Last Message Register Low Lower Global Mask Long Register High Lower Global Mask Long Register Low Upper Global Mask Long Register High Upper Global Mask Long Register Low Global Mask Short Register High Global Mask Short Register Low Bit Timing Register Hihg Bit Timing Register Low Reserved Interrupt Register Status Register Control RegisterGeneral RegistersHF700 F710 H F720 H F730 H F740 H F750 H F760 H F770 H F780 H F790 H F7A0 H F7B0 H F7C0 H F7D0 H F7E0 H F7F0 H HF70F HF70E HF70D HF70C HF70B HF70A HF709 HF708 HF707 HF706 HF705 HF704 HF703 HF702 HF701 F700 H CAN Register Address Area General Registers Message Object 1 Message Object 2 Message Object 3 Message Object 4 Message Object 5 Message Object 6 Message Object 7 Message Object 8 Message Object 9 Message Object 10 Message Object 11 Message Object 12 Message Object 13 Message Object 14 Message Object 15
Semiconductor Group 6-67 1997-08-01 On-Chip Peripheral Components C505C Only CAN Control Register CR (Address F700H ) Reset Value : 01H Bit Function TEST Test mode Make sure that bit 7 is cleared when writing to the control register, as this bit controls a special test mode, that is used for production testing. During normal operation, however, this test mode may lead to undesired behaviour of the device. CCE Configuration change enable Allows or inhibits microcontroller access to the bit timing register. EIE Error interrupt enable Enables or disables interrupt generation on a change of bit BOFF or EWRN in the status register. SIE Status change interrupt enable Enables or disables interrupt generation when a message transfer (reception or transmission) is successfully completed or a CAN bus error is detected (and registered in the status register). IE Interrupt enable Enables or disables interrupt generation from the CAN module to the interrupt controller of the C505C. Does not affect status updates. Additionally, bit ECAN in SFR IEN1 and bit EAL in SFR IEN0 must be set when a CAN controller interrupt should be generated. INIT Initialization Starts the initialization of the CAN controller, when set. MSB LSB CRTEST CCE 0 0 EIE SIE IE INIT 76543210 Bit No. rw rw r r rw rw rw rw F700H
Semiconductor Group 6-68 1997-08-01 On-Chip Peripheral Components C505C Only CAN Status Register SR (Address F701H ) Reset Value : XXH Bit Function BOFF Busoff status Indicates when the CAN controller is in busoff state (see EML). EWRN Error warning status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96. RXOK Received message successfully Indicates that a message has been received successfully, since this bit was last reset by the CPU (the CAN controller does not reset this bit!). TXOK Transmitted message successfully Indicates that a message has been transmitted successfully (error free and acknowledged by at least one other node), since this bit was last reset by the CPU (the CAN controller does not reset this bit!). MSB LSB SRBOFF EWRN – RXOK TXOK 76543210 Bit No. r r r rw rw rw LECF701H
Semiconductor Group 6-69 1997-08-01 On-Chip Peripheral Components C505C Only Note :Reading the SR when an interrupt is pending, resets the pending interrupt request. (please see section 6.4.6 for further details about CAN interrupt handling. LEC Last error code This field holds a code which indicates the type of the last error occurred on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared. Code “7” is unused and may be written by the microcontroller to check for updates. Bit Function LEC2-0 Error Description 0 0 0 No Error – 0 0 1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0 1 0 Form Error A fixed format part of a received frame has the wrong format 0 1 1 Ack Error The message this CAN controller transmitted was not acknowledged by another node. 1 0 0 Bit1 Error During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (“1”), but the monitored bus value was dominant. 1 0 1 Bit0 Error During the transmission of a message (or acknowledge bit, active error flag, or overload flag), the device wanted to send a dominant level (“0”), but the monitored bus value was recessive. During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the microcontroller to monitor the proceeding of the busoff recovery sequence (indicating the bus is not stuck at dominant or continously disturbed). 1 1 0 CRC Error The CRC check sum was incorrect in the message received.
Semiconductor Group 6-70 1997-08-01 On-Chip Peripheral Components C505C Only CAN Interrupt Register IR (Address F702H ) Reset Value : XXH See also section 6.4.6 with table 6-7 for further details about the CAN controller interrupt handling. Bit Function INTID Interrupt identifier This number indicates the cause of the interrupt. When no interrupt is pending, the value will be “00”. MSB LSB IR 76543210 Bit No. r INTIDF702H
Semiconductor Group 6-71 1997-08-01 On-Chip Peripheral Components C505C Only CAN Bit Timing Register Low BTR0 (Address F704H ) Reset Value : UUH Note :This register can only be written, if the configuration change enable bit (CCE) is set. CAN Bit Timing Register High BTR1 (Address F705H ) Reset Value : 0UUUUUUUB Note :This register can only be written, if the configuration change enable bit (CCE) is set. Bit Function SJW (Re)Synchronization jump width Adjust the bit time by (SJW+1) time quanta for resynchronization. BRP Baud rate prescaler For generating the bit time quanta the oscillator frequency is divided by (BRP+1). Bit Function TSEG2 Time segment after sample point There are (TSEG2+1) time quanta after the sample point. Valid values for TSEG2 are “1...7”. TSEG1 Time segment before sample point There are (TSEG1+1) time quanta before the sample point. Valid values for TSEG1 are “2...15”. MSB LSB BTR0 76543210 Bit No. rw BRPSJW rw F704H MSB LSB BTR1 76543210 Bit No. r TSEG10 rw TSEG2 rw F705H
Semiconductor Group 6-72 1997-08-01 On-Chip Peripheral Components C505C Only Mask Registers Messages can use standard or extended identifiers. Incoming frames are masked with their appropriate global masks. Bit IDE of the incoming message determines, if the standard 11-bit mask in global mask short is to be used, or the 29-bit extended mask in global mask long. Bits holding a “0” mean “don’t care”, ie. do not compare the message’s identifier in the respective bit position. The last message object (15) has an additional individually programmable acceptance mask (mask of last message) for the complete arbitration field. This allows classes of messages to be received in this object by masking some bits of the identifier. Note :The mask of last message is ANDed with the global mask that corresponds to the incoming message. C AN Global Mask Short Register Low GMS0 (Address F706H ) Reset Value : UU H CAN Global Mask Short Register High GMS1 (Address F707H ) Reset Value : UUU11111B Bit Function ID28-18 Identifier (11-bit) Mask to filter incoming messages with standard identifier. MSB LSB GMS1 76543210 Bit No. ID20-18 r w rrrrr 11111 GMS0 rw ID28-21F706H F707H
Semiconductor Group 6-73 1997-08-01 On-Chip Peripheral Components C505C Only CAN Upper Global Mask Long Register Low UGML0 (Addr. F708H ) Reset Value : UU H CAN Upper Global Mask Long Register High UGML1 (Addr. F709H ) Reset Value : UU H CAN Lower Global Mask Long Register Low LGML0 (Addr. F70AH ) Reset Value : UU H CAN Lower Global Mask Long Register High LGML1 (Addr. F70BH ) Reset Val. UUUUU000B Bit Function ID28-0 Identifier (29-bit) Mask to filter incoming messages with extended identifier. MSB LSB LGML1 76543210 Bit No. ID4-0 rw rrr 000 UGML0 rw ID28-21 UGML1 rw ID20-13 LGML0 rw ID12-5 F708H F709H F70A H F70B H
Semiconductor Group 6-74 1997-08-01 On-Chip Peripheral Components C505C Only CAN Upper Mask of Last Message Register Low UMLM0 (Addr. F70CH ) Reset Value : UUH CAN Upper Mask of Last Message Register High UMLM1 (Addr. F70DH ) Reset Value : UUH CAN Lower Mask of Last Message Register Low LMLM0 (Addr. F70EH ) Reset Value : UUH CAN Lower Mask of Last Message Reg. High LMLM1 (Addr. F70FH ) Reset Val.: UUUUU000B Bit Function ID28-0 Identifier (29-bit) Mask to filter the last incoming message (no. 15) with standard or extended identifier (as configured). MSB LSB LMLM1 76543210 Bit No. ID4-0 rw rrr 000 UMLM0 rw ID28-21 UMLM1 rw ID17-13 LMLM0 rw ID12-5 ID20-18 rw F70C H F70D H F70E H F70FH
Semiconductor Group 6-75 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.2.2 The Message Object Registers / Data Bytes
The message object is the primary means of communication between microcontroller and CAN controller. Each of the 15 message objects uses 15 consecutive bytes (see figure 6-32) and starts at an address that is a multiple of 16 (message object n base address; N = 1 to FH ). Note :All message objects must be initialized by the C505C, even those which are not going to be used, before clearing the INIT bit. Figure 6-32 Message Object Address Map Message Control Reg. Low Message Control Reg. High Upper Arbitration Reg. Low Upper Arbitration Reg. High Lower Arbitration Reg. Low Message Configuration Reg. Data Byte 0 Reserved +10 +11 +12 +13 +14 +15 Lower Arbitration Reg. High Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 )Figure 6-31(see also Message Object n Base Address + Offset Message Object n Register Address = Register Address Calculation: Message Object n Base Address(n=1 to F Message Object n H H H H H H F E D C B A
1 F710 H
Semiconductor Group 6-76 1997-08-01 On-Chip Peripheral Components C505C Only Each element of the message control register is made of two complementary bits. This special mechanism allows to selectively set or reset specific elements (leaving others unchanged) without requiring read-modify-write cycles. None of these elements will be affected by reset. Table 6-6 below shows how to use and interpret these 2-bit fields. CAN Message Control Register Low MCR0 (Address F7n0H ) Reset Value : UU H CAN Message Control Register High MCR1 (Address F7n1H ) Reset Value : UUH Table 6-6 : Set/Reset Bits Value of the 2-bit Field Function on Write Meaning on Read 00 reserved reserved
01 Reset element Element is reset
10 Set element Element is set
11 Leave element unchanged reserved
Indicates, if the corresponding message object is valid or not. The CAN controller only operates on valid objects. Message objects can be tagged invalid, while they are changed, or if they are not used at all. TXIE Transmit interrupt enable Defines, if bit INTPND is set after successful transmission of a frame. RXIE Receive interrupt enable Defines, if bit INTPND is set after successful reception of a frame. INTPND Interrupt pending Indicates, if this message object has generated an interrupt request (see TXIE and RXIE), since this bit was last reset by the microcontroller, or not. MSB LSB MCR0 76543210 Bit No. rw rw rw rw INTPNDMSGVAL TXIE RXIE MCR1 rw rw rw rw NEWDATRMTPND TXRQ MSGLST CPUUPD F7n0H F7n1H
Semiconductor Group 6-77 1997-08-01 On-Chip Peripheral Components C505C Only 1) In message object 15 (last message) these bits are hardwired to “0” (inactive) in order to prevent transmission of message 15. 2) When the CAN controller writes new data into the message object, unused message bytes will be overwritten by non specified values. Usually the microcontroller will clear this bit before working on the data, and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message. For transmit-objects the microcontroller will set this bit along with clearing bit CPUUPD. This will ensure that, if the message is actually being transmitted during the time the message was being updated by the microcontroller, the CAN controller will not reset bit TXRQ. In this way bit TXRQ is only reset once the actual data has been transferred. 3) When the microcontroller requests the transmission of a receive-object, a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame. This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted, if bit NEWDAT has not been set. If there are several valid message objects with pending transmission request, the message with the lowest message number is transmitted first. RMTPND Remote pending (used for transmit-objects) Indicates that the transmission of this message object has been requested by a remote node, but the data has not yet been transmitted. When RMTPND is set, the CAN controller also sets TXRQ. RMTPND and TXRQ are cleared, when the message object has been successfully transmitted. TXRQ Transmit request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done. TXRQ can be disabled by CPUUPD. 1) 3) MSGLST CPUUPD Message lost (this bit applies to receive-objects only!) Indicates that the CAN controller has stored a new message into this object, while NEWDAT was still set, ie. the previously stored message is lost. CPU update (this bit applies to transmit -objects only!) Indicates that the corresponding message object may not be transmitted now. The microcontroller sets this bit in order to inhibit the transmission of a message that is currently updated, or to control the automatic response to remote requests. NEWDAT New data Indicates, if new data has been written into the data portion of this message object by microcontroller (transmit-objects) or CAN controller (receive-objects) since this bit was last reset, or not. Bit Function
Semiconductor Group 6-78 1997-08-01 On-Chip Peripheral Components C505C Only Arbitration Registers The arbitration registers are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages. A received message is stored into the valid message object with a matching identifier and DIR=”0” (data frame) or DIR=”1” (remote frame). Extended frames can be stored only in message objects with XTD=”1”, standard frames only in message objects with XTD=”0”. For matching, the corresponding global mask has to be considered (in case of message object 15 also the mask of last message). If a received message (data frame or remote frame) matches with more than one valid message object, it is stored into that with the lowest message number. When the CAN controller stores a data frame, not only the data bytes, but the whole identifier and the data length code are stored into the corresponding message object (standard identifiers have bits ID17...0 filled with “0”). This is implemented to keep the data bytes connected with the identifier, even if arbitration mask registers are used. When the CAN controller stores a remote frame, only the data length code is stored into the corresponding message object. The identifier and the data bytes remain unchanged. There must not be more than one valid message object with a particular identifier at any time. If some bits are masked by the global mask registers (ie. “don’t care”), then the identifiers of the valid message objects must differ in the remaining bits which are used for acceptance filtering. If a received data frame is stored into a message object, the identifier of this message object is updated. If some of the identifier bits are set to “don’t care” by the corresponding mask register, these bits may be changed in the message object. If a remote frame is received, the identifier in transmit-object remain unchanged, except for the last message object (which cannot start a transmission). Here, the identifier bits corresponding to the “don’t care” bits of the last message object’s mask may be overwritten by the incoming message.
Semiconductor Group 6-79 1997-08-01 On-Chip Peripheral Components C505C Only CAN Upper Arbitration Register Low UAR0 (Address F7n2H ) Reset Value : UU H CAN Upper Arbitration Register High UAR1 (Address F7n3H ) Reset Value : UU H CAN Lower Arbitration Register Low LAR0 (Address F7n4H ) Reset Value : UU H CAN Lower Arbitration Register High LAR1 (Address F7n5H ) Reset Value : UUUUU000B Bit Function ID28-0 Identifier (29-bit) For standard identifiers bits ID17...0 are “don’t care”. MSB LSB LAR1 76543210 Bit No. ID4-0 rw rrr 000 UAR0 rw ID28-21 UAR1 rw ID17-13 LAR0 rw ID12-5 ID20-18 rw F7n2H F7n3H F7n4H F7n5H
Semiconductor Group 6-80 1997-08-01 On-Chip Peripheral Components C505C Only Message Configuration and Data The following fields hold a description of the message within this object. The data field occupies the following 8 byte positions after the message configuration register. Note: There is no “don’t care” option for bits XTD and DIR. So incoming frames can only match with corresponding message objects, either standard (XTD=0) or extended (XTD=1). Data frames only match with receive-objects, remote frames only match with transmit-objects. When the CAN controller stores a data frame, it will write all the eight data bytes into a message object. If the data length code was less than 8, the remaining bytes of the message object will be overwritten by non specified values. CAN Message Configuration MCFG Register (Address F7n6H ) Reset Value : UUUUUU00B Bit Function DLC Data length code Valid values for the data length are 0...8. DIR Message direction DIR=”1”: transmit. On TXRQ, the respective message object is transmitted. On reception of a remote frame with matching identifier, the TXRQ and RMTPND bits of this message object are set. DIR=”0”: receive. On TXRQ, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, that message is stored in this message object. XTD Extended identifier Indicates, if this message object will use an extended 29-bit identifier or a standard 11-bit identifier MSB LSB MCFG00DIR XTD 76543210 Bit No. rw rw rw r r DLCF7n6H
Semiconductor Group 6-81 1997-08-01 On-Chip Peripheral Components C505C Only CAN Data Bytes DB0-DB7 (Addresses F7n7H -F7nEH ) Reset Value : XXH Message data for message object 15 (last message) will be written into a two-message-alternating buffer to avoid the loss of a message, if a second message has been received, before the microcontroller has read the first one.
6.4.3 Handling of Message Objects
The following diagrams (figures 6-33 to 6-38) summarize the actions that have to be taken in order to transmit and receive messages over the CAN bus. The actions taken by the CAN controller are described as well as the actions that have to be taken by the microcontroller (i.e. the servicing program). MSB LSB DB0-7 76543210 Bit No. rw rw rw rw rw rw rw rw F7n7H - F7nE H
Semiconductor Group 6-82 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-33 CAN Controller Handling of Message Objects with Direction = transmit MCD02739 bus free TXRQ = 1 CPUUPD = 0 received remote frame with same identifier as this message object into buffer load message NEWDAT: = 1 send message transmission successful TXRQ: = 1 RMTPND: = 1 RMTPND: = 1 TXRQ: = 1 TXIE =1 INTPND: = 1 1:set 0:reset RXIE = 1 INTPND: = 1 NoYes NEWDAT = 1 No No No No No No Yes Yes Yes Yes Yes Yes
Semiconductor Group 6-83 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-34 CAN Controller Handling of Message Objects with Direction = receive MCD02740 bus idle TXRQ = 1 CPUUPD = 0 received frame with same identifier as this message object control into buffer load identifier and NEWDAT: = 0 send remote frame NEWDAT = 1 MSGLST: = 1 store message NEWDAT: = 1 TXRQ: = 0 RMTPND: = 0 RMTPND: = 0 TXRQ: = 0 TXIE = 1 INTPND: = 1 1:set 0:reset RXIE = 1 INTPND: = 1 Yes No transmission ?Yes Yes Yes Yes Yes Yes No No No No No No successful
Semiconductor Group 6-84 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-35 Microcontroller Handling of Message Objects with Direction = transmit MCD02741 (all bits undefined) TXIE: = (application specific) RXIE: = (application specific) INTPND: = 0 RMTPND: = 0 TXRQ: = 0 CPUUPD: = 1 Identifier: = (application specific) NEWDAT: = 0 Direction: = transmit DLC: = (application specific) MSGVAL: = 1 XTD: = (application specific) CPUUPD: = 1 NEWDAT: = 1 write/calculate message contents CPUUPD: = 0 want to send TXRQ: = 1 update message Yes Yes No No Power Up Initialization Update: Start Update Update: End 0:reset 1:set
Semiconductor Group 6-85 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-36 Microcontroller Handling of Message Objects with Direction = receive MCD02742 (all bits undefined) TXIE: = (application specific) RXIE: = (application specific) INTPND: = 0 RMTPND: = 0 TXRQ: = 0 MSGLST: = 0 Identifier: = (application specific) NEWDAT: = 0 Direction: = receive DLC: = (value of DLC in transmitter) MSGVAL: = 1 XTD: = (application specific) Power Up Initialization 0:reset 1:set NEWDAT: = 0 process message contents No Yes request updateNo TXRQ: = 1 Restart Process Yes Process:Start Process Process:End NEWDAT = 1
Semiconductor Group 6-86 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-37 Microcontroller Handling of the Last Message Object MCD02743 (all bits undefined) RXIE: = (application specific) INTPND: = 0 RMTPND: = 0 MSGLST: = 0 Identifier: = (application specific) NEWDAT: = 0 Direction: = receive DLC: = (value of DLC in transmitter) MSGVAL: = 1 XTD: = (application specific) Power Up Initialization 0:reset 1:set NEWDAT: = 0 process message contents No YesNEWDAT = 1 Restart Process Process:Start Process Process:End
Semiconductor Group 6-87 1997-08-01 On-Chip Peripheral Components C505C Only Figure 6-38 Microcontroller Handling of the Last Message Object’s Alternating Buffer MCD02744 Buffer 1 = released Buffer 2 = released MCU access to Buffer 2 Reset MCU access to Buffer 1 Buffer 2 = released Buffer 1 = allocatedBuffer 1 = released Buffer 2 = allocated MCU access to Buffer 2 MCU allocates Buffer 2 into Buffer 1 Store received Message MCU access to Buffer 2 Buffer 2 = allocated Buffer 1 = allocated Buffer 1 = allocated Buffer 2 = allocated MCU access to Buffer 1 MCU releases Buffer 1MCU releases Buffer 2 Message into Buffer 1 Store received Store received into Buffer 2 Message Store received Buffer 1 message into MSGLST is set MSGLST is set message into Buffer 2 Store receivedMCU releases Buffer 1 MCU releases Buffer 2 Allocated:NEWDAT = 1 OR RMTPND = 1 Released:NEWDAT = 0 AND RMTPND = 0
Semiconductor Group 6-88 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.4 Initialization and Reset
The CAN controller is reset by a hardware reset, the oscillator watchdog reset or by a watchdog timer reset of the C505C. A reset operation of the CAN controller performs the following actions : – sets the TXDC output to “1” (recessive) – clears the error counters – resets the busoff state – switches the control register’s low byte to 01H – leaves the control register’s high byte and the interrupt register undefined – does not change the other registers including the message objects (notified as UUUU) – selects the prescaler for the CAN controller clock using the bit CMOD in SYSCON register. The first hardware reset after power-on leaves the unchanged registers in an undefined state, of course. The value 01H in the control register’s low byte prepares for software initialization. Software Initialization The very first step of the initialization is the CAN controller input clock selection. A ÷ 2 prescaler is enabled by default after reset (figure 6-39). Setting bit CMOD (SYSCON.3) disables the prescaler. The purpose of the prescaler selection is: i) to ensure that the CAN controller is operable when fosc is over 10 MHz (bit CMOD =0) ii) to achieve the maximum CAN baudrate of 1 Mbaud when fosc is 8 MHz (bit CMOD=1) Figure 6-39 CAN controller input clock selection Note : The switch configuration shows the reset state of bit CMOD. Frequency (MHz) CMOD (SYSCON.3) BRP (BTR0.0- CAN baudrate (Mbaud/sec) fOSC fCAN 8 8 1 000000 B 1 8 4 0 000000 B 0.5 16 8 0 000000 B 1 SYSCON.3 (CMOD) MCS03296 fOSC Full-CAN Module CANf Condition: CMOD = 0, when > 10 MHzOSCf
Semiconductor Group 6-89 1997-08-01 On-Chip Peripheral Components C505C Only Special Function Register SYSCON (Address B1H ) Reset Value : XX100X01 B The software Initialization is enabled by setting bit INIT in the control register. This can be done by the microcontroller via software, or automatically by the CAN controller on a hardware reset, or if the EML switches to busoff state. While INIT is set – all message transfer from and to the CAN bus is stopped – the CAN bus output TXDC is “1” (recessive) – the control bits NEWDAT and RMTPND of the last message object are reset – the counters of the EML are left unchanged. Setting bit CCE in addition, allows to change the configuration in the bit timing register. For initialization of the CAN Controller, the following actions are required: – configure the bit timing register (CCE required) – set the Global Mask Registers – initialize each message object. If a message object is not needed, it is sufficient to clear its message valid bit (MSGVAL), ie. to define it as not valid. Otherwise, the whole message object has to be initialized. After the initialization sequence has been completed, the microcontroller clears the INIT bit. Now the BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (ie. bus idle) before it can take part in bus activities and start message transfers. Bit Function CMOD Prescaler selection for CAN controller Control bit for CAN controller input clock selection. The time quantum (tq) of the CAN controller timing is affected by this (and hecne the baudrate). CMOD = 0 : The ÷ 2 prescaler is enabled (reset value). CMOD = 1 : The ÷ 2 prescaler is disabled. This bit must be cleared when f osc is over 10 MHz. 76543210 EALE RMAP CMODB1H SYSCON Bit No. MSB LSB – XMAP1–– XMAP0 The functions of the shaded bits are not described here.
Semiconductor Group 6-90 1997-08-01 On-Chip Peripheral Components C505C Only The initialization of the message objects is independent of the state of bit INIT and can be done on the fly, the message objects should all be configured to particular identifiers or set to not valid before the BSP starts the message transfer, however. To change the configuration of a message object during normal operation, the microcontroller first clears bit MSGVAL, which defines it as not valid. When the configuration is completed, MSGVAL is set again. Note that the busoff recovery sequence cannot be shortened by setting or resetting INIT. If the device goes busoff, it will set INIT of its own accord, stopping all bus activities. Once INIT has been cleared by the microcontroller, the device will then wait for 129 occurrences of Bus Idle before resuming normal operation. At the end of the busoff recovery sequence, the error management counters will be reset. During the waiting time after the resetting of INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to the control register, enabling the microcontroller to check up whether the CAN bus is stuck at dominant or continously disturbed and to monitor the proceeding of the busoff recovery sequence.
6.4.5 Configuration of the Bit Timing
According to the CAN specification, a bit time is subdivided into four segments (see figure 6-40). Each segment is a multiple of the time quantum tq. The synchronization segment (Sync-Seg) is always one tq long. The propagation time segment and the phase buffer segment1 (combined to Tseg1) defines the time before the sample point, while phase buffer segment2 (Tseg2) defines the time after the sample point. The length of these segments is programmable (except Sync-Seg). Note : For exact definition of these segments please refer to the CAN specification. Figure 6-40 Bit Timing Definition MCT02745 Sync- Seg Sync- SegTSeg1 TSeg2 tq() Sample Point Transmit Point
1 Bit Time
Semiconductor Group 6-91 1997-08-01 On-Chip Peripheral Components C505C Only The bit time is determined by the C505C clock period CLP (see AC characteristics), the Baud Rate Prescaler, and the number of time quanta per bit: bit time = t Sync-Seg + tTSeg1 + tTSeg2 tSync-Seg = 1 · tq tTSeg1 = ( TSEG1 + 1 ) · tq (= min. 4 · tq) tTSeg2 = ( TSEG2 + 1 ) · tq (= min. 3 · tq) tq = (BRP + 1) · 2(1 - CMOD) · CLP TSEG1, TSEG2, and BRP are the programmed numerical values from the respective fields of the Bit Timing Register and the bit CMOD in the SYSCON register (bit 3).
Semiconductor Group 6-92 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.5.1 Hard Synchronization and Resynchronization
To compensate phase shifts between clock oscillators of different CAN controllers, any CAN controller has to synchronize on any edge from recessive to dominant bus level, if the edge lies between a sample point and the next synchronization segment, and on any other edge, if it itself does not send a dominant level. If the hard synchronization is enabled (at the start of frame), the bit time is restarted at the synchronization segment, otherwise, the resynchronization jump width (SJW) defines the maximum number of time quanta a bit time may be shortened or lengthened by one resynchronization. The current bit time is adjusted by t SJW = ( SJW + 1 ) · tq Note: SJW is the programmed numerical value from the respective field of the bit timing register.
6.4.5.2 Calculation of the Bit Time
The programming of the bit time according to the CAN specification depends on the desired baudrate, the CLP microcontroller system clock rate and on the external physical delay times of the bus driver, of the bus line and of the input comparator. These delay times are summarised in the propagation time segment t Prop, where tProp is two times the maximum of the sum of physical bus delay, the input comparator delay, and the output driver delay rounded up to the nearest multiple of tq. To fulfill the requirements of the CAN specification, the following conditions must be met: tTSeg2 ‡ 3 · tq = Information Processing Time tTSeg2 ‡ tSJW tTSeg1 ‡ 4 · tq tTSeg1 ‡ tSJW + tProp Note: In order to achieve correct operation according to the CAN protocol the total bit time should be at least 8 tq, i.e. tTSeg1 + tTSeg2 ‡ 7 tq. So, to operate with a baudrate of 1 MBit/sec, the CLP frequency has to be at least 8 MHz (with bit CMOD = 1). The maximum tolerance for CLP depends on the phase buffer segment1 (PB1), the phase buffer segment2 (PB2), and the resynchronization jump width (SJW): df £ AND df £ min PB1 PB2 ,() tSJW
Semiconductor Group 6-93 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.6 CAN Interrupt Handling
The CAN controller has one interrupt output, which is connected with the interrupt controller unit in the C505C. This interrupt can be enabled/disabled using bit ECAN of SFR IEN1 (further details about interrupt vector, priority, etc. see chapter 7). Additionally, three bits in the CAN control register (F701H ) are used to enable specific interrupt sources for interrupt generation. Since an interrupt request of the CAN-Module can be generated due to different conditions, the appropriate CAN interrupt status register must be read in the service routine to determine the cause of the interrupt request. The interrupt identifier INTID (a number) in the interrupt register indicates the cause of an interrupt. When no interrupt is pending, the identifier will have the value “00”. If the value in INTID is not “00”, then there is an interrupt pending. If bit IE in the control register is set, also the interrupt line is activated. The interrupt line remains active until either INTID gets “00” (ie. the interrupt requester has been serviced) or until IE is reset (ie. interrupts are disabled). The interrupt with the lowest number has the highest priority. If a higher priority interrupt (lower number) occurs before the current interrupt is processed, INTID is updated and the new interrupt overrides the last one. Table 6-7 below lists the valid values for INTID and their corresponding interrupt sources. Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to “00” (idle state). Table 6-7 : Interrupt IDs INTID Cause of the Interrupt
00 Interrupt idle
There is no interrupt request pending.
01 Status change interrupt
The CAN controller has updated (not necessarily changed) the status register. This can refer to a change of the error status of the CAN controller (EIE is set and BOFF or EWRN change) or to a CAN transfer incident (SIE must be set), like reception or transmission of a message (RXOK or TXOK is set) or the occurrence of a CAN bus error (LEC is updated). The microcontroller may clear RXOK, TXOK, and LEC, however, writing to the status partition of the control register can never generate or reset an interrupt. To update the INTID value the status partition of the control register must be read.
02 Message 15 interrupt
Bit INTPND in the message control register of message object 15 (last message) has been set. The last message object has the highest interrupt priority of all message objects. ( 2+N ) Message N interrupt: Bit INTPND in the message control register of message object ‘N’ has been set (N = 1...14). Note that a message interrupt code is only displayed, if there is no other interrupt request with a higher priority.
Semiconductor Group 6-94 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.7 CAN Controller in Power Saving Modes
In the idle mode of the C505C the CAN controller is fully operable. When a CAN controller interrupt becomes active and the CAN controller interrupt is enabled, the C505C restarts, returns to normal operation mode and starts executing the CAN controller interrupt routine. Slow Down Mode When the slow down mode is enabled the CAN controller is clocked with the reduced system clock rate (1/32 of the nominal clock rate). Therefore, also the CAN bit timing in slow down mode is reduced to 1/32 of the bit timing in normal mode. The slow down mode can be also combined with idle mode. Power Down Mode If the C505C enters software Power Down Mode, the system clock signal is turned off which will stop the operation of the CAN-Module. Any message transfer is interrupted. In order to ensure that the CAN controller is not stopped while sending a dominant level (“0”) on the CAN bus, the microcontroller should set bit INIT in the Control Register prior to entering Power Down Mode. The microcontroller can check, if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register. After returning from Power Down Mode the CAN-Module has to be reconfigured.
Semiconductor Group 6-95 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.8 Configuration Examples of a Transmission Object
The microcontroller wishes to configure an object for transmission. It wants to allow automatic transmission in response to remote frames but does not wish to receive interrupts for this object. Initialization: The identifier and direction are set up. Message Control Register CPUUPD is initially set, as the data bytes for the message have not yet been initialized. Configuration after remote frame received. Message Control Register After updating the message the microcontroller should clear CPUUPD and set NEWDAT. If the microcontroller wants to transmit the message it should also set TXRQ, which should otherwise be left alone. MSB LSB MCR0 76543210 Bit No. INTPNDMSGVAL TXIE RXIE MCR1 NEWDATRMTPND TXRQ CPUUPD 00 0 0 1 111 10 1 0 1 010 MSB LSB MCR0 76543210 Bit No. INTPNDMSGVAL TXIE RXIE MCR1 NEWDATRMTPND TXRQ CPUUPD 11 0 0 1 100 10 1 0 1 010
Semiconductor Group 6-96 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.9 Configuration Examples of a Reception Object
The microcontroller wishes to configure an object for reception. It wishes to receive an interrupt each time new data comes in. From time to time the microcontroller sends a remote request to trigger the sending of this data from a remote node. Initialization: The identifier and direction are set up. Message Control Register Configuration after reception of data. Message Control Register To process the message the microcontroller should clear IntPnd, clear NewDat, process the data, and check that NewDat is still clear. If not, it should repeat the process again. To send a remote frame to request the data, the microcontroller simply needs to set the TXRQ bit. This bit will be cleared by the CAN controller, once the remote frame has been sent or if the data is received before the CAN controller could transmit the remote frame. MSB LSB MCR0 76543210 Bit No. INTPNDMSGVAL TXIE RXIE MCR1 NEWDATRMTPND TXRQ MSGLST 00 1 0 1 011 10 0 0 1 110 MSB LSB MCR0 76543210 Bit No. INTPNDMSGVAL TXIE RXIE MCR1 NEWDATRMTPND TXRQ MSGLST 00 1 1 0 011 10 0 1 0 110
Semiconductor Group 6-97 1997-08-01 On-Chip Peripheral Components C505C Only
6.4.10 The CAN Application Interface
The on-chip CAN controller of the C505C does not incorporate the physical layer that connects to the CAN bus. This must be provided externally. The module’s CAN controller is connected to this physical layer (ie. the CAN bus) via two signals: A logic low level (“0”) is interpreted as the dominant CAN bus level, a logic high level (“1”) is interpreted as the recessive CAN bus level. Figure 6-41 Connection to the CAN Bus CAN Signal Function P4.1 / RXDC Receive data from the physical layer of the CAN bus. P4.0 / TXDC Transmit data to the physical layer of the CAN bus. P4.0 / TXDC P4.1 / RXDC C505C CAN Interface Physical Layer CAN Bus MCS03297
Semiconductor Group 6-98 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.5 A/D Converter
The C505 includes a high performance / high speed 8-bit A/D converter with 8 analog input channels. It operates with a successive approximation technique and provides the following features: – 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs – 8-bit resolution – Internal start-of-conversion trigger – Interrupt request generation after each conversion – Single or continuous conversion mode The externally applied reference voltage range has to be held on a fixed value within the DC specifications (chapter 10). The main functional blocks of the A/D converter are shown in Figure 6-42
6.5.1 A/D Converter Operation
An internal start of an A/D conversion is triggered by a write-to-ADST instruction. The start procedure itself is independent of the value which is written to the ADST register. When single conversion mode is selected (bit ADM=0) only one A/D conversion is performed. In continuous mode (bit ADM=1), after completion of one A/D conversion a new A/D conversion is triggered automatically until the bit ADM (ADCON0.3) is reset. The busy flag, BSY (ADCON0.4) is automatically set when an A/D conversion is in progress. After completion of the conversion it is reset by hardware. This flag is read-only and a write has no effect. The interrupt request flag IADC (IRCON.0) is set when an A/D conversion is completed. The bits MX0 to MX2 of special function register ADCON0 are used for selection of the analog input channel. The bits MX0 to MX2 are represented in the register ADCON1 as well but in reality are present only once. Therefore, there are two methods of selecting an anlog input channel. If a new channel is selected in ADCON1, the change is automatically done in the corresponding bits MX0 to MX2 in ADCON0 and vice versa. The ADCON1 register is also used for selecting the required prescaler (bits 6 and 7) for achieving the proper clock input to the A/D converter.
Semiconductor Group 6-99 1997-08-01 On-Chip Peripheral Components C505 / C505C Figure 6-42 Block Diagram of the A/D Converter EAN7 EAN4EAN5EAN6 EAN3 EAN2 EAN1 EAN0 ADCL1 MX2 MX1 MX0 P1ANA (90 )H BD CLK BSY ADM MX2 MX1 MX0 ADCON0 (D8 )H MUX S&H Single / Continuous Mode Conversion Clock fOSC Port 1 LSB MSB ADST (DA ) ADDAT (D9 )HH Conversion Clock Input Clock ADCf INf AREFV AGNDV Start of conversion Shaded Bit locations are not used in ADC-functions. A / D Converter MCB03298 Internal Bus Internal Bus Write to ADST Prescaler ADCL0 ADCON1 (DC )H H EXEN2 IEN1 (B8 ) SWDT EX6 EX5 EX4 EX3 ECAN EADC EXF2 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC IRCON (C0 )H
Semiconductor Group 6-100 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.5.2 A/D Converter Registers
This section describes the bits/functions of the registers which are used by the A/D converter. Special Function Register ADDAT (Address D9H ) Reset Value : 00 H This register holds the result of the 8-bit conversion. The most significant bit of the 8-bit conversion result is bit 7 and the least significant bit is bit 0 of the ADDAT register. The data remains in ADDAT until it is overwritten by the next converted data. ADDAT can be read or written under software control. If the A/D converter of the C505 is not used, register ADDAT can be used as an additional general purpose register. Special Function Register ADST (Address DA H ) Reset Value : XX H This is the A/D conversion start register. Any write operation on the ADST register starts a new conversion process irrespective of the actual data written to this register. Read by the CPU returns unefined values. 76543210 D9 H ADDAT Bit No. MSB LSB 76543210 DA H ADST Bit No. MSB LSB
Semiconductor Group 6-101 1997-08-01 On-Chip Peripheral Components C505 / C505C Special Function Register ADCON0 (Address D8H ) Reset Value : 00X00000 B Special Function Register ADCON1 (Address DCH ) Reset Value : 01XXX000 B Bit Function BSY Busy flag This flag indicates whether a conversion is in progress (BSY = 1). The flag is set by hardware during an A/D conversion and cleared when the conversion is completed. ADM A/D conversion mode When set, a continuous A/D conversion is selected. If cleared during a running A/D conversion, the conversion is stopped after current conversion process is completed. MX2 - MX0 A/D converter input channel select bits Bits MX2-0 can be written or read either in ADCON0 or ADCON1. The channel selection done by writing to ADCON1(0) overwrites the selection in ADCON 0(1) when ADCON1(0) is written after ADCON0(1). The analog inputs are selected according to the following table : 76543210 – BSY ADM MX2 MX1 MX0D8 H ADCON0 ADCL1 MX2 MX1 MX0DC H ADCON1 Bit No. MSB LSB ADCL0 CLKBD –– – The shaded bits are not used for A/D converter control. MX2 MX1 MX0 Selected Analog Input 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2
Semiconductor Group 6-102 1997-08-01 On-Chip Peripheral Components C505 / C505C Note :Generally, before entering the software power-down mode, an A/D conversion in progress must be stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit or waiting for the A/D conversion interrupt. In continuous conversion mode, bit ADM must be cleared and the last A/D conversion must be terminated before entering the software power-down mode. A single A/D conversion is started by writing to SFR ADST with dummy data. A continuous conversion is started under the following conditions: – By setting bit ADM during a running single A/D conversion – By setting bit ADM when at least one A/D conversion has occured after the last reset operation. – By writing ADST with dummy data after bit ADM has been set before (if no A/D conversion has occured after the last reset operation). When bit ADM is reset by software in continuous conversion mode, any ongoing A/D conversion is stopped only after it is completed. In any case the A/D conversion is started with the next S1P1. Bit Function ADCL1 ADCL0 A/D converter clock prescaler selection ADCL1 and ADCL0 select the prescaler ratio for the A/D conversion clock f ADC . Depending on the clock rate fOSC of the C505, fADC must be adjusted in a way that the resulting conversion clock fADC is less than or equal to 1.25 MHz (see section 6.5.3). The prescaler ratio is selected according to the following table: – Reserved bits for future use.Read by CPU returns undefined values. ADCL1 ADCL0 Prescaler Ratio 0 0 0 1 1 0 1 1 divide by 4 divide by 8 (default after reset) divide by 16 divide by 32
Semiconductor Group 6-103 1997-08-01 On-Chip Peripheral Components C505 / C505C The A/D converter interrupt is controlled by bits which are located in the SFRs IEN1 and IRCON. Special Function Register IEN1 (Address B8H ) Reset Value : 00 H Special Function Register IRCON (Address C0H ) Reset Value : 00 H Bit Function EADC Enable A/D converter interrupt If EADC = 0, the A/D converter interrupt is disabled. IADC A/D converter interrupt request flag Set by hardware at the end of an A/D conversion. Must be cleared by software. C7H C6H C5H C4H C3H C2H C1H C0H IEX6 IEX5 IEX4 IEX3 0 IADCC0 H IRCONTF2EXF2 EXEN2 SWDT EX6 EX5B8H IEN1 Bit No. BF H MSB LSB EX4 EX3 ECAN EADC BE H BD H BC H BB H BA H B9H B8H The shaded bits are not used for A/D converter control.
Semiconductor Group 6-104 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.5.3 A/D Converter Clock Selection
The ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC ) and the input clock fIN (1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the XTAL pins via the ADC clock prescaler as shown in figure 6-43. The input clock is equal to fOSC . The conversion clock fADC is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. The table in figure 6-43 shows the prescaler ratio which must be selected by ADCL1 and ADCL0 for typical system clock rates. Up to 5 MHz system clock the prescaler ratio 4 is selected. Using a system clock greater than 5 and less than 10 MHz, the prescaler ratio of at least 8 must be selected. A prescaler ratio of 16 must be selected when using a system clock greater than 10 MHz. Figure 6-43 A/D Converter Clock Selection MCU System Clock Rate (f OSC ) fIN [MHz] Prescaler Ratio fADC [MHz] ADCL1 ADCL0 2 MHz 2 ‚ 4 0.5 0 0 5 MHz 5 ‚ 4 1.25 0 0 6 MHz 6 ‚ 8 0.75 0 1 10 MHz 10 ‚ 8 1.25 0 1 12 MHz 12 ‚ 16 0.75 1 0
16 MHz 16 ‚ 16 1 1 0
20 MHz 20 ‚ 16 1.25 1 0 MCS03299 fOSC MUX Clock Prescaler Conversion Clock Input Clock fADC INf ADCL1 A / D Converter Condition:ADC maxf < 1.25 MHz INf = fOSC = CLP ADCL0
Semiconductor Group 6-105 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.5.4 A/D Converter Timing
An A/D conversion is started by writing into special function register ADST. A write-to-ADST will start a new conversion even if a conversion is currently in progress. The conversion begins with the next machine cycle and the busy flag BSY will be set. The A/D conversion procedure is divided into three parts: – Sample phase (t S), used for sampling the analog input voltage. – Conversion phase (tCO ), used for the A/D conversion. – Write result phase (tWR ), used for writing the conversion result into the ADDAT register. The total A/D conversion time is defined by tADCC which is the sum of the two phase times tS and tCO . The duration of the three phases of an A/D conversion is specified by its specific timing parameter as shown in figure 6-44. Figure 6-44 A/D Conversion Timing Prescalar Ratio (=PS) tS = 2 x PS x tIN tCO = 8 x PS x tIN Conversion Time tADCC CPU Cycles n Time Ref. 32 64 x t IN 256 x t IN 320 x t IN 53 + 2 x tIN a) 16 32 x t IN 128 x t IN 160 x t IN 26 + 4 x tIN b) 8 16 x t IN 64 x t IN 80 x tIN 13 + 2 x tIN a) 4 8 x t IN 32 x t IN 40 x tIN 6 + 4 x tIN b) Start of an AD conversion into ADDAT Result is written tCO ADCCt tS WRt WRt INt= Write Result Phase Conversion PhaseSample Phase A/D Conversion Time Cycle Time ADCCt +St= tCO BSY Bit MCT03300 INtt = OSC
Semiconductor Group 6-107 1997-08-01 On-Chip Peripheral Components C505 / C505C Depending on the selected prescaler ratio (see figure 6-43), two different relationships between machine cycles and A/D conversion are possible. The A/D conversion is always started with the beginning of a processor cycle when it has been started by writing SFR ADST with dummy data. The ADST write operation may take one or two machine cycles. In figure 6-45, the instruction MOV ADST,#0 starts the A/D conversion (machine cycles X-1 and X). The total A/D conversion (sample and conversion phase) is finished with the end of the 10th ADC clock cycle after the A/D conversion start. The actual machine number of machine cycles needed follows the table in Figure 6-44. In the next machine cycle the conversion result is written into the ADDAT register and can be read in the same cycle by an instruction (e.g. MOV A,ADDAT). If continuous conversion is selected (bit ADM set), the next conversion is started with the beginning of the machine cycle which follows the write result cycle. The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset at the beginning of the write result cycle. If continuous conversion is selected, BSY is again set with the beginning of the machine cycle which follows the write result cycle. This means that in continuous conversion mode BSY is not set for a complete machine cycle. Therefore, in continuous conversion mode it is not recommended to poll the BSY bit using for e.g. the JNB instruction. The interrupt flag IADC is set at the end of the A/D conversion so that it is polled the first time in S1P2 of the machine cycle following the completion of conversion. If the A/D converter interrupt is enabled and the A/D converter interrupt is prioritized to be serviced immediately, the first instruction of the interrupt service routine will be executed in the fourth machine cycle which follows the write result cycle. The IADC bit must be reset by software. Depending on the application, typically there are three methods to handle the A/D conversion in the C505. – Software delay The machine cycles during an A/D conversion are counted and the program executes a software delay (e.g. NOPs) before reading the A/D conversion result in the write result cycle. The end of conversion is indicated by the IADC flag. – Polling BSY bit, The BSY bit is polled and the program waits until BSY=0. Attention : a polling JB which is two machine cycles long, possibly may not recognize the BSY=0 condition during the write result cycle in the continuous conversion mode. – A/D conversion interrupt After the start of an A/D conversion the A/D converter interrupt is enabled. The result of the A/D conversion is read in the interrupt service routine. If other C505 interrupts are enabled, the interrupt latency must be regarded. Therefore, this software method is the slowest method to get the result of an A/D conversion.
Semiconductor Group 6-108 1997-08-01 On-Chip Peripheral Components C505 / C505C Depending on the oscillator frequency of the C505 and the selected divider ratio of the conversion clock prescaler the total time of an A/D conversion is calculated according figure 6-44 and table 6-8. Figure 6-46 shows the minimum A/D conversion time in relation to the oscillator frequency fOSC . The minimum conversion time is 8 ms and can be achieved at fOSC of 10 MHz and with a prescalar ratio of 8 (or whenever fADC = 1.25 MHz). Table 6-8 A/D Conversion Time for Dedicated System Clock Rates Note : The prescaler ratios in table 6-8 are minimum values. Figure 6-46 Minimum A/D Conversion Time in Relation to System Clock fOSC [MHz] Prescaler Ratio PS fADC [MHz] Sample Time tS [ms] Total Conversion Time tADCC [ms] 2 MHz ‚ 4 .5 4 20 5 MHz ‚ 4 1.25 1.6 8 6 MHz ‚ 8 0.75 2.67 13.33 10 MHz ‚ 8 1.25 1.6 8 12 MHz ‚ 16 0.75 2.67 13.33
16 MHz ‚ 16 1 2 10
20 MHz ‚ 16 1.25 1.6 8 ADCCt 048 1 0 14 20 OSCf µ s tADCC min = 8 sµ MCT03302 2 6 12 16 MHz 4 8 16
Semiconductor Group 6-109 1997-08-01 On-Chip Peripheral Components C505 / C505C
6.5.5 A/D Converter Analog Input Selection
The analog inputs are located at port 1. The corresponding pins have a port structure, which allows to use them either as digital I/O pins or as analog inputs (see section 6.1.3.2). The analog input function of these digital/analog port lines are selected via the register P1ANA. This register lies in the mapped SFR area and can be accessed when bit RMAP in SFR SYSCON is set when writing to its address (90H ). If a specific bit location of P1ANA is set, the corresponding port line is configured as a digital input. With a 0 in the bit location the port line operates as analog port. Special Function Registers P1ANA (Address 90H ) Reset Value : FF H Bit Function EAN7 - EAN0 Enable analog port 1 inputs If EANx (x = 7-0) is cleared, port pin P1.x is enabled for operation as an analog input. If EANx is set, port pin P1.x is enabled for digital I/O function (default after reset). 76543210 90H P1ANA Bit No. MSB LSB EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0
Semiconductor Group 7-1 1997-08-01
7 Interrupt System
The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One interrupt can be generated by the CAN controller (C505C only) or by a software setting and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/INT0 , P3.3/ Additionally, the P1.5/AN5/T2EX can trigger an interrupt. The wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at either pin P3.2/INT0 or the pin P4.1/RXDC (please refer to chapter 9 for further details). The four external interrupts (INT3, INT4, INT5 and INT6) can also be generated by the timer 2 in capture/compare mode. This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers. Figure 7-1 to 7-3 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections.
Semiconductor Group 7-2 1997-08-01 Interrupt System C505 / C505C Figure 7-1 Interrupt Structure, Overview Part 1 EA ET0 IP1.1 IP0.1 IADC EADC EX0 IP1.0 IP0.0 IE0 IEN0.0 TCON.1 0003 H H0043 H000B H004B IEN1.0 IRCON.0 IEN1.1 IEN0.1 A / D Converter IEN0.7 Highest Priority Level Lowest Priority Level P o l l i n g S e q u e n c e MCB03303 IT0 TCON.5 TF0 TCON.0 P3.2 / INT0 Overflow Timer 0 Bit addressable Request flag is cleared by hardware >1IRCON.1 IE CR.1 CR.2 CR.3 SIE EIE Status Error INTPND TXIE RXIE Message Transmit Receive Message MCR0.0 / 1 MCR0.3 / 2 C505C Only ECAN SWI CAN Controller Interrupt Sources
Semiconductor Group 7-4 1997-08-01 Interrupt System C505 / C505C Figure 7-3 Interrupt Structure, Overview Part 3 EA ET2 IEX5 EX5 ES IP1.4 IP0.4 RI IEN0.4 SCON.0 0023 H H0063 H002B H006B IEN1.4 IRCON.4 IEN1.5 IEN0.5 IEN0.7 Highest Priority Level Lowest Priority Level P o l l i n g S e q u e n c e MCB03305 USART Overflow Timer 2 Bit addressable Request flag is cleared by hardware IP0.5IP1.5 IRCON.5 IEX6 AN2 / P1.2 / INT5 / CC2 EX6 TI SCON.1 CC3 INT6 / P1.3 / IRCON.7 EXF2 TF2 IRCON.6 >1 IEN1.7 EXEN2 AN5 / T2EX P1.5 /
Semiconductor Group 7-5 1997-08-01
7.1 Interrupt Registers
7.1.1 Interrupt Enable Registers
Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 and IEN1. Register IEN0 also contains the global disable bit (EA), which can be cleared to disable all interrupts at once. Generally, after reset all interrupt enable bits are set to 0. That means that the corresponding interrupts are disabled. The IEN0 register contains the general enable/disable flags of the external interrupts 0 and 1, the timer interrupts, and the USART interrupt. Special Function Register IEN0 (Address A8H ) Reset Value : 00 H Bit Function EA Enable/disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ET2 Timer 2 overflow / external reload interrupt enable. If ET2 = 0, the timer 2 interrupt is disabled. If ET2 = 1, the timer 2 interrupt is enabled. ES Serial channel (USART) interrupt enable If ES = 0, the serial channel interrupt 0 is disabled. If ES = 1, the serial channel interrupt 0 is enabled. ET1 Timer 1 overflow interrupt enable. If ET1 = 0, the timer 1 interrupt is disabled. If ET1 = 1, the timer 1 interrupt is enabled. EX1 External interrupt 1 enable. If EX1 = 0, the external interrupt 1 is disabled. If EX1 = 1, the external interrupt 1 is enabled. ET0 Timer 0 overflow interrupt enable. If ET0 = 0, the timer 0 interrupt is disabled. If ET0 = 1, the timer 0 interrupt is enabled. EX0 External interrupt 0 enable. If EX0 = 0, the external interrupt 0 is disabled. If EX0 = 1, the external interrupt 0 is disabled. EA WDT ET2 ESA8H IEN0 Bit No. AF H MSB LSB ET1 EX1 ET0 EX0 AE H AD H AC H AB H AA H A9H A8H The shaded bits are not used for interrupt control.
Semiconductor Group 7-6 1997-08-01 Interrupt System C505 / C505C The IEN1 register contains enable/disable flags of the timer 2 external timer reload interrupt, the external interrupts 2 and 3, the CAN controller interrupt and the A/D converter interrupt. Special Function Register IEN1 (Address B8H ) Reset Value : 00 H Bit Function EXEN2 Timer 2 external reload interrupt enable If EXEN2 = 0, the timer 2 external reload interrupt is disabled. If EXEN2 = 1, the timer 2 external reload interrupt is enabled. The external reload function is not affected by EXEN2. EX6 External interrupt 6 / capture/compare interrupt 3 enable If EX6 = 0, external interrupt 6 is disabled. If EX6 = 1, external interrupt 6 is enabled. EX5 External interrupt 5 / capture/compare interrupt 2 enable If EX5 = 0, external interrupt 5 is disabled. If EX5 = 1, external interrupt 5 is enabled. EX4 External interrupt 4 / capture/compare interrupt 1 enable If EX4 = 0, external interrupt 4 is disabled. If EX4 = 1, external interrupt 4 is enabled. EX3 External interrupt 3 / capture/compare interrupt 0 enable If EX3 = 0, external interrupt 3 is disabled. If EX3 = 1, external interrupt 3 is enabled. ECAN CAN controller interrupt enable (C505C only) If ECAN = 0, the CAN controller interrupt is disabled. If ECAN = 1, the CAN controller interrupt is enabled. This bit must be set in order to enable the software interrupt at bit SWI (for C505 and C505C) EADC A/D converter interrupt enable If EADC = 0, the A/D converter interrupt is disabled. If EADC = 1, the A/D converter interrupt is enabled. EXEN2 SWDT EX6 EX5B8H IEN1 Bit No. BF H MSB LSB EX4 EX3 ECAN EADC BE H BD H BC H BB H BA H B9H B8H The shaded bits are not used for interrupt control.
Semiconductor Group 7-7 1997-08-01
7.1.2 Interrupt Request / Control Flags
Special Function Register TCON (Address 88H ) Reset Value : 00 H The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the flag that generated this interrupt is cleared by the hardware when the service routine is vectored to, but only if the interrupt was transition-activated. lf the interrupt was level-activated, then the requesting external source directly controls the request flag, rather than the on-chip hardware. The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set by a rollover in their respective timer/counter registers. When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. Bit Function TF1 Timer 1 overflow flag Set by hardware on timer/counter 1 overflow. Cleared by hardware when processor vectors to interrupt routine. TF0 Timer 0 overflow flag Set by hardware on timer/counter 0 overflow. Cleared by hardware when processor vectors to interrupt routine. IE1 External interrupt 1 request flag Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when processor vectors to interrupt routine. IT1 External interrupt 1 level/edge trigger control flag If IT1 = 0, low level triggered external interrupt 1 is selected. If IT1 = 1, falling edge triggered external interrupt 1 is selected. IE0 External interrupt 0 request flag Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when processor vectors to interrupt routine. IT0 External interrupt 0 level/edge trigger control flag If IT0 = 0, low level triggered external interrupt 0 is selected. If IT0 = 1, falling edge triggered external interrupt 0 is selected. TF1 TR1 TF0 TR088H TCON Bit No. 8F H MSB LSB IE1 IT1 IE0 IT0 8EH 8D H 8C H 8BH 8AH 89H 88H The shaded bits are not used for interrupt control.
Semiconductor Group 7-8 1997-08-01 Interrupt System C505 / C505C Special Function Register T2CON (Address C8H ) Reset Value : 00X00000 B The external interrupt 3 (INT3) can be either positive or negative transition-activated, depending on bit I3FR in register T2CON. The flag that actually generates this interrupt is bit IEX3 in register IRCON. In addition, this flag will be set if a compare event occurs at pin P1.0/AN0/INT3 /CC0, regardless of the compare mode established and the transition at the respective pin. The flag IEX3 is cleared by hardware when the service routine is vectored to. Bit Function I3FR External interrupt 3 rising/falling edge control flag If I3FR = 0, the external interrupt 3 is activated by a falling edge at P1.0/AN0/INT3 CC0. If I3FR = 1, the external interrupt 3 is activated by a rising edge at P1.0/AN0/INT3 CC0. – This bit has no effect in the C505. T2PS I3FR – T2R1C8 H T2CON Bit No. CF H MSB LSB T2R0 T2CM T2I1 T2I0 CE H CD H CC H CB H CA H C9 H C8 H The shaded bits are not used for interrupt control.
Semiconductor Group 7-9 1997-08-01 Special Function Register IRCON (Address C0H ) Reset Value : 00 H Bit Function EXF2 Timer 2 external reload flag EXF2 is set when a reload is caused by a falling edge on pin T2EX while EXEN2 = 1. If ET2 in IEN0 is set (timer 2 interrupt enabled), EXF2 = 1 will cause an interrupt. EXF2 can be used as an additional external interrupt when the reload function is not used. EXF2 must be cleared by software. TF2 Timer 2 overflow flag Set by a timer 2 overflow and must be cleared by software. If the timer 2 interrupt is enabled, TF2 = 1 will cause an interrupt. IEX6 External interrupt 6 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1.3/AN3/INT6/CC3. Cleared when interrupt is processed. IEX5 External interrupt 5 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1.2/AN2/INT5/CC2. Cleared when interrupt is processed. IEX4 External interrupt 4 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1.1/AN1/INT4/CC1. Cleared when interrupt is processed. IEX3 External interrupt 3 edge flag Set by hardware when external interrupt edge was detected or when a compare event occured at P1.0/AN0/INT3 /CC0. Cleared when interrupt is processed. SWI This bit can be set by software to generate an interrupt. This bit is cleared when the interrupt is processed. The interrupt vector address is 004BH . IADC A/D converter interrupt request flag Set by hardware at the end of an A/D conversion. Must be cleared by software. EXF2 TF2 IEX6 IEX5C0 H IRCON Bit No. C7 H MSB LSB IEX4 IEX3 SWI IADC C6 H C5 H C4 H C3 H C2 H C1 H C0 H
Semiconductor Group 7-10 1997-08-01 Interrupt System C505 / C505C The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in register IRCON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software. The A/D converter interrupt is generated by IADC bit in register IRCON. If an interrupt is generated, in any case the converted result in ADDAT is valid on the first instruction of the interrupt service routine. lf continuous conversion is established, IADC is set once during each conversion. lf an A/D converter interrupt is generated, flag IADC will have to be cleared by software. The external interrupts 4 to 6 (INT4, INT5 and INT6) are positive transition-activated. The flags that actually generate these interrupts are bits IEX4, IEX5 and IEX6 in register IRCON. In addition, these flags will be set if a compare event occurs at the corresponding output pin P1.3/AN3/INT6/ CC3, P1.2/AN2/INT5/CC2, and P1.1/AN1/INT4/CC1, regardless of the compare mode established and the transition at the respective pin. When an interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. All of these interrupt request bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The only exceptions are the request flags IE0 and lE1. lf the external interrupts 0 and 1 are programmed to be level-activated, IE0 and lE1 are controlled by the external source via pin INT0 and INT1, respectively. Thus, writing a one to these bits will not set the request flag IE0 and/or lE1. In this mode, interrupts 0 and 1 can only be generated by software and by writing a 0 to the corresponding pins INT0 (P3.2) and INT1 (P3.3), provided that this will not affect any peripheral circuit connected to the pins. The bit IRCON.1 can be set by software to vector to location 004B H . In the case of the C505C, care should be taken while manipulating this bit to avoid any erroneous CAN interrupt generation.
Semiconductor Group 7-11 1997-08-01 Special Function Register SCON (Address. 98H ) Reset Value : 00 H The serial port interrupt is generated by a logical OR of flag RI and TI in SFR SCON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, and the bit will have to be cleared by software. Bit Function TI Serial interface transmitter interrupt flag Set by hardware at the end of a serial data transmission. Must be cleared by software. RI Serial interface receiver interrupt flag Set by hardware if a serial data byte has been received. Must be cleared by software. SM0 SM1 SM2 REN98H SCON Bit No. 9F H MSB LSB TB8 RB8 TI RI 9EH 9D H 9C H 9BH 9AH 99H 98H The shaded bits are not used for interrupt control.
Semiconductor Group 7-12 1997-08-01 Interrupt System C505 / C505C
7.1.3 Interrupt Priority Registers
The lower six bits of these two registers are used to define the interrupt priority level of the interrupt groups as they are defined in table 7-1 in the next section. Special Function Register IP0 (Address A9H ) Reset Value : 00 H Special Function Register IP1 (Address B9H ) Reset Value : XX000000 B Bit Function IP1.x IP0.x Interrupt group priority level bits (x=0-5, see table 7-1) – Reserved bits for future use. Read by CPU returns undefined values. Bit No. 76543210 MSB LSB Bit No. 76543210 The shaded bits are not used for interrupt control. IP1.x IP0.x Function 0 0 Interrupt group x is set to priority level 0 (lowest) 0 1 Interrupt group x is set to priority level 1 1 0 Interrupt group x is set to priority level 2 1 1 Interrupt group x is set to priority level 3 (highest)
Semiconductor Group 7-13 1997-08-01
7.2 Interrupt Priority Level Structure
The following table shows the interrupt grouping of the C505 interrupt sources. Each pair of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or a lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt source. lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. Thus, within each priority level there is a second priority structure determined by the polling sequence, as follows. – Within one interrupt group the “left“ interrupt is serviced first – The interrupt groups are serviced from top to bottom of the table. Table 7-1 Interrupt Source Structure Interrupt Group Associated Interrupts Priority
1 External interrupt 0 A/D converter interrupt High
2 Timer 0 overflow CAN controller interrupt (C505C) /
Software Interrupt (IRCON.1)
3 External interrupt 1 External interrupt 3
4 Timer 1 overflow External interrupt 4
5 Serial channel interrupt External interrupt 5
6 Timer 2 interrupt External interrupt 6
Semiconductor Group 7-14 1997-08-01 Interrupt System C505 / C505C
7.3 How Interrupts are Handled
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware-generated LCALL is not blocked by any of the following conditions: 1. An interrupt of equal or higher priority is already in progress. 2. The current (polling) cycle is not in the final cycle of the instruction in progress. 3. The instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP0/IP1. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress is completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP0/IP1, then at least one more instruction will be executed before any interrupt is vectored to; this delay guarantees that changes of the interrupt status can be observed by the CPU. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle interrogates only the pending interrupt requests. The polling cycle/LCALL sequence is illustrated in figure 7-4. Figure 7-4 Interrupt Response Timing Diagram MCT01920 S5P2 Interrupt is latched Interrupts are polled Vector Address Long Call to Interrupt Routine Interrupt C2C1 C3 C4 C5
Semiconductor Group 7-15 1997-08-01 Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle labeled C3 in figure 7-4 then, in accordance with the above rules, it will be vectored to during C5 and C6 without any instruction for the lower priority routine to be executed. Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, while in other cases it does not; then this has to be done by the user's software. The hardware clears the external interrupt flags IE0 and IE1 only if they were transition-activated. The hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the program counter with an address that depends on the source of the interrupt being vectored to, as shown in the following table 7-2. Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the two top bytes from the stack and reloads the program counter. Execution of the interrupted program continues from the point where it was stopped. Note that the RETI instruction is very important because it informs the processor that the program left the current interrupt priority level. A simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of the same or lower priority level would be acknowledged. Table 7-2 Interrupt Source and Vectors Interrupt Source Interrupt Vector Address Interrupt Request Flags External Interrupt 0 0003 H IE0 Timer 0 Overflow 000B H TF0 External Interrupt 1 0013 H IE1 Timer 1 Overflow 001B H TF1 Serial Channel 0023 H RI / TI Timer 2 Overflow / Ext. Reload 002BH TF2 / EXF2 A/D Converter 0043 H IADC CAN Controller / Software Interrupt 004BH – External interrupt 3 0053 H IEX3 External Interrupt 4 005B H IEX4 External Interrupt 5 0063 H IEX5 External interrupt 6 006B H IEX6 Wake-up from power-down mode 007BH –
Semiconductor Group 7-16 1997-08-01 Interrupt System C505 / C505C
7.4 External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition activated by setting or clearing bit ITx (x = 0 or 1), respectively in register TCON. If ITx = 0, external interrupt x is triggered by a detected low level at the INTx pin. If ITx = 1, external interrupt x is negative edge-triggered. In this mode, if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx=1 then requests the interrupt. If the external interrupt 0 or 1 is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. The external interrupts 4, 5 and 6 are activated only by a positive transition. The external timer 2 reload trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1.5/AN5/ T2EX but only if bit EXEN2 is set. Since the external interrupt pins (INT4, INT5 and INT6) are sampled once in each machine cycle, an input high or low should be held for at least 6 oscillator periods to ensure sampling. lf the external interrupt is transition-activated, the external source has to hold the request pin low for at least one cycle, and then hold it high for at least one cycle to ensure that the transition is recognized so that the corresponding interrupt request flag will be set (see figure 7-5). The external interrupt request flags will automatically be cleared by the CPU when the service routine is called. Figure 7-5 External Interrupt Detection MCT01921 Level-Activated Interrupt P3.x/INTx e.g. P3.x/INTx Transition-Activated Interrupt > 1 Machine Cycle Low-Level Threshold > 1 Machine Cycle > 1 Machine Cycle Transition to be detected High-Level Threshold Low-Level Threshold
Semiconductor Group 7-17 1997-08-01
7.5 Interrupt Response Time
If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus a minimum of three complete machine cycles will elapse between activation and external interrupt request and the beginning of execution of the first instruction of the service routine. A longer response time would be obtained if the request was blocked by one of the three previously listed conditions. If an interrupt of equal or higer priority is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles since the longest instructions (MUL and DIV) are only 4 cycles long; and, if the instruction in progress is RETI or a write access to registers IEN0, IEN1 or IP0, IP1 the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction, if the instruction is MUL or DIV). Thus a single interrupt system, the response time is always more than 3 cycles and less than 9 cycles.
Semiconductor Group 8-1 1997-08-01 Fail Save Mechanisms C505 / C505C
8 Fail Save Mechanisms
The C505 offers enhanced fail save mechanisms, which allow an automatic recovery from software upset or hardware failure : – a programmable watchdog timer (WDT), with variable time-out period from 192 ms up to approx. 412.5 ms at 16 MHz. – an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on.
8.1 Programmable Watchdog Timer
To protect the system against software upset, the user’s program has to clear this watchdog within a previously programmed time period. lf the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. lt also times out if a software error is based on hardware-related problems. The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of fOSC /12 upto fOSC /192. The machine clock of the C505 is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the watchdog timer can be written. Figure 8-1 shows the block diagram of the watchdog timer unit. Figure 8-1 Block Diagram of the Programmable Watchdog Timer MCB03306 IP0 (A9 )H OSCf WDTS 2 16 WDTL WDTH / 6 External HW Reset Control Logic IEN0 (A8 )H IEN1 (B8 )H 670 WDT Reset - Request WDTPSEL WDTREL (86 )H WDT SWDT OWDS
Semiconductor Group 8-2 1997-08-01
8.1.1 Input Clock Selection
The input clock rate of the watchdog timer is derived from the system clock of the C505. There is a prescaler available, which is software selectable and defines the input clock rate. This prescaler is controlled by bit WDTPSEL in the SFR WDTREL. Tabel 8-1 shows resulting timeout periods at fOSC = 12 and 16 MHz. Special Function Register WDTREL (Address 86H ) Reset Value : 00 H Bit Function WDTPSEL Watchdog timer prescaler select bit. When set, the watchdog timer is clocked through an additional divide-by- 16 prescaler . WDTREL.6 - 0 Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to WDTH when a refresh is triggered by a consecutive setting of bits WDT and SWDT. Table 8-1 Watchdog Timer Time-Out Periods WDTREL Time-Out Period Comments fOSC = 12 MHz fOSC = 16 MHz 00H 32.768 ms 24.576 ms This is the default value 80H 524.2 ms 393.2 ms Maximum time period 7FH 256 ms 192 ms Minimum time period MSB LSB Bit No. WDT86H WDTREL 76543210 PSEL Reload Value
Semiconductor Group 8-3 1997-08-01 Fail Save Mechanisms C505 / C505C
8.1.2 Watchdog Timer Control / Status Flags
The watchdog timer is controlled by two control flags (located in SFR IEN0 and IEN1) and one status flag (located in SFR IP0). Special Function Register IEN0 (Address A8H ) Reset Value : 00 H Special Function Register IEN1 (Address B8H ) Reset Value : 00 H Special Function Register IP0 (Address A9H ) Reset Value : 00 H Immediately after start, the Watchdog Timer is initialized to the reload value programmed in WDTREL.0-WDTREL.6. After an external HW reset, an oscillator watchdog power on reset, or a watchdog timer reset, register WDTREL is cleared to 00H . The lower seven bits of WDTREL can be loaded by software at any time. Bit Function WDT Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. SWDT Watchdog timer start flag. Set to activate the Watchdog Timer. When directly set after setting WDT, a watchdog timer refresh is performed. WDTS Watchdog timer status flag. Set by hardware when a watchdog Timer reset occured. Can be cleared and set by software. EAL WDT ET2 ESA8H IEN0 AF H MSB LSB ET1 EX1 ET0 EX0 AE H AD H AC H AB H AA H A9H A8H EXEN2 SWDT EX6 EX5B8H IEN1 BF H EX4 EX3 ECAN EADC BE H BD H BC H BB H BA H B9H B8H Bit No. 76543210 The shaded bits are not used for fail save control.
Semiconductor Group 8-4 1997-08-01
8.1.3 Starting the Watchdog Timer
The Watchdog Timer can be started by software (bit SWDT in SFR IEN1), but it cannot be stopped during active mode of the device. If the software fails to clear the watchdog timer an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTS in IP0 is set). A refresh of the watchdog timer is done by setting bits WDT (SFR IEN0) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power-down mode of the processor (see section "Power Saving Modes"). It is not possible to use the idle mode in combination with the watchdog timer function. Therefore, even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally.
Semiconductor Group 8-5 1997-08-01 Fail Save Mechanisms C505 / C505C
8.1.4 Refreshing the Watchdog Timer
At the same time the watchdog timer is started, the 7-bit register WDTH is preset by the contents of WDTREL.0 to WDTREL.6. Once started the watchdog cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT (IEN0.6) and by the next instruction setting SWDT (IEN1.6). Bit WDT will automatically be cleared during the second machine cycle after having been set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g. SETB SWDT). This double-instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog. The reload register WDTREL can be written to at any time, as already mentioned. Therefore, a periodical refresh of WDTREL can be added to the above mentioned starting procedure of the watchdog timer. Thus a wrong reload value caused by a possible distortion during the write operation to the WDTREL can be corrected by software.
8.1.5 Watchdog Reset and Watchdog Status Flag
lf the software fails to refresh the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFCH . The duration of the reset signal then depends on the prescaler selection (either 8 cycles or 128 cycles). This internal reset differs from an external one only in so far as the watchdog timer is not disabled and bit WDTS (watchdog timer status, bit 6 in SFR IP0) is set. Figure 8-2 shows a block diagram of all reset requests in the C505 and the function of the watchdog status flags. The WDTS flag is a flip-flop, which is set by a watchdog timer reset and cleared by an external HW reset. Bit WDTS allows the software to eamine from which source the reset was activated. The watchdog timer status flag can also be cleared by software. Figure 8-2 Watchdog Timer Status Flags and Reset Requests OWDS WDTS OWD Reset Request WDT Reset Request Set Set IP0 (A9 )H Internal Bus External HW Reset Request Synchro- nization Internal Reset RESET MCT03307 Clear
Semiconductor Group 8-6 1997-08-01
8.2 Oscillator Watchdog Unit
The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on- chip oscillator has a higher frequency than the RC oscillator), the part, in order to allow the oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog reset is released and the part starts program execution from address 0000H again. – Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. – Control of external wake-up from software power-down mode When the power-down mode is left by a low level at the P3.2/INT0 pin or the P4.1/RXDC pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts program execution by processing a power down interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. Note: The oscillator watchdog unit is always enabled. Figure 8-3 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC oscillator which provides the reference frequency for the comparison with the frequency of the on- chip oscillator. It also shows the additional provisions for integration of the wake-up from power down mode. Special Function Register IP0 (Address A9H ) Reset Value : 00 H The shaded bits are not used for fail save control. Bit Function OWDS Oscillator Watchdog Status Flag. Set by hardware when an oscillator watchdog reset occured. Can be set and cleared by software. MSB LSB Bit No. 76543210
Semiconductor Group 8-7 1997-08-01 Fail Save Mechanisms C505 / C505C Figure 8-3 Functional Block Diagram of the Oscillator Watchdog The frequency coming from the RC oscillator is divided by 10 and compared to the on-chip oscillator's frequency. If the frequency coming from the on-chip oscillator is found lower than the frequency derived from the RC oscillator the watchdog detects a failure condition (the oscillation at the on-chip oscillator could stop because of crystal damage etc.). In this case it switches the input of the internal clock system to the output of the RC oscillator. This means that the part is being clocked even if the on-chip oscillator has stopped or has not yet started. At the same time the watchdog activates the internal reset in order to bring the part in its defined reset state. The reset is performed because clock is available from the RC oscillator. This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions: The Watchdog Timer Status flag WDTS is not reset (the Watchdog Timer is, however, stopped); and bit OWDS is set. This allows the software to examine error conditions detected by the Watchdog unit even if meanwhile an oscillator failure occured. The oscillator watchdog is able to detect a recovery of the on-chip oscillator after a failure. If the frequency derived from the on-chip oscillator is again higher than the reference, the watchdog starts a final reset sequence which takes typ. 1 ms. Within that time the clock is still supplied by the RC Int. Clock XTAL2 XTAL1 OWDS MCB03308 IP0 (A9 )H
3 MHz
2f 1f< P4.1 / RXDC Start / Stop Start / Stop Mode Activated Power - Down Power-Down Mode Wake - Up Interrupt Internal Reset P3.2 / INT0 Control WS (PCON1.4)(PCON1.7) EWPD >1Frequency Comparator RC On-Chip Oscillator Logic Oscillator Logic Control
Semiconductor Group 8-8 1997-08-01 oscillator and the part is held in reset. This allows a reliable stabilization of the on chip oscillator. After that, the watchdog switches the clock supply back to the on-chip oscillator and releases the oscillator watchdog reset. If no other reset is applied at this time the part will start program execution. If an external reset or a watchdog timer reset is active, however, the device will retain the reset state until the other reset request disappears. Furthermore, the status flag OWDS is set if the oscillator watchdog was active. The status flag can be evaluated by software to detect that a reset was caused by the oscillator watchdog. The flag OWDS can be set or cleared by software. An external reset request, however, also resets OWDS (and WDTS). If software power-down mode is activated the RC oscillator and the on-chip oscillator are stopped. Both oscillators are again started in power-down mode when a low level is detected at either the P3.2/INT0 input pin or the P4.1/RXDC pin and when bit EWPD in SFR PCON1 is set (wake-up from power-down mode enabled). The wake-up source is chosen from one of P3.2/INT0 and P4.1/RXDC by bit WS in SFR PCON1. In this case the oscillator watchdog does not execute an internal reset during startup of the on-chip oscillator. After the start-up phase of the on-chip oscillator, the watchdog generates a power-down mode wake-up interrupt. Detailed description of the wake-up from software power-down mode is given in section 9.4.2. Fast Internal Reset after Power-On The C505 can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally the members of the 8051 family (e. g. SAB 80C52) do not enter their default reset state before the on-chip oscillator starts. The reason is that the external reset signal must be internally synchronized and processed in order to bring the device into the correct reset state. Especially if a crystal is used the start up time of the oscillator is relatively long (typ. 1 ms). During this time period the pins have an undefined state which could have severe effects e.g. to actuators connected to port pins. In the C505 the oscillator watchdog unit avoids this situation. After power-on the oscillator watchdog's RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds). Then the watchdog circuitry detects a failure condition for the on-chip oscillator because this has not yet started (a failure is always recognized if the watchdog's RC oscillator runs faster than the on-chip oscillator). As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip. This allows correct resetting of the part and brings all ports to the defined state (see also chapter 5 of this manual).
Semiconductor Group 9-1 1997-08-01 Power Saving Modes C505 / C505C
9 Power Saving Modes
The C505 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode.
9.1 Power Saving Mode Control Registers
The functions of the power saving modes are controlled by bits which are located in the special function registers PCON and PCON1. The SFR PCON is located at SFR address 87H . PCON1 is located in the mapped SFR area (RMAP=1) at SFR address 88H . Bit RMAP, which controls the access to the mapped SFR area, is located in SFR SYSCON (B1H ). The bits PDE, PDS and IDLE, IDLS located in SFR PCON select the power down mode or the idle mode, respectively. If the power down mode and the idle mode are set at the same time, power down takes precedence. Furthermore, register PCON contains two general purpose flags. For example, the flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle. For this, an instruction that activates idle can also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. Special Function Register PCON (Address 87H) Reset Value : 00 H Symbol Function PDS Power down start bit The instruction that sets the PDS flag bit is the last instruction before entering the power down mode IDLS Idle start bit The instruction that sets the IDLS flag bit is the last instruction before entering the idle mode. SD Slow down mode bit When set, the slow down mode is enabled GF1 General purpose flag GF0 General purpose flag PDE Power down enable bit When set, starting of the power down is enabled IDLE Idle mode enable bit When set, starting of the idle mode is enabled MSB LSB 87H PCONSMOD PDS IDLS SD GF1 GF0 PDE IDLE 76543210 Bit No. The function of the shaded bit is not described in this section.
Semiconductor Group 9-2 1997-08-01 Special Function Register PCON1 (Mapped Address 88H) Reset Value : 0XX0XXXXB Symbol Function EWPD External wake-up from power down enable bit Setting EWPD before entering power down mode, enables the external wake- up from power down mode capability (more details see section 9.4.2). WS Wake-up from power-down source select WS = 0 : wake-up via pin P3.2/INT0 WS = 1 : wake-up via pin P4.1/RXDC. Pin P3.2/INT0 is selected as wake-up source after reset. – Reserved bits for future use. Read by CPU returns undefined values. MSB LSB 76543210 Bit No.
Semiconductor Group 9-3 1997-08-01 Power Saving Modes C505 / C505C
9.2 Idle Mode
In the idle mode the oscillator of the C505 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, the CAN controller (C505C only), and all timers with the exception of the watchdog timer are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. The reduction of power consumption, which can be achieved by this feature depends on the number of peripherals running. If all timers are stopped and the A/D converter, and the serial interfaces are not running, the maximum power reduction can be achieved. This state is also the test condition for the idle mode I CC . Thus, the user has to take care which peripheral should continue to run and which has to be stopped during idle mode. Also the state of all port pins – either the pins controlled by their latches or controlled by their secondary functions – depends on the status of the controller when entering idle mode. Normally, the port pins hold the logical state they had at the time when the idle mode was activated. If some pins are programmed to serve as alternate functions they still continue to output during idle mode if the assigned function is on. This especially applies to the serial interface in case it cannot finish reception or transmission during normal operation. The control signals ALE and PSEN are held at logic high levels. As in normal operation mode, the ports can be used as inputs during idle mode. Thus a capture or reload operation can be triggered, the timers can be used to count external events, and external interrupts will be detected. The idle mode is a useful feature which makes it possible to "freeze" the processor's status - either for a predefined time, or until an external event reverts the controller to normal operation, as discussed below. The watchdog timer is the only peripheral which is automatically stopped during idle mode.
Semiconductor Group 9-4 1997-08-01 The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of both bits, IDLE and IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be cleared after being set. If one of these register bits is read the value that appears is 0. This double instruction is implemented to minimize the chance of an unintentional entering of the idle mode which would leave the watchdog timer's task of system protection without effect. Note: PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle mode is obtained by byte-handling instructions, as shown in the following example: ORL PCON,#00000001B ;Set bit IDLE, bit IDLS must not be set ORL PCON,#00100000B ;Set bit IDLS, bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode. There are two ways to terminate the idle mode: – The idle mode can be terminated by activating any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bit IDLS. – The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still running, the hardware reset must be held active only for two machine cycles for a complete reset.
Semiconductor Group 9-5 1997-08-01 Power Saving Modes C505 / C505C
9.3 Slow Down Mode Operation
In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (e.g. if the controller is waiting for an input signal). Since in CMOS devices there is an almost linear dependence of the operating frequency and the power supply current, a reduction of the operating frequency results in reduced power consumption. In the slow down mode all signal frequencies that are derived from the oscillator clock are divided by 32. The slow down mode is activated by setting the bit SD in SFR PCON. If the slow down mode is enabled, the clock signals for the CPU and the peripheral units are reduced to 1/32 of the nominal system clock rate. The controller actually enters the slow down mode after a short synchronization period (max. two machine cycles). The slow down mode is terminated by clearing bit SD. The slow down mode can be combined with the idle mode by performing the following double instruction sequence: ORL PCON,#00000001B ; preparing idle mode: set bit IDLE (IDLS not set) ORL PCON,#00110000B ; entering idle mode combined with the slow down mode: ; (IDLS and SD set) There are two ways to terminate the combined Idle and Slow Down Mode : – The idle mode can be terminated by activation of any enabled interrupt. The CPU operation is resumed, the interrupt will be serviced and the next instruction to be executed after the RETI instruction will be the one following the instruction that had set the bits IDLS and SD. Nevertheless the slow down mode keeps enabled and if required has to be terminated by clearing the bit SD in the corresponding interrupt service routine or at any point in the program where the user no longer requires the slow-down mode power saving. – The other possibility of terminating the combined idle and slow down mode is a hardware reset. Since the oscillator is still running, the hardware reset has to be held active for only two machine cycles for a complete reset.
Semiconductor Group 9-6 1997-08-01
9.4 Software Power Down Mode
In the software power down mode, the RC oscillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ALE and PSEN held at logic low level (see table 9–1). In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level before the power down mode is terminated. The software power down mode can be left either by an active reset signal or by a low signal at one of the wake-up source pins. Using reset to leave power down mode puts the microcontroller with its SFRs into the reset state. Using either the P3.2/INT0 pin or the P4.1/RXDC pin for power down mode exit starts the RC oscillator and the on-chip oscillator and maintains the state of the SFRs, which have been frozen when power down mode is entered. Leaving power down mode should not be done before VCC is restored to its nominal operating level.
9.4.1 Invoking Software Power Down Mode
The software power down mode is entered by two consecutive instructions. The first instruction has to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent setting of both bits, PDE and PDS, does not initiate the power down mode. Bits PDE and PDS will automatically be cleared after having been set and the value shown by reading one of these bits is always 0. This double instruction is implemented to minimize the chance of unintentionally entering the power down mode which could possibly ”freeze” the chip's activity in an undesired status. PCON is not a bit-addressable register, so the above mentioned sequence for entering the power down mode is obtained by byte-handling instructions, as shown in the following example: ORL PCON,#00000010B ;set bit PDE, bit PDS must not be set ORL PCON,#01000000B ;set bit PDS, bit PDE must not be set, enter power down The instruction that sets bit PDS is the last instruction executed before going into power down mode. When the double instruction sequence shown above is used, the power down mode can only be left by a reset operation. If the external wake-up from power down capability has also to be used, its function must be enabled using the following instruction sequence prior to executing the double instruction sequence shown above. ORL SYSCON,#00010000B ;set RMAP ORL PCON1,#80H ;enable wake-up from power down via P3.2/INT0 ANL SYSCON,#11101111B ;reset RMAP (for future SFR accesses) Setting EWPD automatically disables all interrupts still maintaining all actual values of the interrupt enable bits. In the above sequence the value of register PCON1 should be modified for choosing a wake-up via the P4.1/RXDC (bit PCON1.4 should be set). Note : Before entering the power down mode, an A/D conversion in progress must be stopped.
Semiconductor Group 9-7 1997-08-01 Power Saving Modes C505 / C505C
9.4.2 Exit from Software Power Down Mode
If power down mode is exit via a hardware reset, the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed. The reset signal that terminates the power down mode also restarts the RC oscillator and the on-chip oscillatror. The reset operation should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). Figure 9-1 shows the procedure which must is executed when power down mode is left via the P3.2/INT0 or the P4.1/RXDC wake-up capability. Figure 9-1 Wake-up from Power Down Mode Procedure When the power down mode wake-up capability has been enabled (bit EWPD in SFR PCON1 set) prior to entering power down mode and bit WS in SFR PCON1 is cleared, the power down mode can be exit via INT0 while executing the following procedure : 1. In power down mode pin P3.2/INT0 must be held at high level. 2. Power down mode is left when P3.2/INT0 goes low for at least 10 ms (latch phase). After this delay the internal RC oscillator and the on-chip oscillator are started, the state of pin P3.2/INT0 is internally latched, and P3.2/INT0 can be set again to high level if required. Thereafter, the oscillator watchdog unit controls the wake-up procedure in its start-up phase. Invalid Address Invalid Address / Data 00H 7BH 1 st instr. of ISR PSEN ALE P3.2 / INT0 or P4.1 / RXDC Power Down Mode Phase Latch 10 s min. µ typ. 5 ms RETI Insruction Watchdog Circuit Oscillator Start-Up Phase Execution of interrupt at 007B H Detailed Timing of Beginning of Phase 4 MCT03309
Semiconductor Group 9-8 1997-08-01 3. The oscillator watchdog unit starts operation. When the on-chip oscillator clock is detected for stable nominal frequency, the microcontroller starts again with its operation initiating the power down wake-up interrupt. The interrupt address of the first instruction to be executed after wake- up is 007BH . ALE and PSEN are in their power-down state up to this time. At the end of phase 3 the CPU processes the interrupt call and during these two machine cycles, ALE and PSEN behave as shown in figure 9-1 (i.e. at the begining of phase 4). Instruction fetches during the interrupt call are, however, discarded. 4. After the RETI instruction of the power down wake-up interrupt routine has been executed, the instruction which follows the initiating power down mode double instruction sequence will be executed. The peripheral units timer 0/1/2 , CAN controller, and WDT are frozen until end of phase 4. All interrupts of the C505 are disabled from phase 2) until the end of phase 4). Other Interrupts can be first handled after the RETI instruction of the wake-up interrupt routine. The procedure to exit the software power down mode via the P4.1/RXDC pin is identical to the above procedure except that in this case pin P4.1/RXDC replaces pin P3.2/INT0 , and bit WS in SFR PCON1 should be set prior to entering software power down mode.
9.5 State of Pins in Software Initiated Power Saving Modes
In the idle mode and in the power down mode the port pins of the C505 have a well defined status which is listed in the following table 9-1. This state of some pins also depends on the location of the code memory (internal or external). Table 9-1 Status of External Pins During Idle and Software Power Down Mode Outputs Last Instruction Executed from Internal Code Memory Last Instruction Executed from External Code Memory Idle Power Down Idle Power Down ALE High Low High Low PSEN High Low High Low PORT 0 Data Data Float Float PORT 2 Data Data Address Data PORT 1, 3, 4 Data / alternate outputs Data / last output Data / alternate outputs Data / last output
Semiconductor Group 10-1 1997-08-01 Device Specifications C505 / C505C
10 Device Specifications
10.1 Absolute Maximum Ratings
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS ) the Voltage on VCC pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings.
Semiconductor Group 10-2 1997-08-01
10.2 DC Characteristics
VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C505 TA = – 40 to 85 °C for the SAF-C505 TA = – 40 to 110 °C for the SAH-C505 TA = – 40 to 125 °C for the SAK-C505 Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltages all except EA, RESET EA pin RESET pin VIL VIL1 VIL2 – 0.5 – 0.5 – 0.5 0.2 VCC - 0.1 0.2 VCC - 0.3 0.2 VCC + 0.1 V V V Input high voltages all except XTAL1, RESET XTAL1 pin RESET pin VIH VIH1 VIH2 0.2 VCC + 0.9
0.7 VCC
0.6 VCC
VCC + 0.5 VCC + 0.5 VCC + 0.5 V V V Output low voltages Ports 1, 2, 3, 4 Port 0, ALE, PSEN VOL VOL1 0.45 0.45 V V IOL = 1.6 mA 1) IOL = 3.2 mA 1) Output high voltages Ports 1, 2, 3, 4 Port 0 in external bus mode, ALE, PSEN VOH VOH2 2.4 0.9 VCC 2.4 0.9 VCC V V V V IOH = – 80 mA IOH = – 10 mA IOH = – 800 mA IOH = – 80 mA 2) Logic 0 input current Ports 1, 2, 3, 4 IIL – 10 – 70 mA VIN = 0.45 V Logical 0-to-1 transition current Ports 1, 2, 3, 4 ITL – 65 – 650 mA VIN = 2 V Input leakage current Port 0, AN0-7 (Port 1), EA ILI – – 1 mA 0.45 < VIN < VCC Pin capacitance C IO –1 0 p F fc = 1 MHz, TA = 25 °C Overload current IOV – – 5m A 8) 9)
Semiconductor Group 10-3 1997-08-01 Device Specifications C505 / C505C Power Supply Current 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port 0 = VSS ; RESET = VCC ; XTAL2 = N.C.; XTAL1 = VSS ; VAGND = VSS ; VAREF = VCC ; all other pins are disconnected. 4) ICC (active mode) is measured with: XTAL1 driven with tR , tF = 5 ns , VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.; EA = Port 0 = VCC ; RESET = VSS ; all other pins are disconnected. ICC would be slightly higher if the crystal oscillator is used (approx. 1 mA). 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF = 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected; 6) ICC (active mode with slow-down mode) is measured : TBD 7) ICC (idle mode with slow-down mode) is measured : TBD 8) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 9) Not 100% tested, guaranteed by design characterization 10)The typical ICC values are periodically measured at TA = + 25 ˚C but not 100% tested. 11)The maximum ICC values are measured under worst case conditions (TA = 0 ˚C or – 40 ˚C and VCC = 5.5 V). Parameter Symbol Limit Values Unit Test Condition typ. 10) max.11) Active Mode 16 MHz
20 MHz
VCC = 5 V 4) Idle Mode 16 MHz 14.8 17.8 TBD TBD mA VCC = 5 V 5) Active Mode with slow-down enabled
16 MHz
VCC = 5 V 6) Idle Mode with slow-down enabled VCC = 5 V 7) Power down current IPD TBD TBD mA VCC = 2… 5.5 V3)
Semiconductor Group 10-4 1997-08-01
10.3 A/D Converter Characteristics
VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C505 TA = – 40 to 85 °C for the SAF-C505 TA = – 40 to 110 °C for the SAH-C505 TA = – 40 to 125 °C for the SAK-C505 4 V £ VAREF £ VCC + 0.1 V ; VSS – 0.1 V £ VAGND £ V ss + 0.2 V Notes see next page. Clock calculation table : Further timing conditions : tADC min = 800 ns tIN = 1 / fOSC = tCLP Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage VAIN VAGND - 0.2 VAREF + 0.2 V 1) Sample time tS – 64 x tIN 32 x tIN 16 x tIN 8 x tIN ns Prescaler ‚ 32 Prescaler ‚ 16 Prescaler ‚ 8 Prescaler ‚ 4 2) Conversion cycle time tADCC – 320 x tIN 160 x tIN 80 x tIN 40 x tIN ns Prescaler ‚ 32 Prescaler ‚ 16 Prescaler ‚ 8 Prescaler ‚ 4 3) Total unadjusted error TUE – – 2 LSB V SS +0.5V £ VAIN £ VCC -0.5V 4) Internal resistance of reference voltage source RAREF – tADC / 500 - 1 kW tADC in [ns] 5) 6) Internal resistance of analog source RASRC – tS / 500 - 1 kW tS in [ns] 2) 6) ADC input capacitance C AIN –5 0p F 6) Clock Prescaler Ratio ADCL1, 0 t ADC t S t ADCC ‚ 32 1 1 32 x t IN 64 x t IN 320 x t IN ‚ 16 1 0 16 x t IN 32 x t IN 160 x t IN ‚ 8 0 1 8 x t IN 16 x t IN 80 x tIN ‚ 4 0 0 4 x t IN 8 x tIN 40 x tIN
Semiconductor Group 10-5 1997-08-01 Device Specifications C505 / C505C Notes: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 00H or FFH , respectively. 2) During the sample time the input capacitance C AIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE (max.) is tested at –40 £ TA £ 125 °C ; VCC £ 5.5 V; VAREF £ VCC + 0.1 V and VSS £ VAGND . It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization.
Semiconductor Group 10-6 1997-08-01
10.4 AC Characteristics (16 MHz) for C505
VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C505 TA = – 40 to 85 °C for the SAF-C505 (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit 16-MHz clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP = 2 MHz to min. max. min. max. ALE pulse width tLHLL 48 – CLP - 15 – ns Address setup to ALE tAVLL 10 – TCL Hmin -15 – ns Address hold after ALE tLLAX 10 – TCL Hmin -15 – ns ALE to valid instruction in tLLIV – 75 – 2 CLP - 50 ns ALE to PSEN tLLPL 10 – TCL Lmin -15 – ns PSEN pulse width tPLPH 73 – CLP+ TCL Hmin -15 –n s PSEN to valid instruction in tPLIV – 38 – CLP+ TCL Hmin- 50 ns Input instruction hold after PSENtPXIX 0 – 0–n s Input instruction float after PSENtPXIZ *) – 15 – TCL Lmin -10 ns Address valid after PSEN tPXAV *) 20 – TCL Lmin - 5 – ns Address to valid instruction intAVIV – 95 – 2 CLP + TCL Hmin -55 ns Address float to PSEN tAZPL -5 – -5 – ns
Semiconductor Group 10-7 1997-08-01 Device Specifications C505 / C505C AC Characteristics (16 MHz) for C505 (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 16-MHz clock Duty Cycle 0.4 to 0.6 Variable Clock 1/CLP= 2 MHz to 16 MHz min. max. min. max. RD pulse width tRLRH 158 – 3 CLP - 30 – ns WR pulse width tWLWH 158 – 3 CLP - 30 – ns Address hold after ALE tLLAX2 48 – CLP- 15 – ns RD to valid data in tRLDV – 100 – 2 CLP+ TCL Hmin - 50 ns Data hold after RD tRHDX 0–0 – n s Data float after RD tRHDZ – 51 – CLP - 12 ns ALE to valid data in tLLDV – 200 – 4 CLP - 50 ns Address to valid data in tAVDV – 200 – 4 CLP + TCL Hmin -75 ns ALE to WR or RD tLLWL 73 103 CLP + TCL Lmin - 15 CLP+ TCL Lmin+ 15 ns Address valid to WR tAVWL 95 – 2 CLP - 30 – ns WR or RD high to ALE high tWHLH 10 40 TCL Hmin - 15 TCL Hmin + 15 ns Data valid to WR transition tQVWX 5 – TCL Lmin - 20 – ns Data setup before WR tQVWH 163 – 3 CLP + TCL Lmin - 50 –n s Data hold after WR tWHQX 5 – TCL Hmin - 20 – ns Address float after RD tRLAZ –0– 0 n s
Semiconductor Group 10-8 1997-08-01 AC Characteristics (16 MHz) for C505 (cont’d) Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. External Clock Drive Characteristics Parameter Symbol CPU Clock = 16 MHz Duty Cycle 0.4 to 0.6 Variable CPU Clock 1/CLP = 2 to 16 MHz Unit min. max. min. max. Oscillator period CLP 62.5 62.5 62.5 500 ns High time TCL H 25 – 25 CLP - TCL L ns Low time TCL L 25 – 25 CLP - TCL H ns Rise time tR – 10 – 10 ns Fall time tF – 10 – 10 ns Oscillator duty cycle DC 0.4 0.6 25 / CLP 1 - 25 / CLP – Clock cycle TCL 25 37.5 CLP * DC min CLP * DCmax ns
Semiconductor Group 10-9 1997-08-01 Device Specifications C505 / C505C
10.5 AC Characteristics (20 MHz) for C505
VCC = 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C505 TA = – 40 to 85 °C for the SAF-C505 (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C505 to devices with float times up to 25 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit 20-MHz clock Duty Cycle 0.5 to 0.5 Variable Clock 1/CLP = 2 MHz to min. max. min. max. ALE pulse width tLHLL 35 – CLP - 15 – ns Address setup to ALE tAVLL 10 – TCL Hmin - 15 – ns Address hold after ALE tLLAX 10 – TCL Hmin - 15 – ns ALE low to valid instr in tLLIV – 55 – 2 CLP - 45 ns ALE to PSEN tLLPL 10 – TCL Lmin - 15 – ns PSEN pulse width tPLPH 60 – CLP + TCL Hmin - 15 –n s PSEN to valid instr in tPLIV – 25 – CLP + TCL Hmin - 50 ns Input instruction hold after PSENtPXIX 0 – 0–n s Input instruction float after PSENtPXIZ *) – 20 – TCL Lmin - 5 ns Address valid after PSEN tPXAV *) 20 – TCL Lmin - 5 – ns Address to valid instr in tAVIV – 65 – 2 CLP + TCL Hmin - 60 ns Address float to PSEN tAZPL - 5 – - 5 – ns
Semiconductor Group 10-10 1997-08-01 AC Characteristics (20 MHz) for C505 (cont’d) External Data Memory Characteristics Parameter Symbol Limit Values Unit 20-MHz clock Duty Cycle 0.5 to 0.5 Variable Clock 1/CLP = 2 MHz to min. max. min. max. RD pulse width tRLRH 120 – 3 CLP-30 – ns WR pulse width tWLWH 120 – 3 CLP-30 – ns Address hold after ALE tLLAX2 35 – CLP-15 – ns RD to valid data in tRLDV – 75 – 2 CLP+ TCL Hmin-50 ns Data hold after RD tRHDX 0 – 0–n s Data float after RD tRHDZ – 38 – CLP-12 ns ALE to valid data in tLLDV – 150 – 4 CLP-50 ns Address to valid data in tAVDV – 150 – 4 CLP + TCL Hmin-75 ns ALE to WR or RD tLLWL 60 90 CLP + TCL Lmin-15 CLP + TCL Lmin+15 ns Address valid to WR tAVWL 70 – 2 CLP-30 – ns WR or RD high to ALE high tWHLH 10 40 TCL Hmin-15 TCL Hmin+15 ns Data valid to WR transition tQVWX 5 – TCL Lmin-20 – ns Data setup before WR tQVWH 125 – 3 CLP+ TCL Lmin-50 –n s Data hold after WR tWHQX 5 – TCL Hmin-20 – ns Address float after RD tRLAZ – 0 –0n s
Semiconductor Group 10-11 1997-08-01 Device Specifications C505 / C505C External Clock Drive Characteristics Note: The 20 MHz values in the tables are given as an example for a typical duty cycle of the oscillator clock of 50 %. Parameter Symbol Limit Values Unit Variable Clock Freq. = 2 MHz to 20 MHz min. max. Oscillator period CLP 50 500 ns High time TCL H 25 CLP-TCL L ns Low time TCL L 25 CLP-TCL H ns Rise time tR –1 0 n s Fall time tF –1 0 n s
Semiconductor Group 10-12 1997-08-01 Program Memory Read Cycle MCT00096 ALE PSEN Port 2 LHLLt A8 - A15 A8 - A15 A0 - A7 Instr.IN A0 - A7Port 0 tAVLL PLPH t tLLPL tLLIV tPLIV tAZPL tLLAX tPXIZ tPXIX tAVIV tPXAV
Semiconductor Group 10-13 1997-08-01 Device Specifications C505 / C505C Data Memory Read Cycle MCT00097 ALE PSEN Port 2 WHLHt Port 0 RD tLLDV tRLRHtLLWL tRLDV tAVLL tLLAX2 tRLAZ tAVWL tAVDV tRHDX tRHDZ A0 - A7 from Ri or DPL from PCL A0 - A7 Instr. INData IN A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
Semiconductor Group 10-14 1997-08-01 Data Memory Write Cycle External Clock Drive on XTAL1 MCT00098 ALE PSEN Port 2 WHLHt Port 0 WR tWLWHtLLWL tQVWX tAVLL tLLAX2 tQVWH tAVWL tWHQX A0 - A7 from Ri or DPL from PCL A0 - A7 Instr.INData OUT A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH TCL H TCL L CLP tR tF 0.2V CC
0.7 CCV
- 0.1 MCT03310 XTAL1
Semiconductor Group 10-15 1997-08-01 Device Specifications C505 / C505C
10.6 ROM Verification Characteristics for C505-2R
Parameter Symbol Limit Values Unit min. max. Address to valid data tAVQV – 5 CLP ns MCT02629 tAVQV Address Data OUTPort 0 Inputs : P2.6, ALE, RESETData : Address : P1.0 V IH IH1V VSSP2.7, PSEN = EA = - P1.7 = A0 A7- - A13A8=P2.5-P2.0 P0.0 - P0.7 = D0 D7- P2.0 - P2.5 P1.0 - P1.7
Semiconductor Group 10-16 1997-08-01 ROM Verification Mode 2 ROM Verification Mode 2 Parameter Symbol Limit Values Unit min. typ max. ALE pulse width tAWD – CLP – ns ALE period tACY – 6 CLP – ns Data valid after ALE tDVA – – 2 CLP ns Data stable after ALE tDSA 4 CLP – – ns P3.5 setup to ALE low tAS – TCL H –n s Oscillator frequency 1/ CLP 4–6M H z MCT02613 tACY tAWD tDSA DVAt tAS Data Valid ALE Port 0 P3.5
Semiconductor Group 10-17 1997-08-01 Device Specifications C505 / C505C AC Testing: Input, Output Waveforms AC Testing : Float Waveforms Recommended Oscillator Circuits for Crystal Oscillator AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’. 0.45 V VCC0.2 -0.1 +0.90.2 CCV Test Points MCT00039 VCC -0.5 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH /VOL level occurs. IOL /IOH ‡ – 20 mA MCT00038 VLoad VLoad -0.1 V +0.1 VLoadV Timing Reference Points VOH -0.1 V +0.1 VOLV MCS03311 C 2 - 20 MHz XTAL2 XTAL1 XTAL1 XTAL2N.C. External Oscillator Signal Crystal Oscillator Mode Driving from External Source Crystal Mode:C = 20 pF 10 pF (incl. stray capacitance) C
Semiconductor Group 10-18 1997-08-01
10.7 Package Information
Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Plastic Package, P-MQFP-44-2 (SMD) (Plastic Metric Quad Flat Pack) GPM05622
Semiconductor Group 11-1 1997-08-01 Index C505 / C505C
11 Index
Note: Bold page numbers refer to the main definition part of SFRs or SFR bits. A A/D converter characteristics . . 10-5 to 10-6 AC Testing B C Message object address map. . . . 6-75 Message object handling . 6-81 to 6-87 CPU
Semiconductor Group 11-2 1997-08-01 Index C505 / C505C D AC characteristics E Overlapping of data/program memory 4-3 F G H I
Semiconductor Group 11-3 1997-08-01 Index C505 / C505C Interrupts L M N O P Mixed digital/analog I/O pins . . . . 6-11
Semiconductor Group 11-4 1997-08-01 Index C505 / C505C Standard I/O port circuitry . . . 6-3 to 6-4 Power down mode Software power down mode . . . 9-6 to 9-8 R Recommended oscillator circuits . . . . 10-18 Protected ROM verification example 4-12 S with internal baud rate generator . 6-48 Operating mode 2 and 3 . . . 6-57 to 6-59 CAN registers - address ordered . 3-18 to 3-19 Table - address ordered. . . . 3-15 to 3-17 Table - functional order . . . . 3-12 to 3-14 T
Semiconductor Group 11-5 1997-08-01 Index C505 / C505C Mode 2, 8-bit rel. timer/counter . . . 6-21 Mode 3, two 8-bit timer/counter. . . 6-22 Timings U V W X Table - P0/P2 during MOVX instr. . . 3-10 Write page address to XPAGE . . . . 3-7