C504

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Data Sheet 05.96 Microcomputer Components C504 8-Bit CMOS Microcontroller

Edition 05.96 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73,

81541 München

© Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu- man life. If they fail, it is reasonable to assume that the health of the user may be endangered. C504 Revision History: Current Version: 05.96 Previous Version: Page (in previous Version) Page (in new Version) Subjects (major changes since last revision)

8-Bit CMOS Microcontroller C504 Advance Information Semiconductor Group 3 05.96

• Fully compatible to standard 8051 microcontroller
• Up to 40 MHz operating frequency
• 16 K× 8 ROM (C504-2R only, optional ROM protection)
• 256× 8 RAM
• 256× 8 XRAM
• Four 8-bit ports, (2 ports with mixed analog/digital I/O capability)
• Three 16-bit timers/counters (timer 2 with up/down counter feature)
• Capture/compare unit for PWM signal generation and signal capturing - 3-channel, 16-bit capture/compare unit - 1-channel, 10-bit compare unit
• Compare unit
• USART
• 10-bit A/D Converter with 8 multiplexed inputs
• Twelve interrupt sources with two priority levels
• On-chip emulation support logic (Enhanced Hooks Technology TM)
• Programmable 15-bit Watchdog Timer
• Oscillator Watchdog
• Fast Power On Reset
• Power Saving Modes
• M-QFP-44 package
• Temperature ranges: SAB-C504 TA : 0 to 70°C SAF-C504 TA : – 40 to 85°C SAH-C504 TA : – 40 to 110°C (max. operating frequency.: TBD) SAK-C504 TA : – 40 to 125°C (max. operating frequency.: 12 MHz)

The C504 with its capture compare unit (CCU) especially provides a functionality, which allows to use the microcontroller in motor control applications. Further, the C504 is functionally upward compatible with the SAB 80C52/C501 microcontroller and can replace it in existing applications. The C504-2R contains a non-volatile 16K× 8 read-only program memory, a volatile on-chip 512× 8 read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/ compare unit with compare timer, a 10-bit compare timer, a twelve source, two priority level interrupt structure, a serial port, versatile fail save mechanisms, on-chip emulation support logic, and a genuine 10-bit A/D converter. The C504-L is identical to the C504-2R, except that it lacks the program memory on chip. Therefore, the term C504 refers to all versions within this data sheet unless otherwise noted. Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C504) and – 40 ˚C to 125 ˚C (SAK-C504) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer.

Ordering Information

Type Ordering Code Package Description (8-Bit CMOS microcontroller) SAB-C504-LM Q67120-C1048 P-MQFP-44 for external memory (12 MHz) SAB-C504-L24M Q67120-C1049 P-MQFP-44 for external memory (24 MHz) SAB-C504-L40M Q67120-C1050 P-MQFP-44 for external memory (40 MHz) SAB-C504-2RM Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (12 MHz) SAB-C504-2R24M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (24 MHz) SAB-C504-2R40M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (40 MHz)

Pin Configuration (top view)

Pin Definitions and Functions Symbol Pin Number (P-MQFP-44) I/O Function P1.0-P1.7 40-44, 1-3 I/O Port 1 is an 8-bit bidirectional port. Port pins can be used for digital input/output. P1.0 - P1.3 can also be used as analog inputs of the A/D-converter. As secondary digital functions, port 1 contains the timer 2 pins and the capture/compare inputs/outputs. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. The functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / T2 Analog input channel 0 / input to counter 2 P1.1 / AN1 / T2EX Analog input channel 1 / capture/reload trigger of timer 2 / up-down count P1.2 / AN2 / CC0 Analog input channel 2 / input/output of capture/compare channel 0 P1.3 / AN3 / COUT0 Analog input channel 3 / output of capture/compare channel 0 P1.4 / CC1 Input/output of capture/compare channel 1 P1.5 / COUT1 Output of capture/compare channel 1 P1.6 / CC2 Input/output of capture/compare channel 2 P1.7 / COUT2 Output of capture/compare channel 2 RESET 4 I RESET A high level on this pin for one machine cycle while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor toVCC . *) I = Input O = Output

P3.0-P3.7 5, 7-13 I/O Port 3 is an 8-bit bidirectional port. P3.0 (R×D) and P3.1 (T×D) operate as defined for the C501. P3.2 to P3.7 contain the external interrupt inputs, timer inputs, input and as an additional optinal function four of the analog inputs of the A/D-converter. Port 3 pins are assigned to be used as analog inputs via the bits of SFR P3ANA. P3.6/ WR can be assigned as a third interrupt input. The functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / AN4 / INT0 Analog input channel 4 / external interrupt 0 input / timer 0 gate control input P3.3 / AN5 / INT1 Analog input channel 5 / external interrupt 1 input / timer 1 gate control input P3.4 / AN6 / T0 Analog input channel 6 / timer 0 counter input P3.5 / AN7 / T1 Analog input channel 7 / timer 1 counter input P3.6 / WR / INT2 WR control output; latches the data byte from port 0 into the external data memory / external interrupt 2 input P3.7 / RD RD control output; enables the external data memory CTRAP 6 I CCU Trap Input With CTRAP = low the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-44) I/O Function

XTAL2 14 – XTAL2 Output of the inverting oscillator amplifier. XTAL1 15 – XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. P2.0-P2.7 18-25 I/O Port 2 is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( IIL, in the DC characteris-tics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. PSEN 26 O The Program StoreEnable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution. ALE 27 O The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access. When instructions are executed from internal ROM ( EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON. *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-44) I/O Function

COUT3 28 O 10-Bit compare channel output This pin is used for the output signal of the 10-bit compare timer 2 unit. COUT3 can be disabled and set to a high or low state. EA 29 I External Access Enable When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000 H .When held at low level, the C504 fetches all instructions from external program memory. For the C504-L this pin must be tied low. P0.0-P0.7 37-30 I/O Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs.Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup resistors when issuing 1 s. Port 0 also outputs the code bytes during program verification in the C504-2R. External pullup resistors are required during program (ROM) verification. VAREF 38 – Reference voltage for the A/D converter. VAGND 39 – Reference ground for the A/D converter. VSS 16 – Ground (0V) VCC 17 – Power Supply (+5V) *) I = Input O = Output Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number (P-MQFP-44) I/O Function

The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % three- byte instructions. With a 12 MHz crystal, 58 % of the instructions are executed in 1.0µs (24 MHz: 500 ns, 40 MHz : 300 ns). Special Function Register PSW (Address D0H ) Reset Value : 00 H Bit Function CY Carry Flag Used by arithmetic instruction. AC Auxiliary Carry Flag Used by instructions which execute BCD operations. F0 General Purpose Flag RS1 RS0 Register Bank select control bits These bits are used to select one of the four register banks. OV Overflow Flag Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. CY AC F0 RS1 RS0 OV F1 PD0 H PSW D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H Bit No. MSB LSB RS1 RS0 Function 0 0 Bank 0 selected, data address 00 H -07H 0 1 Bank 1 selected, data address 08 H -0FH 1 0 Bank 2 selected, data address 10 H -17H 1 1 Bank 3 selected, data address 18 H -1FH

Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 63 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. The SFRs of the C504 are listed intable 2 andtable 3. Intable 2 they are organized in groups which refer to the functional blocks of the C504.Table 3 illustrates the contents of the SFRs in numeric order of their addresses.

Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL PSW SP SYSCON Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register E0H F0H 83H 82H D0 H 81H B1H 00H 00H 00H 00H 00H 07H XX10XXX0 B Interrupt System IEN0 IEN1 CCIE IP0 IP1 ITCON Interrupt Enable Register 0 Interrupt Enable Register 1 Capture/Compare Interrupt Enable Reg. Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Trigger Condition Register A8 H A9H D6 H B8 H B9H 9AH 0X000000B XX000000 B 00H XX000000 B XX000000 B 00101010B Ports P0 P1ANA P3ANA Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 3 Analog Input Selection Register 80H 90H 90H 1) 4) A0 H B0 H B0 H 1) 4) FFH FFH XXXX1111 B FFH FFH XX1111XX B A/D- Converter ADCON0 ADCON1 ADDATH ADDATL P1ANA P3ANA 2) A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte Port 1 Analog Input Selection Register Port 3 Analog Input Selection Register D8 H DC H D9 H DA H 90H B0H XX000000 B 01XXX000 B 00H 00XXXXXX B XXXX1111 B XX1111XX B Serial Channels PCON 2) SBUF SCON Power Control Register Serial Channel Buffer Register Serial Channel Control Register 87H 99H 98H 000X0000B XX H 00H Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 8C H 8D H 8AH 8BH 89H 00H 00H 00H 00H 00H 00H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Timer 2 Reload Capture Register, High Byte Timer 2 Reload Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte C8 H C9 H CB H CA H CD H CC H 00H XXXXXXX0 B 00H 00H 00H 00H Capture / Compare Unit CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI TRCON CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE CT2CON CP2L CP2H CMP2L CMP2H BCON Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Trap enable control register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Capture/compare interrupt request flag reg. Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register E1H DE H DF H E6H E7H E3H E4H E2H CF H C2 H C3 H C4 H C5 H C6 H C7 H E5H D6 H C1 H D2 H D3 H D4 H D5 H D7 H 00010000B 00H 00H 00H 00H 00H 00H FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00010000B 00H XXXXXX00 B 00H XXXXXX00 B 3)) 00H Watchdog WDCON WDTREL Watchdog Timer Control Register Watchdog Timer Reload Register C0 H 86H XXXX0000 B 00H Power Save Mode PCON 2) PCON1 Power Control Register Power Control Register 1 87H 88H 000X0000B 0XXXXXXX B 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Table 2 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset

Contents of the SFRs, SFRs in Numeric Order of their Addresses Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 86H WDTREL 00 H WDT PSEL 87H PCON 000X- 0000B SMOD PDS IDLS – GF1 GF0 PDE IDLE 88H 2) TCON 00H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88H 3) PCON1 0XXX- XXXX B 89H TMOD 00 H GATE C/ T M1 M0 GATE C/ TM 1 M 0 90H 90H 2)3)P1ANA XXXX- 1111B – – – – EAN3 EAN2 EAN1 EAN0 98H 2) SCON 00H SM0 SM1 SM2 REN TB8 RB8 TI RI 9AH ITCON 0010- 1010B IT2 IE2 I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR A0H A8H 2) IEN0 0X00- 0000B EA – ET2 ES ET1 EX1 ET0 EX0 A9H IEN1 XX00- 0000B – – ECT1 ECCM ECT2 ECEM EX2 EADC B0H 2) P3 FFH RD WR T1 T0 INT1 INT0 TxD RxD 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

2)3)P3ANA XX11- 11XX B – – EAN7 EAN6 EAN5 EAN4 – – B1H SYSCON XX10- XXX0 B B8H 2) IP0 XX00- 0000B – – PT2 PS PT1 PX1 PT0 PX0 B9H IP1 XX00- 0000B – – PCT1 PCCM PCT2 PCEM PX2 PADC C0 H 2) WDCON XXXX- 0000B – – – – OWDS WDTS WDT SWDT C1 H CT2CON 0001- 0000B CT2P ECT2O STE2 CT2 RES CT2R CLK2 CLK1 CLK0 C8 H 2) T2CON 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/ RL2 C9 H T2MOD XXXX- XXX0 B CF H TRCON 00 H TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0 D0 H 2) PSW 00H CY AC F0 RS1 RS0 OV F1 P 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

D3 H CP2H XXXX. XX00 B D5 H CMP2H XXXX. XX00 B D6 H CCIE 00 H ECTP ECTC CC2 FEN CC2 REN CC1 FEN CC1 REN CC0 FEN CC0 REN D7 H BCON 00 H BCMP BCEM PWM1 PWM0 EBCE BCERR BCEN BCM1 BCM0 D8 H 2) ADCON0 XX00- 0000B – – IADC BSY ADM MX2 MX1 MX0 DA H ADDATL 00XX- XXXX B DC H ADCON1 01XX- X000B ADCL1 ADCL0 – – – MX2 MX1 MX0 E0H E1H CT1CON 0001- 0000B CTM ETRP STE1 CT1 RES CT1R CLK2 CLK1 CLK0 E2H COINI FF H COUT COUTX I COUT CC2I COUT CC1I COUT CC0I E3H CMSEL0 00 H CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL CMSEL E4H CMSEL1 00 H 0000 CMSEL CMSEL CMSEL CMSEL E5H CCIR 00 H CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R F0H 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d) Addr Register Content after Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Timer/Counter 0 and 1 can be used in four operating modes as listed intable 4. In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate isfOSC /12. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC /24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements.Figure 5 illustrates the input clock logic. Figure 5 Timer/Counter 0 and 1 Input Clock Logic Table 4 Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock Gate C/ T M1 M0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler XX00 fOSC /12 × 32 fOSC /24 × 32 1 16-bit timer/counter X X 1 1 fOSC /12 fOSC /24 2 8-bit timer/counter with 8-bit autoreload XX00 fOSC /12 fOSC /24

3 Timer/counter 0 used as one

8-bit timer/counter and one 8-bit timer Timer 1 stops XX11 fOSC /12 fOSC /24

Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown intable 5. Note: ↓= falling edge Table 5 Timer/Counter 2 Operating Modes Mode T2CON T2MOD DCEN T2CON EXEN P1.1/ T2EX Remarks Input Clock R ×CLK or T×CLK CP/ RL2 TR2 internal external (P1.0/T2) 16-bit Auto- reload X X X reload upon overflow reload trigger (falling edge) Down counting Up counting fOSC /12 max fOSC /24 16-bit Cap- ture X X X 16 bit Timer/ Counter (only up-counting) capture TH2, TL2 → RC2H, RC2L fOSC /12 max fOSC /24 Baud Rate Gene- rator X X X X X no overflow interrupt request (TF2) extra external interrupt (“Timer 2”) fOSC /2 max fOSC /24 off X X 0 X X X Timer 2 stops – –

The Capture / Compare Unit (CCU) of the C504 is built up by a 16-bit 3-channel capture/compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and non- overlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. In capture mode, the value of the compare timer 1 is stored in the capture registers if a signal transition occurs at the pins CCx.Figure 6 shows the block diagram of the CCU. Figure 6 Block Diagram of the CCU

The compare timer 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers which have each a count rate with a maximum offOSC /2 up tofOSC /256. The compare timer operations with its possible compare output signal waveforms are shown infigure 7. Figure 7 Basic Operating Modes of the CAPCOM Unit Compare timer 1 runs only in operating mode 1 with one output signal of selectable signal polarity at the pin COUT3.

Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated intable 6. The possible baudrates can be calculated using the formulas given intable 6. Figure 8 Block Diagram of Baud Rate Generation for the Serial Interface Table 6 USART Operating Modes Mode SCON Baudrate Description SM0 SM1 00 0 fOSC /12 Serial data enters and exits through R×D. T×D outputs the shift clock. 8-bit are transmitted/received (LSB first) 1 0 1 Timer 1/2 overflow rate 8-bit UART 10 bits are transmitted (through T×D) or received (R×D) 21 0 fOSC /32 orfOSC /64 9-bit UART 11 bits are transmitted (T×D) or received (R×D) 3 1 1 Timer 1/2 overflow rate 9-bit UART Like mode 2 except the variable baud rate

The possible baudrates can be calculated using the formulas given in table 7. Table 7 Formulas for Calculating Baudrates Baud Rate derived from Interface Mode Baudrate Oscillator 0 fOSC /12 (2SMOD × fOSC ) / 64 Timer 1 (16-bit timer) (8-bit timer with 8-bit autoreload) 1,3 1,3 (2SMOD × timer 1 overflow rate) /32 (2SMOD × fOSC ) / (32× 12 × (256-TH1)) Timer 2 1,3 fOSC / (32× (65536-(RC2H, RC2L))

The C504 has a high performance 10-bit A/D converter (figure 9) with 8 inputs included which uses successive approximation technique for the conversion of analog input voltages. Figure 9 A/D Converter Block Diagram

The A/D converter uses two clock signals for operation : the conversion clock fADC (= 1/ tADC ) and the input clock fIN (= 1/ tIN). Both clock signals are derived from the C504 system clock fOSC which is applied at the XTAL pins. The duration of an A/D conversion is a multiple of the period of the fIN clock signal. The table infigure 10 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates. Figure 10 A/D Converter Clock Selection The analog inputs are located at port 1 and port 3 (4 lines on each port). The corresponding port 1 and port 3 pins have a port structure, which allows to use it either as digital I/Os or analog inputs. The analog input function of these mixed digital/analog port lines is selected via the registers P1ANA and P3ANA. MCU System Clock Rate (f OSC ) fIN [MHz] Prescaler f ADC [MHz] A/D Conversion Time [µs]Ratio ADCL1 ADCL0 3.5 MHz 1.75 ÷ 4 0 0 .438 48 x t IN = 27.4 12 MHz 6 ÷ 4 0 0 1.5 48 x t IN = 8

16 MHz 8 ÷ 4 0 0 2 48 x t IN = 6

24 MHz 12 ÷ 8 0 1 1.5 96 x t IN = 8

32 MHz 16 ÷ 8 0 1 2 96 x t IN = 6

40 MHz 20 ÷ 16 1 0 1.25 192 x t IN = 9.6

The C504 provides 12 interrupt sources with two priority levels.Figure 11 and12 give a general overview of the interrupt sources and illustrate the interrupt request and control flags. Figure 11 Interrupt Request Sources (Part 1)

Interrupt Request Sources (Part 2)

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low- priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown intable 9. Table 8 Interrupt Vector Addresses Request Flags Interrupt Source Vector Address IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 IADC IE2 TRF, BCERR CT2P CC0F-CC2F, CC0R-CC2R CT1FP, CT1FC External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt A/D converter interrupt External interrupt 2 CAPCOM emergency interrupt Compare timer 2 interrupt Capture / compare match interrupt Compare timer 1 interrupt Power-down interrupt 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 007BH Table 9 Interrupt Source Structure Interrupt Source Priority External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Channel Timer 2 Interrupt A/D Converter External Interrupt 2 CCU Emergency Interrupt Compare Timer 2 Interrupt Capture / Compare Match Interrupt Compare Timer 1 Interrupt High h Low High Priority Low Priority

The C504 offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure. – 15-bit reloadable watchdog timer – Oscillator Watchdog Watchdog Timer The watchdog timer in the C504 is a 15-bit timer, which is incremented by a count rate of either fSOC / 12 or fCYCLE /32. From the 15-bit watchdog timer count value only the upper 7 bits can be programmed.Figure 5 shows the block diagram of the programmable watchdog timer. Figure 13 Block Diagram of the Programmable Watchdog Timer The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be stopped during active mode of the device. If the software fails to refresh the running watchdog timer an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTS in WDCON is set). A refresh of the watchdog timer is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. Therefore, it is possible to use the idle mode in combination with the watchdog timer function.

The oscillator watchdog of the C504 serves for three functions : – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of an auxiliary RC oscillator, the internal clock is supplied by this RC oscillator and the C504 is put into reset state; if the failure condition again disappears, the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. – Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. – Control of external wake-up from software power-down mode When the power-down mode is left by a low level at the INT0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on- chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. Figure 14 Block Diagram of the Programmable Watchdog Timer

Two power down modes are available, the idle mode and power down mode. – In theidle mode the oscillator of the C504 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, and all timers with the exception of the watchdog timer are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. – In the power down mode, the RC oscillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. Table 10gives a general overview of the power saving modes. In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, thatVCC is not reduced before the power down mode is invoked, and thatVCC is restored to its normal operating level, before the power down mode is terminated. The idle mode can be terminated by activating any enabled peripheral interrupt or by resetting the C504. The power down mode can be terminated using an interrupt by a short low pulse at the pin P3.2/AN4/ INT0 or by resetting the C504. If a power saving mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by a reset operation, the microcontroller state is disturbed and replaced by the reset state of the C504. Table 10 Power Saving Modes Overview Mode Entering 2-Instruction Example Leaving by Remarks Idle mode ORL PCON, #01H ORL PCON, #20H Ocurrence of an interrupt from a peripheral unit CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Hardware Reset Power-Down Mode ORL PCON, #02H ORL PCON, #40H Hardware Reset Oscillator is stopped; contents of on-chip RAM and SFR’s are maintained; Wake-up from power down

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC orVIN < VSS ) the Voltage onVCC pins with respect to ground (VSS ) must not exceed the values defined by the absolute maximum ratings.

VCC = 5 V + 10%, – 15%;VSS =0V TA = 0 to 70°C for the SAB-C504 TA = – 40 to 85°C for the SAF-C504 TA = – 40 to 110°C for the SAH-C504 TA = – 40 to 125°C for the SAK-C504 Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (exceptEA, RESET, CTRAP) VIL – 0.5 0.2 VCC – 0.1 Input low voltage (EA) VIL1 – 0.5 0.2 VCC – 0.3 Input low voltage (RESET, CTRAP) VIL2 – 0.5 0.2 VCC + 0.1 Input high voltage (except XTAL1, RESET and CTRAP) VIH 0.2VCC + 0.9 VCC + 0.5 V – Input high voltage to XTAL1 VIH1 0.7VCC VCC + 0.5 V – Input high voltage to RESET and CTRAP VIH2 0.6VCC VCC + 0.5 V – Output low voltage (ports 1, 2, 3, COUT3) VOL – 0.45 V IOL = 1.6 mA1) Output low voltage (port 0, ALE, PSEN) VOL1 – 0.45 V IOL = 3.2 mA1) Output high voltage (ports 1, 2, 3)VOH 2.4 0.9 VCC V IOH =–8 0 µA, IOH =–1 0 µA Output high voltage (ports 1,3 pins in push-pull mode and COUT3) VOH1 0.9VCC –V IOH = – 800µA Output high voltage (port 0 in external bus mode, ALE,PSEN) VOH2 2.4 0.9 VCC V IOH = – 800µA 2), IOH =–8 0 µA 2) Logic 0 input current (ports 1, 2, 3)IIL –1 0 –5 0 µA VIN = 0.45 V Logical 1-to-0 transition current (ports 1, 2, 3) ITL – 65 – 650 µA VIN =2V Input leakage current (port 0,EA) ILI – ± 1 µA 0.45 < VIN < VCC Pin capacitance C IO –1 0 p F fc = 1 MHz, TA =2 5°C Overload current IOV – ± 5m A 7) 8)

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on theVOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address lines are stabilizing. 3) IPD (power-down mode) is measured under following conditions: EA = Port0 =VCC ; RESET =VSS ; XTAL2 = N.C.; XTAL1 =VSS ;VAGND = VSS ; all other pins are disconnected. 4) ICC (active mode) is measured with: XTAL1 driven withtCLCH ,tCHCL = 5 ns ,VIL= VSS + 0.5 V,VIH = VCC – 0.5 V; XTAL2 = N.C.; EA = Port0 = Port1 = RESET =VCC ; all other pins are disconnected.ICC would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven withtCLCH ,tCHCL = 5 ns,VIL= VSS + 0.5 V,VIH = VCC – 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 =VCC ; all other pins are disconnected. 6) ICC max at other frequencies is given by: active mode: TBD idle mode: TBD where fosc is the oscillator frequency in MHz.ICC values are given in mA and measured atVCC =5V . 7) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 8) Not 100 % tested, guaranteed by design characterization. 9) The typical ICC values are periodically measured atTA = +25 ˚C but not 100% tested. Parameter Symbol Limit Values Unit Test Condition typ.9) max. Power supply current: Active mode, 12 MHz4) Idle mode, 12 MHz5) Active mode, 24 MHz4) Idle mode, 24 MHz5) Active mode, 40 MHz4) Idle mode, 40 MHz5) Power-down mode ICC ICC ICC ICC ICC ICC IPD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA µA VCC =5V ,4) VCC =5V ,5) VCC =5V ,4) VCC =5V ,5) VCC =5V ,4) VCC =5V ,5) VCC =2 … 5.5 V3)

A/D Converter Characteristics VCC = 5 V + 10%, – 15%;VSS =0V TA = 0 to 70°C for the SAB-C504 4V≤ VAREF ≤ VCC + 0.1 V; TA = – 40 to 85°C for the SAF-C504 VSS – 0.1 V≤ VAGND ≤ VSS + 0.2 V; TA = – 40 to 110°C for the SAH-C504 TA = – 40 to 125°C for the SAK-C504 Notes see next page. Clock calculation table : Further timing conditions : tADC min = 500 ns tIN = 2 / fOSC = 2 tCLCL Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage VAIN VAGND VAREF V 1) Sample time tS – 64 x tIN 32 xtIN 16 xtIN 8 xtIN ns Prescaler ÷ 32 Prescaler÷ 16 Prescaler÷ 8 Prescaler÷ 4 2) Conversion cycle time tADCC – 384 x tIN 192 xtIN 96 xtIN 48 xtIN ns Prescaler ÷ 32 Prescaler÷ 16 Prescaler÷ 8 Prescaler÷ 4 3) Total unadjusted errorTUE – ± 2 LSB V SS + 0.5V≤ VIN ≤ VCC – 0.5V 4) – ± 4 LSB V SS < VIN < VSS + 0.5V VCC – 0.5V < VIN < VCC Internal resistance of reference voltage source RAREF – tADC / 250 – 0.25 kΩ tADC in [ns]5) 6) Internal resistance of analog source RASRC – tS / 500 – 0.25 kΩ tS in [ns]2) 6) ADC input capacitance C AIN –5 0p F 6) Clock Prescaler Ratio ADCL1, 0 tADC tS tADCC ÷ 32 1 1 32 x t IN 64 x tIN 384 x tIN ÷ 16 1 0 16 x t IN 32 x tIN 192 x tIN ÷ 8 0 1 8 x t IN 16 x tIN 96 x tIN ÷ 4 0 0 4 x t IN 8 x tIN 48 x tIN

Notes: 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH , respectively. 2) During the sample time the input capacitanceC AIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100 % tested, but guaranteed by design characterization.

AC Characteristics for C504-L / C504-2R VCC = 5 V + 10%, – 15%;VSS =0V TA = 0 to 70°C for the SAB-C504 TA = – 40 to 85°C for the SAF-C504 TA = – 40 to 110°C for the SAH-C504 TA = – 40 to 125°C for the SAK-C504 (C L for port 0, ALE and PSEN outputs = 100 pF;C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C504 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit 12-MHz clock Variable Clock 1/tCLCL = 3.5 MHz to

12 MHz

min. max. min. max. ALE pulse width tLHLL 127 – 2 tCLCL –4 0 – n s Address setup to ALE tAVLL 43 – tCLCL –4 0 – n s Address hold after ALE tLLAX 30 – tCLCL –2 3 – n s ALE low to valid instr in tLLIV – 233 – 4 tCLCL – 100 ns ALE toPSEN tLLPL 58 – tCLCL –2 5 – n s PSEN pulse width tPLPH 215 – 3 tCLCL –3 5 – n s PSEN to valid instr in tPLIV – 150 – 3 tCLCL – 100 ns Input instruction hold afterPSEN tPXIX 0 – 0–n s Input instruction float afterPSEN tPXIZ *) –6 3 – tCLCL –2 0 n s Address valid afterPSEN tPXAV *) 75 – tCLCL –8 – n s Address to valid instr in tAVIV – 302 – 5 tCLCL – 115 ns Address float toPSEN tAZPL 0 – 0–n s

AC Characteristics for C504-L / C504-2R (cont’d) External Data Memory Characteristics External Clock Drive Parameter Symbol Limit Values Unit 12-MHz clock Variable Clock 1/tCLCL = 3.5 MHz to min. max. min. max. RD pulse width tRLRH 400 – 6 tCLCL – 100 – ns WR pulse width tWLWH 400 – 6 tCLCL – 100 – ns Address hold after ALE tLLAX2 114 – 2 tCLCL –5 3 – n s RD to valid data in tRLDV – 252 – 5 tCLCL – 165 ns Data hold afterRD tRHDX 0 – 0–n s Data float afterRD tRHDZ –9 7 – 2 tCLCL –7 0 n s ALE to valid data in tLLDV – 517 – 8 tCLCL – 150 ns Address to valid data in tAVDV – 585 – 9 tCLCL – 165 ns ALE toWR or RD tLLWL 200 300 3 tCLCL –5 0 3 tCLCL +5 0 n s Address valid toWR or RD tAVWL 203 – 4 tCLCL – 130 – ns WR or RD high to ALE high tWHLH 43 123 tCLCL –4 0 tCLCL +4 0 n s Data valid toWR transition tQVWX 33 – tCLCL –5 0 – n s Data setup beforeWR tQVWH 433 – 7 tCLCL – 150 – ns Data hold afterWR tWHQX 33 – tCLCL –5 0 – n s Address float afterRD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 12 MHz min. max. Oscillator period tCLCL 83.3 294 ns High time tCHCX 20 tCLCL –tCLCX ns Low time tCLCX 20 tCLCL –tCHCX ns Rise time tCLCH –2 0 n s Fall time tCHCL –2 0 n s

AC Characteristics for C504-L24 / C504-2R24 VCC = 5 V + 10 %, – 15 %;VSS =0V TA = 0 to 70°C for the SAB-C504 TA = – 40 to 85°C for the SAF-C504 (C L for port 0, ALE and PSEN outputs = 100 pF;C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C504 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit 24-MHz clock Variable Clock 1/tCLCL = 3.5 MHz to

24 MHz

min. max. min. max. ALE pulse width tLHLL 43 – 2 tCLCL –4 0 – n s Address setup to ALE tAVLL 17 – tCLCL –2 5 – n s Address hold after ALE tLLAX 17 – tCLCL –2 5 – n s ALE low to valid instr in tLLIV –8 0 – 4 tCLCL –8 7 n s ALE toPSEN tLLPL 22 – tCLCL –2 0 – n s PSEN pulse width tPLPH 95 – 3 tCLCL –3 0 – n s PSEN to valid instr in tPLIV –6 0 – 3 tCLCL –6 5 n s Input instruction hold afterPSEN tPXIX 0 – 0–n s Input instruction float afterPSEN tPXIZ *) –3 2 – tCLCL –1 0 n s Address valid afterPSEN tPXAV *) 37 – tCLCL –5 – n s Address to valid instr in tAVIV – 148 – 5 tCLCL –6 0 n s Address float toPSEN tAZPL 0 – 0–n s

AC Characteristics for C504-L24 / C504-2R24 (cont’d) External Data Memory Characteristics External Clock Drive Parameter Symbol Limit Values Unit 24-MHz clock Variable Clock 1/tCLCL = 3.5 MHz to min. max. min. max. RD pulse width tRLRH 180 – 6 tCLCL –7 0 – n s WR pulse width tWLWH 180 – 6 tCLCL –7 0 – n s Address hold after ALE tLLAX2 56 – 2 tCLCL –2 7 – n s RD to valid data in tRLDV – 118 – 5 tCLCL –9 0 n s Data hold afterRD tRHDX 0 0–n s Data float afterRD tRHDZ –6 3 – 2 tCLCL –2 0 n s ALE to valid data in tLLDV – 200 – 8 tCLCL – 133 ns Address to valid data in tAVDV – 220 – 9 tCLCL – 155 ns ALE toWR or RD tLLWL 75 175 3 tCLCL –5 0 3 tCLCL +5 0 n s Address valid toWR tAVWL 67 – 4 tCLCL –9 7 – n s WR or RD high to ALE high tWHLH 17 67 tCLCL –2 5 tCLCL +2 5 n s Data valid toWR transition tQVWX 5– tCLCL –3 7 – n s Data setup beforeWR tQVWH 170 – 7 tCLCL – 122 – ns Data hold afterWR tWHQX 15 – tCLCL –2 7 – n s Address float afterRD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 24 MHz min. max. Oscillator period tCLCL 41.7 294 ns High time tCHCX 12 tCLCL –tCLCX ns Low time tCLCX 12 tCLCL –tCHCX ns Rise time tCLCH –1 2 n s Fall time tCHCL –1 2 n s

AC Characteristics for C504-L40 / C504-2R40 VCC = 5 V + 10 %, – 15 %;VSS =0V TA = 0 to 70°C for the SAB-C504 TA = – 40 to 85°C for the SAF-C504 (C L for port 0, ALE and PSEN outputs = 100 pF;C L for all other outputs = 80 pF) Program Memory Characteristics *) Interfacing the C504 to devices with float times up to 25 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Parameter Symbol Limit Values Unit 40-MHz clock Variable Clock 1/tCLCL = 3.5 MHz to

40 MHz

min. max. min. max. ALE pulse width tLHLL 35 – 2 tCLCL –1 5 – n s Address setup to ALE tAVLL 10 – tCLCL –1 5 – n s Address hold after ALE tLLAX 10 – tCLCL –1 5 – n s ALE low to valid instr in tLLIV –5 5 – 4 tCLCL –4 5 n s ALE toPSEN tLLPL 10 – tCLCL –1 5 – n s PSEN pulse width tPLPH 60 – 3 tCLCL –1 5 – n s PSEN to valid instr in tPLIV –2 5 – 3 tCLCL –5 0 n s Input instruction hold afterPSEN tPXIX 0 – 0–n s Input instruction float afterPSEN tPXIZ *) –2 0 – tCLCL –5 n s Address valid afterPSEN tPXAV *) 20 – tCLCL –5 – n s Address to valid instr in tAVIV –6 5 – 5 tCLCL –6 0 n s Address float toPSEN tAZPL – 5 – – 5 – ns

AC Characteristics for C504-L40 / C504-2R40(cont’d) External Data Memory Characteristics External Clock Drive Parameter Symbol Limit Values Unit 40-MHz clock Variable Clock 1/tCLCL = 3.5 MHz to min. max. min. max. RD pulse width tRLRH 120 – 6 tCLCL –3 0 – n s WR pulse width tWLWH 120 – 6 tCLCL –3 0 – n s Address hold after ALE tLLAX2 35 – 2 tCLCL –1 5 – n s RD to valid data in tRLDV –7 5 – 5 tCLCL –5 0 n s Data hold afterRD tRHDX 0 0–n s Data float afterRD tRHDZ –3 8 – 2 tCLCL –1 2 n s ALE to valid data in tLLDV – 150 – 8 tCLCL –5 0 n s Address to valid data in tAVDV – 150 – 9 tCLCL –7 5 n s ALE toWR or RD tLLWL 60 90 3 tCLCL –1 5 3 tCLCL +1 5 n s Address valid toWR tAVWL 70 – 4 tCLCL –3 0 – n s WR or RD high to ALE high tWHLH 10 40 tCLCL –1 5 tCLCL +1 5 n s Data valid toWR transition tQVWX 5– tCLCL –2 0 – n s Data setup beforeWR tQVWH 125 – 7 tCLCL –5 0 – n s Data hold afterWR tWHQX 5– tCLCL –2 0 – n s Address float afterRD tRLAZ – 0 –0n s Parameter Symbol Limit Values Unit Variable Clock Freq. = 3.5 MHz to 40 MHz min. max. Oscillator period tCLCL 25 294 ns High time tCHCX 10 tCLCL –tCLCX ns Low time tCLCX 10 tCLCL –tCHCX ns Rise time tCLCH –1 0 n s Fall time tCHCL –1 0 n s

ROM Verification Characteristics for C504-2R ROM Verification Mode 1 Figure 19 ROM Verification Mode 1 Parameter Symbol Limit Values Unit min. max. Address to valid data tAVQV –4 8 tCLCL ns ENABLE to valid data tELQV –4 8 tCLCL ns Data float after ENABLE tEHQZ 04 8 tCLCL ns Oscillator frequency 1/tCLCL 4 6 MHz

Parameter Symbol Limit Values Unit min. typ max. ALE pulse width tAWD –2 tCLCL –n s ALE period tACY –1 2 tCLCL –n s Data valid after ALE tDVA ––4 tCLCL ns Data stable after ALE tDSA 8 tCLCL ––n s P3.5 setup to ALE low tAS – tCLCL –n s Oscillator frequency 1/tCLCL 4–6M H z