Microcontroller

C167SR

Siemens Semiconductor G...

16-Bit CMOS Single-Chip Microcontroller

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Data Sheet 06.95 Advance Information Microcomputer Components C167SR 16-Bit CMOS Single-Chip Microcontroller

Edition 06.95 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73,

81541 München

© Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third par- ties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within com- ponents or assemblies. The information describes the type of compo- nent and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For in- formation on the types in question please contact your nearest Siemens Office, Semi- conductor Group. Siemens AG is an approved CECC manufac- turer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems 2 with the ex- press written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used

in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support de- vice or system, or to affect its safety or ef- fectiveness of that device or system.

2 Life support devices or systems are in-

tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. Ausgabe 06.95 Herausgegeben von Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, © Siemens AG 1995. Alle Rechte vorbehalten. Wichtige Hinweise! Gewähr für die Freiheit von Rechten Dritter leisten wir nur für Bauelemente selbst, nicht für Anwendungen, Verfahren und für die in Bauelementen oder Baugruppen realisierten Schaltungen. Mit den Angaben werden die Bauelemente spezifiziert, nicht Eigenschaften zugesichert. Liefermöglichkeiten und technische Änderun- gen vorbehalten. Fragen über Technik, Preise und Liefermög- lichkeiten richten Sie bitte an den Ihnen nächstgelegenen Vertrieb Halbleiter in Deutschland oder an unsere Landesgesell- schaften im Ausland. Bauelemente können aufgrund technischer Erfordernisse Gefahrstoffe enthalten. Aus- künfte darüber bitten wir unter Angabe des betreffenden Typs ebenfalls über den Vertrieb Halbleiter einzuholen. Die Siemens AG ist ein Hersteller von CECC- qualifizierten Produkten. Verpackung Bitte benutzen Sie die Ihnen bekannten Ver- werter. Wir helfen Ihnen auch weiter – wen- den Sie sich an Ihren für Sie zuständigen Ver- trieb Halbleiter. Nach Rücksprache nehmen wir Verpackungsmaterial sortiert zurück. Die Transportkosten müssen Sie tragen. Für Verpackungsmaterial, das unsortiert an uns zurückgeliefert wird oder für das wir keine Rücknahmepflicht haben, müssen wir Ihnen die anfallenden Kosten in Rechnung stellen. Bausteine in lebenserhaltenden Geräten oder Systemen müssen ausdrücklich da- für zugelassen sein! Kritische Bauelemente 1 des Bereichs Halblei- ter der Siemens AG dürfen nur mit ausdrückli- cher schriftlicher Genehmigung des Bereichs Halbleiter der Siemens AG in lebenserhalten- den Geräten oder Systemen 2 eingesetzt wer- den.

1 Ein kritisches Bauelement ist ein in einem

lebenserhaltenden Gerät oder System ein- gesetztes Bauelement, bei dessen Ausfall berechtigter Grund zur Annahme besteht, daß das lebenserhaltende Gerät oder Sy- stem ausfällt bzw. dessen Sicherheit oder Wirksamkeit beeinträchtigt wird.

2 Lebenserhaltende Geräte und Systeme

sind (a) zur chirurgischen Einpflanzung in den menschlichen Körper gedacht, oder (b) unterstützen bzw. erhalten das menschliche Leben. Sollten sie ausfallen, besteht berechtigter Grund zur Annahme, daß die Gesundheit des Anwenders ge- fährdet werden kann.

Revision History: Original Version: 06.95 (Advance Information) Previous Releases: Data Sheet C167 06.94 Page Subjects (changes compared to C167)

31 Register PICON added

VILS,VIHS, HYS,IOV added. 36 RRST ,IRWH ,IRWL ,IALEL ,IALEH ,IP6H , test cond.IOZx changed. 37 IP6L,ICC ,IID changed.

37 ICC ,IID typical values added

39 ADC specification changed. 41...43 PLL description added. 44 External Clock Drive specification changed. t14,t15,t16,t17,t22,t39,t46 changed. 47 t47 changed. 52 t14,t15,t16,t17,t20,t21, t22 changed. 53 t39,t46,t47,t55 changed. 56, 57 t53 changed tot68. 58 t36 changed. 61 t63 changed.

Semiconductor Group 1 06.95 l High Performance 16-bit CPU with 4-Stage Pipeline l 100 ns Instruction Cycle Time at 20 MHz CPU Clock l 500 ns Multiplication (16 · 16 bit), 1 ms Division (32 / 16 bit) l Enhanced Boolean Bit Manipulation Facilities l Additional Instructions to Support HLL and Operating Systems l Register-Based Design with Multiple Variable Register Banks l Single-Cycle Context Switching Support l Clock Generation via on-chip PLL or via direct clock input l Up to 16 MBytes Linear Address Space for Code and Data l 2 KBytes On-Chip Internal RAM (IRAM) l 2 KBytes On-Chip Extension RAM (XRAM) l Programmable External Bus Characteristics for Different Address Ranges l 8-Bit or 16-Bit External Data Bus l Multiplexed or Demultiplexed External Address/Data Buses l Five Programmable Chip-Select Signals l Hold- and Hold-Acknowledge Bus Arbitration Support l 1024 Bytes On-Chip Special Function Register Area l Idle and Power Down Modes l 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) l 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns l 16-Channel 10-bit A/D Converter with 9.7 ms Conversion Time l Two 16-Channel Capture/Compare Units l 4-Channel PWM Unit l Two Multi-Functional General Purpose Timer Units with 5 Timers l Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) l Programmable Watchdog Timer l Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis l Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards l On-Chip Bootstrap Loader l 144-Pin MQFP Package (EIAJ) This document describes the SAB-C167SR-LM , the SAF-C167SR-LM and the SAK-C167SR-LM . For simplicity all versions are referred to by the term C167SR throughout this document. C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Advance Information C167SR 16-Bit Microcontroller C167SR

Revision History: Original Version: 06.95 (Advance Information) Previous Releases: Data Sheet C167 06.94 Page Subjects (changes compared to C167) VILS, VIHS, HYS, IOV added. 36 RRST , IRWH , IRWL , IALEL , IALEH , IP6H , test cond. IOZx changed. 37 IP6L, ICC , IID changed.

37 ICC , IID typical values added

39 ADC specification changed. 41...43 PLL description added. 44 External Clock Drive specification changed. t14, t15, t16, t17, t22, t39, t46 changed. 47 t47 changed. 52 t14, t15, t16, t17, t20, t21, t22 changed. 53 t39, t46, t47, t55 changed. 56, 57 t53 changed to t68. 58 t36 changed. 61 t63 changed.

The C167SR is a new derivative of the Siemens C16x Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip high-speed RAM and clock generation via PLL. Figure 1 Logic Symbol

Ordering Information

Type Ordering Code Package Function SAB-C167SR-LM Q67121-C952 P-MQFP-144-1 16-bit microcontroller with 2 · 2 KByte RAM Temperature range 0 to + 70 ˚C SAF-C167SR-LM Q67121-C953 P-MQFP-144-1 16-bit microcontroller with 2 · 2 KByte RAM Temperature range – 40 to + 85 ˚C SAK-C167SR-LM C P-MQFP-144-1 16-bit microcontroller with 2 · 2 KByte RAM Temperature range – 40 to + 125 ˚C C167SR

(top view) Figure 2 C167SR

Pin Definitions and Functions Symbol Pin Number Input (I) Output (O) Function P6.0 - P6.7 1 - ... I/O O ... O I O O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The following Port 6 pins also serve for alternate functions: P6.0 CS0 Chip Select 0 Output P6.4 CS4 Chip Select 4 Output P6.5 HOLD External Master Hold Request Input P6.6 HLDA Hold Acknowledge Output P6.7 BREQ Bus Request Output P8.0 - P8.7 9 - ... I/O I/O ... I/O Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins also serve for alternate functions: P8.0 CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out P8.7 CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out P7.0 - P7.7 19 - ... ... I/O O ... O I/O ... I/O Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: P7.0 POUT0 PWM Channel 0 Output P7.3 POUT3 PWM Channel 3 Output P7.4 CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out P7.7 CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out

P5.0 - P5.15 27 - 36 39 - 44 I I I I I I I I Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input P5.11 T5EUD GPT2 Timer T5 Ext.Up/Down Ctrl.Input P5.12 T6IN GPT2 Timer T6 Count Input P5.13 T5IN GPT2 Timer T5 Count Input P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T2 Ext.Up/Down Ctrl.Input P2.0 - P2.15 47 - 54 57 - 64 ... ... I/O I/O ... I/O I/O I ... I/O I I Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: P2.0 CC0IO CAPCOM: CC0 Cap.-In/Comp.Out P2.7 CC7IO CAPCOM: CC7 Cap.-In/Comp.Out P2.8 CC8IO CAPCOM: CC8 Cap.-In/Comp.Out, EX0IN Fast External Interrupt 0 Input P2.15 CC15IO CAPCOM: CC15 Cap.-In/Comp.Out, EX7IN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input Pin Definitions and Functions (cont’d) Symbol Pin Number Input (I) Output (O) Function

P3.0 - P3.13, P3.15 65 - 70, 73 - 80, I/O I/O I/O I O I O I I I I I/O I/O O I/O O O I/O O Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: P3.0 T0IN CAPCOM Timer T0 Count Input P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 T ·D0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 R ·D0 ASC0 Data Input (Asyn.) or I/O (Syn.) P3.12 BHE Ext. Memory High Byte Enable Signal, WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) P4.0 - P4.7 85 - 92 ... ... I/O O ... O ... O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line P4.4 A20 Least Significant Segment Addr. Line .. : : P4.7 A23 Most Significant Segment Addr. Line RD 95 O External Memory Read Strobe. RD is activated for every external instruction or data read access. Pin Definitions and Functions (cont’d) Symbol Pin Number Input (I) Output (O) Function

96 O External Memory Write Strobe. In WR -mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16- bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. READY 97 I Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ALE 98 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 99 I External Access Enable pin. A low level at this pin during and after Reset forces the C167SR to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. ROMless versions must have this pin tied to ‘0’. PORT0: P0L.0 - P0L.7, P0H.0 - P0H.7 100 - 107 108, 111-117 I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0- P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 Pin Definitions and Functions (cont’d) Symbol Pin Number Input (I) Output (O) Function

PORT1: P1L.0 - P1L.7, P1H.0 - P1H.7 118 - 125 128 - 135 132 133 134 135 I/O I I I I PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 CC24IO CAPCOM2: CC24 Capture Input P1H.5 CC25IO CAPCOM2: CC25 Capture Input P1H.6 CC26IO CAPCOM2: CC26 Capture Input P1H.7 CC27IO CAPCOM2: CC27 Capture Input XTAL1 XTAL2 138 137 I O XTAL1: Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. RSTIN 140 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C167SR. An internal pullup resistor permits power- on reset using only a capacitor connected to VSS . RSTOUT 141 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167SR to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. VAREF 37 – Reference voltage for the A/D converter. VAGND 38 – Reference ground for the A/D converter. VPP 84 – Flash programming voltage. This pin accepts the programming voltage for flash versions of the C167SR. Note: This pin is not connected (NC ) on non-flash versions. Pin Definitions and Functions (cont’d) Symbol Pin Number Input (I) Output (O) Function

VCC 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 – Digital Supply Voltage: + 5 V during normal operation and idle mode. ‡ 2.5 V during power down mode. VSS 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 – Digital Ground. Pin Definitions and Functions (cont’d) Symbol Pin Number Input (I) Output (O) Function

The architecture of the C167SR combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167SR. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). Figure 3 Block Diagram

The memory space of the C167SR is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C167SR is prepared to incorporate on-chip mask-programmable ROM or Flash Memory for code or constant data. Currently no ROM is integrated.

2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the

system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 · 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C16x family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: – 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri- State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Up to 5 external CS signals can be generated in order to save external glue logic. Access to very slow memories is supported via a particular ‘Ready’ function. A HOLD /HLDA protocol is available for bus arbitration. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C167SR’s instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 · 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. Figure 4 CPU Block Diagram

The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C167SR instruction set which includes the following instruction classes: – Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C167SR is capable of reacting very fast to the occurence of non- deterministic events. The architecture of the C167SR supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C167SR has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible C167SR interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Note: Three nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.

CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040 H 10H CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044 H 11H CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048 H 12H CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004C H 13H CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050 H 14H CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054 H 15H CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058 H 16H CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005C H 17H CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060 H 18H CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064 H 19H CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068 H 1AH CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006C H 1BH CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070 H 1C H CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074 H 1D H CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078 H 1EH CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007C H 1FH CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0 H 30H CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4 H 31H CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8 H 32H CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CC H 33H CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0 H 34H CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4 H 35H CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8 H 36H CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DC H 37H CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0 H 38H CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4 H 39H CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8 H 3AH CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00EC H 3BH CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00E0 H 3C H CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110 H 44H CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114 H 45H CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118 H 46H CAPCOM Timer 0 T0IR T0IE T0INT 00’0080 H 20H

CAPCOM Timer 1 T1IR T1IE T1INT 00’0084 H 21H CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4 H 3D H CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8 H 3EH GPT1 Timer 2 T2IR T2IE T2INT 00’0088 H 22H GPT1 Timer 3 T3IR T3IE T3INT 00’008C H 23H GPT1 Timer 4 T4IR T4IE T4INT 00’0090 H 24H GPT2 Timer 5 T5IR T5IE T5INT 00’0094 H 25H GPT2 Timer 6 T6IR T6IE T6INT 00’0098 H 26H GPT2 CAPREL Register CRIR CRIE CRINT 00’009C H 27H A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0 H 28H A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4 H 29H ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8 H 2AH ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C H 47H ASC0 Receive S0RIR S0RIE S0RINT 00’00AC H 2BH ASC0 Error S0EIR S0EIE S0EINT 00’00B0 H 2C H SSC Transmit SCTIR SCTIE SCTINT 00’00B4 H 2D H SSC Receive SCRIR SCRIE SCRINT 00’00B8 H 2EH SSC Error SCEIR SCEIE SCEINT 00’00BC H 2FH PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FC H 3FH X-Peripheral Node XP0IR XP0IE XP0INT 00’0100 H 40H X-Peripheral Node XP1IR XP1IE XP1INT 00’0104 H 41H X-Peripheral Node XP2IR XP2IE XP2INT 00’0108 H 42H PLL Unlock XP3IR XP3IE XP3INT 00’010C H 43H Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number

The C167SR also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run- time: Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow RESET RESET RESET 00’0000 H 00’0000H 00’0000H 00H 00H 00H III III III Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008 H 00’0010H 00’0018H 02H 04H 06H II II II Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028 H 00’0028H 00’0028H 00’0028H 00’0028H 0AH 0AH 0AH 0AH 0AH I I I I I Reserved [2C H – 3CH ] [0BH – 0FH ] Software Traps TRAP Instruction Any [00’0000H – 00’01FCH ] in steps of 4 H Any [00 H – 7FH ] Current CPU Priority

Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 400 ns (at 20-MHz system clock). The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (‘capture’d) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated Double Register Mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.

*) 12 outputs on CAPCOM2

The Pulse Width Modulation Module can generate up to four PWM output signals using edge- aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM signals covers 4.8 Hz to 1 MHz (referred to a CPU clock of 20 MHz), depending on the resolution of the PWM output signal. The level of the output signals is selectable and the PWM module can generate interrupt requests. General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20-MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking. Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer over- flow/underflow. The state of these latches may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. Figure 6 Block Diagram of GPT1

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 ms and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz).

For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C167SR supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). ASC0 is upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 KBaud and half-duplex synchronous communication up to 2.5 Mbaud on the @ 20-MHz system clock. The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20-MHz system clock. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel.

In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. Parallel Ports The C167SR provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ , HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. All port lines that are not used for these alternate functions may be used as general purpose IO lines.

The table below lists the instructions of the C167SR in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C16x Family Instruction Set Manual”. This document also provides a detailled description of each instruction. Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2

MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand. with zero extension 2 / 4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack und update register with word operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI -pin being low) SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2 Instruction Set Summary (cont’d) Mnemonic Description Bytes

Special Function Registers Overview The following table lists all SFRs which are implemented in the C167SR in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Special Function Registers Overview Name Physical Address 8-Bit Address Description Reset Value ADCIC b FF98 H CC H A/D Converter End of Conversion Interrupt Control Register 0000H ADCON b FFA0 H D0 H A/D Converter Control Register 0000 H ADDAT FEA0 H 50H A/D Converter Result Register 0000 H ADDAT2 F0A0 H E 50H A/D Converter 2 Result Register 0000 H ADDRSEL1 FE18 H 0C H Address Select Register 1 0000 H ADDRSEL2 FE1A H 0D H Address Select Register 2 0000 H ADDRSEL3 FE1C H 0EH Address Select Register 3 0000 H ADDRSEL4 FE1E H 0FH Address Select Register 4 0000 H ADEIC b FF9A H CD H A/D Converter Overrun Error Interrupt Control Register 0000H BUSCON0 b FF0C H 86H Bus Configuration Register 0 0XX0 H BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000 H BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000 H BUSCON3 b FF18H 8C H Bus Configuration Register 3 0000 H BUSCON4 b FF1A H 8D H Bus Configuration Register 4 0000 H CAPREL FE4A H 25H GPT2 Capture/Reload Register 0000 H CC0 FE80 H 40H CAPCOM Register 0 0000 H CC0IC b FF78H BC H CAPCOM Register 0 Interrupt Control Register 0000H CC1 FE82 H 41H CAPCOM Register 1 0000 H CC1IC b FF7A H BD H CAPCOM Register 1 Interrupt Control Register 0000H CC2 FE84 H 42H CAPCOM Register 2 0000 H CC2IC b FF7C H BE H CAPCOM Register 2 Interrupt Control Register 0000H

CC3 FE86 H 43H CAPCOM Register 3 0000 H CC3IC b FF7E H BF H CAPCOM Register 3 Interrupt Control Register 0000H CC4 FE88 H 44H CAPCOM Register 4 0000 H CC4IC b FF80H C0 H CAPCOM Register 4 Interrupt Control Register 0000H CC5 FE8A H 45H CAPCOM Register 5 0000 H CC5IC b FF82H C1 H CAPCOM Register 5 Interrupt Control Register 0000H CC6 FE8C H 46H CAPCOM Register 6 0000 H CC6IC b FF84H C2 H CAPCOM Register 6 Interrupt Control Register 0000H CC7 FE8E H 47H CAPCOM Register 7 0000 H CC7IC b FF86H C3 H CAPCOM Register 7 Interrupt Control Register 0000H CC8 FE90 H 48H CAPCOM Register 8 0000 H CC8IC b FF88H C4 H CAPCOM Register 8 Interrupt Control Register 0000H CC9 FE92 H 49H CAPCOM Register 9 0000 H CC9IC b FF8A H C5 H CAPCOM Register 9 Interrupt Control Register 0000H CC10 FE94 H 4AH CAPCOM Register 10 0000 H CC10IC b FF8C H C6 H CAPCOM Register 10 Interrupt Control Register 0000H CC11 FE96 H 4BH CAPCOM Register 11 0000 H CC11IC b FF8E H C7 H CAPCOM Register 11 Interrupt Control Register 0000H CC12 FE98 H 4C H CAPCOM Register 12 0000 H CC12IC b FF90H C8 H CAPCOM Register 12 Interrupt Control Register 0000H CC13 FE9A H 4D H CAPCOM Register 13 0000 H CC13IC b FF92H C9 H CAPCOM Register 13 Interrupt Control Register 0000H CC14 FE9C H 4EH CAPCOM Register 14 0000 H CC14IC b FF94H CA H CAPCOM Register 14 Interrupt Control Register 0000H CC15 FE9E H 4FH CAPCOM Register 15 0000 H CC15IC b FF96H CB H CAPCOM Register 15 Interrupt Control Register 0000H CC16 FE60 H 30H CAPCOM Register 16 0000 H CC16IC b F160H E B0H CAPCOM Register 16 Interrupt Control Register 0000H CC17 FE62 H 31H CAPCOM Register 17 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

CC17IC b F162H E B1H CAPCOM Register 17 Interrupt Control Register 0000H CC18 FE64 H 32H CAPCOM Register 18 0000 H CC18IC b F164H E B2H CAPCOM Register 18 Interrupt Control Register 0000H CC19 FE66 H 33H CAPCOM Register 19 0000 H CC19IC b F166H E B3H CAPCOM Register 19 Interrupt Control Register 0000H CC20 FE68 H 34H CAPCOM Register 20 0000 H CC20IC b F168H E B4H CAPCOM Register 20 Interrupt Control Register 0000H CC21 FE6A H 35H CAPCOM Register 21 0000 H CC21IC b F16A H E B5H CAPCOM Register 21 Interrupt Control Register 0000H CC22 FE6C H 36H CAPCOM Register 22 0000 H CC22IC b F16C H E B6H CAPCOM Register 22 Interrupt Control Register 0000H CC23 FE6E H 37H CAPCOM Register 23 0000 H CC23IC b F16E H E B7H CAPCOM Register 23 Interrupt Control Register 0000H CC24 FE70 H 38H CAPCOM Register 24 0000 H CC24IC b F170H E B8H CAPCOM Register 24 Interrupt Control Register 0000H CC25 FE72 H 39H CAPCOM Register 25 0000 H CC25IC b F172H E B9H CAPCOM Register 25 Interrupt Control Register 0000H CC26 FE74 H 3AH CAPCOM Register 26 0000 H CC26IC b F174H E BA H CAPCOM Register 26 Interrupt Control Register 0000H CC27 FE76 H 3BH CAPCOM Register 27 0000 H CC27IC b F176H E BB H CAPCOM Register 27 Interrupt Control Register 0000H CC28 FE78 H 3C H CAPCOM Register 28 0000 H CC28IC b F178H E BC H CAPCOM Register 28 Interrupt Control Register 0000H CC29 FE7A H 3D H CAPCOM Register 29 0000 H CC29IC b F184H E C2 H CAPCOM Register 29 Interrupt Control Register 0000H CC30 FE7C H 3EH CAPCOM Register 30 0000 H CC30IC b F18C H E C6 H CAPCOM Register 30 Interrupt Control Register 0000H CC31 FE7E H 3FH CAPCOM Register 31 0000 H CC31IC b F194H E CA H CAPCOM Register 31 Interrupt Control Register 0000H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

CCM0 b FF52H A9H CAPCOM Mode Control Register 0 0000 H CCM1 b FF54H AA H CAPCOM Mode Control Register 1 0000 H CCM2 b FF56H AB H CAPCOM Mode Control Register 2 0000 H CCM3 b FF58H AC H CAPCOM Mode Control Register 3 0000 H CCM4 b FF22H 91H CAPCOM Mode Control Register 4 0000 H CCM5 b FF24H 92H CAPCOM Mode Control Register 5 0000 H CCM6 b FF26H 93H CAPCOM Mode Control Register 6 0000 H CCM7 b FF28H 94H CAPCOM Mode Control Register 7 0000 H CP FE10 H 08H CPU Context Pointer Register FC00 H CRIC b FF6A H B5H GPT2 CAPREL Interrupt Control Register 0000 H CSP FE08 H 04H CPU Code Segment Pointer Register (read only) 0000H DP0L b F100H E 80H P0L Direction Control Register 00 H DP0H b F102H E 81H P0H Direction Control Register 00 H DP1L b F104H E 82H P1L Direction Control Register 00 H DP1H b F106H E 83H P1H Direction Control Register 00 H DP2 b FFC2 H E1H Port 2 Direction Control Register 0000 H DP3 b FFC6 H E3H Port 3 Direction Control Register 0000 H DP4 b FFCA H E5H Port 4 Direction Control Register 00 H DP6 b FFCE H E7H Port 6 Direction Control Register 00 H DP7 b FFD2 H E9H Port 7 Direction Control Register 00 H DP8 b FFD6 H EB H Port 8 Direction Control Register 00 H DPP0 FE00 H 00H CPU Data Page Pointer 0 Register (10 bits) 0000H DPP1 FE02 H 01H CPU Data Page Pointer 1 Register (10 bits) 0001H DPP2 FE04 H 02H CPU Data Page Pointer 2 Register (10 bits) 0002H DPP3 FE06 H 03H CPU Data Page Pointer 3 Register (10 bits) 0003H EXICON b F1C0 H E E0H External Interrupt Control Register 0000 H MDC b FF0E H 87H CPU Multiply Divide Control Register 0000 H MDH FE0C H 06H CPU Multiply Divide Register – High Word 0000H MDL FE0E H 07H CPU Multiply Divide Register – Low Word 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

ODP2 b F1C2 H E E1H Port 2 Open Drain Control Register 0000 H ODP3 b F1C6 H E E3H Port 3 Open Drain Control Register 0000 H ODP6 b F1CE H E E7H Port 6 Open Drain Control Register 00 H ODP7 b F1D2 H E E9H Port 7 Open Drain Control Register 00 H ODP8 b F1D6 H E EB H Port 8 Open Drain Control Register 00 H ONES FF1E H 8FH Constant Value 1’s Register (read only) FFFF H P0L b FF00H 80H Port 0 Low Register (Lower half of PORT0) 00H P0H b FF02H 81H Port 0 High Register (Upper half of PORT0) 00H P1L b FF04H 82H Port 1 Low Register (Lower half of PORT1) 00H P1H b FF06H 83H Port 1 High Register (Upper half of PORT1) 00H P2 b FFC0 H E0H Port 2 Register 0000 H P3 b FFC4 H E2H Port 3 Register 0000 H P4 b FFC8 H E4H Port 4 Register (8 bits) 00 H P5 b FFA2 H D1 H Port 5 Register (read only) XXXX H P6 b FFCC H E6H Port 6 Register (8 bits) 00 H P7 b FFD0 H E8H Port 7 Register (8 bits) 00 H P8 b FFD4 H EA H Port 8 Register (8 bits) 00 H PECC0 FEC0 H 60H PEC Channel 0 Control Register 0000 H PECC1 FEC2 H 61H PEC Channel 1 Control Register 0000 H PECC2 FEC4 H 62H PEC Channel 2 Control Register 0000 H PECC3 FEC6 H 63H PEC Channel 3 Control Register 0000 H PECC4 FEC8 H 64H PEC Channel 4 Control Register 0000 H PECC5 FECA H 65H PEC Channel 5 Control Register 0000 H PECC6 FECC H 66H PEC Channel 6 Control Register 0000 H PECC7 FECE H 67H PEC Channel 7 Control Register 0000 H PICON F1C4 H E E2H Port Input Threshold Control Register 0000 H PP0 F038H E 1C H PWM Module Period Register 0 0000 H PP1 F03A H E 1D H PWM Module Period Register 1 0000 H PP2 F03C H E 1EH PWM Module Period Register 2 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

PP3 F03E H E 1FH PWM Module Period Register 3 0000 H PSW b FF10H 88H CPU Program Status Word 0000 H PT0 F030H E 18H PWM Module Up/Down Counter 0 0000 H PT1 F032H E 19H PWM Module Up/Down Counter 1 0000 H PT2 F034H E 1AH PWM Module Up/Down Counter 2 0000 H PT3 F036H E 1BH PWM Module Up/Down Counter 3 0000 H PW0 FE30 H 18H PWM Module Pulse Width Register 0 0000 H PW1 FE32 H 19H PWM Module Pulse Width Register 1 0000 H PW2 FE34 H 1AH PWM Module Pulse Width Register 2 0000 H PW3 FE36 H 1BH PWM Module Pulse Width Register 3 0000 H PWMCON0 b FF30H 98H PWM Module Control Register 0 0000 H PWMCON1 b FF32H 99H PWM Module Control Register 1 0000 H PWMIC b F17E H E BF H PWM Module Interrupt Control Register 0000 H RP0H b F108H E 84H System Startup Configuration Register (Rd. only) XXH S0BG FEB4 H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0 H D8 H Serial Channel 0 Control Register 0000 H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Control Register 0000H S0RBUF FEB2 H 59H Serial Channel 0 Receive Buffer Register (read only) XX H S0RIC b FF6E H B7H Serial Channel 0 Receive Interrupt Control Register 0000H S0TBIC b F19C H E CE H Serial Channel 0 Transmit Buffer Interrupt Control Register 0000H S0TBUF FEB0 H 58H Serial Channel 0 Transmit Buffer Register (write only) 00H S0TIC b FF6C H B6H Serial Channel 0 Transmit Interrupt Control Register 0000H SP FE12 H 09H CPU System Stack Pointer Register FC00 H SSCBR F0B4 H E 5AH SSC Baudrate Register 0000 H SSCCON b FFB2 H D9 H SSC Control Register 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

SSCEIC b FF76H BB H SSC Error Interrupt Control Register 0000 H SSCRB F0B2 H E 59H SSC Receive Buffer (read only) XXXX H SSCRIC b FF74H BA H SSC Receive Interrupt Control Register 0000 H SSCTB F0B0 H E 58H SSC Transmit Buffer (write only) 0000 H SSCTIC b FF72H B9H SSC Transmit Interrupt Control Register 0000 H STKOV FE14 H 0AH CPU Stack Overflow Pointer Register FA00 H STKUN FE16 H 0BH CPU Stack Underflow Pointer Register FC00 H SYSCON b FF12H 89H CPU System Configuration Register 0xx0 H T0 FE50 H 28H CAPCOM Timer 0 Register 0000 H T01CON b FF50H A8H CAPCOM Timer 0 and Timer 1 Control Register 0000H T0IC b FF9C H CE H CAPCOM Timer 0 Interrupt Control Register 0000H T0REL FE54 H 2AH CAPCOM Timer 0 Reload Register 0000 H T1 FE52 H 29H CAPCOM Timer 1 Register 0000 H T1IC b FF9E H CF H CAPCOM Timer 1 Interrupt Control Register 0000H T1REL FE56 H 2BH CAPCOM Timer 1 Reload Register 0000 H T2 FE40 H 20H GPT1 Timer 2 Register 0000 H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000 H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000H T3 FE42 H 21H GPT1 Timer 3 Register 0000 H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000 H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000 H T4 FE44 H 22H GPT1 Timer 4 Register 0000 H T4CON b FF44H A2H GPT1 Timer 4 Control Register 0000 H T4IC b FF64H B2H GPT1 Timer 4 Interrupt Control Register 0000 H T5 FE46 H 23H GPT2 Timer 5 Register 0000 H T5CON b FF46H A3H GPT2 Timer 5 Control Register 0000 H T5IC b FF66H B3H GPT2 Timer 5 Interrupt Control Register 0000 H T6 FE48 H 24H GPT2 Timer 6 Register 0000 H T6CON b FF48H A4H GPT2 Timer 6 Control Register 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

1) The system configuration is selected during reset. 2) Bit WDTR indicates a watchdog timer triggered reset. Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used to generate software controlled interrupt requests by setting the respective XPnIR bit. T6IC b FF68 H B4H GPT2 Timer 6 Interrupt Control Register 0000 H T7 F050H E 28H CAPCOM Timer 7 Register 0000 H T78CON b FF20H 90H CAPCOM Timer 7 and 8 Control Register 0000 H T7IC b F17A H E BE H CAPCOM Timer 7 Interrupt Control Register 0000H T7REL F054H E 2AH CAPCOM Timer 7 Reload Register 0000 H T8 F052H E 29H CAPCOM Timer 8 Register 0000 H T8IC b F17C H E BF H CAPCOM Timer 8 Interrupt Control Register 0000H T8REL F056H E 2BH CAPCOM Timer 8 Reload Register 0000 H TFR b FFAC H D6 H Trap Flag Register 0000 H WDT FEAE H 57H Watchdog Timer Register (read only) 0000 H WDTCON FFAE H D7 H Watchdog Timer Control Register 000X H XP0IC b F186H E C3 H X-Peripheral 0 Interrupt Control Register 0000H XP1IC b F18E H E C7 H X-Peripheral 1 Interrupt Control Register 0000H XP2IC b F196H E CB H X-Peripheral 2 Interrupt Control Register 0000H XP3IC b F19E H E CF H PLL Interrupt Control Register 0000 H ZEROS b FF1C H 8EH Constant Value 0’s Register (read only) 0000 H Special Function Registers Overview (cont’d) Name Physical Address 8-Bit Address Description Reset Value

Ambient temperature under bias (TA): Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions ( VIN > VCC or VIN < VSS ) the voltage on pins with respect to ground (VSS ) must not exceed the values defined by the Absolute Maximum Ratings. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167SR and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (C ontroller C haracteristics): The logic of the C167SR will provide signals with the respective timing characteristics. SR (System R equirement): The external system must provide signals with the respective timing characteristics to the C167SR.

VCC = 5 V – 10 %; VSS = 0 V; fCPU = 20 MHz; Reset active TA = 0 to + 70 ˚C for SAB-C167SR-LM TA = – 40 to + 85 ˚C for SAF-C167SR-LM TA = – 40 to + 125 ˚C for SAK-C167SR-LM Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (TTL) VIL SR – 0.5 0.2 VCC – 0.1 Input low voltage (Special Threshold) VILS SR – 0.5 2.0 V – Input high voltage, all except RSTIN and XTAL1 (TTL) VIH SR 0.2 VCC + 0.9 VCC + 0.5 V – Input high voltage RSTIN VIH1 SR 0.6 VCC VCC + 0.5 V – Input high voltage XTAL1 VIH2 SR 0.7 VCC VCC + 0.5 V – Input high voltage (Special Threshold) VIHS SR 0.8 VCC – 0.2 VCC + 0.5 V – Input Hysteresis (Special Threshold) HYS 400 – mV – Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOL CC – 0.45 V IOL = 2.4 mA Output low voltage (all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR , BHE, CLKOUT, RSTOUT ) VOH CC 0.9 VCC 2.4 –V IOH = – 500 mA IOH = – 2.4 mA Output high voltage 1) (all other outputs) VOH1 CC 0.9 VCC 2.4 V IOH = – 250 mA IOH = – 1.6 mA Input leakage current (Port 5)IOZ1 CC – –200 nA 0.45V < VIN < VCC Input leakage current (all other)IOZ2 CC – –500 nA 0.45V < VIN < VCC Overload current IOV SR – –5m A 5) 8) RSTIN pullup resistor RRST CC 50 250 k W – Read/Write inactive current 4) IRWH 2) – – 40 mA VOUT = 2.4 V Read/Write active current 4) IRWL 3) – 500 – mA VOUT = VOLmax ALE inactive current 4) IALEL 2) –4 0 mA VOUT = VOLmax ALE active current 4) IALEH 3) 500 – mA VOUT = 2.4 V Port 6 inactive current 4) IP6H 2) – – 40 mA VOUT = 2.4 V

1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) The maximum current may be drawn while the respective signal line remains inactive. 3) The minimum current must be drawn in order to drive the respective signal line active. 4) This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. 5) Not 100 % tested, guaranteed by design characterization. 6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at V CCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 7) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC – 0.1 V to VCC , VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 8) Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin currents on all port pins may not exceed 50 mA . Port 6 active current 4) IP6L 3) – 500 – mA VOUT = VOL1max PORT0 configuration current 4) IP0H 2) – – 10 mA VIN = VIHmin IP0L 3) – 100 – mA VIN = VILmax XTAL1 input current IIL CC – – 20 mA 0 V < VIN < VCC Pin capacitance 5) (digital inputs/outputs) C IO CC – 10 pF f = 1 MHz TA = 25 ˚C Power supply current ICC – 20 + 5 · fCPU mA RSTIN = VIL2 fCPU in [MHz] 6) Idle mode supply current IID – 20 + 2 · fCPU mA RSTIN = VIH1 fCPU in [MHz] 6) Power-down mode supply currentIPD – 100 mA VCC = 5.5 V 7) Parameter Symbol Limit Values Unit Test Condition min. max.

Supply/Idle Current as a Function of Operating Frequency

A/D Converter Characteristics VCC = 5 V – 10 %; VSS = 0 V TA = 0 to + 70 ˚C for SAB-C167SR-LM TA = – 40 to + 85 ˚C for SAF-C167SR-LM TA = – 40 to + 125 ˚C for SAK-C167SR-LM 4.0 V £ VAREF £ VCC + 0.1 V; VSS – 0.1 V £ VAGND £ VSS + 0.2 V Sample time and conversion time of the C167SR’s ADC are programmable. The table below should be used to calculate the above timings. Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage range VAIN SR VAGND VAREF V 1) Sample time tS CC – 2 tSC 2) 4) Conversion time tC CC – 14 tCC + tS + 4TCL 3) 4) Total unadjusted error TUE CC – – 2 LSB 5) Internal resistance of reference voltage source RAREF SR – tCC / 165 – 0.25 kW tCC in [ns] 6) 7) Internal resistance of analog source RASRC SR – tS / 330 – 0.25 kW tS in [ns] 2) 7) ADC input capacitance C AIN CC – 33 pF 7) ADCON.15|14 (ADCTC) Conversion Clock tCC ADCON.13|12 (ADSTC) Sample Clock tSC

00 TCL · 24 00 tCC

01 Reserved, do not use 01 tCC · 2

10 TCL · 96 10 tCC · 4

11 TCL · 48 11 tCC · 8

1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH , respectively. 2) During the sample time the input capacitance C I can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tSC depend on programming and can be taken from the table above. 3) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above. 4) This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. 5) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be – 4 LSB. 6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC . The maximum internal resistance results from the programmed conversion timing. 7) Not 100 % tested, guaranteed by design characterization.

Definition of Internal Timing The internal operation of the C167SR is controlled by the internal CPU clock fCPU . Both edges of the The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see figure below). Figure 11 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU . This influence must be regarded when calculating the timings for the C167SR. Direct Drive When pin P0.15 (P0H.7) is low (‘0’) during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL . The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCL min = 1/fXTAL · DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL . The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/ fXTAL . Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL · DCmax ) instead of TCLmin. TCL TCL TCL TCL fCPU fXTAL fCPU fXTAL Phase Locked Loop Operation Direct Clock Drive

When pin P0.15 (P0H.7) is high (‘1’) during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e. fCPU = fXTAL · 4). With every fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL . The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and figure below). For a period of N · TCL the minimum value is computed using the corresponding deviation DN : TCL min = TCLNOM · (1 – DN / 100) D N = – (4 – N /15) [%], where N = number of consecutive TCLs and 1 £ N £ 40. So for a period of 3 TCLs (i.e. N = 3): D3 = 4 – 3/15 = 3.8 %, and TCLmin = TCLNOM · (1 – 3.8 / 100) = TCLNOM · 0.962 (24.1 nsec @ fCPU = 20 MHz). This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Figure 12 Approximated Maximum PLL Jitter

External Clock Drive XTAL1 VCC = 5 V – 10 %; VSS = 0 V TA = 0 to + 70 ˚C for SAB-C167SR-LM TA = – 40 to + 85 ˚C for SAF-C167SR-LM TA = – 40 to + 125 ˚C for SAK-C167SR-LM 1) For temperatures above TA = +85 ˚C the minimum value for t1 and t2 is 25 ns. 2) The clock input signal must reach the defined levels VIL and VIH2. Figure 13 External Clock Drive XTAL1 Parameter Symbol Direct Drive 1:1 PLL 1:4 Unit min. max. min. max. Oscillator period tOSC SR 50 1000 200 333 ns High time t1 SR 23 1) 2) –1 0 –n s Low time t2 SR 23 1) 2) –1 0 –n s Rise time t3 SR – 10 2) – 10 2) ns Fall time t4 SR – 10 2) – 10 2) ns

The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. AC Characteristics Multiplexed Bus VCC = 5 V – 10 %; VSS = 0 V TA = 0 to + 70 ˚C for SAB-C167SR-LM TA = – 40 to + 85 ˚C for SAF-C167SR-LM TA = – 40 to + 125 ˚C for SAK-C167SR-LM C L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF C L (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates) Description Symbol Values ALE Extension tA TCL · <ALECTL> Memory Cycle Time Waitstates tC 2TCL · (15 – <MCTC>) Memory Tristate Time tF 2TCL · (1 – <MTTC>) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. ALE high time t5 CC 15 + tA – TCL – 10 + tA –n s Address setup to ALE t6 CC 10 + tA – TCL – 15 + tA –n s Address hold after ALEt7 CC 15 + tA – TCL – 10 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 15 + tA – TCL – 10 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC – 10 + tA – – 10 + tA –n s Address float after RD, WR (with RW-delay) t10 CC – 5 –5n s Address float after RD, WR (no RW-delay) t11 CC – 30 – TCL + 5 ns RD , WR low time (with RW-delay) t12 CC 40 + tC – 2TCL – 10 + tC –n s RD , WR low time (no RW-delay) t13 CC 65 + tC – 3TCL – 10 + tC –n s

(with RW-delay) t14 SR – 30 + tC – 2TCL – 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 55 + tC – 3TCL – 20 + tC ns ALE low to valid data int16 SR – 55 + tA + tC – 3TCL – 20 + tA + tC ns Address to valid data int17 SR – 70 + 2tA + tC – 4TCL – 30 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD t19 SR – 35 + tF – 2TCL – 15 + tF ns Data valid to WR t22 SR 25 + tC – 2TCL – 25 + tC –n s Data hold after WR t23 CC 35 + tF – 2TCL – 15 + tF –n s ALE rising edge after RD, WR t25 CC 35 + tF – 2TCL – 15 + tF –n s Address hold after RD, WR t27 CC 35 + tF – 2TCL – 15 + tF –n s ALE falling edge to CSt38 CC – 5 – tA 10 – tA – 5 – tA 10 – tA ns CS low to Valid Data Int39 SR – 55 + tC + 2tA – 3TCL – 20 + tC + 2tA ns CS hold after RD, WR t40 CC 60 + tF – 3TCL – 15 + tF –n s ALE fall. edge to RdCS, WrCS (with RW delay) t42 CC 20 + tA – TCL – 5 + tA –n s ALE fall. edge to RdCS, WrCS (no RW delay) t43 CC – 5 + tA –– 5 + tA –n s Address float after RdCS, WrCS (with RW delay) t44 C C – 0 –0n s Address float after RdCS, WrCS (no RW delay) t45 CC – 25 – TCL ns RdCS to Valid Data In (with RW delay) t46 SR – 25 + tC – 2TCL – 25 + tC ns Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max.

(no RW delay) t47 SR – 50 + tC – 3TCL – 25 + tC ns RdCS , WrCS Low Time (with RW delay) t48 CC 40 + tC – 2TCL – 10 + tC –n s RdCS , WrCS Low Time (no RW delay) t49 CC 65 + tC – 3TCL – 10 + tC –n s Data valid to WrCS t50 CC 35 + tC – 2TCL – 15 + tC –n s Data hold after RdCS t51 S R 0 – 0–n s Data float after RdCS t52 SR – 30 + tF – 2TCL – 20 + tF ns Address hold after RdCS , WrCS t54 CC 30 + tF – 2TCL – 20 + tF –n s Data hold after WrCS t56 CC 30 + tF – 2TCL – 20 + tF –n s Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max.

External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data In Data OutAddress Address t38 t44 t10 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t14 t46 t12 t48 t10 t22 t23 t44 t12 t48 t42 t42 t50 t51 t54 t52 t56

External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data OutAddress Data InAddress t38 t44 t10 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t14 t46 t12 t48 t10 t22 t23 t44 t12 t48 t42 t42 t50 t51 t54 t52 t56

External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data OutAddress Address Data In t38 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t15 t47 t13 t49 t22 t23 t13 t49 t43 t43 t11 t45 t11 t45 t50 t51 t54 t52 t56

External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data OutAddress Data InAddress t38 Address ALE CSx A23-A16 (A15-A8) BHE BUS Read Cycle RD RdCSx BUS Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t6 t7 t39 t40 t25 t27 t18 t19 t15 t47 t13 t49 t22 t23 t13 t49 t43 t43 t9 t11 t45 t11 t45 t50 t51 t54 t52 t56

VCC = 5 V – 10 %; VSS = 0 V TA = 0 to + 70 ˚C for SAB-C167SR-LM TA = – 40 to + 85 ˚C for SAF-C167SR-LM TA = – 40 to + 125 ˚C for SAK-C167SR-LM C L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF C L (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. ALE high time t5 CC 15 + tA – TCL – 10 + tA –n s Address setup to ALE t6 CC 10 + tA – TCL – 15 + tA –n s ALE falling edge to RD, WR (with RW-delay) t8 CC 15 + tA – TCL – 10 + tA –n s ALE falling edge to RD, WR (no RW-delay) t9 CC – 10 + tA – – 10 + tA –n s RD , WR low time (with RW-delay) t12 CC 40 + tC – 2TCL – 10 + tC –n s RD , WR low time (no RW-delay) t13 CC 65 + tC – 3TCL – 10 + tC –n s RD to valid data in (with RW-delay) t14 SR – 30 + tC – 2TCL – 20 + tC ns RD to valid data in (no RW-delay) t15 SR – 55 + tC – 3TCL – 20 + tC ns ALE low to valid data int16 SR – 55 + tA + tC – 3TCL – 20 + tA + tC ns Address to valid data int17 SR – 70 + 2tA + tC – 4TCL – 30 + 2tA + tC ns Data hold after RD rising edge t18 S R 0 – 0–n s Data float after RD rising edge (with RW-delay 1)) t20 SR – 35 + tF – 2TCL – 15 + 2tA + tF 1) ns Data float after RD rising edge (no RW-delay 1)) t21 SR – 15 + tF – TCL – 10 + 2tA + tF 1) ns Data valid to WR t22 CC 25 + tC – 2TCL – 25 + tC –n s Data hold after WR t24 CC 15 + tF – TCL – 10 + tF –n s

1) RW-delay and tA refer to the next following bus cycle. ALE rising edge after RD, WR t26 CC – 10 + tF – – 10 + tF – ns Address hold after RD, WR t28 CC 0 + tF –0 + tF –n s ALE falling edge to CSt38 CC – 5 – tA 10 – tA – 5 – tA 10 – tA ns CS low to Valid Data Int39 SR – 55 + tC + 2tA – 3TCL – 20 + tC + 2tA ns CS hold after RD, WR t41 CC 10 + tF – TCL – 15 + tF –n s ALE falling edge to RdCS , WrCS (with RW- delay) t42 CC 20 + tA – TCL – 5 + tA –n s ALE falling edge to RdCS , WrCS (no RW- delay) t43 CC – 5 + tA –– 5 + tA –n s RdCS to Valid Data In (with RW-delay) t46 SR – 25 + tC – 2TCL – 25 + tC ns RdCS to Valid Data In (no RW-delay) t47 SR – 50 + tC – 3TCL – 25 + tC ns RdCS , WrCS Low Time (with RW-delay) t48 CC 40 + tC – 2TCL – 10 + tC –n s RdCS , WrCS Low Time (no RW-delay) t49 CC 65 + tC – 3TCL – 10 + tC –n s Data valid to WrCS t50 CC 35 + tC – 2TCL – 15 + tC –n s Data hold after RdCS t51 S R 0 – 0–n s Data float after RdCS (with RW-delay) t53 SR – 30 + tF – 2TCL – 20 + tF ns Data float after RdCS (no RW-delay) t68 SR – 5 + tF – TCL – 20 + tF ns Address hold after RdCS , WrCS t55 CC – 10 + tF – – 10 + tF –n s Data hold after WrCS t57 CC 10 + tF – TCL – 15 + tF –n s Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max.

External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE BUS (D15-D8) D7-D0 Read Cycle RD RdCSx Write Cycle WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t20 t14 t46 t12 t48 t22 t24 t12 t48 t42 t42 t50 t51 t55 t53 t57 BUS (D15-D8) D7-D0 WR , WRL , WRH

External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE Read Cycle RD RdCSx Write Cycle WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t20 t14 t46 t12 t48 t22 t24 t12 t48 t42 t42 t50 t51 t55 t53 t57 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0 WR , WRL , WRH

External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE Read Cycle RD RdCSx Write Cycle WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t21 t15 t47 t13 t49 t22 t24 t13 t49 t43 t43 t50 t51 t55 t68 t57 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0 WR , WRL , WRH

External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Out Data In t38 Address ALE CSx A23-A16 A15-A0 BHE Read Cycle RD RdCSx Write Cycle WR , WRL , WRH WrCSx t5 t16 t17 t39 t41 t26 t28 t18 t21 t15 t47 t13 t49 t22 t24 t13 t49 t43 t43 t50 t51 t55 t68 t57 BUS (D15-D8) D7-D0 BUS (D15-D8) D7-D0

VCC = 5 V – 10 %; VSS = 0 V TA = 0 to + 70 ˚C for SAB-C167SR-LM TA = – 40 to + 85 ˚C for SAF-C167SR-LM TA = – 40 to + 125 ˚C for SAK-C167SR-LM C L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF C L (for Port 6, CS) = 100 pF Notes 1) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2) Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA refer to the next following bus cycle. Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. CLKOUT cycle time t29 CC 50 50 2TCL 2TCL ns CLKOUT high time t30 CC 20 – TCL – 5 – ns CLKOUT low time t31 CC 15 – TCL – 10 – ns CLKOUT rise time t32 C C – 5 –5n s CLKOUT fall time t33 C C – 5 –5n s CLKOUT rising edge to ALE falling edge t34 CC 0 + tA 10 + tA 0 + tA 10 + tA ns Synchronous READY setup time to CLKOUT t35 SR 15 – 15 – ns Synchronous READY hold time after CLKOUT t36 S R 0 – 0–n s Asynchronous READY low time t37 SR 65 – 2TCL + 15 – ns Asynchronous READY setup time 1) t58 SR 15 – 15 – ns Asynchronous READY hold time 1) t59 SR 0 – 0–n s Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) t60 SR 00 + 2tA + tF

0 TCL – 25

+ 2tA + tF ns

1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR ). 5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). 6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7) The next external bus cycle may start here. CLKOUT ALE t30 t34 Sync READY t35 t36 t35 t36 Async READY t58 t59 t58 t59 waitstate READY MUX/Tristate 6) t32 t33 t29 Running cycle 1) t31 t37 3) 3) Command RD , WR t60 see 6) 3) 3)

VCC = 5 V – 10 %; VSS = 0 V TA = 0 to + 70 ˚C for SAB-C167SR-LM TA = – 40 to + 85 ˚C for SAF-C167SR-LM TA = – 40 to + 125 ˚C for SAK-C167SR-LM C L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF C L (for Port 6, CS) = 100 pF Parameter Symbol Max. CPU Clock = 20 MHz Variable CPU Clock 1/2TCL = 1 to 20 MHz Unit min. max. min. max. HOLD input setup time to CLKOUT t61 SR 20 – 20 – ns CLKOUT to HLDA high or BREQ low delay t62 CC – 20 – 20 ns CLKOUT to HLDA low or BREQ high delay t63 CC – 20 – 20 ns CSx release t64 CC – 20 – 20 ns CSx drive t65 CC – 5 25 – 5 25 ns Other signals release t66 CC – 20 – 20 ns Other signals drive t67 CC – 5 25 – 5 25 ns

External Bus Arbitration, Releasing the Bus Notes 1) The C167SR will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. 3) The CS outputs will be resistive high (pullup) after t64. CLKOUT HOLD t61 HLDA t63 Other Signals t66 CSx (On P6.x) t64 2)BREQ t62

External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C167SR requesting the bus. 2) The next C167SR driven bus cycle may start here. CLKOUT HOLD HLDA Other Signals t62 CSx (On P6.x) t67 t62 t65 t61 BREQ t63t62

Product Information

C167SR specifications and overview.

Summary

16-Bit CMOS Single-Chip Microcontroller

Description

16-Bit CMOS Single-Chip Microcontroller

Source title C167SR Datasheet(PDF) - Siemens Semiconductor Group

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