C167CS-4R_01 INFINEON | Alldatasheet
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Never stop thinking. Microcontrollers Data Sheet, V2.2, Aug. 2001 C167CS-4R C167CS-L 16-Bit Single-Chip Microcontroller
Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, V2.2, Aug. 2001 Never stop thinking. C167CS-4R C167CS-L 16-Bit Single-Chip Microcontroller
Controller Area Network (CAN): License of Robert Bosch GmbH C167CS Revision History: 2001-08 V2.2 Previous Version: 2000-12 V2.1 (Intermediate version) 2000-06 V2.0 1999-06 1999-03 (Advance Information) Page Subjects (major changes from V2.1, 2000-12 to V2.2, 2001-08) 4F i g u r e 2 corrected (pins 98, 99) 25, 27 Figure 5 and Figure 6 updated 50ff Output voltage/current specification improved 52f Limit values for IIDO and IPDR increased due to the usage of a standard oscillator
54 Figure 10 corrected
57 Figure 12 updated for 40 MHz
59 Clock parameters adjusted
60 TUE note includes P1H
1) New package due to new assembly line. MQFP-144-1 for current deliveries only, will be discontinued. Page Subjects (major changes from V2.0, 2000-06 to V2.1, 2000-12) All Maximum operating frequency updated to 40 MHz
2 Derivative table updated
52 RSTIN
level for IDD corrected to VIL (was VIL2)
53 Current unit corrected to µA
56 Input clock range adjusted
64 Parameters tc10, tc12, tc13, tc14, tc15, tc16, tc17, tc18, tc19 changed
65 Relative bus timing parameters added
70 Parameter tc25 changed, notes adapted
71 Notes adapted
72 Parameter tc28 changed
75 Parameters t42, t43, t44, t46, t47 changed
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Data Sheet 1 V2.2, 2001-08 C167CS16-Bit Single-Chip Microcontroller C166 Family C167CS-4R, C167CS-L
- High Performance 16-bit CPU with 4-Stage Pipeline – 80/60/50 ns Instruction Cycle Time at 25/33/40 MHz CPU Clock – 400/303/250 ns Multiplication (16 × 16 bit), 800/606/500 ns Division (32-/16-bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 MBytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30/25 ns 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input On-Chip Memory Modules – 3 KBytes On-Chip Internal RAM (IRAM) – 8 KBytes On-Chip Extension RAM (XRAM) – 32 KBytes On-Chip Program Mask ROM On-Chip Peripheral Modules – 24-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs – Two 16-Channel Capture/Compare Units – 4-Channel PWM Unit – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) – Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2 × 15 Message Objects (Full CAN/Basic CAN), can work on one bus with 30 objects – On-Chip Real Time Clock Up to 16 MBytes External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width – Five Programmable Chip-Select Signals – Hold- and Hold-Acknowledge Bus Arbitration Support Idle, Sleep, and Power Down Modes with Flexible Power Management Programmable Watchdog Timer and Oscillator Watchdog Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
Data Sheet 2 V2.2, 2001-08 Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 144-Pin MQFP Package This document describes several derivatives of the C167 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. For simplicity all versions are referred to by the term C167CS throughout this document. Table 1 C167CS Derivative Synopsis Derivative 1) This Data Sheet is valid for devices starting with and including design step BA. Program Memory Operating Frequency SAK-C167CS-LM SAB-C167CS-LM --- 25 MHz SAK-C167CS-L33M SAB-C167CS-L33M --- 33 MHz SAK-C167CS-L40M SAB-C167CS-L40M --- 40 MHz SAK-C167CS-4RM SAB-C167CS-4RM
32 KByte ROM 25 MHz
32 KByte ROM 33 MHz
32 KByte ROM 40 MHz
Data Sheet 3 V2.2, 2001-08
Ordering Information
The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery. For the available ordering codes for the C167CS please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants. Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. Introduction The C167CS derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM. Figure 1 Logic Symbol MCL04411 XTAL1 XTAL2 RSTOUT ALE NMI RD RSTIN Port 0
16 Bit
15 Bit
8 Bit
Data Sheet 4 V2.2, 2001-08 Pin Configuration (top view) Figure 2 *) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them. Table 2 on the pages below lists the possible assignments. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108 107 106 105 104 103 102 101 100 V AREF V AGND P5.10/AN10/T6EUDP5.11/AN11/T5EUD P5.12/AN12/T6INP5.13/AN13/T5IN P5.14/AN14/T4EUDP5.15/AN15/T2EUD V SS V DD V SS V DD P2.8/CC8IO/EX0INP2.9/CC9IO/EX1IN P2.15/CC15IO/EX7IN/T7IN P3.0/T0IN P3.1/T6OUTP3.2/CAPINP3.3/T3OUTP3.4/T3EUD P3.5/T4IN V SS V DD V DD V SS NMIRSTOUTRSTINV SS XTAL1XTAL2V DD SS V DD SS V DD P0H.0/AD8 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2/AD2 P0L.1/AD1 P0L.0/AD0 EA ALE READY WR/WRL RD VSS VDD P4.7/A23/* P4.6/A22/* P4.5/A21/* P4.4/A20/* P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 N.C. VSS VDDP3.15/CLKOUT/ FOUT P3.13/SCLK P3.12/BHE/WRH P3.111/RxD0 P3.10/TxD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ *P8.0/CC16IO *P8.1/CC17IO *P8.2/CC18IO *P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO VDD VSS P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 C167CS MCP04431
Data Sheet 5 V2.2, 2001-08 Table 2 Pin Definitions and Functions Symbol Pin Num. Input Outp. Function P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 IO O O O O O I I/O O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The Port 6 pins also serve for alternate functions: CS0 Chip Select 0 Output CS1 Chip Select 1 Output CS2 Chip Select 2 Output CS3 Chip Select 3 Output CS4 Chip Select 4 Output HOLD External Master Hold Request Input HLDA Hold Acknowledge Output (master mode) or Input (slave mode) BREQ Bus Request Output P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 IO I/O I I I/O O O I/O I I I/O I I I/O I/O I/O I/O Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). Port 8 pins provide inputs/ outputs for CAPCOM2 and serial interface lines. CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input, CAN2_RxD CAN 2 Receive Data Input CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output, CAN2_TxD CAN 2 Transmit Data Output CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input, CAN2_RxD CAN 2 Receive Data Input CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output, CAN2_TxD CAN 2 Transmit Data Output CC20IO CAPCOM2: CC20 Capture Inp./Compare Outp. CC21IO CAPCOM2: CC21 Capture Inp./Compare Outp. CC22IO CAPCOM2: CC22 Capture Inp./Compare Outp. CC23IO CAPCOM2: CC23 Capture Inp./Compare Outp.
Data Sheet 6 V2.2, 2001-08 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 IO O O O O I/O I/O I/O I/O Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins also serve for alternate functions: POUT0 PWM Channel 0 Output POUT1 PWM Channel 1 Output POUT2 PWM Channel 2 Output POUT3 PWM Channel 3 Output CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp. CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp. CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp. CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp. P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 I I I I I I I I I I I I I I I I I Port 5 is a 16-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10, T6EUD GPT2 Timer T6 Ext. Up/Down Ctrl. Inp. AN11, T5EUD GPT2 Timer T5 Ext. Up/Down Ctrl. Inp. AN12, T6IN GPT2 Timer T6 Count Inp. AN13, T5IN GPT2 Timer T5 Count Inp. AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN15, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 7 V2.2, 2001-08 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 IO I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: CC0IO CAPCOM1: CC0 Capture Inp./Compare Output CC1IO CAPCOM1: CC1 Capture Inp./Compare Output CC2IO CAPCOM1: CC2 Capture Inp./Compare Output CC3IO CAPCOM1: CC3 Capture Inp./Compare Output CC4IO CAPCOM1: CC4 Capture Inp./Compare Output CC5IO CAPCOM1: CC5 Capture Inp./Compare Output CC6IO CAPCOM1: CC6 Capture Inp./Compare Output CC7IO CAPCOM1: CC7 Capture Inp./Compare Output CC8IO CAPCOM1: CC8 Capture Inp./Compare Output, EX0IN Fast External Interrupt 0 Input CC9IO CAPCOM1: CC9 Capture Inp./Compare Output, EX1IN Fast External Interrupt 1 Input CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp., EX2IN Fast External Interrupt 2 Input CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp., EX3IN Fast External Interrupt 3 Input CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp., EX4IN Fast External Interrupt 4 Input CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp., EX5IN Fast External Interrupt 5 Input CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp., EX6IN Fast External Interrupt 6 Input CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp., EX7IN Fast External Interrupt 7 Input, T7IN CAPCOM2: Timer T7 Count Input Note: During Sleep Mode a spike filter on the EXnIN interrupt inputs suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 8 V2.2, 2001-08 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 IO I O I O I I I I I/O I/O O I/O O O I/O O O Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: T0IN CAPCOM1 Timer T0 Count Input T6OUT GPT2 Timer T6 Toggle Latch Output CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Control Input T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. T ×D0 ASC0 Clock/Data Output (Async./Sync.) R×D0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) BHE External Memory High Byte Enable Signal, WRH External Memory High Byte Write Strobe SCLK SSC Master Clock Output / Slave Clock Input. CLKOUT System Clock Output (= CPU Clock) FOUT Programmable Frequency Output N.C. 84 – This pin is not connected in the C167CS. No connection to the PCB is required. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 9 V2.2, 2001-08 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 IO O O O O O I O I O O O O I O I Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. The Port 4 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines and for serial interface lines: A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line, CAN2_RxD CAN 2 Receive Data Input A21 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input A22 Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output, CAN2_TxD CAN 2 Transmit Data Output A23 Most Significant Segment Address Line, CAN1_RxD CAN 1 Receive Data Input, CAN2_TxD CAN 2 Transmit Data Output, CAN2_RxD CAN 2 Receive Data Input RD 95 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/ WRL 96 O External Memory Write Strobe. In WR -mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. READY 97 I Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. An internal pullup device will hold this pin high when nothing is driving it. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 10 V2.2, 2001-08 ALE 98 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 99 I External Access Enable pin. A low level at this pin during and after Reset forces the C167CS to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’. PORT0 P0L.0-7 P0H.0-7 100- 107 108, 111- 117 IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 – D7 P0H.0 – P0H.7: I/O D8 – D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15 Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 11 V2.2, 2001-08 PORT1 P1L.0-7 P1H.0-7 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 P1H.4 P1H.5 P1H.6 P1H.7 118- 125 128- 135 118 119 120 121 122 123 124 125 132 133 134 135 IO I I I I I I I I I/O I/O I/O I/O PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: AN16 Analog Input Channel 16 AN17 Analog Input Channel 17 AN18 Analog Input Channel 18 AN19 Analog Input Channel 19 AN20 Analog Input Channel 20 AN21 Analog Input Channel 21 AN22 Analog Input Channel 22 AN23 Analog Input Channel 23 CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp. CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp. CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp. CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp. XTAL2 XTAL1 137 138 O I XTAL2: Output of the oscillator amplifier circuit. XTAL1: Input to the oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 12 V2.2, 2001-08 RSTIN 140 I/O Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C167CS. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table. Note: To let the reset configuration of PORT0 settle and to let the PLL lock a reset duration of ca. 1 ms is recommended. RST OUT 141 O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C167CS to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. VAREF 37 – Reference voltage for the A/D converter. VAGND 38 – Reference ground for the A/D converter. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 13 V2.2, 2001-08 Note: The following behaviour differences must be observed when the bidirectional reset is active: Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. The reset indication flags always indicate a long hardware reset. The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. Pin RSTIN may only be connected to external reset devices with an open drain output driver. A short hardware reset is extended to the duration of the internal reset sequence. VDD 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 – Digital Supply Voltage: +5 V during normal operation and idle mode. ≥2.5 V during power down mode. VSS 18, 45, 55, 71, 83, 94, 110, 127, 139, 143 – Digital Ground. 1) The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module several assignments can be selected. Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Num. Input Outp. Function
Data Sheet 14 V2.2, 2001-08 Functional Description The architecture of the C167CS combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. Figure 3 gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C167CS. Note: All time specifications refer to a CPU clock of 40 MHz (see definition in the AC Characteristics section). Figure 3 Block Diagram The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resources, the X-Peripherals (see Figure 3). The XBUS resources (XRAM, CAN) of the C167CS can be individually enabled or disabled during initialization. Register XPERCON selects the required modules which are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules that are disabled consume neither address space nor port pins. Note: The default value of register XPERCON after reset selects 2 KByte XRAM and module CAN1, so the default XBUS resources are compatible with the C167CR. C166-Core CPU Port 2 Interrupt Bus XTALOsc / PLL RTC WDT Interrupt Controller 16-Level Priority PEC External Instr. / Data GPT SSC BRGen (SPI) ASC0 BRGen (USART) ADC 10-Bit 16+8 Channels PWM CCOM1 CCOM2 T8EBC XBUS Control External Bus Control IRAM Dual Port Internal RAM
3 KByte
32 KByte
Rev 2.0B active Instr. / Data Port 0 XRAM 6+2 KByte Port 6 Port 1 16 1616 Port 5 Port 3 Port 7 Port 8 Port 4 16 Peripheral Data Bus CAN2 Rev 2.0B active On-C hip X BUS (1 6-B it D em ux) MCB04323_7CS
Data Sheet 15 V2.2, 2001-08 Memory Organization The memory space of the C167CS is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C167CS incorporates 32 KBytes of on-chip mask-programmable ROM (not in the ROM-less derivative, of course) for code or constant data. The 32 KBytes of the on-chip ROM can be mapped either to segment 0 or segment 1.
3 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined
variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, … , RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family.
8 KBytes of on-chip Extension RAM (XRAM), organized as two blocks of 2 KByte and
6 KByte, respectively, are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.
Data Sheet 16 V2.2, 2001-08 External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: – 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed – 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. The C167CS offers the possibility to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is switched off and the CS signals are directly generated from the address. The unlatched CS mode is enabled by setting CSCFG (SYSCON.6). Access to very slow memories or memories with varying access times is supported via a particular ‘Ready’ function. A HOLD /HLDA protocol is available for bus arbitration and allows to share external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7 … P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to ‘1’ the Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the slave controller to another master controller without glue logic. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.
Data Sheet 17 V2.2, 2001-08 Note: When one or both of the on-chip CAN Modules are used with the interface lines assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 … A16. CS lines can be used to increase the total amount of addressable external memory. Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C167CS ’s instructions can be executed in just one machine cycle which requires 50 ns at 40 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so-called ‘Jump Cache ’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. Figure 4 CPU Block Diagram MCB02147 CPU SP STKOV STKUN Instr. Reg. Instr. Ptr. Exec. Unit 4-Stage Pipeline MDH MDL PSW SYSCON Context Ptr. Mul/Div-HW R15 General Purpose Registers Bit-Mask Gen Barrel - Shifter ALU (16-bit) Data Page Ptr. Code Seg. Ptr. Internal RAM R15 ROM BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 4 ADDRSEL 3 ADDRSEL 2 ADDRSEL 1
Data Sheet 18 V2.2, 2001-08 The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C167CS instruction set which includes the following instruction classes: – Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instructions – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Data Sheet 19 V2.2, 2001-08 Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C167CS is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C167CS supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C167CS has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number. Table 3 shows all of the possible C167CS interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Note: Interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).
Data Sheet 20 V2.2, 2001-08 Table 3 C167CS Interrupt Nodes Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM Register 0 CC0IR CC0IE CC0INT 00 ’0040H 10H CAPCOM Register 1 CC1IR CC1IE CC1INT 00 ’0044H 11H CAPCOM Register 2 CC2IR CC2IE CC2INT 00 ’0048H 12H CAPCOM Register 3 CC3IR CC3IE CC3INT 00 ’004CH 13H CAPCOM Register 4 CC4IR CC4IE CC4INT 00 ’0050H 14H CAPCOM Register 5 CC5IR CC5IE CC5INT 00 ’0054H 15H CAPCOM Register 6 CC6IR CC6IE CC6INT 00 ’0058H 16H CAPCOM Register 7 CC7IR CC7IE CC7INT 00 ’005CH 17H CAPCOM Register 8 CC8IR CC8IE CC8INT 00 ’0060H 18H CAPCOM Register 9 CC9IR CC9IE CC9INT 00 ’0064H 19H CAPCOM Register 10 CC10IR CC10IE CC10INT 00 ’0068H 1AH CAPCOM Register 11 CC11IR CC11IE CC11INT 00 ’006CH 1BH CAPCOM Register 12 CC12IR CC12IE CC12INT 00 ’0070H 1CH CAPCOM Register 13 CC13IR CC13IE CC13INT 00 ’0074H 1DH CAPCOM Register 14 CC14IR CC14IE CC14INT 00 ’0078H 1EH CAPCOM Register 15 CC15IR CC15IE CC15INT 00 ’007CH 1FH CAPCOM Register 16 CC16IR CC16IE CC16INT 00 ’00C0H 30H CAPCOM Register 17 CC17IR CC17IE CC17INT 00 ’00C4H 31H CAPCOM Register 18 CC18IR CC18IE CC18INT 00 ’00C8H 32H CAPCOM Register 19 CC19IR CC19IE CC19INT 00 ’00CCH 33H CAPCOM Register 20 CC20IR CC20IE CC20INT 00 ’00D0H 34H CAPCOM Register 21 CC21IR CC21IE CC21INT 00 ’00D4H 35H CAPCOM Register 22 CC22IR CC22IE CC22INT 00 ’00D8H 36H CAPCOM Register 23 CC23IR CC23IE CC23INT 00 ’00DCH 37H CAPCOM Register 24 CC24IR CC24IE CC24INT 00 ’00E0H 38H CAPCOM Register 25 CC25IR CC25IE CC25INT 00 ’00E4H 39H CAPCOM Register 26 CC26IR CC26IE CC26INT 00 ’00E8H 3AH CAPCOM Register 27 CC27IR CC27IE CC27INT 00 ’00ECH 3BH CAPCOM Register 28 CC28IR CC28IE CC28INT 00 ’00E0H 3CH CAPCOM Register 29 CC29IR CC29IE CC29INT 00 ’0110H 44H
Data Sheet 21 V2.2, 2001-08 CAPCOM Register 30 CC30IR CC30IE CC30INT 00 ’0114H 45H CAPCOM Register 31 CC31IR CC31IE CC31INT 00 ’0118H 46H CAPCOM Timer 0 T0IR T0IE T0INT 00 ’0080H 20H CAPCOM Timer 1 T1IR T1IE T1INT 00 ’0084H 21H CAPCOM Timer 7 T7IR T7IE T7INT 00 ’00F4H 3DH CAPCOM Timer 8 T8IR T8IE T8INT 00 ’00F8H 3EH GPT1 Timer 2 T2IR T2IE T2INT 00 ’0088H 22H GPT1 Timer 3 T3IR T3IE T3INT 00 ’008CH 23H GPT1 Timer 4 T4IR T4IE T4INT 00 ’0090H 24H GPT2 Timer 5 T5IR T5IE T5INT 00 ’0094H 25H GPT2 Timer 6 T6IR T6IE T6INT 00 ’0098H 26H GPT2 CAPREL Reg. CRIR CRIE CRINT 00 ’009CH 27H A/D Conversion Complete ADCIR ADCIE ADCINT 00 ’00A0H 28H A/D Overrun Error ADEIR ADEIE ADEINT 00 ’00A4H 29H ASC0 Transmit S0TIR S0TIE S0TINT 00 ’00A8H 2AH ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00 ’011CH 47H ASC0 Receive S0RIR S0RIE S0RINT 00 ’00ACH 2BH ASC0 Error S0EIR S0EIE S0EINT 00 ’00B0H 2CH SSC Transmit SCTIR SCTIE SCTINT 00 ’00B4H 2DH SSC Receive SCRIR SCRIE SCRINT 00 ’00B8H 2EH SSC Error SCEIR SCEIE SCEINT 00 ’00BCH 2FH PWM Channel 0 … 3 PWMIR PWMIE PWMINT 00 ’00FCH 3FH CAN Interface 1 XP0IR XP0IE XP0INT 00 ’0100H 40H CAN Interface 2 XP1IR XP1IE XP1INT 00 ’0104H 41H Unassigned node XP2IR XP2IE XP2INT 00 ’0108H 42H PLL/OWD and RTC XP3IR XP3IE XP3INT 00 ’010CH 43H Table 3 C167CS Interrupt Nodes (cont’d) Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number
Data Sheet 22 V2.2, 2001-08 The C167CS also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 4 shows all of the possible exceptions or error conditions that can arise during run- time: Table 4 Hardware Trap Summary Exception Condition Trap Flag Trap Vector Vector Location Trap Number Trap Priority Reset Functions: – Hardware Reset – Software Reset – W-dog Timer Overflow RESET RESET RESET 00’0000 H 00’0000H 00’0000H 00H 00H 00H III III III Class A Hardware Traps: – Non-Maskable Interrupt – Stack Overflow – Stack Underflow NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00’0008H 00’0010H 00’0018H 02H 04H 06H II II II Class B Hardware Traps: – Undefined Opcode – Protected Instruction Fault – Illegal Word Operand Access – Illegal Instruction Access – Illegal External Bus Access UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00’0028H 00’0028H 00’0028H 00’0028H 00’0028H 0AH 0AH 0AH 0AH 0AH I I I I I Reserved –– [2CH – 3CH] [0BH – 0FH] Software Traps – TRAP Instruction –– Any [00’0000H – 00’01FCH] in steps of 4 H Any [00 H – 7FH] Current CPU Priority
Data Sheet 23 V2.2, 2001-08 Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/ compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched ( ‘capture’d) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode.
Data Sheet 24 V2.2, 2001-08 Table 5 Compare Modes (CAPCOM) Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible. Mode 1 Pin toggles on each compare match; several compare events per timer period are possible. Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated. Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated. Double Register Mode Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible.
Data Sheet 25 V2.2, 2001-08 Figure 5 CAPCOM Unit Block Diagram PWM Module The Pulse Width Modulation Module can generate up to four PWM output signals using edge-aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and single shot outputs. The frequency range of the PWM signals covers
5 Hz to 20 MHz (referred to a CPU clock of 40 MHz), depending on the resolution of the
PWM output signal. The level of the output signals is selectable and the PWM module can generate interrupt requests. MCB02143B Mode Control (Capture or Compare) 2n : 1fCPU Tx Input Control CAPCOM Timer Tx Ty Input Control TxIN Interrupt Request (TyIR) GPT2 Timer T6 Over/Underflow 2n : 1fCPU GPT2 Timer T6 Over/Underflow CCxIO CCxIO
16 Capture Inputs
16 Compare Outputs
Reload Reg. TxREL CAPCOM Timer Ty Reload Reg. TyREL Interrupt Request (TxIR)
16 Capture/Compare
x = 0, 7 y = 1, 8 n = 3 … 10
Data Sheet 26 V2.2, 2001-08 General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over- flow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.
Data Sheet 27 V2.2, 2001-08 Figure 6 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/ down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared Mode Control 2n : 1fCPU 2n : 1fCPU T2 Mode Control GPT1 Timer T2 Reload Capture 2n : 1fCPU Mode Control GPT1 Timer T4 Reload Capture GPT1 Timer T3 T3OTL U/D T2EUD T2IN T3IN T3EUD T4IN T4EUD T3OUT Toggle FF U/D U/D Interrupt Request (T2IR) Interrupt Request (T3IR) Interrupt Request (T4IR) MCT04825 n = 3 … 10
Data Sheet 28 V2.2, 2001-08 after the capture procedure. This allows the C167CS to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. Figure 7 Block Diagram of GPT2 MUX 2n : 1fCPU T5 Mode Control 2n : 1fCPU Mode Control T6OTL T5EUD T5IN CAPIN T6IN T6EUD T6OUT U/D U/D Interrupt Request Interrupt Request Interrupt Request Other Timers Clear Capture CT3 MCB03999 GPT2 Timer T5 GPT2 CAPREL GPT2 Timer T6 n = 2 … 9
Data Sheet 29 V2.2, 2001-08 Real Time Clock The Real Time Clock (RTC) module of the C167CS consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver ( fRTC = fOSC/32) and is therefore independent from the selected clock generation mode of the C167CS. All timers count up. The RTC module can be used for different purposes: System clock to determine the current time and date Cyclic time based interrupt 48-bit timer for long term measurements Figure 8 RTC Block Diagram Note: The registers associated with the RTC are not affected by a reset in order to maintain the correct system time even when intermediate resets are executed. MCD04432 T14REL T14 8:1 RTCf RTCLRTCH Interrupt Request Reload
Data Sheet 30 V2.2, 2001-08 A/D Converter For analog signal measurement, a 10-bit A/D converter with 24 multiplexed input channels (16 standard channels and 8 extension channels) and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 24 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C167CS supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels (standard or extension) are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via registers P5DIDIS (Port 5 Digital Input Disable) and P1DIDIS (PORT1 Digital Input Disable).
Data Sheet 31 V2.2, 2001-08 Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel ( ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 Kbit/s/ 1.03 Mbit/s/1.25 Mbit/s and half-duplex synchronous communication at up to 3.1/ 4.1 Mbit/s/5.0 Mbit/s (@ 25/33/40 MHz CPU clock). A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 6.25/8.25/10 Mbit/s (@ 25/33/40 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet 32 V2.2, 2001-08 CAN-Modules The integrated CAN-Modules handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The modules provide Full CAN functionality on up to 15 message objects each. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/ s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus transceiver. The interface pins are assigned via software. Module CAN2 is identical with the first one, except that it uses a separate address area and a separate interrupt node. The two CAN modules can be internally coupled by assigning their interface pins to the same two port pins, or they can interface to separate CAN buses. Note: When any CAN interface is assigned to Port 4, the respective segment address lines on Port 4 cannot be used. This will limit the external address space. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/ 256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 12.8 µs and 419 ms can be monitored (@ 40 MHz). The default Watchdog Timer interval after reset is 3.27 ms (@ 40 MHz).
Data Sheet 33 V2.2, 2001-08 Parallel Ports The C167CS provides up to 111 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7, and Port 8 is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17 … A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2, Port 8 and Port 7 (and parts of PORT1) are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 6 provides optional bus arbitration signals (BREQ , HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE /WRH, and the system clock output CLKOUT (or the programmable frequency output FOUT). Port 5 (and parts of PORT1) is used for the analog input channels to the A/D converter or timer control signals. The edge characteristics (transition time) and driver characteristics (output current) of the C167CS ’s port drivers can be selected via the Port Output Control registers (POCONx).
Data Sheet 34 V2.2, 2001-08 Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency. In direct drive mode the PLL base frequency is used directly ( fCPU = 2 … 5 MHz). In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 … 2.5 MHz). Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON. In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also no interrupt request will be generated in case of a missing oscillator clock. Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time. Thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the RD line low upon a reset, similar to the standard reset configuration via PORT0.
Data Sheet 35 V2.2, 2001-08 Power Management The C167CS provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): Power Saving Modes switch the C167CS into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may optionally continue running). Sleep Mode can be terminated by external interrupt signals. Clock Generation Management controls the distribution and the frequency of internal and external clock signals (control via register SYSCON2). Slow Down Mode lets the C167CS run at a CPU clock frequency of fOSC/1 … 32 (half for prescaler operation) which drastically reduces the consumed power. The PLL can be optionally disabled while operating in Slow Down Mode. External circuitry can be controlled via the programmable frequency output FOUT. Peripheral Management permits temporary disabling of peripheral modules (control via register SYSCON3). Each peripheral can separately be disabled/enabled. A group control option disables a major part of the peripheral set by setting one single bit. The on-chip RTC supports intermittent operation of the C167CS by generating cyclic wakeup signals. This offers full performance to quickly react on action requests while the intermittent sleep phases greatly reduce the average power consumption of the system.
Data Sheet 36 V2.2, 2001-08 Instruction Set Summary Table 6 lists the instructions of the C167CS in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”. This document also provides a detailed description of each instruction. Table 6 Instruction Set Summary Mnemonic Description Bytes ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2 DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4 PRIOR Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2
Data Sheet 37 V2.2, 2001-08 MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ 2 / 4 JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4 JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update register with word operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI -pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT -pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2 Table 6 Instruction Set Summary (cont’d) Mnemonic Description Bytes Move byte operand to word operand with zero extension
Data Sheet 38 V2.2, 2001-08 Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C167CS in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within on-chip X-peripherals are marked with the letter “X” in column “Physical Address”. An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Table 7 C167CS Registers, Ordered by Name Name Physical Address 8-Bit Addr. Description Reset Value ADCIC b FF98 H CCH A/D Converter End of Conversion Interrupt Control Register 0000H ADCON b FFA0H D0H A/D Converter Control Register 0000 H ADDAT FEA0H 50H A/D Converter Result Register 0000 H ADDAT2 F0A0H E 50H A/D Converter 2 Result Register 0000 H ADDRSEL1 FE18H 0CH Address Select Register 1 0000 H ADDRSEL2 FE1AH 0DH Address Select Register 2 0000 H ADDRSEL3 FE1CH 0EH Address Select Register 3 0000 H ADDRSEL4 FE1EH 0FH Address Select Register 4 0000 H ADEIC b FF9AH CDH A/D Converter Overrun Error Interrupt Control Register 0000H BUSCON0 b FF0CH 86H Bus Configuration Register 0 0XX0 H BUSCON1 b FF14H 8AH Bus Configuration Register 1 0000 H BUSCON2 b FF16H 8BH Bus Configuration Register 2 0000 H BUSCON3 b FF18H 8CH Bus Configuration Register 3 0000 H BUSCON4 b FF1AH 8DH Bus Configuration Register 4 0000 H C1BTR EF04H X --- CAN1 Bit Timing Register UUUU H C1CSR EF00H X --- CAN1 Control/Status Register XX01 H C1GMS EF06H X --- CAN1 Global Mask Short UFUU H C1PCIR EF02H X --- CAN1 Port Control/Interrupt Register XXXX H C1LGML EF0AH X --- CAN1 Lower Global Mask Long UUUU H C1LMLM EF0EH X --- CAN1 Lower Mask of Last Message UUUU H
Data Sheet 39 V2.2, 2001-08 C1UAR EFn2H X --- CAN1 Upper Arbitration Reg. (msg. n) UUUU H C1UGML EF08H X --- CAN1 Upper Global Mask Long UUUU H C1UMLM EF0CH X --- CAN1 Upper Mask of Last Message UUUU H C2BTR EE04H X --- CAN2 Bit Timing Register UUUU H C2CSR EE00H X --- CAN2 Control/Status Register XX01 H C2GMS EE06H X --- CAN2 Global Mask Short UFUU H C2PCIR EE02H X --- CAN2 Port Control/Interrupt Register XXXX H C2LGML EE0AH X --- CAN2 Lower Global Mask Long UUUU H C2LMLM EE0EH X --- CAN2 Lower Mask of Last Message UUUU H C2UAR EEn2H X --- CAN2 Upper Arbitration Reg. (msg. n) UUUU H C2UGML EE08H X --- CAN2 Upper Global Mask Long UUUU H C2UMLM EE0CH X --- CAN2 Upper Mask of Last Message UUUU H CAPREL FE4AH 25H GPT2 Capture/Reload Register 0000 H CC0 FE80H 40H CAPCOM Register 0 0000 H CC0IC b FF78H BCH CAPCOM Reg. 0 Interrupt Ctrl. Reg. 0000 H CC1 FE82H 41H CAPCOM Register 1 0000 H CC10 FE94H 4AH CAPCOM Register 10 0000 H CC10IC b FF8CH C6H CAPCOM Reg. 10 Interrupt Ctrl. Reg. 0000 H CC11 FE96H 4BH CAPCOM Register 11 0000 H CC11IC b FF8EH C7H CAPCOM Reg. 11 Interrupt Ctrl. Reg. 0000 H CC12 FE98H 4CH CAPCOM Register 12 0000 H CC12IC b FF90H C8H CAPCOM Reg. 12 Interrupt Ctrl. Reg. 0000 H CC13 FE9AH 4DH CAPCOM Register 13 0000 H CC13IC b FF92H C9H CAPCOM Reg. 13 Interrupt Ctrl. Reg. 0000 H CC14 FE9CH 4EH CAPCOM Register 14 0000 H CC14IC b FF94H CAH CAPCOM Reg. 14 Interrupt Ctrl. Reg. 0000 H CC15 FE9EH 4FH CAPCOM Register 15 0000 H CC15IC b FF96H CBH CAPCOM Reg. 15 Interrupt Ctrl. Reg. 0000 H CC16 FE60H 30H CAPCOM Register 16 0000 H CC16IC b F160H E B0H CAPCOM Reg. 16 Interrupt Ctrl. Reg. 0000 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 40 V2.2, 2001-08 CC17 FE62H 31H CAPCOM Register 17 0000 H CC17IC b F162H E B1H CAPCOM Reg. 17 Interrupt Ctrl. Reg. 0000 H CC18 FE64H 32H CAPCOM Register 18 0000 H CC18IC b F164H E B2H CAPCOM Reg. 18 Interrupt Ctrl. Reg. 0000 H CC19 FE66H 33H CAPCOM Register 19 0000 H CC19IC b F166H E B3H CAPCOM Reg. 19 Interrupt Ctrl. Reg. 0000 H CC1IC b FF7AH BDH CAPCOM Reg. 1 Interrupt Ctrl. Reg. 0000 H CC2 FE84H 42H CAPCOM Register 2 0000 H CC20 FE68H 34H CAPCOM Register 20 0000 H CC20IC b F168H E B4H CAPCOM Reg. 20 Interrupt Ctrl. Reg. 0000 H CC21 FE6AH 35H CAPCOM Register 21 0000 H CC21IC b F16AH E B5H CAPCOM Reg. 21 Interrupt Ctrl. Reg. 0000 H CC22 FE6CH 36H CAPCOM Register 22 0000 H CC22IC b F16CH E B6H CAPCOM Reg. 22 Interrupt Ctrl. Reg. 0000 H CC23 FE6EH 37H CAPCOM Register 23 0000 H CC23IC b F16EH E B7H CAPCOM Reg. 23 Interrupt Ctrl. Reg. 0000 H CC24 FE70H 38H CAPCOM Register 24 0000 H CC24IC b F170H E B8H CAPCOM Reg. 24 Interrupt Ctrl. Reg. 0000 H CC25 FE72H 39H CAPCOM Register 25 0000 H CC25IC b F172H E B9H CAPCOM Reg. 25 Interrupt Ctrl. Reg. 0000 H CC26 FE74H 3AH CAPCOM Register 26 0000 H CC26IC b F174H E BAH CAPCOM Reg. 26 Interrupt Ctrl. Reg. 0000 H CC27 FE76H 3BH CAPCOM Register 27 0000 H CC27IC b F176H E BBH CAPCOM Reg. 27 Interrupt Ctrl. Reg. 0000 H CC28 FE78H 3CH CAPCOM Register 28 0000 H CC28IC b F178H E BCH CAPCOM Reg. 28 Interrupt Ctrl. Reg. 0000 H CC29 FE7AH 3DH CAPCOM Register 29 0000 H CC29IC b F184H E C2H CAPCOM Reg. 29 Interrupt Ctrl. Reg. 0000 H CC2IC b FF7CH BEH CAPCOM Reg. 2 Interrupt Ctrl. Reg. 0000 H CC3 FE86H 43H CAPCOM Register 3 0000 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 41 V2.2, 2001-08 CC30 FE7CH 3EH CAPCOM Register 30 0000 H CC30IC b F18CH E C6H CAPCOM Reg. 30 Interrupt Ctrl. Reg. 0000 H CC31 FE7EH 3FH CAPCOM Register 31 0000 H CC31IC b F194H E CAH CAPCOM Reg. 31 Interrupt Ctrl. Reg. 0000 H CC3IC b FF7EH BFH CAPCOM Reg. 3 Interrupt Ctrl. Reg. 0000 H CC4 FE88H 44H CAPCOM Register 4 0000 H CC4IC b FF80H C0H CAPCOM Reg. 4 Interrupt Ctrl. Reg. 0000 H CC5 FE8AH 45H CAPCOM Register 5 0000 H CC5IC b FF82H C1H CAPCOM Reg. 5 Interrupt Ctrl. Reg. 0000 H CC6 FE8CH 46H CAPCOM Register 6 0000 H CC6IC b FF84H C2H CAPCOM Reg. 6 Interrupt Ctrl. Reg. 0000 H CC7 FE8EH 47H CAPCOM Register 7 0000 H CC7IC b FF86H C3H CAPCOM Reg. 7 Interrupt Ctrl. Reg. 0000 H CC8 FE90H 48H CAPCOM Register 8 0000 H CC8IC b FF88H C4H CAPCOM Reg. 8 Interrupt Ctrl. Reg. 0000 H CC9 FE92H 49H CAPCOM Register 9 0000 H CC9IC b FF8AH C5H CAPCOM Reg. 9 Interrupt Ctrl. Reg. 0000 H CCM0 b FF52H A9H CAPCOM Mode Control Register 0 0000 H CCM1 b FF54H AAH CAPCOM Mode Control Register 1 0000 H CCM2 b FF56H ABH CAPCOM Mode Control Register 2 0000 H CCM3 b FF58H ACH CAPCOM Mode Control Register 3 0000 H CCM4 b FF22H 91H CAPCOM Mode Control Register 4 0000 H CCM5 b FF24H 92H CAPCOM Mode Control Register 5 0000 H CCM6 b FF26H 93H CAPCOM Mode Control Register 6 0000 H CCM7 b FF28H 94H CAPCOM Mode Control Register 7 0000 H CP FE10H 08H CPU Context Pointer Register FC00 H CRIC b FF6AH B5H GPT2 CAPREL Interrupt Ctrl. Reg. 0000 H CSP FE08H 04H CPU Code Seg. Pointer Reg. (read only) 0000 H DP0L b F100H E 80H P0L Direction Control Register 00 H DP0H b F102H E 81H P0H Direction Control Register 00 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 42 V2.2, 2001-08 DP1L b F104H E 82H P1L Direction Control Register 00 H DP1H b F106H E 83H P1H Direction Control Register 00 H DP2 b FFC2H E1H Port 2 Direction Control Register 0000 H DP3 b FFC6H E3H Port 3 Direction Control Register 0000 H DP4 b FFCAH E5H Port 4 Direction Control Register 00 H DP6 b FFCEH E7H Port 6 Direction Control Register 00 H DP7 b FFD2H E9H Port 7 Direction Control Register 00 H DP8 b FFD6H EBH Port 8 Direction Control Register 00 H DPP0 FE00H 00H CPU Data Page Pointer 0 Reg. (10 bits) 0000 H DPP1 FE02H 01H CPU Data Page Pointer 1 Reg. (10 bits) 0001 H DPP2 FE04H 02H CPU Data Page Pointer 2 Reg. (10 bits) 0002 H DPP3 FE06H 03H CPU Data Page Pointer 3 Reg. (10 bits) 0003 H EXICON b F1C0H E E0H External Interrupt Control Register 0000 H EXISEL b F1DAH E EDH External Interrupt Source Select Reg. 0000 H FOCON b FFAAH D5H Frequency Output Control Register 0000 H IDCHIP F07CH E 3EH Identifier 0CXX H IDMANUF F07EH E 3FH Identifier 1820 H IDMEM F07AH E 3DH Identifier X040 H IDMEM2 F076H E 3BH Identifier XXXX H IDPROG F078H E 3CH Identifier XXXX H ISNC b F1DEH E EFH Interrupt Subnode Control Register 0000 H MDC b FF0EH 87H CPU Multiply Divide Control Register 0000 H MDH FE0CH 06H CPU Multiply Divide Reg. – High Word 0000 H MDL FE0EH 07H CPU Multiply Divide Reg. – Low Word 0000 H ODP2 b F1C2H E E1H Port 2 Open Drain Control Register 0000 H ODP3 b F1C6H E E3H Port 3 Open Drain Control Register 0000 H ODP4 b F1CAH E E5H Port 4 Open Drain Control Register 00 H ODP6 b F1CEH E E7H Port 6 Open Drain Control Register 00 H ODP7 b F1D2H E E9H Port 7 Open Drain Control Register 00 H ODP8 b F1D6H E EBH Port 8 Open Drain Control Register 00 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 43 V2.2, 2001-08 ONES b FF1EH 8FH Constant Value 1’s Register (read only) FFFF H P0H b FF02H 81H Port 0 High Reg. (Upper half of PORT0) 00 H P0L b FF00H 80H Port 0 Low Reg. (Lower half of PORT0) 00 H P1DIDIS FEA4H 52H Port 1 Digital Input Disable Register 0000 H P1H b FF06H 83H Port 1 High Reg. (Upper half of PORT1) 00 H P1L b FF04H 82H Port 1 Low Reg. (Lower half of PORT1) 00 H P2 b FFC0H E0H Port 2 Register 0000 H P3 b FFC4H E2H Port 3 Register 0000 H P4 b FFC8H E4H Port 4 Register (8 bits) 00 H P5 b FFA2H D1H Port 5 Register (read only) XXXX H P5DIDIS b FFA4H D2H Port 5 Digital Input Disable Register 0000 H P6 b FFCCH E6H Port 6 Register (8 bits) 00 H P7 b FFD0H E8H Port 7 Register (8 bits) 00 H P8 b FFD4H EAH Port 8 Register (8 bits) 00 H PECC0 FEC0H 60H PEC Channel 0 Control Register 0000 H PECC1 FEC2H 61H PEC Channel 1 Control Register 0000 H PECC2 FEC4H 62H PEC Channel 2 Control Register 0000 H PECC3 FEC6H 63H PEC Channel 3 Control Register 0000 H PECC4 FEC8H 64H PEC Channel 4 Control Register 0000 H PECC5 FECAH 65H PEC Channel 5 Control Register 0000 H PECC6 FECCH 66H PEC Channel 6 Control Register 0000 H PECC7 FECEH 67H PEC Channel 7 Control Register 0000 H PICON b F1C4H E E2H Port Input Threshold Control Register 0000 H POCON0H F082H E 41H Port P0H Output Control Register 0000 H POCON0L F080H E 40H Port P0L Output Control Register 0000 H POCON1H F086H E 43H Port P1H Output Control Register 0000 H POCON1L F084H E 42H Port P1L Output Control Register 0000 H POCON2 F088H E 44H Port P2 Output Control Register 0000 H POCON20 F0AAH E 55H Dedicated Pin Output Control Register 0000 H POCON3 F08AH E 45H Port P3 Output Control Register 0000 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 44 V2.2, 2001-08 POCON4 F08CH E 46H Port P4 Output Control Register 0000 H POCON6 F08EH E 47H Port P6 Output Control Register 0000 H POCON7 F090H E 48H Port P7 Output Control Register 0000 H POCON8 F092H E 49H Port P8 Output Control Register 0000 H PP0 F038H E 1CH PWM Module Period Register 0 0000 H PP1 F03AH E 1DH PWM Module Period Register 1 0000 H PP2 F03CH E 1EH PWM Module Period Register 2 0000 H PP3 F03EH E 1FH PWM Module Period Register 3 0000 H PSW b FF10H 88H CPU Program Status Word 0000 H PT0 F030H E 18H PWM Module Up/Down Counter 0 0000 H PT1 F032H E 19H PWM Module Up/Down Counter 1 0000 H PT2 F034H E 1AH PWM Module Up/Down Counter 2 0000 H PT3 F036H E 1BH PWM Module Up/Down Counter 3 0000 H PTCR F0AEH E 57H Port Temperature Compensation Reg. 0000 H PW0 FE30H 18H PWM Module Pulse Width Register 0 0000 H PW1 FE32H 19H PWM Module Pulse Width Register 1 0000 H PW2 FE34H 1AH PWM Module Pulse Width Register 2 0000 H PW3 FE36H 1BH PWM Module Pulse Width Register 3 0000 H PWMCON0 b FF30H 98H PWM Module Control Register 0 0000 H PWMCON1 b FF32H 99H PWM Module Control Register 1 0000 H PWMIC b F17EH E BFH PWM Module Interrupt Control Register 0000 H RP0H b F108H E 84H System Start-up Config. Reg. (Rd. only) XX H RSTCON b F1E0H m --- Reset Control Register 00XX H RTCH F0D6H E 6BH RTC High Register XXXX H RTCL F0D4H E 6AH RTC Low Register XXXX H S0BG FEB4H 5AH Serial Channel 0 Baud Rate Generator Reload Register 0000H S0CON b FFB0H D8H Serial Channel 0 Control Register 0000 H S0EIC b FF70H B8H Serial Channel 0 Error Interrupt Ctrl. Reg 0000 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 45 V2.2, 2001-08 S0RBUF FEB2H 59H Serial Channel 0 Receive Buffer Reg. (read only) XXH S0RIC b FF6EH B7H Serial Channel 0 Receive Interrupt Control Register 0000H S0TBIC b F19CH E CEH Serial Channel 0 Transmit Buffer Interrupt Control Register 0000H S0TBUF FEB0H 58H Serial Channel 0 Transmit Buffer Register (write only) 00H S0TIC b FF6CH B6H Serial Channel 0 Transmit Interrupt Control Register 0000H SP FE12H 09H CPU System Stack Pointer Register FC00 H SSCBR F0B4H E 5AH SSC Baudrate Register 0000 H SSCCON b FFB2H D9H SSC Control Register 0000 H SSCEIC b FF76H BBH SSC Error Interrupt Control Register 0000 H SSCRB F0B2H E 59H SSC Receive Buffer XXXX H SSCRIC b FF74H BAH SSC Receive Interrupt Control Register 0000 H SSCTB F0B0H E 58H SSC Transmit Buffer 0000 H SSCTIC b FF72H B9H SSC Transmit Interrupt Control Register 0000 H STKOV FE14H 0AH CPU Stack Overflow Pointer Register FA00 H STKUN FE16H 0BH CPU Stack Underflow Pointer Register FC00 H SYSCON b FF12H 89H CPU System Configuration Register 1)0XX0H SYSCON1 b F1DCH E EEH CPU System Configuration Register 1 0000 H SYSCON2 b F1D0H E E8H CPU System Configuration Register 2 0000 H SYSCON3 b F1D4H E EAH CPU System Configuration Register 3 0000 H T0 FE50H 28H CAPCOM Timer 0 Register 0000 H T01CON b FF50H A8H CAPCOM Timer 0 and Timer 1 Ctrl. Reg. 0000 H T0IC b FF9CH CEH CAPCOM Timer 0 Interrupt Ctrl. Reg. 0000 H T0REL FE54H 2AH CAPCOM Timer 0 Reload Register 0000 H T1 FE52H 29H CAPCOM Timer 1 Register 0000 H T1IC b FF9EH CFH CAPCOM Timer 1 Interrupt Ctrl. Reg. 0000 H T1REL FE56H 2BH CAPCOM Timer 1 Reload Register 0000 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 46 V2.2, 2001-08 T14 F0D2H E 69H RTC Timer 14 Register XXXX H T14REL F0D0H E 68H RTC Timer 14 Reload Register XXXX H T2 FE40H 20H GPT1 Timer 2 Register 0000 H T2CON b FF40H A0H GPT1 Timer 2 Control Register 0000 H T2IC b FF60H B0H GPT1 Timer 2 Interrupt Control Register 0000 H T3 FE42H 21H GPT1 Timer 3 Register 0000 H T3CON b FF42H A1H GPT1 Timer 3 Control Register 0000 H T3IC b FF62H B1H GPT1 Timer 3 Interrupt Control Register 0000 H T4 FE44H 22H GPT1 Timer 4 Register 0000 H T4CON b FF44H A2H GPT1 Timer 4 Control Register 0000 H T4IC b FF64H B2H GPT1 Timer 4 Interrupt Control Register 0000 H T5 FE46H 23H GPT2 Timer 5 Register 0000 H T5CON b FF46H A3H GPT2 Timer 5 Control Register 0000 H T5IC b FF66H B3H GPT2 Timer 5 Interrupt Control Register 0000 H T6 FE48H 24H GPT2 Timer 6 Register 0000 H T6CON b FF48H A4H GPT2 Timer 6 Control Register 0000 H T6IC b FF68H B4H GPT2 Timer 6 Interrupt Control Register 0000 H T7 F050H E 28H CAPCOM Timer 7 Register 0000 H T78CON b FF20H 90H CAPCOM Timer 7 and 8 Control Reg. 0000 H T7IC b F17AH E BEH CAPCOM Timer 7 Interrupt Ctrl. Reg. 0000 H T7REL F054H E 2AH CAPCOM Timer 7 Reload Register 0000 H T8 F052H E 29H CAPCOM Timer 8 Register 0000 H T8IC b F17CH E BFH CAPCOM Timer 8 Interrupt Ctrl. Reg. 0000 H T8REL F056H E 2BH CAPCOM Timer 8 Reload Register 0000 H TFR b FFACH D6H Trap Flag Register 0000 H WDT FEAEH 57H Watchdog Timer Register (read only) 0000 H WDTCON b FFAEH D7H Watchdog Timer Control Register 2)00XXH XP0IC b F186H E C3H CAN1 Module Interrupt Control Register 0000 H XP1IC b F18EH E C7H CAN2 Module Interrupt Control Register 0000 H XP2IC b F196H E CBH Unassigned Interrupt Control Register 0000 H Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 47 V2.2, 2001-08 XP3IC b F19EH E CFH RTC/PLL Interrupt Control Register 0000 H XPERCON F024H E 12H X-Peripheral Control Register 0401 H ZEROS b FF1CH 8EH Constant Value 0’s Register (read only) 0000 H 1) The system configuration is selected during reset. 2) The reset value depends on the indicated reset source. Table 7 C167CS Registers, Ordered by Name (cont’d) Name Physical Address 8-Bit Addr. Description Reset Value
Data Sheet 48 V2.2, 2001-08 Absolute Maximum Ratings Note: Stresses above those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions ( VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground ( VSS) must not exceed the values defined by the absolute maximum ratings. Table 8 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes min. max. Storage temperature TST -65 150 °C – Junction temperature TJ -40 150 °C under bias Voltage on VDD pins with respect to ground (VSS) VDD -0.5 6.5 V – Voltage on any pin with respect to ground (VSS) VIN -0.5 VDD + 0.5 V – Input current on any pin during overload condition – -10 10 mA – Absolute sum of all input currents during overload condition Power dissipation PDISS – 1.5 W –
Data Sheet 49 V2.2, 2001-08 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C167CS. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 9 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes min. max. Digital supply voltage VDD 4.5 5.5 V Active mode, fCPUmax = 40 MHz 2.51) 1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.
5.5 V PowerDown mode
Digital ground voltage VSS 0 V Reference voltage Overload current IOV – ±5m A P e r p i n 2)3) 2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD , WR, etc. 3) Not 100% tested, guaranteed by design and characterization. Absolute sum of overload currents Σ|IOV| – 50 mA 3) External Load Capacitance CL – 50 pF Pin drivers in fast edge mode4) 4) The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in dynamic current mode must be respected when designing the system. Ambient temperature TA 07 0 °C SAB-C167CS … -40 85 °C SAF-C167CS … -40 125 °C SAK-C167CS …
Data Sheet 50 V2.2, 2001-08 Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C167CS and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the C167CS will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the C167CS. DC Characteristics (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Input low voltage (TTL, all except XTAL1) VIL SR -0.5 0.2 VDD - 0.1 V – Input low voltage XTAL1 VIL2 SR -0.5 0.3 VDD V – Input low voltage (Special Threshold) VILS SR -0.5 2.0 V – Input high voltage (TTL, all except RSTIN and XTAL1) VIH SR 0.2 VDD + 0.9 VDD + 0.5 V – Input high voltage RSTIN (when operated as input) VIH1 SR 0.6 VDD VDD + 0.5 V – Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + 0.5 V – Input high voltage (Special Threshold) VIHS SR 0.8 VDD - 0.2 VDD + 0.5 V – Input Hysteresis (Special Threshold) HYS 400 – mV Series resistance = 0 Ω Output low voltage2) VOL CC – 1.0 V IOL ≤ IOLmax – 0.45 V IOL ≤ IOLnom 3)4) Output high voltage5) VOH CC VDD - 1.0 – V IOH ≥ IOHmax VDD - 0.45 – V IOH ≥ IOHnom 3)4) Input leakage current (Port 5) IOZ1 CC – ±200 nA 0 V < VIN < VDD
Data Sheet 51 V2.2, 2001-08 Input leakage current (all other) IOZ2 CC – ±500 nA 0.45 V < VIN < VDD RSTIN inactive current6) IRSTH 7) – -10 µA VIN = VIH1 RSTIN active current6) IRSTL 8) -100 – µA VIN = VIL READY/RD/WR inact. current9) IRWH 7) – -40 µA VOUT = 2.4 V READY/RD/WR active current9) IRWL 8) -500 – µA VOUT = VOLmax ALE inactive current9) IALEL 7) – 40 µA VOUT = VOLmax ALE active current9) IALEH 8) 500 – µA VOUT = 2.4 V Port 6 inactive current9) IP6H 7) – -40 µA VOUT = 2.4 V Port 6 active current9) IP6L 8) -500 – µA VOUT = VOL1max PORT0 configuration current10) IP0H 7) – -10 µA VIN = VIHmin IP0L 8) -100 – µA VIN = VILmax XTAL1 input current IIL CC – ±20 µA0 V < VIN < VDD Pin capacitance11) (digital inputs/outputs) CIO CC – 10 pF f = 1 MHz TA = 25 °C 1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current IOV. 2) For pin RSTIN this specification is only valid in bidirectional reset mode. 3) The maximum deliverable output current of a port driver depends on the selected output driver mode, see Table 10, Current Limits for Port Output Drivers. The limit for pin groups must be respected. 4) As a rule, with decreasing output current the output levels approach the respective supply level ( VOL → VSS, VOH → VDD). However, only the levels for nominal output currents are guaranteed. 5) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 6) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 k Ω. 7) The maximum current may be drawn while the respective signal line remains inactive. 8) The minimum current must be drawn in order to drive the respective signal line active. 9) This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The READY-pullup is always active, except for Powerdown mode. 10) This specification is valid during Reset and during Adapt-mode. 11) Not 100% tested, guaranteed by design and characterization. DC Characteristics (cont’d) (Operating Conditions apply)1) Parameter Symbol Limit Values Unit Test Condition min. max.
Data Sheet 52 V2.2, 2001-08 Table 10 Current Limits for Port Output Drivers Port Output Driver Maximum Output Current (IOLmax, -IOHmax)1) Nominal Output Current IOLnom, -IOHnom) P2.7 - P2.0 10 mA 2.5 mA (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT, RSTIN2)) ----- 2.5 mA All other outputs ----- 1.6 mA 1) An output current above |IOXnom| may be drawn from up to three pins (P2.7-P2.0 only) at the same time. For any group of 16 neighboring port output pins the total output current in each direction ( ΣIOL and/or Σ-IOH) must remain below 50 mA. 2) Valid for VOL in bidirectional reset mode only. Power Consumption C167CS (Operating Conditions apply) Parameter Symbol Limit Values Unit Test Condition min. max. Power supply current (active) with all peripherals active IDD5 – 20 + 3.2 × fCPU mA RSTIN = VIL fCPU in [MHz]1) 1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. Idle mode supply current with all peripherals active IIDX5 2) These values are not 100% tested but verified by means of system characterization. – 15 + 1.4 × fCPU mA RSTIN = VIH1 fCPU in [MHz]1) Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 IIDO 3)2) 3) This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry (see also application notes AP2420: Crystal Oscillator, AP2424: Ceramic Resonator Oscillator). – 800 + 60 × fOSC µAR S T I N = VIH1 fOSC in [MHz]1) Sleep and Power-down mode supply current with RTC running IPDR 3)2) – 800 + 30 × fOSC µA VDD = VDDmax fOSC in [MHz]4) 4) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. Sleep and Power-down mode supply current with RTC disabled IPDO – 50 µA VDD = VDDmax
Data Sheet 53 V2.2, 2001-08 Figure 9 Idle and Power Down Supply Current as a Function of Oscillator Frequency I [µA] fOSC [MHz]10 20 30 40 IPDOmax IPDRmax IIDOmax IIDOtyp 1000 2000 3000
Data Sheet 54 V2.2, 2001-08 Figure 10 Supply/Idle Current as a Function of Operating Frequency I [mA] fCPU [MHz]10 20 30 40 IDD5max IDD5typ IIDX5max IIDX5typ 100 120 140
Data Sheet 55 V2.2, 2001-08 AC Characteristics Definition of Internal Timing The internal operation of the C167CS is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11). Figure 11 Generation Mechanisms for the CPU Clock The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C167CS. Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4. The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins MCT04338 fOSC fCPU Phase Locked Loop Operation TCL fOSC fCPU Direct Clock Drive fOSC fCPU Prescaler Operation TCL TCL TCL TCL TCL
Data Sheet 56 V2.2, 2001-08 P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Prescaler Operation When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fOSC. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fOSC for any TCL. Phase Locked Loop When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is enabled and provides the CPU clock (see Table 11). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fOSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Table 11 C167CS Clock Generation Modes CLKCFG (RP0H.7-5) CPU Frequency fCPU = fOSC × F External Clock Input Range1) 1) The external clock input range refers to a CPU clock range of 10 … 40 MHz. Notes 11 1 fOSC × 4 2.5 to 10 MHz Default configuration 110 fOSC × 3 3.33 to 13.33 MHz – 101 fOSC × 2 5 to 20 MHz – 100 fOSC × 5 2 to 8 MHz – 011 fOSC × 1 1 to 40 MHz Direct drive 2) 2) The maximum frequency depends on the duty cycle of the external clock signal. 010 fOSC × 1.5 6.66 to 26.66 MHz – 001 fOSC / 2 2 to 50 MHz 3) 3) In prescaler mode the full CPU clock range cannot be used. CPU clock via prescaler 000 fOSC × 2.5 4 to 16 MHz –
Data Sheet 57 V2.2, 2001-08 Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and Figure 12). For a period of N × TCL the minimum value is computed using the corresponding deviation DN: (N × TCL)min = N × TCLNOM - DN; DN [ns] = ±(13.3 + N × 6.3) / fCPU [MHz], where N = number of consecutive TCLs and 1 ≤ N ≤ 40. and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12). Figure 12 Approximated Maximum Accumulated PLL Jitter ±10 1 5 10 20 DN ±20 ±26.5 ns ±30 40 and 10 MHz This approximated formula is valid for 1 N 40 MHz.CPUf
25 MHz
33 MHz
N
16 MHz
20 MHz
10 MHz
Max. jitter
40 MHz
Data Sheet 58 V2.2, 2001-08 Direct Drive When direct drive is configured (CLKCFG = 011 B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fOSC × DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated so the duration of 2TCL is always 1/ fOSC. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1, 3, … ). Timings that require an even number of TCLs (2, 4, … ) may use the formula 2TCL = 1/fOSC.
Data Sheet 59 V2.2, 2001-08 AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Figure 13 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 40 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). Table 12 External Clock Drive Characteristics Parameter Symbol Direct Drive 1:1 Prescaler 2:1 PLL 1:N Unit Oscillator period tOSC SR 25 – 20 – 371) 1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. 5001) ns High time2) 2) The clock input signal must reach the defined levels VIL2 and VIH2. t1 SR 12 3) 3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency ( fCPU) in direct drive mode depends on the duty cycle of the clock input signal. – 5 – 10 – ns Low time2) t2 SR 12 3) – 5 – 10 – ns Rise time2) t3 SR – 8 – 5 – 10 ns Fall time2) t4 SR – 8 – 5 – 10 ns MCT02534 3t 4t VIH2 VIL VDD0.5 OSCt
Data Sheet 60 V2.2, 2001-08 A/D Converter Characteristics (Operating Conditions apply) Table 13 A/D Converter Characteristics Parameter Symbol Limit Values Unit Test Conditionmin. max. Analog reference supply VAREF SR 4.0 VDD + 0.1 V 1) 1) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages within the defined voltage range. If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V (i.e. VAREF = VDD = +0.2 V) the maximum TUE is increased to ±3/11 LSB. This range is not 100% tested. The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins and P1H pins (see IOV specification) does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be ±4 LSB (±12 LSB for channels 16 … 23). Analog reference ground VAGNDSR VSS - 0.1 VSS + 0.2 V – Analog input voltage range VAIN SR VAGND VAREF V 2) 2) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. Basic clock frequency fBC 0.5 6.25 MHz 3) 3) The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. Conversion time tC CC – 40 tBC + tS + 2tCPU – 4) tCPU = 1/fCPU 4) This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock tBC depend on programming and can be taken from Table 14. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. Calibration time after reset tCAL CC – 3328 tBC – 5) Total unadjusted error TUE CC 1) – ±2 LSB Channels 0 … 15 – ±10 LSB Channels 16 … 23 Internal resistance of reference voltage source RAREF SR – tBC/60 - 0.25 kΩ tBC in [ns]6)7) Internal resistance of analog source RASRC SR – tS/450 - 0.25 kΩ tS in [ns]7)8) ADC input capacitance CAIN CC – 33 pF 7)
Data Sheet 61 V2.2, 2001-08 Sample time and conversion time of the C167CS ’s A/D Converter are programmable. Table 14 should be used to calculate the above timings. The limit values for fBC must not be exceeded when selecting ADCTC. Converter Timing Example: Assumptions: fCPU = 25 MHz (i.e. tCPU = 40 ns), ADCTC = ‘00’, ADSTC = ‘00’. Basic clock fBC = fCPU / 4 = 6.25 MHz, i.e. tBC = 160 ns. Sample time tS = tBC × 8 = 1280 ns. Conversion time tC = tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.8 µs. 5) As the default basic clock after reset is fBC = fCPU / 4 the ADC’s prescaler (ADCTC) must be programmed to a valid factor as early as possible. A timeframe of approx. 6000 CPU clock cycles is sufficient to ensure a proper reset calibration. This corresponds to minimum 300 instructions (worst case: external MUX bus with maximum waitstates). This is required for fCPU > 33 MHz and is recommended for fCPU > 25 MHz. During the reset calibration conversions can be executed (with the current accuracy). The time required for these conversions is added to the total reset calibration time. 6) During the conversion the ADC ’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. 7) Not 100% tested, guaranteed by design and characterization. 8) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from Table 14. Table 14 A/D Converter Computation Table ADCON.15|14 (ADCTC) A/D Converter Basic Clock fBC ADCON.13|12 (ADSTC) Sample time tS 00 fCPU / 4 00 tBC × 8 01 fCPU / 2 01 tBC × 16 10 fCPU / 16 10 tBC × 32 11 fCPU / 8 11 tBC × 64
Data Sheet 63 V2.2, 2001-08 AC Characteristics Figure 16 CLKOUT Signal Timing Variable Memory Cycles The bus timing shown below is programmable via the BUSCONx registers. The duration of ALE and two types of waitstates can be selected. This table summarizes the possible bus cycle durations. Table 15 CLKOUT Reference Signal Parameter Symbol Limits Unit min. max. CLKOUT cycle time tc5 CC 40/30/25 1) 1) The CLKOUT cycle time is influenced by the PLL jitter (given values apply to fCPU = 25/33/40 MHz). For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for fCPU > 25 MHz). For longer periods the relative deviation decreases (see PLL deviation formula). ns CLKOUT high time tc6 CC 8 – ns CLKOUT low time tc7 CC 6 – ns CLKOUT rise time tc8 CC – 4n s CLKOUT fall time tc9 CC – 4n s Table 16 Variable Memory Cycles Bus Cycle Type Bus Cycle Duration Unit 25/33/40 MHz, 0 Waitstates Demultiplexed bus cycle with normal ALE + 2 × (1 - <MTTC>) TCL 80 ns / 60.6 ns / 50 ns Demultiplexed bus cycle with extended ALE + 2 × (1 - <MTTC>) TCL 120 ns / 90.9 ns / 75 ns Multiplexed bus cycle with normal ALE + 2 × (1 - <MTTC>) TCL 120 ns / 90.9 ns / 75 ns Multiplexed bus cycle with extended ALE + 2 × (1 - <MTTC>) TCL 160 ns / 121.2 ns / 100 ns MCT04415 CLKOUT tc5 tc6 7tc 8tc 9tc
Data Sheet 64 V2.2, 2001-08 Table 17 External Bus Cycle Timing (Operating Conditions apply) Parameter Symbol Limits Unit min. max. Output delay from CLKOUT falling edge Valid for: address (MUX on PORT0), write data out tc10 CC 0 14 ns Output delay from CLKOUT edge Valid for: latched CS, ALE (normal) tc11 CC -3 6 ns Output delay from CLKOUT edge Valid for: WR, WRL, WRH, WrCS tc12 CC -4 7 ns Output delay from CLKOUT edge Valid for: RD, RdCS tc13 CC -2 7 ns Input setup time to CLKOUT falling edge Valid for: read data in tc14 SR 10 – ns Input hold time after CLKOUT falling edge Valid for: read data in1) tc15 SR 0 – ns Output delay from CLKOUT falling edge Valid for: address (on PORT1 and/or P4), BHE tc16 CC 0 9 2) ns Output hold time after CLKOUT falling edge Valid for: address, BHE3) tc17 CC -2 8 ns Output hold time after CLKOUT edge4) Valid for: write data out tc18 CC -1 – ns Output delay from CLKOUT falling edge Valid for: ALE (extended), early CS tc19 CC -4 4 ns Turn off delay after CLKOUT edge4) Valid for: write data out tc20 CC – 7n s Turn on delay after CLKOUT falling edge4) Valid for: write data out tc21 CC -5 – ns Output hold time after CLKOUT edge Valid for: early CS tc22 CC -6 4 ns 1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. 2) If the capacitive load on the respective output pins is limited to 30 pF the maximum output delay tc16 can be reduced to 8 ns. 3) Due to comparable propagation delays the address does not change before WR goes high. The minimum output delay (tc17min) is therefore the actual value of tc12. 4) Not 100% tested, guaranteed by design and characterization.
Data Sheet 65 V2.2, 2001-08 The bandwidth of a parameter (minimum and maximum value) covers the whole operating range (temperature, voltage) as well as process variations. Within a given device, however, this bandwidth is smaller than the specified range. This is also due to interdependencies between certain parameters. Some of these interdependencies are described as relative timing (see below) or in additional notes (see standard timing). General Notes For The Following Bus Timing Figures These standard notes apply to all subsequent timing figures. Additional individual notes are placed at the respective figure. 1) The falling edge of signals RD and WR /WRH/WRL/WrCS is controlled by the Read/Write delay feature (bit BUSCON.RWDCx). 2) The rising edge of signal WR/WRH/WRL/WrCS is controlled by the early write feature (bit BUSCON.EWENx). 3) A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive. 4) A bus cycle is extended here, if an MTTC waitstate is selected. Table 18 External Bus Relative Timing (Operating Conditions apply)1) 1) Not 100% tested, guaranteed by design and characterization. Parameter Symbol Limits Unit min. max. Output hold time after WR rising edge2) Valid for: address, write data out 2) See also note 3) in Table 17. t50 CC 0 – ns Input hold time after RD rising edge Valid for: read data in t51 SR – 0n s
Data Sheet 66 V2.2, 2001-08 Figure 17 Demultiplexed Bus, Write Access Normal ALE Cycle Extended ALE Cycle WR, WrCS D15-D0 A23-A0, WRL, WRH, BHE 16tc tc tc Extended ALE CSxE, CSxL CLKOUT Normal ALE tc tc19 11 tc 19tc tc tc MCTC 12tc Valid MTTC tc12 tc17 MCT04435 tc19 tc19 tc18 20tc10tc tc21 tc12 Data OUT Note: Write data is deactivated 1 TCL earlier if early write is enabled (same timing).
Data Sheet 67 V2.2, 2001-08 Figure 18 Demultiplexed Bus, Read Access Normal ALE Cycle Extended ALE Cycle RdCS D15-D0 A23-A0, RD, BHE 16tc tc tc Extended ALE CSxE, CSxL CLKOUT Normal ALE tc tc19 11 tc 19tc tc tc tc MCTC 13tc Valid MTTC Data IN tc tc13 tc17 MCT04436 tc19 tc19
Data Sheet 68 V2.2, 2001-08 Figure 19 Multiplexed Bus, Write Access Normal ALE Cycle Extended ALE Cycle AD15-AD0 A23-A16, BHE 16tc tc16 Extended ALE CSxE, CSxL CLKOUT Normal ALE tc tc19 11 tc 19tc tc tc MCTC Valid MTTC tc17 MCT04437 tc19 tc19 Low Address tc tc21 10 tc 17tc Data OUT tc tc20 10tc tc21 Low Address tc17 tc Data OUT tc18 tc20 tc tc12 12 tc tc12 WRL, WRH, WR, WrCS (Normal ALE) (Extended ALE) AD15-AD0 Note: Write data is deactivated 2 TCL earlier if early write is enabled (same timing).
Data Sheet 69 V2.2, 2001-08 Figure 20 Multiplexed Bus, Read Access Normal ALE Cycle Extended ALE Cycle RdCS AD15-AD0 A23-A16, RD, BHE 16tc tc tc Extended ALE CSxE, CSxL CLKOUT Normal ALE tc tc19 11 tc 19tc tc tc tc MCTC 13tc Valid MTTC Data IN tc tc13 tc17 MCT04438 tc19 tc19 (Extended ALE) AD15-AD0 (Normal ALE) Data IN tc tc Low Address tc10 tc21 tc17 20tc tc Low Address 1721 tc10 tc 20tc
Data Sheet 70 V2.2, 2001-08 Bus Cycle Control via READY Input The duration of an external bus cycle can be controlled by the external circuitry via the READY input signal. Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT. Asynchronous READY puts no timing constraints on the input signal but incurs one waitstate minimum due to the additional synchronization stage. Notes (Valid for Table 19 and Figure 21) 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 3) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT, it must fulfill tc27 in order to be safely synchronized. Proper deactivation of READY is guaranteed if READY is deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 4) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 5) If the next following bus cycle is READY controlled, an active READY signal must be disabled before the first valid sample point for the next bus cycle. This sample point depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates and the ALE mode of the next following cycle. If the current cycle uses a multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time. Table 19 READY Timing (Operating Conditions apply) Parameter Symbol Limit Values Unit min. max. Input setup time to CLKOUT rising edge Valid for: READY input tc25 CC 12 – ns Input hold time after CLKOUT rising edge Valid for: READY input tc26 CC 0 – ns Asynchronous READY input low time3) tc27 CC tc5 + tc25 – ns
Data Sheet 71 V2.2, 2001-08 Figure 21 READY Timing MCT04820 CLKOUT D15-D0 Data IN 14tc tc Running Cycle1) READY WS MUX/MTTC D15-D0 Data OUT 20tc tc18 tc10 tc21 (RD, WR) Command 12tc 13tc tc13 19tc/ Synchronous READY tc25 26tc 4) 4) 25tc 26tc 26tc Asynchronous READY 25tc tc 25tc 27tc The next external bus cycle may start here.
Data Sheet 72 V2.2, 2001-08 External Bus Arbitration Table 20 Bus Arbitration Timing (Operating Conditions apply) Parameter Symbol Limit Values Unit min. max. HOLD input setup time to CLKOUT falling edge tc28 SR 14 – ns CLKOUT to BREQ delay tc29 CC -3 6 ns CLKOUT to HLDA delay tc30 CC -2 6 ns CSx release1) 1) Not 100% tested, guaranteed by design and characterization. tc31 CC 0 10 ns CSx drive tc32 CC -3 4 ns Other signals release1) tc33 CC 0 10 ns Other signals drive1) tc34 CC 0 6 ns
Data Sheet 73 V2.2, 2001-08 Figure 22 External Bus Arbitration, Releasing the Bus Notes 1) The C167CS will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. 3) The CS outputs will be resistive high (pullup) after t33. Latched CS outputs are driven high for 1 TCL before the output drivers are switched off. tc MCT04421 CS Signals Other 33tc HOLD HLDA BREQ CLKOUT 28tc 30tc 29tc
Data Sheet 74 V2.2, 2001-08 Figure 23 External Bus Arbitration, (Regaining the Bus) Notes 4) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C167CS requesting the bus. 5) The next C167CS driven bus cycle may start here. tc MCT04422 CS Signals Other 34tc HOLD HLDA BREQ CLKOUT 28tc 30tc 29tc tc29tc29
Data Sheet 75 V2.2, 2001-08 External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C167CS can be accessed (during hold states) by an external master like an asynchronous SRAM. Figure 24 External Access to the XRAM Table 21 XRAM Access Timing (Operating Conditions apply) Parameter Symbol Limit Values Unit min. max. Address setup time before RD/WR falling edge t40 SR 4 – ns Address hold time after RD/WR rising edge t41 SR 0 – ns Data turn on delay after RD falling edge Read t42 CC 2 – ns Data output valid delay after address latched t43 CC – 37 ns Data turn off delay after RD rising edge t44 CC 0 10 ns Write data setup time before WR rising edge Write t45 SR 10 – ns Write data hold time after WR rising edge t46 SR 1 – ns WR pulse width t47 SR 18 – ns WR signal recovery time t48 SR t40 – ns Read Data t42 t 44t MCT04423 (RD, WR) Write Data Command Address 40t 45t 47t 46t 48t 41t
Data Sheet 76 V2.2, 2001-08 Package Outlines P-MQFP-144-6 (Plastic Metric Quad Flat Package) GPM09391 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device
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