BW0405XA SAMSUNG | Alldatasheet
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Technical content
0.35µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC BW0405XA GENERAL DESCRIPTION This product is SD Digital-To-Analog Converter for digital audio System (CDP). The product contains Serial-to- Parallel Converter and Compensation Filter, Digital Volume Attenuator by the MICOM Interface, De-Emphasis Filter, FIR filter, Sinc Filter, digital sigma-delta modulator, analog postfilter, AIF (Anti-Image-Filter). The normal input and output channels provides 90dB SNR (Signal to Noise Ratio) over in band (20kHz). The product employs the 1bit 4th-order sigma-delta architecture with 16bit resolution, over sampling of 64X. And analog postfilter with low clock sensitivity and linear phase, filters the shaping-nosie and outputs analog voltage with high resolution. An on-chip reference voltage is included to allow single supply operations.
FEATURES
16bit SD Digital-To-Analog Converter On-Chip Analog Postfilter Filtered Line-Level Outputs, Linear Phase Filtering On-Chip Voltage Reference 90dB SNR Sampling Rate 44.1kHz Input Rate 1Fs or 2Fs by Normal Mode/Double Mode Selection Zero Input Detection Mute On-Chip Compensation Filter Input Volume Attenuator by the MICOM Interface On-Chip De-Emphasis Filter On-Chip 4 times oversampling Digital Filter Low Clock Jitter Sensitivity Single 3.3V~2.5V Power Supply
APPLICATIONS
CD Player, Portable CD Player, CD-ROM, Video-CD, Mini-Disk, DVD etc
BW0405XA 0.35 µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC FUNCTIONAL BLOCK DIAGRAM DAC Analog Postfilter Sinc Filter Sigma-Delta Modulator Compensation Filter De-emphsis FIR Filter Anti-Imaging Filter Timing Generation Voltage Reference S/P Converter Attenuator SDATA BCK LRCK AOUTL VREF VHALF IREF AOUT R M L D M D A T A M C L K MICOM Interface D E E M D N M S C K R S T B B I S T O N P M U T E L P D L T S E L I A D S R I A D S L I F S O D S R O D S L O F S S D I A G S E R R O R B VDDD VSSD VDDA VSSA
0.35µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC BW0405XA EMBEDDED CORE BLOCK DIAGRAM MSCK BCK LRCK SDATA AOUTL VHALF VREF AOUTR DEEM DN MUTEL PDL RSTB V S S A V D D A V D D D V S S D Audio Processor (DSP) bw0405xa SDIAG SERRORB OFS64 ODSL ODSR BISTONP TSEL IFS64 IADSL IADSR MUX_SEL External Input s These are test pins for internal blocks of the core. So you don't need the internal test mode. Make the test control pins disable ('L') state and Output and bidirectional pins leave foalting. MCLK MLD MDATA M U X 4 IREF VSSD External EMBEDDED CORE USER GUIDE Digital serial data input and clock input refer to digital input format. Digital control pins inform refer to pin description. Micom I/F pin inform refer to micom interface. External application of analog output pins refer to application circuit. I f you want to test only embedded analog core block (Sigma-Delta DAC), you can do it just adding the 4 pins to supply digital serial input data (LRCK, BCK, SDATA, MSCK) and MUX block. Analog power(VDDA,VSSA) and digital power(VDDD, VSSD) should be seperated. Two pads should be dedicated to analog power(VDDA, VSSA) I f you need not use test mode for the testability of internal core block, you make internal core block test pins disable state. (Test Input pins are 'L' state and Test output, bidirection pins leave floating)
BW0405XA 0.35 µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC CORE PIN DESCRIPTION Symbol I/O Type I/O Pad Description Power Supply Pins VDDD DP vdd3t_bb Digital Supply VSSD DG vsst_bb Digital Ground VDDA AP vdd3t_bb Analog Supply VSSA AG vsst_bb Analog Ground Digital Pins MSCK DI picc_bb Master Clock Input. 384Fs Clock BCK DI picc_bb Bit Clock Input. (32Fs or 64Fs) LRCK DI picc_bb Sample Rate Clock Input. (Fs or 2Fs) SDATA DI picc_bb Serial Digital Input MCLK DI picc_bb Micom Interface Clock Input MLD DI picc_bb Micom Interface Command load Input (When low,load) MDATA DI picc_bb Micom Interface Command Data Input DEEM DI picc_bb De-Emphasis On/Off. "H" is enabled. "L" is disabled. DN DI picc_bb Input Rate Select. High is Double(2Fs) Mode, Low is Normal(Fs) Mode. MUTEL DI picc_bb Analog Output Mute. "L" enabled PDL DI picc_bb Power Down. "L" enabled RSTB DI picc_bb Reset Input. "L" Enabled Analog Pins AOUTL AO poa_bb Analog Output for L-CH AOUTR AO poa_bb Analog Output for R-CH VHALF AO poar50_bb Reference Voltage Output for Bypass VREF AO poar50_bb Reference Voltage Output for Bypass Core Internal Block Test Pins BISTONP DI picc_bb Memory Bist Test Mode. "H" enabled TSEL DI picc_bb Test pin for Analog Postfilter Input Selection IFS64 DI picc_bb 64X Sampling Clock Input for Analog Postfilter (When TSEL=H) IADSL DI picc_bb Inputs for Analog Postfilter of L-CH (When TSEL=H) IADSR DI picc_bb Inputs for Analog Postfilter of R-CH (When TSEL=H) SDIAG DO pot2_bb Test Output pin for embeded memory BIST (BIST_ON="H") SERRORB DO pot2_bb Test Output Pin for Embeded memory BIST (BIST_ON="H") OFS64 DO pot2_bb 64X Sampling Clock output for Digital sigma-delta Modulator ODSL DO pot2_bb L-CH Output for Digital sigma-delta Modulator. ODSR DO pot2_bb R-CH Output for Digital sigma-delta Modulator. IREF AB poa_bb Test Pin for Analog Supply Current
0.35µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC BW0405XA I/O Type Abbr. AI: Analog Input DI: Digital Input AO: Analog Output DO: Digital Output AB: Analog Bidirectional DB: Digital Bidirectional AP: Analog Power DP: Digital Power AG: Analog Ground DG: Digital Ground
BW0405XA 0.35 µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC CORE CONFIGURTION bw0405xa Used Power: (VDDD VSSD VDDA VSSA) MSCK BCK LRCK SDATA MCLK MLD MDATA DEEM DN MUTEL PDL RSTB BISTONP TSEL IFS64 IADSL IADSR AOUTL AOUTR VHALF VREF IREF SDIAG SERRORB OFS64 ODSL ODSR ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Values Unit Supply Voltage VDDD,VDDA -0.15 ~ 3.8 V Voltage on Any Digital Pin Vin VSS-0.15 to VDD+0.15 V Storage Temperature Range Tstg -45 to +125 °C RECOMMENDED OPERATING CONDITIONS Charateristics SYMBOL MIN TYP MAX UNITS Supply Voltage VDDD VDDA 2.3 2.5 3.6 V Operating Temp. Topr 0 25 70 °C
0.35µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC BW0405XA
ELECTRICAL CHARACTERISTICS
(VDDD,VDDA=2.5V, Temp=25°C, Fs=44.1kHz, Signal Frequency=20-20kHz, Cload of AoutL, AoutR=10pF) Parameter Min Typ Max Units Resolution 16 bits SNR<1> 80 90 dB SND(THD+Noise)<3> 76 80 dB Dynamic Range<4> 85 90 dB Reference Voltage Ouput 0.5 x VDDA V Frequency Responce ± 0.1 ± 0.5 dB Analog Output Voltage Range 0.75 x VDDA Vpp Load Impedance 10k Ω Digital Filter Pass Band Ripple ± 0.0072 dB Stop Band Attenuation 62.7 dB Pass Band 0.45 Fs Power Supply Analog Current 2 3 mA Digital Current 5 6 mA Power Dissipation 17.5 22.5 mW Power Down Current 0.1 1 mA NOTES: 1. 1kHz 0dB Sinewave Input, EIAJ 2. 1kHz -3dB Sinewave Input 3. 1kHz 0dB Sinewave Input, (Not EIAJ) 4. 1kHz -60dB Sinewve Input, and then measured data + 60dB
0.5 VDDD
Figure 1. Timing Chart
Table 2. Digital Attenuation Level
5 D 0 0 0 0 0 0
5 D 0 0 0 0 0 1
5 D 0 0 0 0 1 0
5 D 0 0 0 0 1 1
5 D 1 0 0 0 0 0
5 D 1 0 0 0 0 1
5 D 1 0 0 0 1 0
5 D 1 0 0 0 1 1
5 D 0 0 0 1 0 0
5 D 0 0 0 1 0 1
5 D 0 0 0 1 1 0
5 D 0 0 0 1 1 1
5 D 1 0 0 1 0 0
5 D 1 0 0 1 0 1
5 D 1 0 0 1 1 0
5 D 1 0 0 1 1 1
5 D 0 0 1 0 0 0
5 D 0 0 1 0 0 1
5 D 0 0 1 0 1 0
5 D 0 0 1 0 1 1
5 D 1 0 1 0 0 0
5 D 1 0 1 0 0 1
5 D 1 0 1 0 1 0
5 D 1 0 1 0 1 1
5 D 0 0 1 1 0 0
5 D 0 0 1 1 0 1
5 D 0 0 1 1 1 0
5 D 0 0 1 1 1 1
5 D 1 0 1 1 0 0
5 D 1 0 1 1 0 1
5 D 1 0 1 1 1 0
5 D 1 0 1 1 1 1
5 D 0 1 0 0 0 0
5 D 0 1 0 0 0 1
5 D 0 1 0 0 1 0
5 D 0 1 0 0 1 1
5 D 1 1 0 0 0 0
5 D 1 1 0 0 0 1
5 D 1 1 0 0 1 0
5 D 1 1 0 0 1 1
5 D 0 1 0 1 0 0
5 D 0 1 0 1 0 1
5 D 0 1 0 1 1 0
5 D 0 1 0 1 1 1
5 D 1 1 0 1 0 0
5 D 1 1 0 1 0 1
5 D 1 1 0 1 1 0
5 D 1 1 0 1 1 1
5 D 0 1 1 0 0 0
5 D 0 1 1 0 0 1
5 D 0 1 1 0 1 0
5 D 0 1 1 0 1 1
5 D 1 1 1 0 0 0
5 D 1 1 1 0 0 1
5 D 1 1 1 0 1 0
5 D 1 1 1 0 1 1
5 D 0 1 1 1 0 0
5 D 0 1 1 1 0 1
5 D 0 1 1 1 1 0
5 D 0 1 1 1 1 1
5 D 1 1 1 1 0 0
5 D 1 1 1 1 0 1
5 D 1 1 1 1 1 0
5 D 1 1 1 1 1 1
Figure 4. Funtional Block Diagram frequency spectrum, which greatly attenuates the energy of images at the multifules of 4Fs(or 8Fs). oversampled 1-bit PDM outputs from the modulator drives a analog postfilter. the high resolution analog output.
Reference (VHALF, VREF) bypass capacitors (Fig6) should be located as close as possible to chip. Figure 7. Ananlog output application common level to analog ground. Recommended component values are 1uF and 100kΩ. This analog Core Verilog behavioral-modeling will be supplied.
BW0405XA 0.35 µµµµm 16-BIT 44.1KHZ SIGMA-DELTA STEREO DAC FEEDBACK REQUEST Sigma-Delta DAC Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks supply voltage V Max master clock frequency Hz Operating temperature °C Sampling Frequency Hz Dynamic range dB Total harmonic distortion dB Signal-to-noise ratio dB Input format resolution (Serial/Parallel interface) Bit Channel Mono Stereo Power dissipation mW Full scale output voltage range Vpp Group delay sec Phase linearity deviation for passband region (Deg) Peak-to-peak frequency response ripple for passband region dB Could you explain external/internal pin configurations as required? Specially requested function list: