BTS774G SIEMENS | Alldatasheet

Document overview

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Technical content

Features

  • Quad switch driver
  • Free configurable as bridge or quad-switch
  • Optimized for DC motor management applications
  • Ultra low RDS ON @2 5 °C: High-side switch: typ.165 mW , Low-side switch: typ. 45 mW
  • Very high peak current capability
  • Very low quiescent current
  • Space- and thermal optimized power P-DSO-Package
  • Full short-circuit-protection
  • Operates up to 40 V
  • Status flag diagnosis
  • Overtemperature shut down with hysteresis
  • Short-circuit detection and diagnosis
  • Open-load detection and diagnosis
  • C-MOS compatible inputs
  • Internal clamp diodes
  • Isolated sources for external current sensing
  • Over- and under-voltage detection with hysteresis

Description

The BTS 774 G is aTrilithIC contains one double high-side switch and two low-side switches inone P-DSO-28-9 -Package. “Silicon instead of heatsink” becomes true The ultra low RDS ON of this device avoids powerdissipation. It saves costs in mechanical construction and mounting and increases the efficiency. The high-side switches are produced in theSIEMENS SMART SIPMOS ® technology. It is fully protected and contains the signal conditioning circuitry for diagnosis. (The comparable standard high-side product is theBTS 611L1.) Type Ordering Code Package BTS 774 G Q67007-A9336 P-DSO-28-9

Semiconductor Group 2 1999-01-07 For minimizedRDS ON the two low-side switches are N channel vertical power FETs in the SIEMENS SMART SIPMOS ® technology. Fully protected by embedded protection functions. (The comparable standard product is theBSP 78). Each drain of these three chips is mounted on separated leadframes (seeP-DSO-28-9 pin configuration). The sources of all four power transistors are connected to separate pins. So theBTS 774 G can be used in H-Bridge configuration as well as in any other switch configuration. Moreover, it is possible to add current sense resistors. All these features open a broad range of automotive and industrial applications.

Semiconductor Group 3 1999-01-07 Figure 1 Pin Configuration (top view) AEP02071 42 5 LS-Lead Frame 1 HS-Lead Frame DL1 GL1 DL1 N.C. DHVS GND GH1 ST GH2 DHVS N.C. DL2 GL2 DL2 DL1 SL1 SL1 DL1 DHVS SH2 SH2 SH1 SH1 DHVS DL2 SL2 SL2 DL2 LS-Lead Frame 2

Semiconductor Group 4 1999-01-07 Bold type: Pin needs power wiring 1) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe. Pin Definitions and Functions Pin No. Symbol Function 1, 3, 25, 28 DL1 Drain of low-side switch1 Leadframe 11)

2 GL1 Gate of low-side switch1

4 N.C. not connected 5, 10, 19, 24 DHVS Drain of high-side switches and power supply voltage Leadframe 2

6 GND Ground

7 GH1 Gate of high-side switch1

8 ST Status of high-side switches; open Drain output

9 GH2 Gate of high-side switch2

11 N.C. not connected 12, 14, 15, 18 DL2 Drain of low-side switch2 Leadframe 3

13 GL2 Gate of low-side switch2

16, 17 SL2 Source of low-side switch2 20, 21 SH2 Source of high-side switch2 22, 23 SH1 Source of high-side switch1 26, 27 SL1 Source of low-side switch1

Semiconductor Group 5 1999-01-07 Figure 2 Block Diagram AEB02676 Driver IN OUT LL00 HL10 LH01 HH11 Diagnosis 7GH1 ST GH2 9 GND 6 R O1 O2R Biasing and Protection GL1 2 GL2 13 SH2 DL2 SH1 DL1 2120, 1815,14,12, 22, 23 25, 283,1, 26, 16,27 17 2419,10,5, SL1 SL2 DHVS Protection Gate Driver Protection Gate Driver

Semiconductor Group 6 1999-01-07 Circuit Description Input Circuit The control inputs GH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs GL1 and GL2 are connected to the internal gate-driving units of the fully protected N-channel vertical power-MOS-FETs. Output Stages The output stages consist of an ultra low RDS ON Power-MOS H-Bridge. Embedded protective circuits make the outputs short circuit proof to ground, to the supply voltage and load short circuit proof. Positive and negative voltage spikes, which occur when driving inductive loads, are limited by integrated power clamp diodes. Short Circuit Protection The outputs are protected against – output short circuit to ground – output short circuit to the supply voltage, and – overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-Voltage- Drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. If the HS-Switches are in OFF-state-Condition internal resistors RO1,2 from SH1,2 to GND pull the voltage at SH1,2 to low values. On each output pin SH1 and SH2 an output examiner circuit compares the output voltages with the internal reference voltage VEO. This results in switching the status output to low. The fully protected low-side switches have no status output. Overtemperature Protection The highside and the lowside switch also incorporates an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low. Undervoltage-Lockout (UVLO) When VS reaches the switch-on voltageVUVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltageVS drops below the switch off valueVUVOFF .

Semiconductor Group 7 1999-01-07 Overvoltage-Lockout (OVLO) When VS reaches the switch-off voltageVOVOFF the High-Side output transistors are switched off with a hysteresis. The IC becomes active if the supply voltageVS drops below the switch-on valueVOVON . Open Load Detection Open load is detected by current measurement. If the output current drops below an internal fixed level the error flag is set with a delay. Status Flag Various errors as listed in the table “Diagnosis” are detected by switching the open drain output ST to low.

Semiconductor Group 8 1999-01-07 Truthtable and Diagnosis (valid only for the High-Side-Switches) Flag GH1 GH2 SH1 SH2 ST Remarks Inputs Outputs Normal operation; identical with functional truth table L L H H L H L H stand-by mode switch2 active switch1 active both switches active Open load at high-side switch1 Open load at high-side switch2 X X Z Z H L H X L H X Z Z H detected detected Short circuit to DHVS at high-side switch1 Short circuit to DHVS at high-side switch2 X X H H H L H X L H X H H H detected detected Overtemperature high-side switch1 0 X X L L X X 0 detected Overtemperature high-side switch2 X X X X L L 0 detected Overtemperature both high-side switch 0 X X L L L L L L detected detected Over- and Under-Voltage X X L L 1 not detected Inputs: Outputs: Status: 0 = Logic LOW Z = Output in tristate condition 1 = No error 1 = Logic HIGH L = Output in sink condition 0 = Error X = don’t care H = Output in source condition X = Voltage level undefined

Semiconductor Group 9 1999-01-07

Electrical Characteristics

Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Absolute Maximum Ratings – 40°C < Tj < 150°C Parameter Symbol Limit Values Unit Remarks min. max. High-Side-Switches (Pins DHVS, GH1,2 and SH1,2) Supply voltage VS – 0.3 43 V – HS-drain current IDHS – 8 * A * internally limited HS-input current IGH – 2 2 mA Pin GH1 and GH2 HS-input voltage VGH – 10 16 V Pin GH1 and GH2 Status Output ST Status Output current IST – 5 5 mA Pin ST Low-Side-Switches (Pins DL1,2, GL1,2 and SL1,2) Break-down voltage V(BR)DSS 40 V VGS = 0 V;ID <= 1 mA LS-drain current IDLS 16 * A * internally limited LS-input voltage VGL – 0.3 10 V Pin GL1 and GL2 Temperatures Junction temperature Tj – 40 150 °C– Storage temperature Tstg – 50 150 °C– Thermal Resistances (one HS-LS-Path active) LS-junction case RthjCLS – 20 K/W measured to pin3 or 12 HS-junction case RthjCHS – 20 K/W measured to pin19 Junction ambient Rthja – 60 K/W –

Semiconductor Group 10 1999-01-07 Note: In the operating range the functions given in the circuit description are fulfilled. Operating Range Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS VUVOFF 36 V After VS rising above VUVON Input voltages VGH – 0.3 15 V – Input voltages VGL – 0.3 10 V – Output current IST 0 2 mA – HS-junction temperature TjHS – 40 150 °C– LS-junction temperature TjLS – 40 150 °C–

Semiconductor Group 11 1999-01-07 ISH1 =ISH2 =ISL1 =ISL2 = 0 A; – 40°C < Tj < 150°C; 8 V >VS > 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current Consumption Quiescent current IS –1 6 3 0 mA GH1 = GH2 = L VS = 13.2 V Tj = 25°C Quiescent current IS ––3 5 mA GH1 = GH2 = L VS = 13.2 V Supply current IS – 2 3.5 mA GH1 or GH2 = H Supply current IS – 4 7 mA GH1 and GH2 = H Under Voltage Lockout (UVLO) Switch-ON voltage VUVON – 5.4 7 V VS increasing Switch-OFF voltage VUVOFF 3.5 4.2 – V VS decreasing Switch ON/OFF hysteresisVUVHY – 1.2 – V VUVON –VUVOFF Over Voltage Lockout (OVLO) Switch-OFF voltage VOVOFF 36 37.8 43 V VS increasing Switch-ON voltage VOVON 35 37.3 – V VS decreasing Switch OFF/ON hysteresisVOVHY – 0.7 – V VOVOFF –VOVON Short Circuit of Highside Switch to GND Initial peak SC currentISCP 81 0 1 3 A Tj = – 40°C Initial peak SC currentISCP 6.5 8.5 11 A Tj = 25°C Initial peak SC currentISCP 3.9 5 7 A Tj = 150°C

Semiconductor Group 12 1999-01-07 Short Circuit of Highside Switch toV S OFF-state examiner-voltage VEO 234V VGH = 0 V Output pull-down-resistorRO 4 1 03 0k W – Open Circuit Detection of Highside Switch Detection current IOCD 10 90 200 mA – Switching Times of Highside Switch Switch-ON-time; to 90%VSH tON – 0.2 0.4 ms resistive load ISH = 1 A;VS = 12 V Switch-OFF-time; to 10%VSH tOFF – 0.15 0.4 ms resistive load ISH = 1 A;VS = 12 V Note: switching times are guaranteed by design Control Inputs of Highside Switches GH 1, 2 H-input voltage VGHH – 2.8 3.5 V – L-input voltage VGHL 1.5 2.3 – V – Input voltage hystereseVGHHY – 0.5 – V – H-input current IGHH 20 60 90 mA VGH = 5 V L-input current IGHL 12 5 5 0 mA VGH = 0.4 V Input series resistanceRI 2.5 3.5 6 k W – Zener limit voltage VGHZ 5.4 – – V IGH = 1.6 mA Electrical Characteristics(cont’d) ISH1 =ISH2 =ISL1 =ISL2 = 0 A; – 40°C < Tj < 150°C; 8 V >VS > 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 13 1999-01-07 Control Inputs GL1, 2 Gate-threshold-voltage VGL(th) 0.9 1.7 2.2 V IDL = 2 mA Input current IGLN –1 0 3 0 mA VGL = 5 V; normal operation Input current IGLF – 150 300 mA VGL = 5 V; failure mode Short Circuit of Lowside Switch toV S Initial peak SC currentISCP 18 26 34 A Tj = – 40°C 15 21 27 A Tj = 25°C 10 14 18 A Tj = 150°C Switching Times of Lowside Switch Switch-ON-time; to 90%VSL tON – 100 200 ms resistive load ISH = 1 A;VS = 12 V Switch-OFF-time; to 10%VSL tOFF – 50 200 ms resistive load ISH = 1 A;VS = 12 V Note: Switching times are guaranteed by design. Status Flag Output ST of Highside Switch Low output voltage VSTL – 0.2 0.6 V IST = 1.6 mA Leakage current ISTLK ––1 0 mA VST = 5 V Zener-limit-voltage VSTZ 5.4 – – V IST = 1.6 mA Electrical Characteristics(cont’d) ISH1 =ISH2 =ISL1 =ISL2 = 0 A; – 40°C < Tj < 150°C; 8 V >VS > 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 14 1999-01-07 Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply atTA = 25°C and the given supply voltage. Thermal Shutdown Thermal shutdown junction temperature TjSD 155 – 190 °C– Thermal switch-on junction temperature TjSO 150 – 180 °C– Temperature hysteresis DT –1 0 – °C DT = TjSD – TjSO Output Stages Leakage current of highside switch IHLK ––1 2 mA VGH =VSH = 0 V Leakage current of lowside switch ILKL – 1.3 10 mA VGL = 0 V VDS = 13 V Clamp-diode of highside switch; forward-Voltage VFH – 0.8 1.5 V IFH = 3 A Clamp-diode leakage- current of highside switch ILKCL – – 10 mA IFH = 3 A Clamp-diode of lowside switch; forward-voltage VFL – 0.8 1.2 V IFL = 3 A Static drain-source on-resistance of highside switch RDS ON H – 165 220 m W ISH =1A Tj = 25°C Static drain-source on-resistance of lowside switch RDS ON L – 4 56 0m W ISL = 1 A; VGL = 5 V Tj = 25°C Static path on-resistanceRDS ON – – 500 m W RDS ON H +R DS ON L ISH = 1 A; Electrical Characteristics(cont’d) ISH1 =ISH2 =ISL1 =ISL2 = 0 A; – 40°C < Tj < 150°C; 8 V >VS > 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Semiconductor Group 15 1999-01-07 Figure 3 Test Circuit HS-Source-Current Named during Short Circuit Named during Open Circuit Named during Leakage-Cond. ISH1,2 ISCP IOCD IHSLK AES02677 SV = 12 V Driver IN OUT LL00 HL10 LH01 HH11 CS 470 nF Diagnosis 7GH1 ST GH2 9 GND 6 R O1 O2R Biasing and Protection GL1 2 GL2 13 SH2 DL2 SH1 DL1 12, 14, 15, 18 22, 23 25, 28 1, 3, SL1 SL2 26, 27 16, 17 DHVS 5, 10, 19, 24 F100 CL ISL2SL1I VDSL1 EO1V FL1V-- VFL2 VEO2 DSL2V VOVOFF OVONV VUVON UVOFFV VDSH1 FL1V--VFL2 DSH2V IFH1, 2 SI SH2I DL2I IDL1 ISH1 ILKL LKLI VGL2 GL(th)2V VGL(th)1 GL1V IGND LKCL1,I 2 GH2V VGH1 VSTL STV STZV m Protection Gate Driver Protection Driver Gate

Semiconductor Group 16 1999-01-07 Figure 4 Application Circuit AES02678 SV =1 2 V Watchdog Reset Q D GND I WD R CCV Driver IN OUT LL00 HL10 LH01 HH11 R Q 100 kW R S Wk10 C Q C D 47 nF Diagnosis 7GH1 ST GH2 9 GND 6 R O1 O2R Biasing and Protection GL1 2 GL2 13 SH2 DL2 SH1 DL1 12, 14, 15, 18 22, 23 25, 28 1, 3, SL1 SL2 26, 27 16, 17 DHVS 5, 10, 19, 24 DO1 M 22 F P 10 F C S TLE 4278G m m m 1N4001 DO1 Z39 GND Protection Gate Driver Protection Gate Driver

Semiconductor Group 17 1999-01-07 Package Outlines 11 4 1528 18.1-0.4 Index Marking 2.45 -0.1 7.6 10.3±0.3 -0.2 0.2 2.65 max -0.2 1.27 0.23 +0.09 0.1 0.4 0.35 x 45˚ +0.8 +0.150.35 2) 8˚ max 0.2 28x 2) Does not include dambar protrusion of 0.05 max per side 1) Does not include plastic or metal protrusions of 0.15 max rer side GPS05123 P-DSO-28-9 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device