BTS7710G INFINEON | Alldatasheet
Document overview
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Technical content
1.1 Features
Quad D-MOS switch driver Free configurable as bridge or quad-switch Optimized for DC motor management applications L o w RDS ON: 70 mτ high-side switch, 40 mτ low-side switch (typical values @ 25 C) Maximum peak current: typ. 15 A @ 25 C= Very low quiescent current: typ. 5 ←A @ 25 C= Small outline, enhanced power P-DSO-package Load and GND-short-circuit-protection Operates up to 40 V Status flag diagnosis Overtemperature shut down with hysteresis Internal clamp diodes Isolated sources for external current sensing Under-voltage detection with hysteresis PWM frequencies up to 50 kHz
1.2 Description
The BTS 7710 G is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated leadframes. The sources are connected to individual pins, so the BTS 7710 G can be used in H-bridge- as well as in any other configuration. The double high-side is manufactured in SMART SIPMOS ® technology which combines low RDS ON vertical DMOS power stages with CMOS control circuitry. The high-side switch is fully protected and contains the control and diagnosis circuitry. To achieve low RDS ON and fast switching performance, the low-side switches are manufactured in S-FET logic level technology. The equivalent standard product is the BUZ 103 SL. In contrast to the BTS 7710 GP, which consists of the same chips in an P-TO263-15 package, the P-DSO-28-14 package offers a smaller outline and a lower price for applications, which do not need the thermal properties of the P-TO263-15. Type Ordering Code Package BTS 7710 G Q67007-A9399 P-DSO-28-14
1.3 Pin Configuration
(top view) Figure 1
28 DL1
25 DL1
27 SL1
26 SL1
24 DHVS
23 SH1
22 SH1
21 SH2
20 SH2
19 DHVS
18 DL2
15 DL2
16 SL2
17 SL2
4N.C. 3DL1 2IL1 6GND 7IH1 8ST 9IH2 10DHVS DL2 N.C. DL2 IL2 HS-Leadframe LS-Leadframe LS-Leadframe
Pins written in bold type need power wiring.
1.4 Pin Definitions and Functions
Pin No. Symbol Function 1, 3, 25, 28 DL1 Drain of low-side switch1, leadframe 1 1)
2 IL1 Analog input of low-side switch1
4 N.C. not connected 5, 10, 19, 24 DHVS Drain of high-side switches and power supply voltage, leadframe 2
6 GND Ground
7 IH1 Digital input of high-side switch1
8 ST Status of high-side switches; open Drain output
9 IH2 Digital input of high-side switch2
11 N.C. not connected 12, 14, 15, 18 DL2 Drain of low-side switch2, leadframe 3
13 IL2 Analog input of low-side switch2
16,17 SL2 Source of low-side switch2 20,21 SH2 Source of high-side switch2 22,23 SH1 Source of high-side switch1 26,27 SL1 Source of low-side switch1 1) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe.
1.5 Functional Block Diagram
5,10,19,24 20,21 16, 17 RO1 RO2 Biasing and ProtectionDiagnosis Driver OUT IN
0 L L
22, 23 1,3,25,28 26, 27 12,14,15,18
1.6 Circuit Description
The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes. The inputs IL1 and IL2 are connected to the gates of the standard N-channel vertical power-MOS-FETs. Output Stages The output stages consist of an low RDS ON Power-MOS H-bridge. In H-bridge configuration, the D-MOS body diodes can be used for freewheeling when commutating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes. Short Circuit Protection The outputs are protected against – output short circuit to ground – overload (load short circuit). An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-Voltage- Drop with an internal reference voltage. Above this trippoint the OP-Amp reduces the output current depending on the junction temperature and the drop voltage. In the case of overloaded high-side switches the status output is set to low. Overtemperature Protection The high-side switches incorporate an overtemperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low. Undervoltage-Lockout (UVLO) When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis. The High-Side output transistors are switched off if the supply voltage VS drops below the switch off value VUVOFF.
The status flag output is an open drain output with Zener-diode which requires a pull-up resistor, c.f. the application circuit on page 14. Various errors as listed in the table “Diagnosis” are detected by switching the open drain output ST to low. A open load detection is not available. Freewheeling condition does not cause an error.
2 Truthtable and Diagnosis (valid only for the High-Side-Switches)
Flag IH1 IH2 SH1 SH2 ST Remarks Inputs Outputs Normal operation; identical with functional truth table L L H H L H L H stand-by mode switch2 active switch1 active both switches active Overtemperature high-side switch1 0 X X L L X X 0d e t e c t e d Overtemperature high-side switch2 X X X X L L 0d e t e c t e d Overtemperature both high-side switches 0 X X L L L L L L detected detected Undervoltage X X L L 1 not detected Inputs: Outputs: Status: 0 = Logic LOW Z = Output in tristate condition 1 = No error 1 = Logic HIGH L = Output in sink condition 0 = Error X = don’t care H = Output in source condition X = Voltage level undefined
3 Electrical Characteristics
3.1 Absolute Maximum Ratings
Parameter Symbol Limit Values Unit Remarks min. max. High-Side-Switches (Pins DHVS, IH1,2 and SH1,2) Supply voltage VS – 0.3 42 V – Supply voltage for full short circuit protection VS(SCP) 28 V – HS-drain current* IS – 8 ** A TA = 25°C; t < 100 ms HS-input current IIH – 5 5 mA Pin IH1 and IH2 HS-input voltage VIH – 10 16 V Pin IH1 and IH2 Note: * single pulse ** internally limited Status Output ST Status pull up voltage VST – 0.3 5.4 V – Status Output current IST – 5 5 mA Pin ST Low-Side-Switches (Pins DL1,2, IL1,2 and SL1,2) Drain- source break down voltage VDSL 55 – V VIL =0V ; ID 1m A LS-drain current* TA = 25°C IDL –8 8 A t < 100 ms –1 1 A t < 10 ms –2 4 A t < 1 ms LS-input voltage VIL – 20 20 V Pin IL1 and IL2 Note: * single pulse Temperatures Junction temperature Tj – 40 150 C– Storage temperature Tstg – 55 150 C–
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Note: In the operating range the functions given in the circuit description are fulfilled. Thermal Resistances (one HS-LS-Path active) LS-junction case RthjC L – 20 K/W measured to pin 3 or 12 HS-junction case RthjC H – 20 K/W measured to pin 19 Junction ambient Rthja = Tj(HS)/(P(HS)+P(LS)) Rthja – 60 K/W device soldered to reference PCB with 6c m2 cooling area ESD Protection (Human Body Model acc. MIL STD 883D, method 3015.7 and EOS/ ESD assn. standard S5.1 - 1993) Input LS-Switch VESD –0 . 5 k V Input HS-Switch VESD –1k V Status HS-Switch VESD –2k V Output LS and HS-Switch VESD – 8 kV all other pins connected to Ground
3.2 Operating Range
Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS VUVOFF 42 V After VS rising above VUVON Input voltages HS VIH – 0.3 15 V – Input voltages LS VIL – 0.3 20 V – Output current IST 02m A – Junction temperature Tj – 40 150 C–
3.1 Absolute Maximum Ratings (cont’d)
Parameter Symbol Limit Values Unit Remarks min. max.
3.3 Electrical Characteristics
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current Consumption HS-switch Quiescent current IS –58 ←A IH1 = IH2 = 0 V Tj = 25 C ––1 2 ←A IH1 = IH2 = 0 V Supply current IS – 1.5 2.6 mA IH1 or IH2 = 5 V VS = 12 V – 3 5.2 mA IH1 and IH2 = 5 V VS = 12 V Leakage current of highside switch ISH LK ––6 ←A VIH = VSH = 0 V Leakage current through logic GND in free wheeling condition ILKCL = IFH + ISH ––1 0 m A IFH = 3 A Current Consumption LS-switch Input current IIL – 10 100 nA VIL = 20 V; VDSL = 0 V Tj = 25 C Leakage current of lowside switch IDL LK ––1 0 ←A VIL = 0 V VDSL = 40 V Under Voltage Lockout (UVLO) HS-switch Switch-ON voltage VUVON ––4 . 5 V VS increasing Switch-OFF voltage VUVOFF 1.8 – 3.2 V VS decreasing Switch ON/OFF hysteresis VUVHY –1–V VUVON – VUVOFF
Inverse diode of high-side switch; Forward-voltage VFH –0 . 8 1 . 2 V IFH = 3A Inverse diode of lowside switch; Forward-voltage VFL –0 . 8 1 . 2 V IFL = 3 A Static drain-source on-resistance of highside switch RDS ON H – 7 09 0m τ ISH =1A Tj = 25 C Static drain-source on-resistance of lowside switch RDS ON L – 4 05 0m τ ISL =1A ; VIL = 5 V Tj = 25 C Static path on-resistance RDS ON ––2 6 0 m τ RDS ON H +R DS ON L ISH =1A ; Short Circuit of highside switch to GND Initial peak SC current ISCP H 15 18 20 A Tj = – 40 °C Initial peak SC current ISCP H 13 15 17 A Tj = + 25 °C Initial peak SC current ISCP H 9 1 11 3A Tj = + 150 °C Short Circuit of highside switch to VS Output pull-down-resistor RO 8 1 53 5k τ VDSL = 3 V Thermal Shutdown Thermal shutdown junction temperature Tj SD 155 180 190 C– Thermal switch-on junction temperature Tj SO 150 170 180 C– Temperature hysteresis αT –1 0 – C αT = TjSD – TjSO
3.3 Electrical Characteristics (cont’d)
ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.
Status Flag Output ST of highside switch Low output voltage VST L –0 . 2 0 . 6 V IST = 1.6 mA Leakage current IST LK ––1 0 ←A VST = 5 V Zener-limit-voltage VST Z 5.4 – V IST = 1.6 mA Switching times of highside switch Turn-ON-time; to 90% VSH tON – 75 160 ←sR Load = 12 τ VS = 12 V Turn-OFF-time; to 10% VSH tOFF – 60 160 ←sR Load = 12 τ VS = 12 V Slew rate on 10 to 30% VSH dV/dtON ––1 . 5 V /←sR Load = 12 τ VS = 12 V Slew rate off 70 to 40% VSH -dV/ dtOFF ––2 . 0 V /←sR Load = 12 τ VS = 12 V Note: switching times are guaranteed by design Switching times of low-side switch Turn-ON delay time; VIL = 5V; RG = 7τ td_ON_L – 9 14 ns resistive load ISL = 3 A; VS = 30 V Switch-ON time; VIL= 5V; RG = 7τ tON_L – 2 54 0n s r e s i s t i v e l o a d ISL = 3 A; VS = 30 V Switch-OFF delay time; VIL= 5V; RG = 7τ td_OFF_L – 3 65 5n s r e s i s t i v e l o a d ISL = 3 A; VS = 30 V Switch-OFF time; VIL= 5V; RG = 7τ tOFF_L – 2 23 3n s r e s i s t i v e l o a d ISL = 3 A; VS = 30 V ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Gate charge of lowside switch Input to source charge; QIS –46n C ISL = 3 A; VS = 14 V Input to drain charge; QID – 1 01 6n C ISL = 3 A; VS = 14 V Input charge total; QI – 2 84 3n C ISL = 3 A; VS = 14 V VIL = 0 to 10 V Input plateau voltage; V(plateau) –2 . 7 5 - V ISL = 3 A; VS = 14 V Note: switching times and input charges are guaranteed by design Control Inputs of highside switches IH 1, 2 H-input voltage VIH High ––2 . 5 V – L-input voltage VIH Low 1––V – Input voltage hysterese VIH HY –0 . 3 –V – H-input current IIH High 15 30 60 ←A VGH = 5 V L-input current IIH Low 5–2 0 ←A VGH = 0.4 V Input series resistance RI 2.7 4 5.5 k τ – Zener limit voltage VIH Z 5 . 4 ––V IGH = 1.6 mA Control Inputs IL1, 2 Gate-threshold-voltage VIL th 0.9 1.7 2.2 V IDL = 1 mA ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 C < Tj < 150 C; 8 V < VS < 18 V unless otherwise specified Parameter Symbol Limit Values Unit Test Condition min. typ. max.
HS-Source-Current Named during Short Circuit Named during Leakage- Cond. ISH1,2 ISCP H IDL LK SH2 DHVS ST IL1 GND IH1 SL2 5,10,19,24 20,21 16,17 RO1 RO2 Biasing and Protection 22,23 1,3,25,28 IH2 IL2 26,27 12,14,15,18 SL1 DL2 SH1 DL1 IGND ILKCL VS=12V CL 100µF CS 470nF IFH1,2 IS ISH2 IDL2 ISH1 IDL1 IDL LK 2 IDL LK 1 VDSL1 -VFL1 VDSL2 -VFL2 -VFH2 VDSH2 -VFH1 VDSH1 VUVON VUVOFF ISL2ISL1 ISCP L 1 ISCP L 2 VIL2 VIL th 2 VIL1 VIL th 1 VST VSTL VSTZ VIH1 VIH2 Gate Driver Gate Driver Diagnosis IST IST LK IIH1 IIH1 IIL1 IIL2
5,10,19,24 20,21 16,17 TLE 4278G VS=12V D01 Z39 CS 10µF CD 47nF D I Q Reset Watchdog CQ 22µF VCCWD R GND µP RO1 RO2 Biasing and Protection M 22,23 1,3,25,28 IH2 IL2 26,27 12,14,15,18 SL1 DL2 SH1 DL1 RQ 100 kττττ RS 10 kττττ Gate Driver Gate Driver Diagnosis
4 Package Outlines
18.1-0.4 Index Marking 2.45 -0.1 7.6 10.3 ±0.3 -0.2 0.2 2.65 max -0.2 1.27 0.23 +0.09 0.1 0.4 0.35 x 45˚ +0.8 +0.150.35 2) 8˚ max 0.2 28x 2) Does not include dambar protrusion of 0.05 max per side 1) Does not include plastic or metal protrusions of 0.15 max rer side GPS05123 P-DSO-28-14 (Plastic Transistor Single Outline Package) GPS05123 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device
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