BTS71040-4ESE

BTS71040-4ESE INFINEON | Alldatasheet

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Data Sheet Rev. 1.00 www.infineon.com 1 2018-10-16 BTS71040-4ESE

1 Overview

• Suitable for resistive, induc tive and capacitive loads
• Replaces electromechanical rela ys, fuses and discrete circuits
• Driving capability suitable for 3 A lo ads and high inrush current loads such as 27W bulb or LED equivalent Figure 1 Application Diagram. Further information in Chapter 11 SPOC™+2 4x 22.5 m Ω SPI Power Controller Package PG-TSDSO-24 Marking 71040-4ESE SPI VS OUT3 OUT2 OUT1 OUT0 27W 27W 27W 27W External Driver Control IS SO SCLK SI CSN GND LHI RLHI EDD EDO VDD GND VDD CVD D µC e.g. XC2267 VSS VCC VBAT AD RVD D SPI RSO RSI RSC LK RCS N RIN RIN GPIO IN 1 IN 0 CVS 1 PRO FETIN OUT VS GND DEN IS CAD C DZ1 RED O RED D DZ2CVS 2 A ppl ica ti on_04 0_E D.em f COUT COUT CVS 1 RPR O T Fa il-safe Co ntro l Fa il-safe Co ntro l RIN logic supply

Data Sheet 2 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Overview Basic Features

• High-Side Switch with Diagn osis and Embedded Protection
• Part of SPOC™+2 Family
• Daisy Chain capable SPI interface
• 3.3 V and 5 V compatible logic pins
• Slew rate control for internal Channels
• Integrated control for one external smart power switch
• ReverSave™ for low power diss ipation in Reverse Polarity
• Switch ON capability while Inve rse Current condition (InverseON)
• Green Product (RoHS compliant)
• Qualified in accordance with AEC Q100 grade 1 Protection Features
• Absolute and dynamic temperature li mitation with controlled restart
• Overcurrent protection (tripping) with Prog rammable Restart Control and Current Threshold
• Undervoltage shutdown
• Overvoltage protection with external components Diagnostic Features
• Proportional load current sense multiplexed
• Open Load in ON and OFF state
• Short circuit to ground and battery
• Diagnosis feedback via SPI Functional Safety Features
• Limp Home mode
• Monitoring of Input pin status (IN and LHI)
• Checksum verification of Configuration Registers
• Current Sense verification mode

Description

The BTS71040-4ESE is a SPI Power Cont roller, providing protection func tions and diagnosis. The device is integrated in SMART7 technology. Table 1 Product Summary Parameter Symbol Values Minimum Operating voltage (at switch ON) V S(OP) 4.1 V Minimum Operating voltage (cranking) VS(UV) 3.1 V Maximum Operating voltage VS 28 V Digital Supply voltage VDD 3 . 3V o r 5V Minimum Overvoltage protection (TJ = 25 °C) VDS(CLAMP)_25 35 V Maximum current in Sleep mode (TJ ≤ 85 °C) IVS(SLEEP)_85 0.4 µA

Data Sheet 3 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Overview Maximum operative current IGND(ACTIVE) 7 mA Maximum ON-state resistance (TJ = 150 °C) RDS(ON)_150 38 mΩ Nominal load current (TA = 85 °C) IL(NOM) 3 A Typical current sense ratio at IL = IL(NOM) kILIS 2000 Serial Clock Frequency fSCLK(max) 5 MHz Table 1 Product Summary (continued) Parameter Symbol Values

Data Sheet 4 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Block Diagram and Terms

2 Block Diagram and Terms

2.1 Block Diagram

Figure 2 Block Diagram of BTS71040-4ESE IS SO SI VDD BlockDiagram_4chED.emf GND Circuitry VS GND OUT2 OUT3 Reverse Pola rity Protection OUT0 OUT1 IN0 IN1 ESD Protection I/O Logic SCLK CSN LHI Limp Home Control SPI Interface Channe l 0 Channel 1 Channel 2 Channe l 3 T Driver Logic Overtemperature Overvoltage Clamping Overcurrent Protection Output Voltage Limitation Voltage Sensor ReverSave™ InverseOn EDD EDO Load Current Sense Multiplexer Overvoltage Protection VS Monitoring Internal Power Supply Internal Logic Supply External Driver Control Gate Control Chargepump

Data Sheet 5 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Block Diagram and Terms

2.2 Terms

Figure 3 shows all terms used in this data sheet, with associated convention for positive values. Figure 3 Voltage and Current Convention IDD VDD VSO VS IIS IVS VDD SO SI SCLK IS VS VSI VSCLK VCSN VINn IINn INn ICSN CSN VIS VLH I ILH I LHI I Ln VOU Tn VDS n ISO Te rms_ED .e mf IGN D EDO EDD IEDO IEDD VED O VEDD GN D OUTn VSIS

Data Sheet 6 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 4 Pin Configuration VS SI OUT0 SCLK CSN LHI IN0 IN1 EDD OUT1 OUT2 OUT2 OUT3 ex pos ed pad (bo tto m) 13IS GND SO EDO VDD OUT1 n.c. n.c. OUT0 n.c. n.c. OUT3 Pi nO ut_SP OC_040_ED .emf (top view)

Data Sheet 7 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Pin Configuration

3.2 Pin Definitions and Functions

(exposed pad) - Power Supply Voltage Battery voltage 1G N D - Ground 2V D D - Digital Supply Voltage 3S O O Serial output of SPI interface 4S I I Serial input of SPI interface (“high” active) 5S C L K I Serial clock of SPI interface (“high” active) 6C S N I Chip select of SPI interface (“low” active); integrated pull up to VDD 7L H I I Limp Home activation signal (“high” active) 8, 9 INn I Input Channel n Digital signal to switch ON the channel n (“high” active) If not used: connect with a 10 kΩ resistor either to GND pin or to module ground

10 EDD O External driver diagnosis enable signal

Digital signal to activate the diagnosis of an external controlled device

11 EDO O External driver output enable signal

Digital signal to activate the output of an external controlled device

12 IS O Current sense output signal

23-24 n.c. - Not connected, internally not bonded, shorted together 21-22 19-20 17-18 15-16 OUTn O Output n Protected high-side power output of channel n 1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. 13-14 n.c. - Not connected, internally not bonded, shorted together

Data Sheet 8 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings - General

Table 3 Absolute Maximum Ratings 1) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply pins Power Supply Voltage VS -0.3 – 28 V – P_4.1.0.1 Load Dump Voltage VBAT(LD) – – 35 V suppressed Load Dump acc. to ISO16750-2 (2010). R i = 2 Ω P_4.1.0.3 Supply Voltage for Short Circuit Protection VBAT(SC) 0–2 4 V S e t u p a c c . t o AEC-Q100-012 P_4.1.0.25 Reverse Polarity Voltage - VBAT(REV) ––1 6 V t ≤ 2 min TA = +25 °C Setup as described in Chapter 11 P_4.1.0.5 Current through GND Pin I GND -50 – 50 mA RGND according to Chapter 11 P_4.1.0.9 Current through VDD Pin IVDD(REV) -10 – 30 mA t ≤ 2 min P_4.1.0.10 Counter Reset Delay Time after Fault Condition tRETRY 5 0 ––m s – P_4.1.0.35 Logic & control pins (Digital Input = DI) DI = INn, CS, SCLK, SI, LHI Current through DI Pin IDI -1 – 2 mA 2) P_4.1.0.14 Current through DI Pin Reverse Battery Condition IDI(REV) -1 – 10 mA 2) t ≤ 2 min P_4.1.0.36 Logic & control pins (Digital Output = DO) DO = SO, EDO, EDD Current through DO Pin IDO -2 – 1 mA 2) P_4.1.0.33 Current through DO Pin Reverse Battery Condition IDO(REV) -10 – 1 mA 2) t ≤ 2 min P_4.1.0.37

Data Sheet 9 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 General Product Characteristics Notes 1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. IS pin Voltage at IS Pin VIS -1.5 – VS V IIS = 10 μA P_4.1.0.16 Current through IS Pin IIS -25 – IIS(SAT),M AX mA – P_4.1.0.18 Temperatures Junction Temperature TJ -40 – 150 °C – P_4.1.0.19 Storage Temperature TSTG -55 – 150 °C – P_4.1.0.20 ESD Susceptibility ESD Susceptibility all Pins (HBM) V ESD(HBM) -2 – 2 kV HBM 3) P_4.1.0.21 ESD Susceptibility OUTn vs GND and VS connected (HBM) VESD(HBM)_OUT -4 – 4 kV HBM 3) P_4.1.0.22 ESD Susceptibility all Pins (CDM) VESD(CDM) -500 – 500 V CDM 4) P_4.1.0.23 ESD Susceptibility Corner Pins (pins 1, 12, 13, 24) VESD(CDM)_CRN -750 – 750 V CDM 4) P_4.1.0.24 1) Not subject to production test - specified by design. 2) Maximum VDI to be considered for Latch-Up tests: 5.5 V. 3) ESD susceptibility, Human Body Mode l "HBM", according to AEC Q100-002. 4) ESD susceptibility, Charged Device Mo del "CDM", according to AEC Q100-011. Table 3 Absolute Maximum Ratings 1) (continued) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 10 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 General Product Characteristics

4.2 Absolute Maximum Ratings - Power Stages

4.2.1 Power Stages - 27 W channels

Table 4 Absolute Maximum Ratings - 27 W channels 1) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Maximum Energy Dissipation Single Pulse EAS ––2 8 m J IL = 2*IL(NOM) TJ(0) = 150 °C VS = 28 V P_4.2.16.1 Maximum Energy Dissipation Repetitive Pulse EAR ––8 . 5 m J IL = IL(NOM) TJ(0) = 85 °C VS = 13.5 V 1M cycles P_4.2.16.2 Load Current | IL|– – IL(OVL),MAX A– P_4.2.16.3

Data Sheet 11 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 General Product Characteristics

4.3 Functional Range

Note: Within the functional or operatin g range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics tables. Table 5 Functional Range - Su pply Voltages and Temperature1) 1) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Power Supply Voltage Range for Normal Operation Lower Extended Power Supply Voltage Range for Operation V S(EXT,LOW) 3.1 – 6 V 2)3) (parameter deviations possible) 2) In case of VS voltage decreasing: VS(EXT,LOW),MIN =3 . 1V . I n c a s e o f VS voltage increasing: VS(EXT,LOW),MIN =4 . 1V . P_4.3.0.2 Upper Extended Power Supply Voltage Range for Operation VS(EXT,UP) 18 – 28 V 3) (parameter deviations possible) 3) Protection functions still operative. P_4.3.0.3 Digital Supply Voltage Range Junction Temperature TJ -40 – 150 °C – P_4.3.0.5

Data Sheet 12 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 General Product Characteristics

4.4 Thermal Resistance

Note: This thermal data was generated in accord ance with JEDEC JESD51 standards. For more information, go to www.jedec.org.

4.4.1 PCB Setup

Figure 5 1s0p PCB Cross Section Figure 6 2s2p PCB Cross Section Table 6 Thermal Resistance 1) 1) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Thermal Characterization Parameter Junction-Top ΨJTOP –35K / W 2) 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C, PDISSIPATION = 1 W. P_4.4.0.4 Thermal Resistance Junction-to-Case RthJC –35K / W 2) simulated at exposed pad P_4.4.0.5 Thermal Resistance Junction to Ambient RthJA – 26.5 – K/W 2) P_4.4.0.10 70 µm modeled (traces, cooling area) 1,5 mm 70 µm, 5% metalization* PC B_Z th_1s0p.emf *: means percentual Cu metalization on each layer 70 µm modeled (traces) 35 µm, 90% metalization* 1,5 mm 70 µm, 5% metalization* PCB_Zth_2s2p.emf 35 µm, 90% metalization* *: means percentual Cu metalization on each layer

Data Sheet 14 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 General Product Characteristics

4.4.2 Thermal Impedance

Figure 9 Typical Thermal Impe dance. PCB setup according Chapter 4.4.1 Figure 10 Thermal Resistan ce on 1s0p PCB with various cooling surfaces 0.01 0.1 100 0.0001 0.001 0.01 0.1 1 10 100 1000 ZthJA [K/W] TAMBIENT = 105 °C Time [s] BTS71040-4ESx 2s2p 1s0p - 600 mm² 1s0p - 300 mm² 1s0p - footprint 0 100 200 300 400 500 600 RthJA [K/W] Cooling area [mm²] BTS71040-4ESx 1s0p - Ta = 105 °C

Data Sheet 15 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Logic Pins

5 Logic Pins

The device has 9 digital pins to configure and control the device. They can be grouped based on their function into input pins, SPI pins, external driver pins and Limp Home pin.

5.1 Input Pins (INn)

The input pins IN0 and IN1 activate th e corresponding output channel, if the device is either in Sleep, Stand- by, Ready or in Limp Home mode. The input circuitry is compatible with 3.3V an d 5V microcontroller. The electrical equivalent of the input circuitry is shown in Figure 11. In case the pin is not used, it must be connected with a 10 kΩ resistor either to GND pin or to module ground. Figure 11 Input circuitry The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always higher than the voltage needed to ensure a “low” state. GND IN IGND IDI VDI Input_IN_INTDIO.emf VS VS(CLAMP) RGND IDIESD VDI (CLAM P)

Data Sheet 16 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Logic Pins Figure 12 Input Threshold voltages and hysteresis There are two ways of using the input pi ns in combination with the register OUT by programming bit HWCR.COL in register HWCR (see Table 30).

• HWCR.COL = 0B: A channel is switched ON either by the according OUT.OUTn bit or by the input pin.
• HWCR.COL = 1B: A channel is switched ON by the according OUT.OUTn bit only, when the input pin is “high”. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by the SPI register OUT (see Table 30). The default state ( HWCR.COL = 0B) is the OR-combination of the input signal and the SPI-bit. In Limp Home mode (LHI pin set to “high”) the combinatorial logic is in default state to enable a channel activation via the input pins only. Figure 13 shows the complete input switch matrix. The logic level of the input pins can be monitored via the input status monitor. In case of a “high” level on an input pin, the corresponding ICS.INSTn bit is set and cleared on read. Input _V DITH_ 2.emf VDI (TH ), MAX VDI (HYS) t VDI VDI (TH ) ,MIN I nternal channel activation signal t 0 x 1 x 0 VDI (T H)

Data Sheet 17 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Logic Pins Figure 13 Input Switch Matrix

5.2 Advanced Features Pins

5.2.1 SPI Pins

The serial peripheral interface (SPI) is a full duplex sy nchronous serial slave interf ace, which uses four lines: SO, SI, SCLK and CSN. See Chapter 10 for further information.

5.2.2 Limp Home Input (LHI) Pin

For activating the fail-safe state, the device features a Limp Home Input pin. When the pin is set to “high” for further information.

5.2.3 External Driver Pins

One external smart power driver can be controlled by the BTS71040-4ESE via the external driver control block. There are two control outputs availa ble: one output for controlling the input (EDO) and one output for diagnosis enable input (EDD). The current sense output of the external smart power driver can be connected to the IS pin. For details please refe r to the Application Circuit Example in Chapter 11. The external driver output signals can be used in Stand-by and Active mode. The external driver can be activated via SPI bit OUT.OUT4. Note: The usable duty cycle range an d diagnostic timings depend on the external driver’s characteristics. LogicPins_InputMatr ix_4chED_PCC.emf IN0 Gate Control 3 Gate Control 0& OR IIN 0 IN1 OR IIN 2 PCC0 PCC1 OR Gate Control 2 Gate Control 1 OR OUT1 OUT3 OUT0OUT2 & & & & MUX≠111 COL

Data Sheet 18 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Logic Pins

5.3 Electrical Characteristics Logic Pins

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Digital Input (DI) pins = IN

5.4 Electrical Characteristics Logic Pins - Advanced Features

Table 7 Electrical Characteri stics: Logic Pins - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Digital Input Voltage Threshold VDI(TH) 0.8 1.3 2 V See Figure 11 and Figure 12 P_5.4.0.1 Digital Input Clamping Voltage VDI(CLAMP1) –7–V 1) IDI = 1 mA See Figure 11 and Figure 12 1) Not subject to production test - specified by design. P_5.4.0.2 Digital Input Clamping Voltage VDI(CLAMP2) 6.5 7.5 8.5 V IDI = 2 mA See Figure 11 and Figure 12 P_5.4.0.3 Digital Input Hysteresis VDI(HYS) –0 . 2 5 –V 1) See Figure 11 and Figure 12 P_5.4.0.4 Digital Input Current (“high”) IDI(H) 21 0 2 5 µ A VDI = 2 V See Figure 11 and Figure 12 P_5.4.0.5 Digital Input Current (“low”) IDI(L) 21 0 2 5 µ A VDI = 0.8 V See Figure 11 and Figure 12 P_5.4.0.6 Table 8 Electrical Characteri stics: Logic Pins - Advanced Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SPI pins Digital Input Voltage Threshold of Pin CSN Digital Input Voltage Threshold of Pin SCLK Digital Input Voltage Threshold of Pin SI Digital Input Clamping Voltage of Pin CSN VCSN(CLAMP1) –7–V 2) ICSN = 1 mA P_5.5.0.4 Digital Input Clamping Voltage of Pin CSN

Data Sheet 19 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Logic Pins Digital Input Clamping Voltage of Pin SCLK VSCLK(CLAMP1) –7–V 2) ISCLK = 1 mA P_5.5.0.6 Digital Input Clamping Voltage of Pin SCLK Digital Input Clamping Voltage of Pin SI VSI(CLAMP1) –7–V 2) ISI = 1 mA P_5.5.0.8 Digital Input Clamping Voltage of Pin SI Digital Input Hysteresis of Pin CSN VCSN(HYS) –0 . 2 5 –V 2) See Figure 12 P_5.5.0.11 Digital Input Hysteresis of Pin SCLK VSCLK(HYS) –0 . 2 5 –V 2) See Figure 12 P_5.5.0.13 Digital Input Hysteresis of Pin SI VSI(HYS) –0 . 2 5 –V 2) See Figure 12 P_5.5.0.15 Digital Input Current (“low”) of Pin CSN -ICSN(L) 21 0 2 5 μA VCSN = 0.5 V P_5.5.0.10 Digital Input Current (“high”) of Pin CSN -ICSN(H) 21 0 2 5 μA VCSN = 2.6 V P_5.5.0.12 Digital Input Current (“low”) of Pin SCLK ISCLK(L) 21 0 2 5 μA VSCLK = 0.5 V P_5.5.0.14 Digital Input Current (“high”) of Pin SCLK ISCLK(H) 21 0 2 5 μA VSCLK = 2.6 V P_5.5.0.16 Digital Input Current (“low”) of Pin SI ISI(L) 21 0 2 5 μA VSI = 0.5 V P_5.5.0.18 Digital Input Current (“high”) of Pin SI ISI(H) 21 0 2 5 μA VSI = 2.6 V P_5.5.0.20 Digital Output Voltage (“low”) of Pin SO Digital Output Voltage (“high”) of Pin SO VSO(H) VDD - 0.5 V – VDD V ISO = 0.5 mA P_5.5.0.23 Output Tristate Leakage Current of Pin SO ISO(OFF) -1 – 1 μA VCSN = VDD VSO = 0 V or VCSN = VDD VSO = VDD P_5.5.0.24 LHI pin Digital Input Voltage Threshold of Pin LHI Digital Input Clamping Voltage of Pin LHI VLHI(CLAMP1) –7–V 2) ILHI = 1 mA P_5.5.0.27 Digital Input Clamping Voltage of Pin LHI Table 8 Electrical Characteri stics: Logic Pins - Advanced (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 20 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Logic Pins Digital Input Hysteresis of Pin LHI VLHI(HYS) –0 . 2 5 –V 2) P_5.5.0.29 Digital Input Current (“high”) of Pin LHI ILHI(H) 10 32 65 µA VLHI = 5 V VDD = 0 V P_5.5.0.30 Digital Input Current (“low”) of Pin LHI ILHI(L) 10 24 45 µA VLHI = 0.8 V VDD = 0 V P_5.5.0.32 External Driver Pins Digital Output Voltage (“low”) of Pin EDO Digital Output Voltage (“high”) of Pin EDO VEDO(H) VDD - 0.5 V – VDD V IEDO = 0.2 mA P_5.5.0.34 Digital Output Voltage (“low”) of Pin EDD Digital Output Voltage (“high”) of Pin EDD VEDD(H) VDD - 0.5 V – VDD V IEDD = 0.2 mA P_5.5.0.37 1) Functional test only. 2) Not subject to production test - specified by design. Table 8 Electrical Characteri stics: Logic Pins - Advanced (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 21 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply

6 Power Supply

The BTS71040-4ESE is supplied by two supply voltages:

• Power Supply Voltage ( VS)
• Digital Supply Voltage ( VDD) The VS supply line is connected to a battery feed and used for the driv ing circuitry of the power stages, while VDD is used for the SPI logic and for driving SO pin. VS and VDD supply voltages have an undervoltage detection circuit, which prevents the activation of the associated function in case the measured voltage is below the undervoltage threshold. More in detail:
• An undervoltage on VDD supply prevents SPI communication. SPI registers are reset to their default values
• An undervoltage on VS supply switches OFF all channels, even in Limp Home mode. The channels are enabled again as soon as VS ≥ VS(OP) The voltage at pin VS is also monitored. In case of a negative voltage transient on VS resulting in VS < VS(TP) when the device is out of Sleep mode, any SPI command sent by the microcontrol ler is not accepted (see Chapter 6.2 and Chapter 10.5 for further information). An overview of channel behavior according to different VS and VDD supply voltages is shown in Table 9. Table 9 Device capability as function of VS and VDD 1) Valid after a successful supply voltage ramp-up. VDD ≤ VDD(PO) (VDD(PO) see P_6.4.1.1) VDD > VDD(PO) VS ≤ VS(TP) (VS(TP) see P_6.4.0.5) Channels are OFF Channels are OFF SPI registers reset SPI registers protected SPI communication not available (fSCLK = 0 MHz) SPI communication available2) (fSCLK = 5 MHz) 2) Write commands are ignored. Furthe rmore the device responds with STDDIAG only. Limp Home mode not available Limp Home mode not available VS(TP) < VS ≤ VS(UV) (VS(UV) see P_6.4.0.1) Channels are OFF Channels are OFF SPI registers reset SPI registers available SPI communication not available (fSCLK = 0 MHz) SPI communication available (fSCLK = 5 MHz) Limp Home mode available (channels are OFF) Limp Home mode available (channels are OFF) VS > VS(UV) 3) The undervoltage condition on VS supply must be considered. See Chapter 6.2. Channels cannot be controlled by SPI Channels can be controlled by SPI SPI registers reset SPI registers available SPI communication not available SCLK = 0 MHz) SPI communication available (fSCLK = 5 MHz) Limp Home mode available Limp Home mode available

Data Sheet 22 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply

6.1 Operation Modes

BTS71040-4ESE has the following operation modes:

• S l e e p m o d e
• A c t i v e m o d e
• S t a n d - b y m o d e
• Ready mode
• Limp Home mode
• Limp Home Active mode The transition between operation modes is determined according to these variables:
• Digital supply level ( V DD)
• Logic level at INn pins
• Logic level at LHI pin
• Current sense multiplexer state ( DCR.MUX)
• Output register state ( OUT.OUTn)
• Configuration registers state The state diagram including the possible transitions is shown in Figure 14. The behavior of BTS71040-4ESE as well as some parameters may change in dependence from the operation mode of the device. Furthermore, due to the undervoltage detection circuitry which monitors V S supply voltage, some changes within the same operation mode can be seen accordingly. There are five parameters describing each operation mode of BTS71040-4ESE:
• Status of the output channels
• Status of SPI registers
• Status of SPI communication
• Current consumption at VS pin (measured by I VS in Sleep mode, IGND in all other operative modes)
• Current consumption at VDD pin ( IVDD) Table 10 shows the correlation between operation modes, VS and VDD supply voltages, and the state of the most important functions (channel status, SPI communication and SPI registers).

Data Sheet 23 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply Figure 14 Operation Mode state diagram Table 10 Device function in relation to operation modes, VDD and VS voltages Operative Mode Function VS ≤ VS(TP) VS(TP) ≤ VS ≤ VS(UV) VS > VS(UV) Sleep Channels OFF OFF OFF SPI registers available 1) 1) In case VDD > VDD(PO) otherwise not available or in reset. available1) available1) SPI comm. available 1) available1) available1) Stand-by Channels OFF OFF OFF SPI registers protected 1) available1) available1) SPI comm. all commands rejected 1) available1) available1) Ready Channels OFF OFF OFF SPI registers protected 1) available1) available1) SPI comm. all commands rejected 1) available1) available1) Active Channels OFF OFF follow SPI and/or Input pins SPI registers protected 1) available1) available1) SPI comm. all commands rejected 1) available1) available1) Limp Home / Limp Home Active Channels OFF OFF follow Input pins SPI registers protected 1) reset (Diagnosis available)1) reset (Diagnosis available) SPI comm. all commands rejected1)2) 2) In case all input pins are set to “low”, SPI communication is in read-only mode. read-only1) read-only1) P owerS up pl y_O pMo des .em f DCR.MUX ≠ 111B Power-up DCR.MUX = 111B or SPI_Reset OUT.OUTn = 1B or INn = "high" INn = "low" & OUT.OUTn = 0B DCR.MUX ≠ 111B or INn = "hi gh" DCR.MUX = 111B & INn = "low" OUT.OUTn = 1B OUT.OUTn = 0B or SPI_Reset LHI = "high" LHI = "high" & INn = "high" LHI = "high" LHI = "low" LHI = "high" Ready Limp Home Sleep Active INn = "low" or INn = "low" & SPI_Reset Stand-by No te: SPI bits which are not stated are considered to have the default value or are unchanged compared to the previous state. Supply voltages are considered to be in operative range if not specified different. SPI_Reset is p er formed i f VDD < VDD(PO) or HWCR.RST = 1B Dashed lines indicate transitions between modes which should not be used for normal operation. LHI = "low" & INn = "high" INn = "high" Limp Home Active LHI = "high" & INn = "low" Unsupplied INn = "low" INn = "high"

Data Sheet 24 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply

6.1.1 Unsupplied

In this state, the device is either unsupplied (no voltage applied to VS pin and VDD pin) or the supply voltages are both below the corresponding undervoltage threshold.

6.1.2 Power-up

The Power-up condition is entered when one of the supply voltages ( VS or VDD) is applied to the device. Both supplies are rising until they are above the undervoltage thresholds VS(OP) and VDD(PO) therefore the internal Power-On signals are set. The SPI interface can be accessed after wake up time tWU(PO).

6.1.3 Sleep mode

The device is in Sleep mode when all Digita l Input pins (INn, LHI) are set to “low” and DCR.MUX is still set to 111B. When BTS71040-4ESE is in Sleep mode, all outputs are OFF. The SPI registers can be programmed if VDD > VDD(PO). The current consumption is minimum (see parameter IVS(SLEEP)). No Overtemperature or Overload protection mechanism is active when the device is in Sleep mode. The circuitry that monitors VS versus VS(UV) and VS versus VS(TP) is disabled. This allows the programming of the registers even if VS < VS(TP).

6.1.4 Stand-by mode

The device is in Stand-by mode when DCR.MUX≠111B and no command to switch ON a channel was received (either via SPI or via Input pins). All channels are OFF but the internal supply circuitry is working and therefore the device current consumption is increased. A command to switch ON one or more outputs is accepted and executed, bringing the device into Active mode. SPI communication is possible.

6.1.5 Ready mode

I n R ead y mo de, o ne o r m or e o utp uts rec ei v ed a c o mma n d to s wi tc h O N (ei th er vi a SP I o r v i a I np ut pi n s i f HWCR.COL = 1 B). Nevertheless, all outputs are OFF because of DCR.MUX bits still set to 111B. It is necessary to change the value of those bits to bring the device into Active mode and switch ON the channels. Note: Since OUT register is blanked with DCR.MUX = 111B it is not possible to enter Active mode when HWCR.COL bit is set to 1B.

6.1.6 Active mode

Active mode is the normal operation mode of BTS71040-4ESE when no Limp Home condition is set and one or more outputs are switched ON. Device curr ent consumption is specified by parameter IGND(ACTIVE). An undervoltage condition on VDD supply voltage brings the device into Sleep mode in case all Input pins are set to “low”.

6.1.7 Limp Home mode

The device enters Limp Home mode when LHI pin is set to “high” for t>t LHI(AC). SPI registers are reset to the default values when Limp Home mode is entered. The corresponding bit in the standard diagnosis (STDDIAG.LHI) will be set to 1 B once the LHI pin is set to “high” and latched until next STDDIAG transmission. See Figure 15 for further information. SPI registers are available for read access. ERRDIAG, STDDIAG, WRNDIAG and ICS can be used for diagnosis in Limp Home. When the device is in transient protection ( VS ≤ VS(TP)) and the LHI pin is set to "high", the STDDIAG.LHI bit will be set but the device will not change its state to Limp Home mode. Furthermore STDDIAG.VSMON and STDDIAG.TER bits will be set to report the battery transient protection.

Data Sheet 25 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply Figure 15 Limp Home Activation as function of VS

6.1.8 Limp Home Active mode

Limp Home Active mode is entered wh en the device is in Limp Home mode and one of the IN pins is set to “high”. Overload, Overtemperature an d Overvoltage protections are acti ve. Since SPI registers cannot be written current sensing is not available. LHI pin STDDIAG .LHI SP I comm. registers tLHI(AC ) t < tLHI(AC ) tLHI(AC ) Po werS upp ly_Lim pH omeActi ve .emf ava il a bl e re ad-only ava il a bl e VS VS(TP) t t t t al l co mm an d rej ect ed Read STDDIAG Note: Devic e out o f Sleep mod e w hen SP I c omm . „av ailab le“ tLH I(AC ) Read STDDIAG Read STDDIAG ava il a bl e re se t ava il a bl e protected

Data Sheet 26 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply

6.1.9 Definition of Operation modes transition times

The channel turn-ON time is as defined by parameter tON when BTS71040-4ESE is in Active mode or in Limp Home mode. In all other cases, it is necessary to add the transition time required to reach one of the two aforementioned operation modes (as shown in Figure 16). Figure 16 Transition Time diagram

6.2 Undervoltage on VS

Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active or Limp Home Active mode) and the supply voltag e drops below the unde rvoltage threshold VS(UV), the internal logic switches OFF the output cha nnels. When the device is either in Stand-by, Active or Limp Home mode the bit STDDIAG.VSMON is set and latched until readout. When the st ate is changed from Sleep to any other state, a delay of t ≥ tTRANS2STBY has to be considered until STDDIAG.VSMON is valid. As soon as the supply voltage VS is above the operative threshold VS(OP), the channels having the corresponding input pin set to “high” or the bit in the OUT register set to 1B are switched ON again. The restart is delayed with a time tDELAY(UV) which protects the device in case the undervoltage condition is caused by a short circuit event (according to AEC-Q100-012), as shown in Figure 17. P owerS up pl y_O pMo des _Ti min gs .em f Ready Limp Home SleepStand-by tTRANS2STBY tON tON tLHI(AC) + tTRANS2STBY tLHI(AC) tLHI(AC) Limp Home Active tOFF + tLHI(AC) tOFF tOFF tTRANS2SLP tON + tTRANS2STBY tOFF + tTRANS2SLP tLHI(AC) + tTRANS2SLP

1 SPI frame

Unsupplied tWU(PO) tLHI(AC) + tTRANS2STBY Active tLHI(AC) No te: Dashed lines indicate transition timings between modes which should not be used for normal operation.

Data Sheet 27 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply Figure 17 VS undervoltage behavior

6.3 Reset Condition

One of the following conditions reset the SPI registers to their default value:

• VDD is not present or below the undervoltage threshold VDD(PO) – SPI registers will be reset to their default va lues (in the first communication after reset the STDDIAG.TER will be set to 1B). – Restart counters will not be reset if VS is available or LHI is "high".
• LHI pin is set to “high” for t > tLHI(AC) and VS > VS(TP) – Configuration registers will be reset to their default values. ERRDIAG and WRNDIAG will be reset. – Restart counters will be reset.
• Reset command ( HWCR.RST=1 B) is executed and VS > VS(TP) – Configuration registers will be reset to their default values. ERRDIAG, WRNDIAG and STDDIAG will not be reset. – Restart counters will not be reset. In case all Input pins are set to “low” after any reset condition, all channels are switched OFF. Po werS upp ly_UVRVS.emf VS(O P) VS(UV) VS(HYS) VOU T VS tDE L AY(UV ) Op era tio n Mode STDDIAG. VSMON STDDIAG. TER VS(TP) t t t t t Ac tiveStand-by Read STDDIAG Read STDDIAG Sl eep Ac tiveReady Read STDDIAG Read STDDIAG

Data Sheet 28 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply

6.4 Electrical Characteristics Power Supply

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω Table 11 Electrical Characteri stics: Power Supply - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. VS pin Power Supply Undervoltage Shutdown VS(UV) 1.8 2.3 3.1 V VS decreasing IN = “high” or OUT.OUTn = 1B From VDS ≤ 0.5 V to VDS = VS See Figure 17 P_6.4.0.1 Power Supply Minimum Operating Voltage VS(OP) 2.0 3.0 4.1 V VS increasing IN = “high”or OUT.OUTn = 1 B From VDS = VS to VDS ≤0.5 V See Figure 17 P_6.4.0.3 Power Supply Voltage Threshold for Battery Transients Protection VS(TP) 0.6 1.0 1.8 V VS decreasing STDDIAG.VSMON = 1B STDDIAG.TER = 1B DCR.MUX ≠111B See Figure 17 P_6.4.0.5 Power Supply Undervoltage Shutdown Hysteresis VS(HYS) –0 . 7 –V 1) VS(OP) - VS(UV) See Figure 17 1) Not subject to production test - specified by design. P_6.4.0.6 Power Supply Undervoltage Recovery Time tDELAY(UV) 2.5 4 5.5 ms 1) See Figure 17 P_6.4.0.10 Breakdown Voltage between GND and VS Pins in Reverse Battery S(REV) 16 – 30 V 1) IGND(REV) = 14 mA TJ = 150 °C P_6.4.0.9

Data Sheet 29 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply

6.4.1 Electrical Characteristics Power Supply - SPOC™

6.5 Electrical Characteristics Power Supply - Product Specific

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω Table 12 Electrical Characteri stics: Power Supply - SPOC™ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. VDD pin Digital Supply Operating Voltage VDD(OP) 2.45 4.3 5.5 V 1) fSCLK = 5 MHz 1) Not subject to production test - specified by design. P_6.4.1.1 Digital Supply Power-On Reset Threshold Voltage VDD(PO) 1.4 1.9 2.3 V 1) VDD increasing P_6.4.1.9 Digital Supply Undervoltage Shutdown VDD(UV) 1.3 1.8 2.2 V VDD decreasing OUT.OUTn = 1B From VDS ≤ 0.5 V to VDS = VS P_6.4.1.2 Digital Supply Undervoltage Shutdown Hysteresis VDD(HYS) –0 . 1 –V 1) P_6.4.1.3 Digital Supply Clamping Voltage VDD(CLAMP1) –6 . 5 –V 1) IDD =1m A P_6.4.1.11 Digital Supply Clamping Voltage VDD(CLAMP2) 678V IDD =2 0m A P_6.4.1.12 Power-On Wake Up Time tWU(PO) –1 0 3 0 μs 1) P_6.4.1.13 Transition Time to Stand-by Mode tTRANS2STBY 51 0 3 0 μs 1) P_6.4.1.4 Transition Time to Sleep Mode tTRANS2SLP 156 0 μs 1)2) SRC.SRCn = 0B 2) If output channel enters inductive cl amping, clamping time has to be added. P_6.4.1.5 Transition Time to Sleep Mode with adjusted Slew Rate t TRANS2SLP 1 5 170 μs 1)2) SRC.SRCn = 1B P_6.4.1.7 Limp Home Acknowledgement Time tLHI(AC) 10 20 40 µs 1) P_6.4.1.6

Data Sheet 30 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Supply

6.5.1 BTS71040-4ESE

Table 13 Electrical Characterist ics: Power Supply BTS71040-4ESE Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Digital Supply Current Consumption in Normal Operation I DD – 80 200 µA fSCLK = 0 MHz VS > VS(UV) VCSN = VDD = 5 V DCR.MUX ≠ 111B P_6.5.32.1 Digital Supply Current Consumption in Sleep Mode IDD(SLEEP) – 1 75 0µ A fSCLK = 0 MHz VS > VS(UV) VCSN = VDD = 5 V DCR.MUX = 111B P_6.5.32.3 Digital Supply Current Consumption in Sleep Mode IDD(SLEEP) – 1 73 5µ A fSCLK = 0 MHz VS > VS(UV) VCSN = VDD = 5 V DCR.MUX = 111B TJ ≤ 85 °C P_6.5.32.12 Power Supply Current Consumption in Sleep Mode with Loads at TJ ≤85 °C IVS(SLEEP)_85 – 0.05 0.4 µA 1)2) VS = 18 V VOUT = 0 V INx = “low” T J ≤ 85 °C 1) Not subject to production test - specified by design. 2) If VDD < VDD(PO), LHI =”low” and any restart counter > 0, IGND(STBY) has to be considered. P_6.5.32.4 Power Supply Current Consumption in Sleep Mode with Loads at TJ = 150 °C IVS(SLEEP)_150 – 2 100 µA VS = 18 V VOUT = 0 V INx = “low” TJ = 150 °C P_6.5.32.5 Operating Current in Active Mode (all Channels ON) IGND(ACTIVE) –57m A VS = 18 V VDD = 5 V INx = “high” or OUT.OUTn = 1B P_6.5.32.6 Operating Current in Ready Mode IGND(READY) – 80 200 µA VS = 18 V VCSN = VDD = 5 V fSCLK = 0 MHz DCR.MUX = 111B OUT.OUTn = 1B P_6.5.32.8 Operating Current in Stand- by Mode IGND(STBY) –1 . 2 5 2m A VS = 18 V VDD = 5 V DCR.MUX ≠ 111B P_6.5.32.9

Data Sheet 31 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages

7 Power Stages

The high-side power stages are built using a N-channel vertical Power MOSFET with charge pump.

7.1 Output ON-State Resistance

The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 18 shows the variation of RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured at TJ = 150 °C. Figure 18 RDS(ON) variation factor The behavior in Reverse Polarity is described in Chapter 8.4.1.

7.2 Switching loads

7.2.1 Switching Resistive Loads

When switching resistive loads, the switching times and slew rates shown in Figure 19 can be considered. The switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 RDS(ON) variation factor Junction Temperature (°C) RDS(ON) variation over TJ Typical Reference value: "2" = RDS(ON),MAX @ 150 °C

Data Sheet 32 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages Figure 19 Switching a Resistive Load

7.2.2 Switching Inductive Loads

When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to overvoltage, a voltage clamp mechanism is implem ented. The clamping structure limits the negative output voltage so that VDS = VDS(CLAMP). Figure 20 shows a concept drawing of the implementation. The clamping structure protects the device in all operation modes listed in Chapter 6.1. Figure 20 Output Clamp concept IN / OUT.OUTn t VOUT VIN(TH) (dV/dt)ON VIN(HYS) PDMOS EON EOFF tON tON(DELAY) tOFF(DELAY) -(dV/dt)OFF tOFF 10% of VS 90% of VS 70% of VS 30% of VS 30% of VS 70% of VS t t PowerStage_Clamp_INTDIO.emf High-sid e Channel VS RL VOU Tn I L VDS(CLAM P) IL VS OUTn VDS GND VS(CLAM P) IS VSI S(CLAM P) RSE N SE RGND

Data Sheet 33 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages During demagnetization of inductive loads, energy has to be dissipated in BTS71040-4ESE. The energy can be calculated with Equation (7.1): (7.1) The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design of the component.

7.2.3 Output Voltage Limitation

To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while the channel is diagnosed (channel selected via DCR.MUX - see Figure 21) bringing VDS equal or lower than VDS(SLC), the output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC) even for very small output currents. The VDS increase allows the current sensing circuitry to work more efficiently, providing better kILIS accuracy for output current in the low range. Figure 21 Output Voltage Limitati on activation during diagnosis

7.2.4 Switching Capacitive Loads

When switching ON a capacitive load, the capacitanc e is causing a high inrush current. The current is depending on the value of the capaci tance, the ESR, the impedance of th e system and the slew rate of the driver. To improve the load driving capability, BTS71040-4ESE offers a slew rate control feature. When the slew rate bit SRC.SRCn is set, the slew rate of the respective channel is reduced to the half (see Chapter 7.4.1). EV DS CLAMP() VS VDS CLAMP()– RL RL I⋅ L ⎛⎞ IL+ln⋅ L RL IN / OUT.OUTn IL t PowerStage_GBR_diag.emf CS tsIS (O N) tsIS (O FF) t VDS VDS(SLC) VS 000110 110DCR.MUX t t

Data Sheet 34 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages

7.3 Advanced Switching Characteristics

7.3.1 Inverse Current behavior

When VOUT > VS, a current IINV flows into the power output transistor (see Figure 22). This condition is known as “Inverse Current”. If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses therefore an increase of overall device temperature. This may lead to a switch OFF of unaffected channels due to Overtemperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output stage is comparable to normal operation in RDS(ON). During Inverse Current condition, the channel remains in ON or OFF state as long as IINV < IL(INV). With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as IINV < IL(INV) (see Figure 23). Figure 22 Inverse Current Circuitry OUT VS VBAT IINVINV Comp. VINV = VOU T > VS Gate Driver Device Logic GND PowerStage_InvC urr_INTDIO.emf RGND

Data Sheet 35 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages Figure 23 InverseON - Channel behavior in case of applied Inverse Current Note: No protection mechanism like Overtemperature or Overload protection is active during applied Inverse Currents.

7.3.2 Switching Channels in Parallel

When switching channels in parallel to drive a single lo ad it may happen that th e two channels switch OFF asynchronously in case of a fault co ndition which brings additional stress to the channel that switches OFF last. In order to avoid this condition, it is possible to synchronize the protection of two channels when used in parallel. There are 2 bits in the SPI (PCS.PCCn), which allow to synchronize channels 0&3 and 1&2. When the corresponding PCS.PCCn bit is set, the switch-OFF and restart of the channels are synchronized and the current trip levels will be reduced to IL(OVL3). In case the current trip level for one channel is set to the low level (OCR.OCTn = 1 B), the current for both cha nnels will be reduced to IL(OVL2). Since the restart counters of the channels in parallel are synchronized, both channe ls will latch-OFF as soon one counter has reached nRESTART(CR). Due to this reason it is recommended to clear counters before switching channels in parallel. In case the slew rate adjustment for one channels is used, (SRC.SRCn = 1B), both channels operating in parallel mode will use the adjusted slew rate. Wh en channels are swit ched in parallel ( PCS.PCCn = 1 B), the Output Voltage Drop Limitation at Small Load Currents is disabled. Therefore the current sense ratio specifications at lower currents are not valid. See Chapter 9.7 for further information. To improve current sense accuracy in parallel channel operation, parallel mode has to be deactivated (PCS.PCCn = 0B). Since the current sense of the two channels used in parallel is not synchronized, the total current has to be calculated out of the current sense reading of each single channel. Unless otherw ise specified parameter de viations are possible when parallel mode is activated. OFF OFF CASE 2 : Switch is OFFIN t IL t DMOS state t INVERSE NORMALNORMAL ON INVERSE NORMAL IL t DMOS state t ON CASE 1 : Switch is ONIN t NORMAL OFF ON CASE 4 : Switch OFF into Inverse Curren t IN t IL t DMOS state t INVERSE NORMALNORMAL ON INVERSE NORMAL IL t DMOS state t OFF CASE 3 : Switch ON into Inverse Curren t IN t NORMAL OFF ON ON OFF Power St age_InvCurr_INVON.emf

Data Sheet 36 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages When two channels are used in parallel, the total current capability IL(NOM) is doubled. It has to be ensured that the outputs used in parallel mode are connected toge ther with a symmetric and low impedance connection either on the PCB or in the wire harness.

7.3.3 Cross Current robustness with H-Bridge configuration

When BTS71040-4ESE is used as high-sid e switch e.g. in a bridge configur ation (therefore paired with a low- side switch as shown in Figure 24), the maximum slew rate applied to the output by the low-side switch must be lower than | d VOUT / dt |. Otherwise the output stage may turn ON in linear mode (not in RDS(ON)) while the low-side switch is commutating. Th is creates an unprotected overheat ing for the DMOS due to the cross- conduction current. Figure 24 High-Side switch used in Bridge configuration INx INy OUTx OUTy VS Power St age_Passive Slew_S PO C.emf T T VBAT R/L cable M ON (DC) OFF ON (PWM) OFF Current through Motor Cross Current | dVOU T / dt |

Data Sheet 37 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages

7.4 Electrical Characteristics Power Stages

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω

7.4.1 Electrical Characteristics Power Stages - SPOC™

Table 14 Electrical Characterist ics: Power Stages - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltages Drain to Source Clamping Voltage at TJ = -40 °C VDS(CLAMP)_-40 33 36.5 42 V IL = 5 mA TJ = -40°C See Figure 20 P_7.4.0.1 Drain to Source Clamping Voltage at TJ ≥ 25 °C VDS(CLAMP)_25 35 38 44 V 1) IL = 5 mA TJ ≥ 25°C See Figure 20 1) Tested at TJ = 150°C. P_7.4.0.2 Table 15 Electrical Characteristics: Power Stages - SPOC™ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Timings Switch-ON Delay tON(DELAY) 10 30 60 μs VS = 13.5 V VOUT = 10% VS PCS.PCCn = 0B P_7.4.2.1 Switch-ON Delay (parallel mode) tON(DELAY) 10 40 80 μs 2) VS = 13.5 V VOUT = 10% VS PCS.PCCn = 1B P_7.4.2.16 Switch-OFF Delay tOFF(DELAY) 10 30 60 μs VS = 13.5 V VOUT = 90% VS P_7.4.2.2 Switch-ON Time tON 20 55 100 μs VS = 13.5 V VOUT = 90% VS SRC.SRCn = 0B PCS.PCCn = 0B P_7.4.2.3 Switch-ON Time (parallel mode) tON 20 70 125 μs 2) VS = 13.5 V VOUT = 90% VS SRC.SRCn = 0B PCS.PCCn = 1B P_7.4.2.20

Data Sheet 38 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages Switch-ON Time tON 30 75 150 μs VS = 13.5 V VOUT = 90% VS SRC.SRCn = 1B P_7.4.2.4 Switch-OFF Time tOFF 20 55 100 μs VS = 13.5 V VOUT = 10% VS SRC.SRCn = 0B P_7.4.2.6 Switch-OFF Time tOFF 30 75 150 μs VS = 13.5 V VOUT = 10% VS SRC.SRCn = 1B P_7.4.2.7 Switch-ON/OFF Matching tON - tOFF ΔtSW -50 0 50 μs VS = 13.5 V PCS.PCCn = 0B P_7.4.2.9 Voltage Slope Switch-ON Slew Rate (d V/dt)ON 0.3 0.6 0.9 V/ μs VS = 13.5 V VOUT = 30% to 70% of VS SRC.SRCn = 0B P_7.4.2.11 Switch-ON Slew Rate (d V/dt)ON 0.15 0.3 0.45 V/ μs VS = 13.5 V VOUT = 30% to 70% of VS SRC.SRCn = 1B P_7.4.2.12 Switch-OFF Slew Rate -(d V/dt)OFF 0.3 0.6 0.9 V/ μs VS = 13.5 V VOUT = 70% to 30% of VS SRC.SRCn = 0B P_7.4.2.14 Switch-OFF Slew Rate -(d V/dt)OFF 0.125 0.3 0.45 V/ μs VS = 13.5 V VOUT = 70% to 30% of VS SRC.SRCn = 1B P_7.4.2.15 Slew Rate Matching Δ(dV/dt)SW -30 0 30 % 1) VS = 13.5 V P_7.4.2.17 Voltages Output Voltage Drop Limitation at Small Load Currents VDS(SLC) 21 0 1 8 m V 2) IL = IL(OL) = 20 mA P_7.4.2.18 1) Δ(dV/dt)SW =( ( dV/dt)ON -( dV/dt)OFF) / (((dV/dt)ON +( dV/dt)OFF)/2 ) . 2) Not subject to production test - specified by design. Table 15 Electrical Characteristics: Power Stages - SPOC™ (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 39 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages

7.5 Electrical Characteristics - Power Output Stages

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω

7.5.1 Power Output Stage - 27 W

Table 16 Electrical Characteristics: Power Stages - 27 W Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output characteristics ON-State Resistance at T J =2 5° C RDS(ON)_25 – 22.5 – m Ω 1) TJ = 25 °C P_7.5.16.1 ON-State Resistance at TJ = 150 °C RDS(ON)_150 ––3 8 m Ω TJ = 150 °C P_7.5.16.2 ON-State Resistance in Cranking RDS(ON)_CRANK ––4 4 m Ω TJ = 150 °C VS = 3.1 V P_7.5.16.3 ON-State Resistance in Inverse Current at TJ = 25 °C RDS(INV)_25 – 22.5 – m Ω 1) TJ = 25 °C IL = -IL(NOM) P_7.5.16.4 ON-State Resistance in Inverse Current at TJ = 150 °C RDS(INV)_150 ––4 4 m Ω 1) TJ = 150 °C IL = -IL(NOM) P_7.5.16.5 ON-State Resistance in Reverse Polarity at TJ = 25 °C RDS(REV)_25 –4 5 –m Ω 1) TJ = 25 °C VS = -13.5 V IL = -IL(NOM) RSENSE = 1.2 kΩ P_7.5.16.6 ON-State Resistance in Reverse Polarity at TJ = 150 °C RDS(REV)_150 ––7 0 m Ω 1) TJ = 150 °C VS = -13.5 V IL = -IL(NOM) RSENSE = 1.2 kΩ P_7.5.16.7 Nominal Load Current per Channel (all Channels Active) I L(NOM) –3–A 1) TA = 85 °C TJ ≤ 150 °C P_7.5.16.8 Output Leakage Current at TJ ≤ 85 °C IL(OFF)_85 –0 . 0 3 0 . 1 5 μA 1) VOUT = 0 V VIN = “low” and OUT.OUTn = 0B TA ≤ 85 °C P_7.5.16.9

Data Sheet 40 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Power Stages Output Leakage Current at TJ = 150 °C IL(OFF)_150 ––1 0 μA VOUT = 0 V VIN = “low” and OUT.OUTn = 0B TA = 150 °C P_7.5.16.10 Inverse Current Capability IL(INV) –3–A 1) VS < VOUT IN = “high” or OUT.OUTn = 1B P_7.5.16.11 Voltage Slope Passive Slew Rate (e.g. for Half Bridge Configuration) |dVOUT / dt| ––1 0 V / μs 1) VS = 13.5 V P_7.5.16.12 Voltages Drain Source Diode Voltage | VDS(DIODE)| – 500 600 mV 1) IL = -190 mA TJ = 150 °C P_7.5.16.13 Switching Energy Switch-ON Energy EON –0 . 3 0 –m J 1) VS = 18 V SRC.SRCn = 0B PCS.PCCn = 0B P_7.5.16.14 Switch-OFF Energy EOFF –0 . 3 8 –m J 1) VS = 18 V SRC.SRCn = 0B PCS.PCCn = 0B P_7.5.16.15 1) Not subject to production test - specified by design. Table 16 Electrical Characteristics: Power Stages - 27 W (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 41 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection

8 Protection

The BTS71040-4ESE is protected against Overtemperature, Overload, Reverse Battery (with ReverSave™) and Overvoltage. Overtemperature and Over load protections are working when the device is not in Sleep mode. Overvoltage protection works in all operation modes. Reverse Battery protection works when the GND and VS pins are reverse supplied.

8.1 Overtemperature Protection

The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for each channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN)) switches OFF the overheated channel to prevent destruction. The corresponding WRNDIAG.WRNn bits are set and cleared on read. The channel remains switched OFF until junction temperature has reached the “Restart” condition described in Table 17. The behavior is shown in Figure 25 (absolute Overtemperature Protection) and Figure 26 (dynamic Overtemperature Protection). TJ(REF) is the reference temperature used for dynamic temperature protection. Figure 25 Overtemperature Protection (Absolute) IL(O V L) IL t TJ IIS Protect io n_OT _Resta rt.em f IN / OUT.OUTn WRNDIAG.WRNn Internal count er TJ(ABS) t t t t t Read WRNDIAG

Data Sheet 42 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection Figure 26 Overtemperature Protection (Dynamic) When the Overtemperature protection circuitry allows the channel to be switched ON again, the restart strategy described in Chapter 8.3.1 is followed. Pr ote cti on_dT _Re star t.e mf IN / OUT.OUTn t IIS IL(O V L) IL TJ WRNDIAG.WRNn 0 1 ERRDIAG.ERRn Internal cou nt er 0 1 0 1 t t t t t t TJ(ABS) 2 3 4 5 6 0 1 01 HWCR.CLC = 1B Read WRNDIAG TJ(start ) Read WRNDIAG TJ(DY N) TJ(REF) nRESTART(CR) + 1

Data Sheet 43 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection

8.2 Overload Protection

The BTS71040-4ESE is protected in case of Overload or short circuit to ground. Two Overload thresholds are defined (see Figure 27) and selected automatically depending on the voltage VDS across the power DMOS:

• IL(OVL0) when VDS < 13 V
• IL(OVL1) when VDS > 22 V In addition, the Overload threshold can be reduced by setting OCR.OCTn. Figure 27 Overload current thresholds When IL ≥ IL(OVL) (either IL(OVL0) or IL(OVL1)), the channel is switched OFF. The channel is allowed to restart according to the restart strategy described in Chapter 8.3.1.

8.3 Protection and Diagnosis in case of Fault

Any event that triggers a protection mechanism (either Overtemperature or Overload) has 3 consequences:

• The affected channel switches OFF an d the internal counter is incremented
• The current sense of the affected channel is set to high impedance
• T h e c o r r e s p o n d i n g WRNDIAG.WRNn are set to 1B and latched until readout. The channel can be switched ON again if all the pr otection mechanisms fulfi ll the “restart” conditions described in Table 17 and the internal restart counter is enabled (RCD.RCDn set to 0B). 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 4 8 12 16 20 24 28 Drain Source Voltage (V) Overload threshold variation ("1" = IL(OVL0) @ VDS = 5 V) OCR.OCTn = 0 OCR.OCTn = 1 IL(OVL0) IL(OVL1)

Data Sheet 44 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection

8.3.1 Restart Strategy

When INx or OUT.OUTn is set to “high”, the corresponding channel is switched ON. In case of fault condition the output stage is switched OFF. The channel is allowed to restart only in case the “restart” conditions for the protection mechanisms are fulfilled (see Table 17). The WRNDIAG.WRNn is set during Overcurrent shutdown. It is reset when the internal fault signal is cleared and the WRNDIAG is transmitted, unless latched state is reached by exceeding nRESTART(CR). The next Overcurrent event set the WRNDIAG.WRNn again. In case the automatic restarts are not required, they can be deactivated by setting RCD.RCDn to 1B. When RCD.RCDn is set to 1 B, the restart counter will be reset. When a channel reaches latched state, the corresponding ERRDIAG.ERRn bit is set. The restart latch and counter are cleared by setting the SPI bit HWCR.CLC to 1B. If the input pin is “high” or OUT.OUTn is still set to 1 B, the channel is switched ON immediately after the command that set HWCR.CLC bit to 1 B. To ensure an adequate cool down after latch-OFF condition, application software needs to wait for t > tRETRY before restarting the channel. The restart strategy is shown in Figure 28. Figure 28 Restart Strategy timing diagram Table 17 Protection “Restart” Condition Fault condition Switch OFF event “Restart” Condition Overtemperature TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN) TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN) (including hysteresis) nRESTART < nRESTART(CR) RCD.RCDn = 0 Overload IL ≥ IL(OVL) IL < 50 mA TJ within TJ(ABS) and TJ(DYN) ranges (including hysteresis) nRESTART < nRESTART(CR) RCD.RCDn = 0 WRNDIAG.WRNn RCS.RCSn 0 0 1 t IN/ OUT.OUTn Sh ort circuit to gr ound IL 0 1 nRESTART(CR) + 1Internal count er Protecti on_Restart.emf nRESTART(CR) + 1 0 t t t t t 2 3 4 5 6 t > tRETRY HWCR.CLC = 1B 0 1 Read WRNDIAG RCD.RCDn = 1B 1 72 4 5 63 IL(O V L) 1 2 ... 1 71 2 ... HWCR.CLC = 1B

Data Sheet 45 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection Figure 29 Restart Strategy timing diagram in Limp Home

8.4 Additional protections

8.4.1 Reverse Polarity Protection

In Reverse Polarity condition (also known as Revers e Battery), the output stages are switched ON (see parameter RDS(REV)) because of ReverSave™ featur e which limits the power dissip ation in the output stages. Each ESD diode of the logic contributes to total powe r dissipation. The reverse current through the output stages must be limited by the connected loads. The current through digital power supply VDD and Digital Input pins has to be limited as well by an external resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application Information in Chapter 11). Figure 30 shows a typical application including a device with ReverSave™. A current flowing into GND pin (-IGND) during Reverse Polarity condition is necessary to activate ReverSave™, therefore a resistive path between module ground and device GND pin must be present. WRNDIAG.WRNn 0 1 t LHI Sh ort circuit to gr ound IL 0 1 nRESTART(CR) + 1Internal cou nt er Protect io n_Resta rt_LH.emf t t t t 2 3 4 5 6 0 1 Read WRNDIAG t IN 0 1 nRESTART(CR) + 12 3 4 5 6 0 1 nRESTART(CR) + 12 3 4 5 6 1 1 Read WRNDIAG tLH I(AC ) IL(OV L) Read WRNDIAG t < tDEL AY(CR) Read WRNDIAG Read WRNDIAG t ≥ tDEL AY(CR) t ≥ tRETRY

Data Sheet 46 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection Figure 30 Reverse Battery Protection (application example)

8.4.2 Overvoltage Protection

In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistors are still operational and follow the input pins or the OUT register. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there is a clamp mechanism av ailable for Overvoltage protection for the logic and the output channels, monitoring the voltage between VS and GND pins (VS(CLAMP)). Prote cti on_RevBa tt_SP I.e mf High-side Channel L, C, R VS OUT n GNDISRSEN SE RGN D DI µC DO GND -IOU T -IGN D-IIS IDI -VBAT(REV) RDI VDD Rev erSaveTM VDD RVD D IVDD 5V (reverse pr otected)

Data Sheet 47 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection

8.5 Protection against loss of connection

8.5.1 Loss of Battery and Loss of Load

The loss of connection to battery or to the load has no influence on device robustness when load and wire harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be handled. BTS71040-4ESE can handle the inductivit y of the wire harness up to 10 µH with IL(NOM). In case of applications where currents and/or the aforementioned inductivit y are exceeded, an external suppressor diode (like diode DZ2 shown in Chapter 11) is recommended to handle the energy and to provide a well- defined path to the load current. Note: In case of a lost battery connect ion the VS monitoring function protects the SPI registers as soon the device is out of Sleep mode. This means that any command sent to the device will be ignored and the device will just send back the STDDIAG. Furthermore, the status of the LHI pin is blanked, which means that it is not possible to enter Limp Home mode.

8.5.2 Loss of Ground

In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin and the microcontroller to ensure a channel switch OFF (as described in Chapter 11). Note: In case any Digital Input pin is pulled to ground (e ither by a resistor or active) a parasitic ground path is available, which could keep the device operational during loss of device ground. The same behavior applies for the SPI functionality.

Data Sheet 48 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection

8.6 Electrical Characteristics Protection

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω

8.6.1 Electrical Characteristics Protection - SPOC™

Table 18 Electrical Characteri stics: Protection - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Thermal Shutdown Temperature (Absolute) TJ(ABS) 150 175 200 °C 1)2) See Figure 25 1) Functional test only. 2) Tested at TJ = 150°C only. P_8.6.0.1 Thermal Shutdown Hysteresis (Absolute) THYS(ABS) –3 0 –K 3) See Figure 25 3) Not subject to production test - specified by design. P_8.6.0.2 Thermal Shutdown Temperature (Dynamic) TJ(DYN) –8 0 –K 3) See Figure 26 P_8.6.0.3 Power Supply Clamping Voltage at TJ = -40 °C VS(CLAMP)_-40 33 36.5 42 V IVS = 5 mA TJ = -40 °C See Figure 20 P_8.6.0.6 Power Supply Clamping Voltage at TJ ≥ 25 °C VS(CLAMP)_25 35 38 44 V 2) IVS = 5 mA TJ ≥ 25 °C See Figure 20 P_8.6.0.7 Power Supply Voltage Threshold for Overcurrent Threshold Reduction in case of Short Circuit V S(JS) 20.5 22.5 24.5 V 3) Setup acc. to AEC- Q100-012 P_8.6.0.8 Table 19 Electrical Characteri stics: Protection - SPOC™ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Counter Reset Delay Time after Fault Condition in Limp Home tDELAY(CR) 40 70 100 ms 1) LHI = “high” INx = “low” 1) Not subject to production test - specified by design. P_8.6.2.1 Automatic Restarts in Case of Fault after a Counter Reset nRESTART(CR) –6–– 1) P_8.6.2.2

Data Sheet 49 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Protection

8.7 Electrical Characteristics Pr otection - Power Output Stages

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω

8.7.1 Protection Power Output Stage - 27 W channels

Table 20 Electrical Characterist ics: Protection - 27 W channels Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Overload Detection Current High Level IL(OVL0) 44 48 53 A 1) OCR.OCTn= 0B TJ = -40 °C to 50 °C dI/dt = 0.2 A/µs 1) Tested at TJ =- 4 0° C . P_8.7.16.3 Overload Detection Current High Level IL(OVL0) 35 39 44 A 2) OCR.OCTn= 0B TJ = 150 °C dI/dt = 0.2 A/µs 2) Not subject to production test - specified by design. P_8.7.16.4 Overload Detection Current Low Level IL(OVL2) 19 24 29 A 2) OCR.OCTn= 1B dI/dt = 0.2 A/µs P_8.7.16.2 Overload Detection Current High Level (parallel mode) IL(OVL3) 22 31 36 A 2)3) OCR.OCTn= 0B PCS.PCCn= 1B dI/dt = 0.2 A/µs 3) IL(OVL3) applies for one channel. Total current for two channels in parallel IL(OVL) ≤ 2 x IL(OVL3). P_8.7.16.6 Overload Detection Current at High VDS IL(OVL1) –2 9 –A 2) dI/dt = 0.2 A/µs P_8.7.16.5 Overload Detection Current Jump Start Condition IL(OVL_JS) –2 9 –A 2) OCR.OCTn= 0B VS > VS(JS) dI/dt = 0.2 A/µs P_8.7.16.7

Data Sheet 50 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Diagnosis

9 Diagnosis

For diagnosis purpose, the BTS71040-4ESE provides a current sense at pin IS as well as a diagnosis feedback via SPI. In case of disabled diagnostic, IS pin be comes high impedance. The integrated current sense multiplexer is controlled via SPI. A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ. Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS pin to the sense current output of ot her devices, if they are supplied by a different battery feed or using a different sense concept. See Figure 31 for details as an overview. For diagnosis feed back at different operation modes, please see Chapter 9.2. Figure 31 Diagnosis block diagram Channel 0 Load Current Sense RSENSE Current Sense Multip lexer T Gate Control Overcurrent Pr ot ec ti on Latch Temperature Sensor ERR0 OR Latch DCR.MUX OUT3 OUT2 OUT1 OUT0 VS IS VS VDS(SB) DCR.SBM Diag nosis_4ch.emf IIS0

Data Sheet 51 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Diagnosis

9.1 Overview

Table 21 gives a quick reference to the state of the IS pin during BTS71040-4ESE operation. Table 21 Diagnosis feedback, Function of Operation Mode Operation Mode Input level OUT.OUTn VOUT Current sense IIS WRNDIAG .WRNn STDDIAG .SBM Normal operation Low / 0 B OFF ~ GND Z 0 1 Short circuit to GND ~ GND Z 0 1 Overtemperature Z Z 1 x Short circuit to V S VS Z0 0 Open Load < VS - VDS(SB) > VS - VDS(SB) 1) With additional pull-up resistor. Z Z Sense verification2) 2) DCR.MUX = 101B. x IIS(VER) x0 Normal operation High / 1 B ON ~ VS IIS = IL(NOM) / kILIS 00 Overload < VS IIS = IL / kILIS 0x Short circuit to GND ~ GND Z 1 1 Overtemperature Z Z 1 x Short circuit to V S VS IIS < IL / kILIS 00 Open Load ~ VS 3) The output current ha s to be smaller than IL(OL). IIS = IIS(EN) 00 Sense verification2) x IIS(VER) x0 Under load (e.g. Output Voltage Limitation condition) ~ V S 4) The output current has to be higher than IL(OL). IIS(EN) < IIS < IL(NOM) / kILIS 00

9.2 Diagnosis Word at SPI

protection latches are cleared by SPI command HWCR.CLC.

9.3 Diagnosis in ON state

• A power output stage is switched ON with VDS < VDS(SB)
• The diagnosis is enabled for that channel
• No fault (as described in Chapter 8.3) is present If a “hard” failure mode is present or occurs for the channel selected using the DCR.MUX bits, the IS pin remains in or changes to “high impedance” state.

9.3.1 Current Sense ( kILIS)

Figure 33. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).

• A well-defined and precise current ( IL(CAL)) is applied at the output during End of Line test at customer side
• The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
• Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by ΔkILIS The derating of kILIS after calibration is calculated using the formulas in Figure 32 and it is specified by ΔkILIS Figure 32 ΔkILIS calculation formulas The calibration is intend ed to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H. Diagnosis_dKILIS.emf

9.3.2 Current Sense Multiplexer

Figure 34. In addition DCR.MUX is used in combination with other SPI bits to address further functions of the sense verification mode is enabled when DCR.MUX = 101B.

• The main function of DCR.MUX is to switch the current sense multiplexer
• E x e c u t i n g PCS.CLCS = 1B clears the counter and latches OFF the channel selected by DCR.MUX
• E x e c u t i n g PCS.SRCS = 1B the slew rate of the channel selected by DCR.MUX will be changed. See Chapter 7.4.1 for further information
• When reading RCS.RCSn bits, the status of the internal counter of the channel selected by DCR.MUX is responded
• When setting DCR.MUX = 101B the sense verification mode is enabled
• When setting PCS.SRCS = 1b, the slew rate of the channel selected by DCR.MUX will be adjusted IIS IL Di agn o si s_ OLON . em f IIS(EN)

Data Sheet 54 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Diagnosis Figure 34 Current Sense Multiplexer Timings

9.4 Diagnosis in OFF state

When a power output stage is in OFF state, the BTS71040-4ESE can measure the output voltage and compare it with a threshold voltage. In this way, using some additional external components (a pull-down resistor and a switchable pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to battery.

9.4.1 Switch Bypass Monitor

To detect short circuit to VS, there is a switch bypass monitor implem ented. In case of short circuit between the output pin OUT and VS in ON state, the current flow s through the power transistor as well as through the short circuit (bypass) with undefined share between the two. As a result, the current sense signal shows lower values than expected by the load current. In OFF state, the output voltage remains close to VS potential which leads to a small VDS. The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX). The result of the comparison can be read in the standard diagnosis STDDIAG.SBM. In addition the switch bypass monitor can be used to detect an Open Load in OFF state. In this case a switchable pull-up resistor has to be placed to pull the OUT to VS potential.

9.5 SENSE Timings

Figure 35 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load change). As a proper signal cannot be established before the load current is stable (therefore before tON), tsIS(DIAG) = tsIS(ON) + tON. Figure 35 SENSE Settling / Disabling Timing Di agn o sis_MuxT i mi ng .em f CS N IIS t 001DCR.MUX 010110 110 tsI S(ON) tsI S(CC) tsI S (O F F) t Di agn o sis_S en se Ti mi ng.em f SEN SE EN AB LE IIS t t t IL t ON tON tsIS(DI A G) tsI S(LC) OF F tOFF OF F IN / OUT.OUTn tON(DE LA Y ) tOFF(DE LA Y ) tsIS(OFF) tsIS(ON) tdI S (O FF )

Data Sheet 55 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Diagnosis

9.6 Electrical Characteristics Diagnosis

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω Table 22 Electrical Characteri stics: Diagnosis - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SENSE Saturation Current IIS(SAT) 4.2 – 15 mA 1) RSENSE = 1.2 kΩ P_9.6.0.12 SENSE Leakage Current when Disabled IIS(OFF) –0 . 0 1 0 . 5 µ A IL ≥ IL(NOM) VIS = 0 V DCR.MUX = 110B P_9.6.0.2 SENSE Leakage Current when Enabled at TJ ≤ 85 °C IIS(EN)_85 –0 . 2 1µ A 1) TJ ≤ 85 °C DCR.MUX ≠ <110B,111B> See Figure 33 1) Not subject to production test - specified by design. P_9.6.0.3 SENSE Leakage Current when Enabled at TJ = 150 °C IIS(EN)_150 –12µ A TJ = 150 °C DCR.MUX ≠ <110B,111B> See Figure 33 P_9.6.0.11 SENSE Operative Range for kILIS Operation (VS - VIS) VSIS_k –0 . 5 1V 1) VS = 6 V INx = “high” or OUT.OUTn = 1B IL ≤ 2 * IL(NOM) P_9.6.0.6 Power Supply to IS Pin Clamping Voltage at TJ =- 4 0° C VSIS(CLAMP)_-40 33 36.5 42 V IIS = 1 mA TJ = -40 °C See Figure 20 P_9.6.0.9 Power Supply to IS Pin Clamping Voltage at TJ ≥25 °C VSIS(CLAMP)_25 35 38 44 V 2) IIS = 1 mA TJ ≥ 25 °C See Figure 20 2) Tested at TJ = 150°C. P_9.6.0.10

Data Sheet 56 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Diagnosis

9.6.1 Electrical Characteristics Diagnosis - SPOC™

Table 23 Electrical Characteristics: Diagnosis - Thresholds, Timings Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Switch Bypass Monitor Threshold SENSE Settling Time with Nominal Load Current Stable t sIS(ON) –82 0 µ s VS = 13.5 V IL = IL(NOM) DCR.MUX: 110B → 001B P_9.6.2.2 SENSE Settling Time with Small Load Current Stable tsIS(ON)_SLC ––6 0 µ s 2) VS = 13.5 V IL = IL(CAL)_OL DCR.MUX: 110B → 001B P_9.6.2.10 SENSE Settling Time after Channel Change tsIS(CC) ––2 0 µ s 1) VS = 13.5 V IL = IL(NOM) DCR.MUX: 001B → 010B 1) Production test for functionality within parameter limits. P_9.6.2.4 SENSE Settling Time after Channel Change with Small Load Current tsIS(CC)_SLC ––6 0 µ s 2) VS = 13.5 V Start channel: I L = IL(CAL) End channel: IL = IL(CAL)_OL DCR.MUX: 001B → 010B P_9.6.2.11 SENSE Disable Time tsIS(OFF) ––2 0 µ s 1) VS = 13.5 V IL = IL(NOM) DCR.MUX: 010B → 110B P_9.6.2.5 SENSE Settling Time after Load Change tsIS(LC) ––2 0 µ s 2) 2) Not subject to production test - specified by design. P_9.6.2.6 SENSE Settling Time after Load Change with Small Load Current t sIS(LC)_SLC – 250 400 µs 2) VS = 13.5 V from IL = IL(CAL) to IL = IL(CAL)_OL P_9.6.2.12 SENSE Disable Time after Channel Deactivation tdIS(OFF) ––2 0 µ s 2) P_9.6.2.7 SENSE Current in Sense Verification Mode IIS(VER) 400 500 600 µA DCR.MUX = 101B P_9.6.2.8

Data Sheet 57 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Diagnosis

9.7 Electrical Characteristics Diagnosis - Power Output Stages

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): 27W output: RL = 4.8 Ω

9.7.1 Diagnosis Power Output Stage 27 W Channels

Table 24 Electrical Characteristics: Di agnosis - 27 W channels - high range1) 1) Parameter valid only if KRC.KRCn = 0B. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Open Load Output Current at IIS = 4 µA IL(OL)_4u 271 5 m A 2) IIS = IIS(OL) = 4 µA P_9.7.16.1 Current Sense Ratio at IL = IL01 kILIS01 -65% 2000 +65% 2) IL01 = 10 mA P_9.7.16.3 Current Sense Ratio at IL = IL03 kILIS03 -60% 2000 +60% 2) IL03 = 30 mA 2) Parameter valid only if PCS.PCCn = 0B. P_9.7.16.5 Current Sense Ratio at IL = IL05 kILIS05 -55% 2000 +55% 2) IL05 = 100 mA P_9.7.16.7 Current Sense Ratio at IL = IL07 kILIS07 -45% 2000 +45% 2) IL07 = 250 mA P_9.7.16.9 Current Sense Ratio at IL = IL10 kILIS10 -24% 2000 +24% IL10 = 1 A P_9.7.16.12 Current Sense Ratio at IL = IL12 kILIS12 -8% 2000 +8% IL12 = 2 A P_9.7.16.14 Current Sense Ratio at IL = IL15 kILIS15 -8% 2000 +8% IL15 = 5.5 A P_9.7.16.17 SENSE Current Derating with Low Current Calibration ΔkILIS(OL) -30 0 +30 % 2)3) IL(CAL)_OL = IL03 IL(CAL)_OL_H = IL05 IL(CAL)_OL_L = IL01 TA(CAL) = 25 °C 3) Not subject to production test - specified by design. P_9.7.16.37 SENSE Current Derating with Nominal Current Calibration ΔkILIS(NOM) -9 0 +9 % 3) IL(CAL) = IL12 IL(CAL)_H = IL15 IL(CAL)_L = IL10 TA(CAL) = 25 °C P_9.7.16.38

Data Sheet 58 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Diagnosis Table 25 Electrical Characteristics: Diagnosis - 27 W channels - low range1) 1) Parameter valid only if KRC.KRCn = 1B. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Open Load Output Current at IIS = 4 µA IL(OL)_4u 0.5 3.2 6 mA 2)3) IIS = IIS(OL) = 4 µA P_9.7.16.18 Current Sense Ratio at IL = IL00 kILIS00 -65% 660 +65% 2)3) IL00 = 5 mA P_9.7.16.19 Current Sense Ratio at IL = IL01 kILIS01 -60% 660 +60% 2)3) IL01 = 10 mA 2) Parameter valid only if PCS.PCCn = 0B. 3) kILIS accuracy valid if 1 µs RC filter is placed at ADC input. P_9.7.16.20 Current Sense Ratio at IL = IL03 kILIS03 -55% 660 +55% 2)3) IL03 = 30 mA P_9.7.16.23 Current Sense Ratio at IL = IL05 kILIS05 -45% 660 +45% 2)3) IL05 = 100 mA P_9.7.16.26 Current Sense Ratio at IL = IL07 kILIS07 -30% 660 +30% 2)3) IL07 = 250 mA P_9.7.16.29 Current Sense Ratio at IL = IL08 kILIS08 -20% 660 +20% 3) IL08 = 450 mA P_9.7.16.31 Current Sense Ratio at IL = IL10 kILIS10 -8% 660 +8% 3) IL10 = 1 A P_9.7.16.33 Current Sense Ratio at IL = IL12 kILIS12 -8% 660 +8% 3) IL12 = 2 A P_9.7.16.35 SENSE Current Derating with Low Current Calibration ΔkILIS(OL) -30 0 +30 % 2)4) IL(CAL)_OL = IL01 IL(CAL)_OL_H = IL03 IL(CAL)_OL_L = IL00 TA(CAL) = 25 °C 4) Not subject to production test - specified by design. P_9.7.16.39 SENSE Current Derating with Nominal Current Calibration ΔkILIS(NOM) -9 0 +9 % 2)4) IL(CAL) = IL10 IL(CAL)_H = IL12 IL(CAL)_L = IL08 TA(CAL) = 25 °C P_9.7.16.40

Data Sheet 59 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a full duplex sy nchronous serial slave interf ace, which uses four lines: SO, SI, SCLK and CSN. Data is transfer red by the lines SI and SO at the rate given by SCLK. The falling edge of CSN indicates the beginning of an access. Data is sampled-in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo 8 counter ensures that data is taken only when a multiple of 8 bit has been transfer red. The interface provides daisy chain capability with modulo 8 bit SPI devices. Figure 36 Serial Peripheral Interface

10.1 SPI Signal Description

The system microcontroller selects the BTS71040-4ESE by means of the CSN pin. Whenever the pin is in “low” state, data transfer can take place. When CSN is in “high” state, any signals at the SCLK and SI pins are ignored and SO is forced into a “high impedance” state. CSN “high” to “low” Transition

• The requested information is tran sferred into the shift register.
• SO changes from “high impeda nce” state to “low” state. CSN “low” to “high” Transition
• Command decoding is only done, when after the falling edge of CSN exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of an incorrect SCLK count, the transmission error flag (STDDIAG.TER) is set and the command is ignored.
• Data from shift register is transferred into the addressed register. SCLK - Serial Clock This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (SO) shifts diagno stic information out on the rising edge of the serial clock. It is essential that th e SCLK pin is in “low” state whenever chip select CSN makes any transition, otherwise the command may not be accepted. SI - Serial Input Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 10.5 for further information. 6 5 4 3 2 1 LSB6 5 4 3 2 1MS BSO SI CS N SCLK tim e SPI _8bit .emf LSBMSB

Data Sheet 60 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI) SO Serial Output Data is shifted out serially at this pi n, the most significant bi t first. SO is in “high impedance” state until the CSN pin goes to “low” state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Chapter 10.5 for further information.

10.2 Daisy Chain Capability

The SPI of BTS71040-4ESE provides daisy chain capability for modulo 8 bit SPI device s. In this configuration several devices are activated by the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see Figure 37), in order to build a chain. The end of the chain is connected to the output and input of the master device, MO and MI respective ly. The master device prov ides the master clock MCLK which is connected to the SCLK line of each device in the chain. Figure 37 Daisy Chain Configuration In the SPI block of each devi ce, there is one shift register where each bi t from SI line is shifted in each SCLK. The bit is shifted out on SO pin. After eight SCLK cycles , the data transfer for one device is finished. In single chip configuration, the CSN line mu st turn “high” to make the device acknowledge the transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted into device 2. When using three devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCSN line must turn “high” (see Figure 38). Figure 38 Data Transfer in Daisy Chain Configuration SI device 1 SPI SCLK SO CSN SI device 2 SPI SCLK SO CSN SI device 3 SPI SCLK SO CSN MO MI MCSN MCLK SP I_Da isyCh ai n_1.e mf MI MO MC SN MCLK SI device 3 SI device 2 SI device 1 SO d evice 3 SO d evice 2 SO d evice 1 tim e SPI_D aisyChain _2.emf

Data Sheet 61 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10.3 Timing Diagrams

Figure 39 Timing Diagram SPI Access CSN SCLK SI tCSN(L E AD) tCSN(TD)tCSN(LA G ) tSCL K(H) tSCL K(L) tSCL K(P) SO tSO(V)tSO(EN) tSO(DIS ) SP I_Ti mi ng s.e mf VCSN(TH), max VCSN(TH), mi n VSCL K(TH), max VSCL K(TH), mi n VSI(TH), max VSI(TH), mi n VSO(H) VSO(L) tSI(SU) tSI(H)

Data Sheet 62 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10.4 Electrical Characteristics

VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VDD = 4.3 V, VS = 13.5 V, TJ = 25 °C Table 26 Electrical Characteristics Serial Peripheral Interface (SPI) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Timings Enable Lead Time (falling CSN to rising SCLK) t CSN(LEAD) 200 – – ns 1) 1) Not subject to production test - specified by design. P_10.4.0.1 Enable Lag Time (falling SCLK to rising CSN) tCSN(LAG) 200 – – ns 1) P_10.4.0.2 Transfer Delay Time (rising CSN to falling CSN) tCSN(TD) 500 – – ns 1) P_10.4.0.3 Output Enable Time (falling CSN to SO valid) tSO(EN) – 30 100 ns 1) CL(SO) = 50 pF P_10.4.0.4 Output Disable Time (rising CSN to SO tristate) tSO(DIS) – 30 100 ns 1) CL(SO) = 50 pF P_10.4.0.5 Serial Clock Frequency fSCLK 0–5M H z 1) P_10.4.0.6 Serial Clock Period tSCLK(P) 200 – – ns 1) P_10.4.0.7 Serial Clock “High” Time tSCLK(H) 90 – – ns 1) P_10.4.0.8 Serial Clock “Low” Time tSCLK(L) 90 – – ns 1) P_10.4.0.9 Data Setup Time (required Time SI to falling SCLK) tSI(SU) 20 – – ns 1) P_10.4.0.10 Data Hold Time (falling SCLK to SI) Output Data Valid Time with Capacitive Load tSO(V) ––6 0 n s 1) CL(SO) = 50 pF P_10.4.0.12

Data Sheet 63 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10.5 SPI Protocol

The relationship between SI and SO conten t during SPI communication is shown in Figure 40. SI line represents the frame sent from the µC and SO line is the answer provided by BTS71040-4ESE. The “previous response” means that the frame sent back depends on the command frame sent from the µC before. Figure 40 Relationship between SI and SO during SPI communication The SPI protocol provides th e answer to a command frame only with the next transmission triggered by the µC. The responses of write commands are deterministic and can be decoded as STDDIAG or WRNDIAG frame. For responses of read commands previous transmission has to be considered for decoding. More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows: Figure 41 Register content sent back to µC (a) Figure 42 Register content sent back to µC (b) There are 3 special situations where the frame sent back to the µC doesn't depend on the previous received frame:

• In case an error in transmission happened during th e previous frame (for instance, the clock pulses were not multiple of 8), shown in Figure 43
• When BTS71040-4ESE digital supp ly comes out of Power-On reset condition, as shown in Figure 44
• W h e n VS < VS(TP) and DCR.MUX ≠ 111B, as shown in Figure 45 SI SO SP I_SI 2SO .e mf frame A frame B frame C previous response response to frame A response to frame B SI SO SP I_RW se q_a.e mf write register A previous response read register Awrite register B STDDIAG register A content new command WRNDIAG SI SO SP I_RW se q_b.e mf write register A previous response read register A write reg ister B STDDIAG register A content new com mand WRNDIAG

Data Sheet 65 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI) Table 27 SPI Command Summary Requested Operation Frame sent to SPOC™ (SI pin) Frame received from SPOC™ (SO pin) with the next command Write OUT register DCR.SWR = xB 100dddddB where: “dddddB” = new OUT register content 00ddddddB - STDDIAG or 01ddddddB - WRNDIAG (Standard Diagnosis or Warning Diagnosis will be sent alternating) Read OUT register 0xxxaaaaB where: “aaaaB” = ADDR1 1) (“xB” = don't care) 1) ADDR0 and ADDR1 are defined according to Table 28. 100dddddB (“dddddB” = OUT register content) Read RCS register 0xxxaaaaB where: “aaaaB” = ADDR1 1) (“xB” = don't care) 10000dddB (“dddB” = RCS register content) Write Configuration registers 11aaddddB where: “aaB” = ADDR0 1) “ddddB” = new register content 00ddddddB - STDDIAG 01ddddddB - WRNDIAG (Standard Diagnosis or Warning Diagnosis will be sent alternating) Read Configuration registers 0xxxaaaaB where: “aaaaB” = ADDR1 1) (“xB” = don't care) 11aaddddB where: “aaB” = ADDR0 1) “ddddB” = register content Read Warning Diagnosis 0xxxx001B (“xB” = don't care) 0100ddddB - WRNDIAG (Warning Diagnosis) Read Standard Diagnosis 0xxxx010B (“xB” = don't care) 00ddddddB - STDDIAG (Standard Diagnosis) Read Error Diagnosis 0xxxx011B (“xB” = don't care) 0100ddddB - ERRDIAG (Error Diagnosis)

Data Sheet 66 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10.6 SPI Diagnosis Registers

10.6.1 Diagnosis Regist ers - Read Commands

10.6.2 Diagnosis Registers - Responses

N a m e 7 6 543210 D e f a u l t WRNDIAG 010 0 WRNDIAG.WRNn 40 H STDDIAG 00 STDDIAG .TER STDDIAG .CSV STDDIAG .LHI STDDIAG .SLP STDDIAG .SBM STDDIAG .VSMON 24H ERRDIAG 010 0 ERRDIAG.ERRn 40 H Field Bits Type Description STDDIAG.TER 5r Transmission Error 0B Previous transmission was successful (modulo 8 clocks received) 1B (default) Previous transmission failed or first transmission after Power-On reset or VS < VS(TP) if STDDIAG.VSMON = 1B STDDIAG.CSV 4r Checksum Verification1) 0B (default) Checksum verification was pass or no checksum calculated 1B Previous checksum verification was fail STDDIAG.LHI 3r Limp Home monitor 0B (default) “Low” level at pin LHI 1B “High” level at pin LHI STDDIAG.SLP 2r Sleep mode monitor 0B Device out of Sleep mode 1B (default) Device is in Sleep mode STDDIAG.SBM 1r Switch Bypass Monitor2) 0B VDS < VDS(SB) 1B VDS > VDS(SB) STDDIAG.VSMON 0r VS monitor 0B (default) VS always > VS(UV) since last Standard Diagnosis readout 1B VS < VS(UV) at least once or VS < VS(TP) if STDDIAG.TER = 1B

Data Sheet 67 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10.7 SPI Configuration Registers

The following table provides an overview on the registers available and the available address space. WRNDIAG.WRNn n = 3 to 0 3:0 r Warning Diagnosis of Channel n 0B (default) No failure 1B Overcurrent, Overtemperature or delta T detected ERRDIAG.ERRn n = 3 to 0 3:0 r Error Diagnosis of Channel n 0B (default) No failure 1B Channel latched OFF 1) See Chapter 10.8 for details on checksum calculation. 2) The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX). Table 28 Register Overview Name SWR 1) 1) DCR.SWR bit is only changed for write commands. For read commands it is used as part of the read address. RB ADDR0 ADDR1 Content OUT x/0 2) 2) For writing to OUT register DCR.SWR = x, for read address DCR.SWR = 0B. 0 (na) 0000 Output configuration RCS 1 0 (na) 1000 Restart counter status (read-only) SRC 1 0 (na) 1001 Slew Rate Contro l register (read-only) OCR 0 1 00 0100 Overcurrent thre shold configuration RCD 1 1 00 1100 Restart counter disable KRC 0 1 01 0101 KILIS range control PCS 1 1 01 1101 Parallel channel and Slew Rate control HWCR 0 1 10 0110 Hardware configuration ICS 1 1 10 1110 Input status & checksum input DCR x 1 11 x111 Diagnostic configuration and Swap bit Table 29 Configuration Registers - Write Commands RB-0 B i t 7 6 543210 N a m e S W R 7 R B 543210 OUT x1 0 0 OUT.OUTn 1) 1) OUT.OUT4 controls the logic state of EDO pin. Table 30 Configuration Registers - Write Commands RB-1 B i t 7654 3 2 1 0 N a m e S W R 7 R B A D D R 0 3210 OCR 0 1100 OCR.OCTn RCD 1 1100 RCD.RCDn KRC 0 1101 KRC.KRCn Field Bits Type Description

Data Sheet 68 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI) PCS 1 1101 PCS.PCCn PCS.CLCS PCS.SRCS HWCR 0 11100 HWCR.COL HWCR.RST HWCR.CLC ICS 1 1110 ICS.CSRn 1) DCR x 1111 DCR.SWR DCR.MUX 1) See Chapter 10.8 for details on checksum calculation. Table 31 Configuration Registers - Read Commands B i t 76543210 N a m e 7654 A D D R 1 OUT 0xxx0000 RCS 0xxx1000 SRC 0xxx1001 OCR 0xxx0100 RCD 0xxx1100 KRC 0xxx0101 PCS 0xxx1101 HWCR 0xxx0110 ICS 0xxx1110 DCR 0xxxx111 Table 30 Configuration Registers - Write Commands RB-1 B i t 7654 3 2 1 0 N a m e S W R 7 R B A D D R 0 3210

Data Sheet 69 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI) Table 32 Configuration Registers - Responses B i t 7 6 5 4 3210 N a m e 7654 3 2 1 0 D e f a u l t OUT 100 OUT.OUTn 1) 1) OUT.OUT4 controls the logic state of EDO pin. 80H RCS 10000 RCS.RCSn 80H SRC 1001 SRC.SRCn 90 H OCR 1100 OCR.OCTn C0 H RCD 1100 RCD.RCDn C0 H KRC 1101 KRC.KRCn D0 H PCS 1101 PCS.PCCn 00D 0 H HWCR 11100 HWCR.COL HWCR.SLP 0E 2 H ICS 11100 0 ICS.INSTn E0 H DCR 1111 DCR.SWR DCR.MUX F7H Field Bits Type Description RB 6r w Register Bank 0B (default) Read/write to OUT/RCS register 1B Read/write to other registers OUT.OUTn n = 4 to 0 4:0 rw Output Control Register of Channel n 0B (default) channel is OFF 1B Channel is ON RCS.RCSn n = 2 to 0 2:0 r Restart Counter Status of Channel selected via MUX 000B (default) Restart counter value = 0 001B Restart counter value = 1 010B Restart counter value = 2 011B Restart counter value = 3 100B Restart counter value = 4 101B Restart counter value = 5 110B Restart counter value = 6 111B Restart counter value = 7 SRC.SRCn n = 3 to 0 3:0 r Set Slew Rate control for Channel n (read only) 0B (default) Normal Slew Rate 1B Adjusted Slew Rate OCR.OCTn n = 3 to 0 3:0 rw Set Overcurrent Level for Channel n 0B (default) High level of overcurrent threshold IL(OVL0) 1B Low level of overcurrent threshold IL(OVL2) RCD.RCDn n = 3 to 0 3:0 rw Set Restart Strategy for Channel n 0B (default) Automatic restart mode 1B Latch mode KRC.KRCn n = 3 to 0 3:0 rw Set Current Sense Ratio Range for Channel n 0B (default) High range of current sense ratio 1B Low range of current sense ratio

Data Sheet 70 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI) PCS.SRCS 0w Set Slew Rate control for Channel selected by DCR.MUX 0B (default) Normal Slew Rate 1B Adjusted Slew Rate PCS.CLCS 1w Clear Restart Counters and Latches for Channel selected by DCR.MUX 0B (default) Restart counters and latches are untouched 1B Restart counters and latches are reset PCS.PCCn n = 1 to 0 3:2 rw Parallel Channel Configuration 00B (default) Channels are operating independent 01B OUT0 + OUT3 are in parallel configuration 10B OUT1 + OUT2 are in parallel configuration 11B OUT0 + OUT3 and OUT1 + OUT2 are in parallel configuration HWCR.CLC 0w Clear Restart Counters and Latches 0B (default) Restart counters and latches are untouched 1B Restart counters and latches are reset for all channels HWCR.RST 1w Reset Command 0B (default) Normal operation 1B Execute reset command HWCR.SLP 1r Sleep Mode 0B Device is awake 1B (default) DCR.MUX = 111B HWCR.COL 2r w Input Combinatorial Logic Configuration 0B (default) Input signal OR-combined with according OUT register bit1) 1B Input signal AND-combined with according OUT register bit ICS.CSRn n = 3 to 0 3:0 w Checksum Input Register 4 bit Checksum is written to this register ICS.INSTn n = 1 to 0 1:0 r Input Status Monitor Channel n 0B (default) Input signal is “low” 1B Input signal is “high” Field Bits Type Description

Data Sheet 71 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI) DCR.MUX 2:0 rw Set Current Sense Multiplexer Configuration in OFF state 000B IS pin is “high impedance” 001B IS pin is “high impedance” 010B IS pin is “high impedance” 011B IS pin is “high impedance” 100B Diagnosis enable of external driver activated (EDD set to “high”) 101B Current sense verification mode 110B IS pin is “high impedance” 111B Sleep mode (IS pin is “high impedance”) Set Multiplexer Configuration in ON state 000B Current sense of channel 0 is routed to IS pin 001B Current sense of channel 1 is routed to IS pin 010B Current sense of channel 2 is routed to IS pin 011B Current sense of channel 3 is routed to IS pin 100B Diagnosis enable of external driver activated (EDD set to “high”) 101B Current sense verification mode 110B IS pin is “high impedance” 111B Sleep mode (IS pin is “high impedance”) DCR.SWR 3r w Switch Register 0B (default) Registers OUT, OCR, KRC, HWCR and DCR can be written 1B Registers OUT, RCD, PCS, ICS and DCR can be written 1) In Limp Home mode (LHI pin set to “high”) the combinatorial logic is switched to OR-mode. Field Bits Type Description

Data Sheet 72 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10.8 SPI Checksum Verification

BTS71040-4ESE offers a simple parity check to iden tify unexpected content or unintended changes of configuration registers. For the chec ksum calculation a subset of the co nfiguration bits is used, which is expected not to be changed periodically. The checksum calculation is an easy column parity calculation. The configuration bits which are used for the calculation are shown in Table 34. The SPI master writes the result to ICS.CSRn. After the 4bit checksum is written to ICS register, the device is doing once the comparison and the result can be read within the next STDDIAG frame in the bit STDDIAG.CSV. The STDDIAG.CSV bit is cleared with the next STDDIAG readout. In case the ICS register is not written, the checksum comparison is disabled and the bit STDDIAG.CSV = 0B. If Limp Home mode is entered after ICS.CSRn is written but before STDDIAG.CSV is read, the checksum verification is not valid. Same applies in case STDDIAG.TER and STDDIAG.VSMON are set to 1B. In these cases checksum verification result shall be discarded. Table 33 Conventions fo r parity calculation Number of ‘1’ in a column Result wi th EVEN-parity Result with ODD-parity EVEN 0 1 ODD 1 0 Table 34 Checksum ca lculation bit matrix N a m e 3210 OCR OCT3 OCT2 OCT1 OCT0 RCD RCD3 RCD2 RCD1 RCD0 KRC KRC3 KRC2 KRC1 KRC0 SRC SRC3 SRC2 SRC1 SRC0 HWCR/PCS 0 COL PCC PCC0 Parity even odd even odd ICS CSR3 CSR2 CSR1 CSR0 Table 35 Checksum calculat ion bit matrix example N a m e 3210 OCR 0100 RCD 1000 KRC 0110 SRC 0010 HWCR/PCS 0000 Parity even odd even odd ICS 1101

Data Sheet 73 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Serial Peripheral Interface (SPI)

10.9 SPI command quick list

A summary of the most used SPI commands (read and write operations) is shown in Table 154. Table 36 SPI command quick list Name “read” command 1) 1) x = don’t care bits. “write” command 2) 2) d = data bits. SWR 3) 3) DCR.SWR bit needs to be set for writing a register. For reading a register the DCR.SWR bit is part of the read address. OUT 0xxx0000B 10ddddddB x RCS 0xxx1000B SRC 0xxx1001B OCR 0xxx0100B 1100ddddB 0 RCD 0xxx1100B 1100ddddB 1 KRC 0xxx0101B 1101ddddB 0 PCS 0xxx1101B 1101ddddB 1 HWCR 0xxx0110B 1110ddddB 0 ICS 0xxx1110B 1110ddddB 1 DCR 0xxxx111B 1111ddddB x WRNDIAG 0xxx0001B STDDIAG 0xxx0010B ERRDIAG 0xxx0011B

Data Sheet 74 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2

Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

11.1 Application setup - SPOC™

Figure 46 Application Diagram Note: This is a very simplified example of an applicatio n circuit. The function must be verified in the real application. SPI VS OUT3 OUT2 OUT1 OUT0 27W 27W 27W 27W External Driver Control IS SO SCLK SI CSN GND LHI RLHI EDD EDO VDD GND VDD CVD D µC e.g. XC2267 VSS VCC VBAT AD RVD D SPI RSO RSI RSC LK RCS N RIN RIN GPIO I N1 IN 0 CVS 1 PRO FETIN OUT VS GND DEN IS CAD C DZ1 RED O RED D DZ2CVS 2 Ap pli catio n_040 _ED .e mf COUT COUT CVS 1 RPR O T Fa il-safe Co ntro l Fa il-safe Co ntro l RIN logic supply

Data Sheet 75 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2

11.2 External Components

Note: The suggested component values above are de termined for typical applications. Based on the application circuit and the used components connected to BTS71040-4ESE, it could be necessary to adjust the recommended values to stay below the maximum ratings for all components (e.g. reverse battery, transients on battery, etc.).

11.3 Further Application Information

• Please contact us for information regarding the Pin FMEA
• For further information you may contact http://www.infineon.com/ Table 37 Suggested Component values Reference Value Purpose RVDD 470 Ω Device logic protection RIN 4.7 kΩ Protection of the microcontroller during overvoltage, reverse polarity Guarantee BTS71040-4ESE output OFF during Loss of Ground RPROT 4.7 kΩ Protection resistor for overvoltage, reverse polarity and Loss of Ground Value to be tuned with µC specification RSENSE 1.2 kΩ Sense resistor RADC 1.0 kΩ µC-ADC voltage spikes filtering RCSN 1.2 kΩ Protection of the µC during overvoltage and reverse polarity RSCLK 1.2 kΩ Protection of the µC during overvoltage and reverse polarity RSO 1.2 kΩ Protection of the µC during overvoltage and reverse polarity RSI 1.2 kΩ Protection of the µC during overvoltage and reverse polarity RLHI 4.7 kΩ Protection of the µC during overvoltage and reverse polarity REDO 4.7 kΩ Protection of the device during overvoltage, reverse polarity of external driver REDD 4.7 kΩ Protection of the device during overvoltage, reverse polarity of external driver CADC 1.0 nF µC-ADC voltage spikes filtering CVDD 470 nF Digital supply voltage spikes filter ing and for improved robustness against battery voltage transients CVS1 100 nF Battery voltage spikes filtering CVS2 100 nF Battery voltage spikes filtering COUT 10 nF For improved electromag netic compatibility (EMC) RGND 47 Ω (1/16 W) Ground voltage spikes filtering for improved robustness against battery voltage transients T1 BC 807 Switch the battery voltage for Open Load in OFF diagnosis RPD 47 kΩ Output polarization (pull-down) Ensure polarization of BTS71040-4ESE output to distinguish between Open Load and Short to VS in OFF diagnosis ROL 1.5 kΩ Output polarization (pull-up) Ensure polarization of BTS71040-4ESE output during Open Load in OFF diagnosis

Data Sheet 76 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Package Outlines Figure 47 PG-TSDSO-24 (Thin (Slim) Dual Small Outline 24 pins) Package drawing s 0$; 6($7,1* 3/$1( &23/$1$5,7< s 67$1'2)) s s s [ ' *$8*( 3/$1( rr %27720 9,(: s ,1'(; 0$5.,1* s [ $% & s

Data Sheet 77 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Package Outlines Figure 48 PG-TSDSO-24 (Thin (Slim) Dual Small Outline 24 pins) Package pads and stencil Green Product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages FRSSHU VROGHU PDVN VWHQFLO DSHUWXUHV

Data Sheet 78 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2

Revision History

Table 38 BTS71040-4ESE - List of changes Revision Changes 1.00, 2018-10-16 Data Sheet available

Data Sheet 79 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2 Table of Contents

Data Sheet 80 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2

Data Sheet 81 Rev. 1.00 2018-10-16 BTS71040-4ESE SPOC™+2

All referenced product or service names and trademarks are the property of their respective owners. Edition 2018-10-16 Published by Infineon Technologies AG

81726 Munich, Germany

© 2018 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. Please read the Important Notice and Warnings at the end of this document