BTS7080-2EPA

BTS7080-2EPA INFINEON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 62

Technical content

Data Sheet Rev. 1.06 www.infineon.com 1 2019-10-30 BTS7080-2EPA

1 Overview

• Suitable for resistive, induc tive and capacitive loads
• Replaces electromechanical rela ys, fuses and discrete circuits
• Driving capability suitable for 3 A lo ads and high inrush current loads such as P21W lamps or equivalent electronic loads (e.g. LED modules) Figure 1 BTS7080-2EPA Application Di agram. Further information in Chapter 10 PROFET™+2 12V 2x 80 m Ω Smart High-Side Power Switch Package PG-TSDSO-14 Marking 7080-2A PROFET™+2 12V Ap p_2CH_INTDI O_CVG_LO.emf Microcontroller VDD DZ2 CVS2 Logic Supply Logic GND Power GND VSS GPIO RIN IN0 GPIO RIN IN1 GPIO RDEN DEN GPIO RDS EL DSEL CVS GND RGN D CVSGND ROL RPD COUT0 ZWIRE DZ1 ISADC RADC RIS_PROT RSENSECSENSE ZWIRE COUT1 Optional Optional Chassis GND VBAT Optional ZWIRE ZLOAD* ZLOAD* *See Chapter 1 „Potential Applications“ VS OUT0 OUT1

Data Sheet 2 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Overview Basic Features

• High-Side Switch with Diagn osis and Embedded Protection
• Part of PROFET™+2 12V Family
• ReverseON for low power dissipation in Reverse Polarity
• Switch ON capability while Inve rse Current condition (InverseON)
• Green Product (RoHS compliant) Protection Features
• Absolute and dynamic temperature li mitation with controlled restart
• Overcurrent protection (tripping) with Intelligent Restart Control
• Undervoltage shutdown
• Overvoltage protection with external components Diagnostic Features
• Proportional load current sense
• Open Load in ON and OFF state
• Short circuit to ground and battery Product Validation Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.

Description

The BTS7080-2EPA is a Smart High-Sid e Power Switch, providing protecti on functions and diagnosis. The device is integrated in SMART7 technology. Table 1 Product Summary Parameter Symbol Values Minimum Operating voltage (at switch ON) V S(OP) 4.1 V Minimum Operating voltage (cranking) VS(UV) 3.1 V Maximum Operating voltage VS 28 V Minimum Overvoltage protection (TJ ≥ 25 °C) VDS(CLAMP)_25 35 V Maximum current in Sleep mode (TJ ≤ 85 °C) IVS(SLEEP)_85 0.5 µA Maximum operative current IGND(ACTIVE) 4 mA Maximum ON-state resistance (TJ = 150 °C) RDS(ON)_150 39.6 mΩ Nominal load current (TA = 85 °C) IL(NOM) 3 A Typical current sense ratio at IL = IL(NOM) kILIS 1800

Data Sheet 3 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Block Diagram and Terms

2 Block Diagram and Terms

2.1 Block Diagram

Figure 2 Block Diagram of BTS7080-2EPA IN0 ESD Protection Input Logic IS DEN DSEL IN1 Internal Power Supply Bloc k_PR OFET2ch_REVON.emf GND Circuitry Supply Voltage Mo nitoring Overvoltage Protection Intelligent Restart Control SENSE Output VS GND OUT1 OUT0 Internal Reverse Polarity Protection Channel 1 T dr iver logic Gate Control Chargepump Load Current Sense Overtemperat ure Overvoltage Clamping Overcurrent Protection Output Voltage Limitation Voltage Sensor ReverseON InverseON Channel 0 T Driver Logic Gate Control Chargepump Overtemperature Overvoltage Clamping Overcurrent Protection Output Voltage Limitation Voltage Sensor ReverseO N InverseON Load Current Sense

Data Sheet 4 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Block Diagram and Terms

2.2 Terms

Figure 3 shows all terms used in this data sheet, with associated convention for positive values. Figure 3 Voltage and Current Convention IINn IDEN IIS VS IGND ILn IDSEL INn DEN DSEL IS GND VS OUTn VINn VDEN VDSEL VIS VOUTn VDSn IVS Te r ms_PRO F ET.e mf VSIS

Data Sheet 5 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 4 Pin Configuration VS GND OUT0 IN0 DEN IS DSEL IN1 n.c. OUT0 OUT0 n.c. OUT1 OUT1 OUT1 Pi nO ut_PRO FET2ch.emf ex pos ed pad (bo tto m)

Data Sheet 6 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Pin Configuration

3.2 Pin Definitions and Functions

(exposed pad) Supply Voltage Battery voltage 1G N D Ground Signal ground 2, 6 INn Input Channel n Digital signal to switch ON channel n (“high” active) If not used: connect with a 10 kΩ resistor either to GND pin or to module ground 3D E N Diagnostic Enable Digital signal to enable device diagnosis (“high” active) and to clear the protection counter of channel selected with DSEL pin If not used: connect with a 10 kΩ resistor either to GND pin or to module ground 4I S SENSE current output Analog/digital signal for diagnosis If not used: left open 5D S E L Diagnosis Selection Digital signal to select one channel to perform ON and OFF state diagnosis (“high” active) If not used: connect with a 10 kΩ resistor either to GND pin or to module ground 7, 11 n.c. Not connected, internally not bonded 8-10, 12- OUTn Output n Protected high-side power output channel n 1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow.

Data Sheet 7 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings - General

Table 3 Absolute Maximum Ratings 1) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply pins Power Supply Voltage VS -0.3 – 28 V – P_4.1.0.1 Load Dump Voltage VBAT(LD) – – 35 V suppressed Load Dump acc. to ISO16750-2 (2010). R i = 2 Ω P_4.1.0.3 Supply Voltage for Short Circuit Protection VBAT(SC) 0–2 4 V S e t u p a c c . t o AEC-Q100-012 P_4.1.0.25 Reverse Polarity Voltage - VBAT(REV) ––1 6 V t ≤ 2 min TA = +25 °C Setup as described in Chapter 10 P_4.1.0.5 Current through GND Pin I GND -50 – 50 mA RGND according to Chapter 10 P_4.1.0.9 Logic & control pins (Digital Input = DI) DI = INn, DEN, DSEL Current through DI Pin IDI -1 – 2 mA 2) P_4.1.0.14 Current through DI Pin Reverse Battery Condition IDI(REV) -1 – 10 mA 2) t ≤ 2 min P_4.1.0.36 IS pin Voltage at IS Pin VIS -1.5 – VS V IIS = 10 μA P_4.1.0.16 Current through IS Pin IIS -25 – IIS(SAT),M AX mA – P_4.1.0.18 Temperatures Junction Temperature TJ -40 – 150 °C – P_4.1.0.19 Storage Temperature TSTG -55 – 150 °C – P_4.1.0.20 ESD Susceptibility

Data Sheet 8 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V General Product Characteristics Notes 1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

4.2 Absolute Maximum Ratings - Power Stages

4.2.1 Power Stage - 80 m Ω

ESD Susceptibility all Pins (HBM) VESD(HBM) -2 – 2 kV HBM 3) P_4.1.0.21 ESD Susceptibility OUTn vs GND and VS connected (HBM) VESD(HBM)_OU T ESD Susceptibility all Pins (CDM) VESD(CDM) -500 – 500 V CDM 4) P_4.1.0.23 ESD Susceptibility Corner Pins (CDM) (pins 1, 7, 8, 14) V ESD(CDM)_CR N -750 – 750 V CDM 4) P_4.1.0.24 1) Not subject to production test - specified by design. 2) Maximum VDI to be considered for Latch-Up tests: 5.5 V. 3) ESD susceptibility, Human Body Mode l “HBM”, according to AEC Q100-002. 4) ESD susceptibility, Charged Device Mo del “CDM”, according to AEC Q100-011. Table 4 Absolute Maximum Ratings 1) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Maximum Energy Dissipation Single Pulse EAS ––3 6 m J IL = 2*IL(NOM) TJ(0) = 150 °C VS = 28 V P_4.2.7.1 Table 3 Absolute Maximum Ratings 1) (continued) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 9 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V General Product Characteristics

4.3 Functional Range

Note: Within the functional or operatin g range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics tables. Maximum Energy Dissipation Repetitive Pulse EAR ––1 3 m J IL = IL(NOM) TJ(0) = 85 °C VS = 13.5 V 1M cycles P_4.2.7.2 Load Current | IL|– – IL(OVL),M AX A– P_4.2.7.3 1) Not subject to production test - specified by design. Table 5 Functional Range - Supply Voltage and Temperature 1) 1) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply Voltage Range for Normal Operation Lower Extended Supply Voltage Range for Operation VS(EXT,LOW) 3.1 – 6 V 2)3) (parameter deviations possible) 2) In case of VS voltage decreasing: VS(EXT,LOW),MIN =3 . 1V . I n c a s e o f VS voltage increasing: VS(EXT,LOW),MIN =4 . 1V . P_4.3.0.2 Supply Voltage Range reached after Overload Protection activation leading to “Undervoltage on V S” condition VS(EXT,CVG) –– 3 . 1 V CVSGND is required when the Overload Protection is triggered (see Chapter 8.2) and the observed number of retries is different from what specified in Chapter 8.3.1 P_4.3.0.7 Upper Extended Supply Voltage Range for Operation V S(EXT,UP) 18 – 28 V 3) (parameter deviations possible) 3) Protection functions still operative. P_4.3.0.3 Junction Temperature TJ -40 – 150 °C – P_4.3.0.5 Table 4 Absolute Maximum Ratings 1) (continued) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 10 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V General Product Characteristics

4.4 Thermal Resistance

Note: This thermal data was generated in accord ance with JEDEC JESD51 standards. For more information, go to www.jedec.org.

4.4.1 PCB Setup

Figure 5 1s0p PCB Cross Section Figure 6 2s2p PCB Cross Section Table 6 Thermal Resistance 1) 1) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Thermal Characterization Parameter Junction-Top ΨJTOP –2 . 4 4 . 1 K / W 2) 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C, PDISSIPATION = 1 W. P_4.4.0.1 Thermal Resistance Junction-to-Case RthJC –1 . 6 2 . 7 K / W 2) simulated at exposed pad P_4.4.0.2 Thermal Resistance Junction-to-Ambient RthJA – 31.8 – K/W 2) P_4.4.0.3 70 µm modeled (traces, cooling area) 1,5 mm 70 µm, 5% metalization* PC B_Z th_1s0p.emf *: means percentual Cu metalization on each layer 70 µm modeled (traces) 35 µm, 90% metalization* 1,5 mm 70 µm, 5% metalization* PCB_Zth_2s2p.emf 35 µm, 90% metalization* *: means percentual Cu metalization on each layer

Data Sheet 11 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V General Product Characteristics Figure 7 PCB setup for thermal simulations Figure 8 Thermal vias on PCB for 2s2p PCB setup

4.4.2 Thermal Impedance

PCB_sim_setup_TSDSO14.emf PCB 1s0p + 600 mm2 cooling PCB 2s2p / 1s0p footprint PCB_ 2s2p_vi as_T S DS O14. em f

Data Sheet 13 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Logic Pins

5 Logic Pins

The device has 4 digital pins for direct control.

5.1 Input Pins (INn)

The input pins IN0, IN1 activate the corresponding output channel. The input circuitry is compatible with 3.3V and 5V microcontroller (see Chapter 10 for the complete application setup overview). The electrical equivalent of the input circuitry is shown in Figure 11. In case the pin is not used, it must be connected with a 10 kΩ resistor either to GND pin or to module ground. Figure 11 Input circuitry The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always higher than the voltage needed to ensure a “low” state. Figure 12 Input Threshold voltages and hysteresis GND IN IGND IDI VDI Input_IN_INTDIO.emf VS VS(CLAMP) RGND IDIESD VDI (CLAM P) Input _V DITH_ 2.emf VDI (TH ), MAX VDI (HYS) t VDI VDI (TH ) ,MIN I nternal channel activation signal t 0 x 1 x 0 VDI (T H)

Data Sheet 14 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Logic Pins

5.2 Diagnosis Pin

The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is set to “high”, the diagnosis is enabled (see Chapter 9.2 for more details). When it is set to “low”, the diagnosis is disabled (IS pin is set to high impedance). The Diagnosis Selection (DSEL) pin selects the channel where diagnosis is performed (see Chapter 9.1.1). The transition from “high” to “low” of DEN pin clears the protection latc h of the channel selected with DSEL pin depending on the logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal structure of diagnosis pins is the same as the one of input pins. See Figure 11 for more details.

5.3 Electrical Characteristics Logic Pins

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Digital Input (DI) pins = IN, DEN, DSEL Table 7 Electrical Characteri stics: Logic Pins - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Digital Input Voltage Threshold VDI(TH) 0.8 1.3 2 V See Figure 11 and Figure 12 P_5.4.0.1 Digital Input Clamping Voltage VDI(CLAMP1) –7–V 1) IDI = 1 mA See Figure 11 and Figure 12 1) Not subject to production test - specified by design. P_5.4.0.2 Digital Input Clamping Voltage VDI(CLAMP2) 6.5 7.5 8.5 V IDI = 2 mA See Figure 11 and Figure 12 P_5.4.0.3 Digital Input Hysteresis VDI(HYS) –0 . 2 5 –V 1) See Figure 11 and Figure 12 P_5.4.0.4 Digital Input Current (“high”) IDI(H) 21 0 2 5 µ A VDI = 2 V See Figure 11 and Figure 12 P_5.4.0.5 Digital Input Current (“low”) IDI(L) 21 0 2 5 µ A VDI = 0.8 V See Figure 11 and Figure 12 P_5.4.0.6

Data Sheet 15 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Supply

6 Power Supply

The BTS7080-2EPA is supplied by VS, which is used for the internal logic as well as supply for the power output stages. VS has an undervoltage detection circuit, which prevents the activation of the power output stages and diagnosis in case the applied voltage is below the undervoltage threshold.

6.1 Operation Modes

BTS7080-2EPA has the following operation modes:

• S l e e p m o d e
• A c t i v e m o d e
• S t a n d - b y m o d e The transition between operation modes is determined according to these variables:
• Logic level at INn pins
• Logic level at DEN pin The state diagram including the possible transitions is shown in Figure 13. The behavior of BTS7080-2EPA as well as some parameters may change in dependence from the operation mode of the device. Furthermore, due to the undervoltage detection circuitry which monitors V S supply voltage, some changes within the same operation mode can be seen accordingly. There are three parameters describing each operation mode of BTS7080-2EPA:
• Status of the output channels
• Status of the diagnosis
• Current consumption at VS pin (measured by I VS in Sleep mode, IGND in all other operative modes) Table 8 shows the correlation between operation modes, VS supply voltage, and the state of the most important functions (channel status, diagnosis). Figure 13 Operation Mode State Diagram Po wer Su p ply_O pMo d e_PR O FET .emf Sleep Active IN = „hig h“ IN = „low“ & DEN = „high“ Stand-by IN = „low “ & DEN = „low“ Power-up IN = „low“ & DEN = „high“ IN = „low “ & DEN = „low“ V S > VS(OP) Un supplied IN = „high“ DEN = „high“ DEN = „low“

Data Sheet 16 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Supply

6.1.1 Unsupplied

In this state, the device is either unsupplied (no voltage applied to VS pin) or the supply voltage is below the undervoltage threshold.

6.1.2 Power-up

The Power-up condition is ente red when the supply voltage ( VS) is applied to the device. The supply is rising until it is above the undervoltage threshold VS(OP) therefore the internal Power-On signals are set.

6.1.3 Sleep mode

The device is in Sleep mode when all Digital Input pins (INn, DEN, DSEL) are set to “low”. When BTS7080-2EPA is in Sleep mode, all outputs are OFF. The current consumption is minimum (see parameter IVS(SLEEP)). No Overtemperature or Overload protecti on mechanism is active when the de vice is in Sleep mode. The device can go in Sleep mode only if the protection is not active (counter = 0, see Chapter 8.3.1 for further details).

6.1.4 Stand-by mode

The device is in Stand-by mode as long as DEN pin is set to “high” while input pins are set to “low”. All channels are OFF therefore only Open Load in OFF diagnosis is possible. Depending on the load condition, either a fault current IIS(FAULT) or an Open Load in OFF current IIS(OLOFF) may be present at IS pin. In such situation, the current consumption of the device is increased.

6.1.5 Active mode

Active mode is the normal operation mode of BTS7080-2EPA. The device enters Active mode as soon as one IN pin is set to “high”. Device current consumption is specified with IGND(ACTIVE) (measured at GND pin because the current at VS pin includes the lo ad current). Overload, Overtemperat ure and Overvoltage protections are active. Diagnosis is available.

6.2 Undervoltage on VS

Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active mode) and the supply voltage drops be low the undervoltage threshold VS(UV), the internal logic switches OFF the output channels. As soon as the supply voltage VS is above the operative threshold VS(OP), the channels having the corresponding input pin set to “high” are switched ON a gain. The restart is delayed with a time tDELAY(UV) which protects the device in case the undervoltage co ndition is caused by a short circui t event (according to AEC-Q100-012), as shown in Figure 14. Table 8 Device function in relation to operation modes and VS voltage Operative Mode Function VS in undervoltage VS not in undervoltage Sleep Channels OFF OFF Diagnosis OFF OFF Active Channels OFF available Diagnosis OFF available in OFF and ON states Stand-by Channels OFF OFF Diagnosis OFF available in OFF state

Data Sheet 17 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Supply If the device is in Sleep mode and one input is set to “high”, the corresponding channel is switched ON if VS > VS(OP) without waiting for tDELAY(UV). Figure 14 VS undervoltage behavior Po werS upp ly_UVRVS.emf t VS(OP) VS(UV) VS(HYS) t VOUT VS tDELAY (UV) Channel activa tion signal t

Data Sheet 18 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Supply

6.3 Electrical Characteristics Power Supply

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω

6.4 Electrical Characteristics Power Supply - Product Specific

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω

6.4.1 BTS7080-2EPA

Table 9 Electrical Characteri stics: Power Supply - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. VS pin Power Supply Undervoltage Shutdown VS(UV) 1.8 2.3 3.1 V VS decreasing IN = “high” From VDS ≤ 0.5 V to VDS = VS See Figure 14 P_6.4.0.1 Power Supply Minimum Operating Voltage VS(OP) 2.0 3.0 4.1 V VS increasing IN = “high” From VDS = VS to VDS ≤0.5 V See Figure 14 P_6.4.0.3 Power Supply Undervoltage Shutdown Hysteresis VS(HYS) –0 . 7 –V 1) VS(OP) - VS(UV) See Figure 14 1) Not subject to production test - specified by design. P_6.4.0.6 Power Supply Undervoltage Recovery Time tDELAY(UV) 2.5 5 7.5 ms d VS/dt ≤0.5 V/µs VS ≥-1 V See Figure 14 P_6.4.0.7 Breakdown Voltage between GND and VS Pins in Reverse Battery -VS(REV) 16 – 30 V 1) IGND(REV) = 7 mA TJ = 150 °C P_6.4.0.9

Data Sheet 19 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Supply Table 10 Electrical Characterist ics: Power Supply BTS7080-2EPA Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Power Supply Current Consumption in Sleep Mode with Loads at TJ ≤85 °C IVS(SLEEP)_85 –0 . 0 3 0 . 5 µ A 1) VS = 18 V VOUT = 0 V IN = DEN = “low” T J ≤ 85 °C 1) Not subject to production test - specified by design. P_6.5.7.1 Power Supply Current Consumption in Sleep Mode with Loads at TJ = 150 °C IVS(SLEEP)_150 –31 0 µ A VS = 18 V VOUT = 0 V IN = DEN = “low” TJ = 150 °C P_6.5.7.2 Operating Current in Active Mode (all Channels ON) IGND(ACTIVE) –34m A VS = 18 V IN = DEN = “high” P_6.5.7.3 Operating Current in Stand- by Mode IGND(STBY) –1 . 2 1 . 8 m A VS = 18 V IN = “low” DEN = “high” P_6.5.7.5

Data Sheet 20 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages

7 Power Stages

The high-side power stages are built using a N-channel vertical Power MOSFET with charge pump.

7.1 Output ON-State Resistance

The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 15 shows the variation of RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured at TJ = 150 °C. Figure 15 RDS(ON) variation factor The behavior in Reverse Polarity is described in Chapter 8.4.1.

7.2 Switching loads

7.2.1 Switching Resistive Loads

When switching resistive loads, the switching times and slew rates shown in Figure 16 can be considered. The switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 RDS(ON) variation factor Junction Temperature (°C) RDS(ON) variation over TJ Typical Reference value: "2" = RDS(ON),MAX @ 150 °C

Data Sheet 21 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages Figure 16 Switching a Resistive Load

7.2.2 Switching Inductive Loads

When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to overvoltage, a voltage clamp mechanism is implem ented. The clamping structure limits the negative output voltage so that VDS = VDS(CLAMP). Figure 17 shows a concept drawing of the implementation. The clamping structure protects the device in all operation modes listed in Chapter 6.1. Figure 17 Output Clamp concept IN t VOUT VIN(TH) (dV/dt)ON VIN(HYS) PDMOS t t Power St age_Swi tch Res.emf EON EOFF tON tON(DELAY) tOFF(DELAY) -(dV/dt)OFF tOFF 10% of VS 90% of VS 70% of VS 30% of VS 30% of VS 70% of VS PowerStage_Clamp_INTDIO.emf High-sid e Channel VS RL VOU Tn I L VDS(CLAM P) IL VS OUTn VDS GND VS(CLAM P) IS VSI S(CLAM P) RSE N SE RGND

Data Sheet 22 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages During demagnetization of inductive loads, energy has to be dissipated in BTS7080-2EPA. The energy can be calculated with Equation (7.1): (7.1) The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design of the component.

7.2.3 Output Voltage Limitation

To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while the channel is diagnosed (DEN pin set to “high”, channel selected with DSEL pins - see Figure 18) bringing VDS equal or lower than VDS(SLC), the output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC) even for very small output currents. The VDS increase allows the current sensing circuitry to work more efficiently, providing better kILIS accuracy for output current in the low range. Figure 18 Output Voltage Limitati on activation during diagnosis

7.3 Advanced Switching Characteristics

7.3.1 Inverse Current behavior

When VOUT > VS, a current IINV flows into the power output transistor (see Figure 19). This condition is known as “Inverse Current”. If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses therefore an increase of overall device temperature. This may lead to a switch OFF of unaffected channels due to Overtemperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output stage is comparable to normal operation in RDS(ON). During Inverse Current condition, the channel remains in ON or OFF state as long as IINV < IL(INV). If one channel has inverse current applied, the ne ighbor channel is not influenced, meaning that switching ON and OFF timings, protection (Overcurrent, Overtemperature) and current sensing (kILIS) are still within specified limits. EV DS CLAMP() VS VDS CLAMP()– RL RL I⋅ L æö IL+ln⋅ L RL IN IL t t PowerStage_GBR_diag.emf t DEN tsIS(ON) tsIS(OFF) t VDS VDS(SLC) VS

Data Sheet 24 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages Note: No protection mechanism like Overtemperature or Overload protection is active during applied Inverse Currents.

7.3.2 Switching Channels in Parallel

In case of appearance of a short circuit with connected in parallel to drive a single load, it may happen that the two channels switch OFF asynchronously, therefore bringing an additional thermal stress to the channel that switches OFF last. For this reason it is not recommended to use the device with channels in parallel.

7.3.3 Cross Current robustness with H-Bridge configuration

When BTS7080-2EPA is used as high-side switch e.g. in a bridge configuration (therefore paired with a low-side switch as shown in Figure 21), the maximum slew rate ap plied to the output by the low-side switch must be lower than | dVOUT / dt |. Figure 21 High-Side switch used in Bridge configuration IN0 IN1 OUT0 OUT1 VS PowerStage_Pass iveSl ew_PROFET.emf T T VBAT R/L cable M ON (DC) OFF ON (PWM) OFF Current through Motor Cross Current | dVOUT / dt |

Data Sheet 25 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages

7.4 Electrical Characteristics Power Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω

7.4.1 Electrical Characteristics Power Stages - PROFET™

Table 11 Electrical Characterist ics: Power Stages - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltages Drain to Source Clamping Voltage at TJ = -40 °C VDS(CLAMP)_-40 33 36.5 42 V IL = 5 mA TJ = -40°C See Figure 17 P_7.4.0.1 Drain to Source Clamping Voltage at TJ ≥ 25 °C VDS(CLAMP)_25 35 38 44 V 1) IL = 5 mA TJ ≥ 25°C See Figure 17 1) Tested at TJ = 150°C. P_7.4.0.2 Table 12 Electrical Characterist ics: Power Stages - PROFET™ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Timings Switch-ON Delay tON(DELAY) 10 35 60 μs VS = 13.5 V VOUT = 10% VS See Figure 16 P_7.4.1.1 Switch-OFF Delay tOFF(DELAY) 10 25 50 μs VS = 13.5 V VOUT = 90% VS See Figure 16 P_7.4.1.2 Switch-ON Time tON 30 60 110 μs VS = 13.5 V VOUT = 90% VS See Figure 16 P_7.4.1.3 Switch-OFF Time tOFF 15 50 100 μs VS = 13.5 V VOUT = 10% VS See Figure 16 P_7.4.1.4 Switch-ON/OFF Matching tON - tOFF ΔtSW -20 20 60 μs VS = 13.5 V P_7.4.1.5 Voltage Slope

Data Sheet 26 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages

7.5 Electrical Characteristics - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω

7.5.1 Power Output Stage - 80 m Ω

Switch-ON Slew Rate (d V/dt)ON 0.3 0.6 0.9 V/ μs VS = 13.5 V VOUT = 30% to 70% of VS See Figure 16 P_7.4.1.6 Switch-OFF Slew Rate -(d V/dt)OFF 0.3 0.6 0.9 V/ μs VS = 13.5 V VOUT = 70% to 30% of VS See Figure 16 P_7.4.1.7 Slew Rate Matching (dV/dt)ON - (dV/dt)OFF Voltages Output Voltage Drop Limitation at Small Load Currents VDS(SLC) 271 8 m V 1) DEN = “high” channel selected with DSEL pin I L = IL(OL) = 20 mA See Figure 18 P_7.4.1.9 1) Not subject to production test - specified by design. Table 13 Electrical Characteri stics: Power Stages - 80 mΩ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output characteristics ON-State Resistance at TJ =2 5° C RDS(ON)_25 – 20.9 – m Ω 1) TJ = 25 °C P_7.5.7.1 ON-State Resistance at TJ = 150 °C RDS(ON)_150 – – 39.6 m Ω TJ = 150 °C IL = 2 A P_7.5.7.2 ON-State Resistance in Cranking RDS(ON)_CRAN K – – 49.5 m Ω TJ = 150 °C VS = 3.1 V IL = 0.75 A P_7.5.7.3 Table 12 Electrical Characterist ics: Power Stages - PROFET™ (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 27 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages ON-State Resistance in Inverse Current at TJ = 25 °C RDS(INV)_25 – 23.1 – m Ω 1) TJ = 25 °C VS = 13.5 V IL = -2 A DEN = “low” see Figure 19 P_7.5.7.4 ON-State Resistance in Inverse Current at TJ = 150 °C RDS(INV)_150 – – 49.5 m Ω TJ = 150 °C VS = 13.5 V IL = -2 A DEN = “low” see Figure 19 P_7.5.7.5 ON-State Resistance in Reverse Polarity at TJ = 25 °C RDS(REV)_25 – 23.1 – m Ω 1) TJ = 25 °C VS = -13.5 V IL = -2 A RSENSE = 1.2 kΩ P_7.5.7.6 ON-State Resistance in Reverse Polarity at TJ = 150 °C RDS(REV)_150 ––8 0 m Ω TJ = 150 °C VS = -13.5 V IL = -2 A RSENSE = 1.2 kΩ P_7.5.7.7 Nominal Load Current per Channel (all Channels Active) IL(NOM) –3–A 1) TA = 85 °C TJ ≤ 150 °C P_7.5.7.8 Output Leakage Current at TJ ≤ 85 °C IL(OFF)_85 –0 . 0 1 0 . 5 μA 1) VOUT = 0 V VIN = “low” TA ≤ 85 °C P_7.5.7.9 Output Leakage Current at TJ = 150 °C IL(OFF)_150 –1 . 2 4 μA VOUT = 0 V VIN = “low” TA = 150 °C P_7.5.7.10 Inverse Current Capability IL(INV) –3–A 1) VS < VOUT IN = “high” see Figure 19 P_7.5.7.11 Voltage Slope Passive Slew Rate (e.g. for Half Bridge Configuration) |dVOUT / dt|– – 1 0 V / μs 1) VS = 13.5 V see Figure 21 P_7.5.7.12 Voltages Drain Source Diode Voltage | VDS(DIODE)| – 650 700 mV IL = -190 mA TJ = 150 °C P_7.5.7.13 Switching Energy Table 13 Electrical Characteri stics: Power Stages - 80 mΩ (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 28 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Power Stages Switch-ON Energy EON –0 . 3 2 –m J 1) VS = 18 V see Figure 16 P_7.5.7.14 Switch-OFF Energy EOFF –0 . 3 5 –m J 1) VS = 18 V see Figure 16 P_7.5.7.15 1) Not subject to production test - specified by design. Table 13 Electrical Characteri stics: Power Stages - 80 mΩ (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 29 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection

8 Protection

The BTS7080-2EPA is protected against Overtemperature, Overload, Reve rse Battery (with ReverseON) and Overvoltage. Overtemperature and Over load protections are working when the device is not in Sleep mode. Overvoltage protection works in all operation modes. Reverse Battery protection works when the GND and VS pins are reverse supplied.

8.1 Overtemperature Protection

The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for each channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN)) switches OFF the overheated channe l to prevent destruction. The ch annel remains switched OFF until junction temperature has reached the “Restart” condition described in Table 14. The behavior is shown in Figure 22 (absolute Overtemperature Protection) and Figure 23 (dynamic Overtemperature Protection). TJ(REF) is the reference temperature used for dynamic temperature protection. Figure 22 Overtemperature Protection (Absolute) IL(OVL) IL t TJ IIS Pr otection_PROFE T_OT_IRC.emf DEN In ter nal count er TJ(ABS) t t t t IN t IIS (S AT ) IIS (FA UL T ) THYS(ABS) tIS (FA UL T )_D IL / kILI S

Data Sheet 30 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection Figure 23 Overtemperature Protection (Dynamic) When the Overtemperature protection circuitry allows the channel to be switched ON again, the retry strategy described in Chapter 8.3 is followed.

8.2 Overload Protection

The BTS7080-2EPA is protected in case of Overload or short circuit to ground. Two Overload thresholds are defined (see Figure 24) and selected automatically depending on the voltage VDS across the power DMOS:

• IL(OVL0) when VDS < 13 V
• IL(OVL1) when VDS > 22 V IL(OVL) IL t TJ IIS Protecti on_PRO FET_dT_IRC.emf DEN In ter nal count er TJ(ABS) t t t t IN t IIS (FA UL T ) TJ(DYN) tIS(FAUL T)_D IL / kILI S TJ(REF)

Data Sheet 31 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection Figure 24 Overload Current Thresholds variation with VDS In order to allow a higher load inrush at low ambien t temperature, Overload th reshold is maximum at low temperature and decreases when TJ increases (see Figure 25). IL(OVL0) typical value remains constant up to a junction temperature of +75 °C. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 4 6 8 10 12 14 16 18 20 22 24 26 28 Drain Source Voltage (V) Overload threshold variation ("1" = IL(OVL) typ @ VDS = 5 V) IL(OVL0) IL(OVL1)

Data Sheet 33 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection

8.3 Protection and Diagnosis in case of Fault

Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:

• The affected channel switches OFF an d the internal counter is incremented
• If the diagnosis is active for the affected channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2 for further details) The channel can be switched ON again if all the pr otection mechanisms fulfi ll the “restart” conditions described in Table 14. Furthermore, the device has an internal retry counter (one for each channel) to maximize the robustness in case of fault.

8.3.1 Retry Strategy

When IN is set to “high”, the channe l is switched ON. In case of fault condition the output stage is switched OFF. The channel can be allowed to restart only if the “restart” conditions for the protection mechanisms are fulfilled (see Table 14). The channel is allowed to switch ON for nRETRY(CR) times before switching OFF. After a time tRETRY, if the input pin is set to “high”, the channel switches ON again for nRETRY(NT) times before switching OFF again (“retry” cycle). After nRETRY(CYC) consecutive “retry” cycles, the channel latches OFF. It is necessary to set the input pin to “low” for a time longer than tDELAY(CR) to de-latch the channel (“counter rese t delay” time) and to reset the internal counter to the default value. During the “counter reset delay” time, if the input is set to “high” the channel remains switched OFF and the timer counting tDELAY(CR) is reset, starting to count again as soon as the input pin is set to “low” again. If the input pin remains “low” for a time longer than tDELAY(CR) the internal retry counter is reset to the default value, allowing nRETRY(CR) retries at the next channel activation. The retry strategy is shown in Figure 29 (flowchart), Figure 27 (timing diagram - input pin always “high”) and Figure 28 (timing diagram - channel controlled in PWM). Table 14 Protection “Restart” Condition Fault condition Switch OFF event “Restart” Condition Overtemperature TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN) TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN) (including hysteresis) Overload IL ≥ IL(OVL) IL < 50 mA TJ within TJ(ABS) and TJ(DYN) ranges (including hysteresis)

Data Sheet 35 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection Figure 29 Retry Strategy Flowchart Protection_P RO FET _Flo w.emf Fault (Overtemperature or Overload) Swit ch channel ON no Channel remains ON Switch channel OFF yes Counter++ IN is "high" yes yes "Retry" cycles = nRETRY(CYC) no Wait for tRETRY "Retry" cycles++ yes Wait until IN is "low" then start counting for t DELAY(CR) IN is "low" tDE LAY(CR) elapsed Continue counting for tDE LAY (CR) yes no no yes Counter = 0 "Retry" cycles = 0 Counter < n RETRY(CR) no "Retry" cycles = nRETRY(CYC) yes yes IN is "high" yes Swi t ch channel OF F no START no ALL "Restart" conditions fulfilled no no Channel remains OFF

Data Sheet 36 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection It is possible to “force” a reset of the internal counter without waiting for tDELAY(CR) by applying a pulse (rising edge followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a duration longer than tDEN(CR) to ensure a reset of the internal counter. The DSEL pin must select the channel that has to be de-latched and keep the same logic value while DEN pin toggles twice (rising edge followed by a falling edge). The timings are shown in Figure 30. Figure 30 Retry Strategy Timing Diagram with Forced Reset

8.4 Additional protections

8.4.1 Reverse Polarity Protection

In Reverse Polarity condition (also known as Revers e Battery), the output stages are switched ON (see parameter RDS(REV)) because of ReverseON feature which limits the power dissipation in the output stages. Each ESD diode of the logic contributes to total powe r dissipation. The reverse current through the output stages must be limited by the connected loads. The current through digital input pins has to be limited as well by an external resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application Information in Chapter 10). Figure 31 shows a typical application including a device with ReverseON. A current flowing into GND pin (-IGND) during Reverse Polarity condition is necessary to ac tivate ReverseON, therefore a resistive path between module ground and device GND pin must be present. t IN Short circu it to ground IL 0 1In ter nal count er nRE T RY (CR ) t t t Prote cti on_PRO FET_DEN fo rce_tim e2.e mf DEN nRE T RY (CR ) ttDEN(CR ) tDEN(CR ) nRE T RY (CR ) tDEN(CR ) nRE T RY (CR ) 0

Data Sheet 37 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection Figure 31 Reverse Battery Protection (application example)

8.4.2 Overvoltage Protection

In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistors are still operational and follow the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there is a clamp mechanism available for Overvoltage protection for the logic and the output channels, monitoring the voltage between VS and GND pins (VS(CLAMP)).

8.5 Protection against loss of connection

8.5.1 Loss of Battery and Loss of Load

The loss of connection to battery or to the load has no influence on device robustness when load and wire harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be handled. PROFET™+2 12V devices can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In case of applications where currents and/ or the aforementioned inductivity ar e exceeded, an external suppressor diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide a well- defined path to the load current.

8.5.2 Loss of Ground

In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin and the microcontroller to ensure a channel switch OFF (as described in Chapter 10). Note: In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground path is available, which could keep the device operational during loss of device ground. Protection_RevBatt.emf High-side Channel L, C, R VS OUTn GNDISRSENSE RGND DI Mic roco ntroller DO RDI GND -IL -IGND-IIS IDI -VBAT(R EV ) ReverseO N

Data Sheet 38 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection

8.6 Electrical Characteristics Protection

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω

8.6.1 Electrical Characterist ics Protection - PROFET™

Table 15 Electrical Characteri stics: Protection - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Thermal Shutdown Temperature (Absolute) TJ(ABS) 150 175 200 °C 1)2) See Figure 22 1) Functional test only. 2) Tested at TJ = 150°C only. P_8.6.0.1 Thermal Shutdown Hysteresis (Absolute) THYS(ABS) –3 0 –K 3) See Figure 22 3) Not subject to production test - specified by design. P_8.6.0.2 Thermal Shutdown Temperature (Dynamic) TJ(DYN) –8 0 –K 3) See Figure 23 P_8.6.0.3 Power Supply Clamping Voltage at TJ = -40 °C VS(CLAMP)_-40 33 36.5 42 V IVS = 5 mA TJ = -40 °C See Figure 17 P_8.6.0.6 Power Supply Clamping Voltage at TJ ≥ 25 °C VS(CLAMP)_25 35 38 44 V 2) IVS = 5 mA TJ ≥ 25 °C See Figure 17 P_8.6.0.7 Power Supply Voltage Threshold for Overcurrent Threshold Reduction in case of Short Circuit V S(JS) 20.5 22.5 24.5 V 3) Setup acc. to AEC- Q100-012 P_8.6.0.8 Table 16 Electrical Characteri stics: Protection - PROFET™ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Automatic Retries in Case of Fault after a Counter Reset nRETRY(CR) –5– 1) See Figure 27 and Figure 28 P_8.6.1.1 Automatic Retries in Case of Fault after the First tRETRY Activation nRETRY(NT) –1– 1) See Figure 27 and Figure 28 P_8.6.1.3 Maximum “Retry” Cycles allowed before Channel Latch OFF n RETRY(CYC) –2– 1) See Figure 27 and Figure 28 P_8.6.1.4

Data Sheet 39 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection

8.7 Electrical Characteristics Pr otection - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω

8.7.1 Protection Power Output Stage - 80 m Ω

Auto Retry Time after Fault Condition tRETRY 40 70 100 ms 1) See Figure 27 and Figure 28 P_8.6.1.5 Counter Reset Delay Time after Fault Condition tDELAY(CR) 40 70 100 ms 1) See Figure 27 and Figure 28 P_8.6.1.6 Minimum DEN Pulse Duration for Counter Reset tDEN(CR) 50 100 150 µs 2) See Figure 30 P_8.6.1.7 1) Functional test only. 2) Not subject to production test - specified by design. Table 17 Electrical Characteri stics: Protection - 80 mΩ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Overload Detection Current at TJ = -40 °C IL(OVL0)_-40 32 36 40 A 1) TJ = -40 °C dI/dt = 0.2 A/µs see Figure 24 and Figure 25 P_8.7.7.1 Overload Detection Current at TJ = 25 °C IL(OVL0)_25 30 36 40 A 2) TJ = 25 °C dI/dt = 0.2 A/µs see Figure 24 and Figure 25 P_8.7.7.7 Overload Detection Current at TJ = 150 °C IL(OVL0)_150 26 30 34 A 2) TJ = 150 °C dI/dt = 0.2 A/µs see Figure 24 and Figure 25 P_8.7.7.8 Table 16 Electrical Characteri stics: Protection - PROFET™ (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 40 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Protection Overload Detection Current at High VDS IL(OVL1) – 21.5 – A 2) dI/dt = 0.2 A/µs see Figure 24 P_8.7.7.5 Overload Detection Current Jump Start Condition IL(OVL_JS) – 21.5 – A 2) VS > VS(JS) dI/dt = 0.2 A/µs see Figure 26 P_8.7.7.6 1) Functional test only. 2) Not subject to production test - specified by design. Table 17 Electrical Characteri stics: Protection - 80 mΩ (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 41 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9 Diagnosis

For diagnosis purpose, the BTS7080-2EPA provides a combination of digital and analog signals at pin IS. These signals are generically named SENSE and written IIS. In case of disabled diagnostic (DEN pin set to “low”), IS pin becomes high impedance. A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ. Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS pin to the sense current output of other devices, if they are supplied by a different battery feed. See Figure 32 for details as an overview. Figure 32 Diagnosis Block Diagram

9.1 Overview

Table 18 gives a quick reference to the state of the IS pin during BTS7080-2EPA operation. Channel 1 Diagnosis_PROFET_2CH.emf IS Pin Control Logic Internal Counters INn DSEL DEN Overtemperature IIS(FAULT) OUT0 VS MUX VDS(OLOFF) IIS(OLOFF) MUX IS RSE NSE OUT1 MUX Channel 0 T IL / kIL IS

Data Sheet 42 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.1.1 SENSE signal truth table

In case DEN is set to “high”, the SENSE for the selected channel is enabled or disabled using DSEL pin. Table 19 gives the truth table.

9.2 Diagnosis in ON state

A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions are fulfilled: Table 18 SENSE Signal, Function of Application Condition Application Condition Input level DEN level VOUT Diagnostic Output Normal operation “low” “high” ~ GND Z IIS(FAULT) if counter > 0 Short circuit to GND ~ GND Z IIS(FAULT) if counter > 0 Overtemperature Z IIS(FAULT) Short circuit to VS VS IIS(OLOFF) (IIS(FAULT) if counter > 0) Open Load < VS - VDS(OLOFF) > VS - VDS(OLOFF) 1) With additional pull-up resistor. Z IIS(OLOFF) (in both cases IIS(FAULT) if counter > 0) Inverse current ~ VINV = VOUT > VS IIS(OLOFF) (IIS(FAULT) if counter > 0) Normal operation “high” ~ VS IIS = IL / kILIS Overcurrent < VS IIS(FAULT) Short circuit to GND ~ GND IIS(FAULT) Overtemperature Z IIS(FAULT) Short circuit to VS VS IIS < IL / kILIS Open Load ~ VS 2) The output current ha s to be smaller than IL(OL). IIS = IIS(EN) Under load (e.g. Output Voltage Limitation condition) ~ VS 3) The output current has to be higher than IL(OL). IIS(EN) < IIS < IL(NOM) / kILIS Inverse current ~ VINV = VOUT > VS IIS = IIS(EN) All conditions n.a. “low” n.a. Z Table 19 Diagnostic Truth Table DEN DSEL IS “low” not relevant Z “high” “low” SENSE output 0 “high” “high” SENSE output 1

• The power output stage is switched ON with VDS < VDS(OLOFF)
• The diagnosis is enabled for that channel
• No fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for further details) If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.

9.2.1 Current Sense ( kILIS)

Figure 34. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).

• A well-defined and precise current ( IL(CAL)) is applied at the output during End of Line test at customer side
• The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
• Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by ΔkILIS The derating of kILIS after calibration is calculated using the formulas in Figure 33 and it is specified by ΔkILIS Figure 33 ΔkILIS calculation formulas The calibration is intend ed to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H. Figure 34 Current Sense Ratio in Open Load at ON condition Diagnosis_dKILIS.emf IIS ILIL(OL) IIS(OL ) Di agn o s i s_ OLON _adv .em f IIS(EN)

Data Sheet 44 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.2.2 Fault Current ( IIS(FAULT))

As soon a protection event occurs, changing the value of the internal retry counter (see Chapter 8.3 for more details) from its reset state, a current IIS(FAULT) is provided by pin IS when DEN is set to “high” and the affected channel is selected. The following 3 situations may occur:

• If the channel is ON and the numb er of retries is lower than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current IIS(FAULT) is provided for a time tIS(FAULT)_D after the channel is allowed to restart, after which IIS = IL / kILIS (as shown in Figure 35). During a retry cycle (while timer tRETRY is running) the current IIS(FAULT) is provided each time the channel diagnosis is checked
• If the channel is ON and the numb er of retries is equal than “nRETRY(CR) + nRETRY(CYC) * nRETRY(NT)”, the current IIS(FAULT) is provided until the internal counter is reset (either by expiring of tDELAY(CR) time or by DEN pin pulse, as described in Chapter 8.3.1)
• If the channel is OFF and the internal coun ter is not in the reset state, the current IIS(FAULT) is provided each time the channel diagnosis is checked Figure 35 IIS(FAULT) at Load Switching Figure 36 adds the behavior of SENSE signal to the timing diagram seen in Figure 28, while Figure 37 shows the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT). t IN IL 0 1In ter nal count er t t Diagnosis_PROFET_IISFAUL T_load.emf t DEN t IIS IIS (FA UL T ) IL / kILI S tIS(FAUL T)_D IIS (FA UL T ) IL(OVL)

Data Sheet 45 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis Figure 36 SENSE behavior in Fault condition Figure 37 SENSE behavior - overview

9.3 Diagnosis in OFF state

When a power output stage is in OFF state, the BT S7080-2EPA can measure the output voltage and compare it with a threshold voltage. In this way, using some additional external components (a pull-down resistor and a switchable pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to battery. If a Fault condition was detected by the device (the internal counter has a value different from the reset value, as described in Chapter 9.2.2) a current IIS(FAULT) i s p r o v i d e d b y I S p i n e a c h t i m e t h e c h a n n e l diagnosis is checked also in OFF state. t IN tRE T RY Short circu it to ground IL 0 1 nRE T RY ( CR ) In ter nal count er nRE T RY (CR ) + nRE T RY (NT) nRE T RY (CR ) + ( nRE T RY ( CYC ) * nRE T RY ( NT)) tDELAY (CR )tRE T RY nRE T RY ( CR ) nRE T RY ( NT) "retry" cy cle nRE T RY ( NT) t t t Dia gnosi s_PRO F ET_IIS FAU LT .emf t DEN t IIS IIS (FA UL T ) IIS (FA UL T ) IL / kILI S nRE T RY (CYC ) IIS (FA UL T ) Dia g nosi s_PRO FET_IIS FAU LT _IIS SA T.emf IIS IL IIS (S AT ) IIS (FA UL T ) IL / kILI S IIS(SA T),min = IIS(FAUL T),min IIS(FAUL T),max IIS(SA T),max IL(OVL)

Data Sheet 46 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.3.1 Open Load current ( IIS(OLOFF))

I n O F F s t a t e , w h e n D E N p i n i s s e t t o “ h i g h ” and a channel is selected using DSEL pin, the VDS voltage is compared with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to battery, VDS ~ VS therefore VDS > VDS(OLOFF). When the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. Figure 38 shows the relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two currents do not overlap ma king it always possible to differentia te between Open Load in OFF and Fault condition. Figure 38 IIS in OFF State It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the inpu t pin and the sensing at pin IS for Open Load in OFF diagnosis to allow th e internal comparator to settle. In Figure 39 the timings for an Open Load detection are shown - the load is always disconnected. Figure 39 Open Load in OFF Timings - load disconnected Di agn o s is_P R OFE T_I I SOL OFF .em f IIS VDS IIS (OLOFF) VDS(OLOFF) IIS (FA UL T ) t IN t DEN VOUT ~ VS tIS(OLOFF)_D t IIS (OLOFF) IIS IIS (OL) VDS(OLOFF) t Diagnosis_PROFE T_OLOF F_time.emf Loa d conn ect ed

Data Sheet 47 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.4 SENSE Timings

Figure 40 and Figure 42 show the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load change). As a proper signal cannot be established before the load current is stable (therefore before tON), tsIS(DIAG) = tsIS(ON) + tON. Figure 40 SENSE Settling / Disabling Timing Figure 41 SENSE Timing with Small Load Current t t t IL IIS DEN t ONOFF OFF Dia g nose _PRO F ET_SE N SE_tim ing s.emf IN tsI S(DI AG) tsI S(LC) tsIS(O F F)tsIS(ON)tsIS(O F F) tOF F DEN t t t t ONOFF IN OFF Di agn o se_PROFE T_S ENS E_ti mi n gs_S LC.em f tsIS(ON)_SLC tsIS(ON) tsIS(LC)_SLC IL IIS

Data Sheet 48 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis Figure 42 SENSE Settling Timing - Channel Change Diagnose_PROFET_SENSE_timings_CC.emf DSEL IIS t t t IL1 t tsI S(CC) tsIS(O F F) DEN tsI S(ON) tsI S(CC)_SLC t IL0 IL(CAL)_L IL(CAL) IL(CAL)_O L

Data Sheet 49 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.5 Electrical Characteristics Diagnosis

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω Table 20 Electrical Characteri stics: Diagnosis - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SENSE Saturation Current IIS(SAT) 4.4 – 15 mA 1) VS = 8 V to 18 V RSENSE = 1.2 kΩ See Figure 37 P_9.6.0.13 SENSE Saturation Current IIS(SAT) 4.1 – 15 mA 1) VS = 6 V to 18 V RSENSE = 1.2 kΩ See Figure 37 P_9.6.0.14 SENSE Leakage Current when Disabled IIS(OFF) –0 . 0 1 0 . 5 µ A D E N = “ l o w ” IL ≥ IL(NOM) VIS = 0 V P_9.6.0.2 SENSE Leakage Current when Enabled at TJ ≤ 85 °C IIS(EN)_85 –0 . 2 1µ A 1) TJ ≤ 85 °C DEN = “high” I L = 0 A See Figure 34 P_9.6.0.3 SENSE Leakage Current when Enabled at TJ = 150 °C IIS(EN)_150 –0 . 2 1µ A TJ = 150 °C DEN = “high” IL = 0 A See Figure 34 P_9.6.0.4 SENSE Operative Range for kILIS Operation (VS - VIS) VSIS_k –0 . 5 1V 1) VS = 6 V IN = DEN = “high” IL ≤ 1.2 * IL(NOM) P_9.6.0.6 SENSE Operative Range for Open Load at OFF Diagnosis (VS - VIS) VSIS_OL –0 . 5 1V 1) VS = 6 V IN = “low” DEN = “high” P_9.6.0.7 SENSE Operative Range for Fault Diagnosis S - VIS) VSIS_F –0 . 5 1V 1) VS = 6 V IN = “low” DEN = “high” counter > 0 P_9.6.0.8

Data Sheet 50 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.5.1 Electrical Characteristics Diagnosis - PROFET™

TJ =- 4 0° C VSIS(CLAMP)_- 33 36.5 42 V IIS = 1 mA TJ = -40 °C See Figure 17 P_9.6.0.9 Power Supply to IS Pin Clamping Voltage at TJ ≥25 °C VSIS(CLAMP)_25 35 38 44 V 2) IIS = 1 mA TJ ≥ 25 °C See Figure 17 P_9.6.0.10 1) Not subject to production test - specified by design. 2) Tested at TJ = 150°C. Table 21 Electrical Characteri stics: Diagnosis - PROFET™ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SENSE Fault Current IIS(FAULT) 4.4 5.5 10 mA See Figure 37 and Figure 38 P_9.6.1.1 SENSE Open Load in OFF Current IIS(OLOFF) 1.9 2.5 3.5 mA See Figure 37 and Figure 38 P_9.6.1.2 SENSE Delay Time at Channel Switch ON after Last Fault Condition t IS(FAULT)_D – 500 – µs 1) See Figure 35 P_9.6.1.3 SENSE Open Load in OFF Delay Time tIS(OLOFF)_D 30 70 120 µs VDS < VOL(OFF) from IN falling edge to IIS = IS(OLOFF),MIN * 0.9 DEN = “high” counter = 0 See Figure 39 P_9.6.1.4 Open Load VDS Detection Threshold in OFF State SENSE Settling Time with Nominal Load Current Stable t sIS(ON) –52 0 µ s IL = IL(CAL) from DEN rising edge to IIS = IL / (kILIS,MAX @ IL) * 0.9 See Figure 40 P_9.6.1.6 SENSE Settling Time with Small Load Current Stable tsIS(ON)_SLC ––6 0 µ s 1) IL = IL(CAL)_OL from DEN rising edge to IIS = IL / (kILIS,MAX @ IL) * 0.9 P_9.6.1.13 Table 20 Electrical Characteri stics: Diagnosis - General (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 51 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.6 Electrical Characteristics Diagnosis - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive loads connected to the outputs for testing (unless otherwise specified): RL = 3.8 Ω SENSE Disable Time tsIS(OFF) –52 0 µ s 1) From DEN falling edge to IIS = IIS(OFF) See Figure 40 P_9.6.1.8 SENSE Settling Time after Load Change tsIS(LC) –52 0 µ s 1) from IL = IL(CAL)_L to IL = IL(CAL) (see ΔkILIS(NOM)) See Figure 40 P_9.6.1.9 SENSE Settling Time after Load Change with Small Load Current t sIS(LC)_SLC – 250 400 µs 1) DEN = “high” from Load Change to IIS = IL / (kILIS @ IL) from IL(CAL) to IL(CAL)_OL P_9.6.1.14 SENSE Settling Time after Channel Change tsIS(CC) –52 0 µ s 1) Start channel: IL = IL(CAL) End channel: IL = IL(CAL)_L (see ΔkILIS(NOM)) See Figure 42 P_9.6.1.10 SENSE Settling Time after Channel Change with Small Load Current t sIS(CC)_SLC ––6 0 µ s 1) DEN = “high” from DSEL toggling to IIS = IL / (kILIS,MIN @ IL) * 1.1 Start channel: IL = IL(CAL) End Channel: IL = IL(CAL)_OL (see ΔkILIS(NOM) and ΔkILIS(OL)) P_9.6.1.15 1) Not subject to production test - specified by design. Table 21 Electrical Characteri stics: Diagnosis - PROFET™ (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 52 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Diagnosis

9.6.1 Diagnosis Power Output Stage - 80 m Ω

Table 22 Electrical Characte ristics: Diagnosis - 80 mΩ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Open Load Output Current at IIS = 4 µA IL(OL)_4u 161 1 m A IIS = IIS(OL) = 4 µA See Figure 34 P_9.7.7.1 Current Sense Ratio at IL = IL01 Current Sense Ratio at IL = IL02 Current Sense Ratio at IL = IL04 Current Sense Ratio at IL = IL08 Current Sense Ratio at IL = IL11 Current Sense Ratio at IL = IL13 Current Sense Ratio at IL = IL15 SENSE Current Derating with Low Current Calibration Δk ILIS(OL) -30 0 +30 % 1) IL(CAL)_OL = IL02 IL(CAL)_OL_H = IL04 IL(CAL)_OL_L = IL01 TA(CAL) = 25 °C See Figure 33 P_9.7.7.27 SENSE Current Derating with Nominal Current Calibration ΔkILIS(NOM) -4 0 +4 % 1) IL(CAL) = IL13 IL(CAL)_H = IL15 IL(CAL)_L = IL11 TA(CAL) = 25 °C See Figure 33 1) Not subject to production test - specified by design. P_9.7.7.29

Data Sheet 53 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V

Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

10.1 Application Setup

Figure 43 BTS7080-2EP A Application Diagram Note: This is a very simplified example of an applicatio n circuit. The function must be verified in the real application. Table 23 Loads considered for Reverse Polarity setup (see P_4.1.0.5) Output RDS(ON),max @ TJ = 150 °C Load connected 80 mΩ 39.6 mΩ P21W PROFET™+2 12V Ap p_2CH_IN TD I O_CV G_LO.e mf Microcontroller VDD DZ2 CVS2 Logic Supply Logic GND Power GND VSS GPIO RIN IN0 GPIO RIN IN1 GPIO RDEN DEN GPIO RDSEL DSEL CVS GND RGN D CVSGND ROL RPD COUT0 ZWIRE DZ1 ISADC RADC RIS_PROT RSENSECSENSE ZWIRE COUT1 Optional Optional Chassis GND VBAT Optional ZWIRE ZLOAD* ZLOAD* *See Chapter 1 „Potential Applications“ VS OUT0 OUT1

Data Sheet 54 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V

10.2 External Components

10.3 Further Application Information

• Please contact us for information regarding the Pin FMEA Table 24 Suggested Component values Reference Value Purpose RIN 4.7 kΩ Protection of the microcontroller during Overvoltage and Reverse Polarity Necessary to switch OFF BTS7080-2EPA output during Loss of Ground RDEN 4.7 kΩ Protection of the microcontroller during Overvoltage and Reverse Polarity Necessary to switch OFF BTS7080-2EPA output during Loss of Ground RDSEL 4.7 kΩ Protection of the microcontroller during Overvoltage and Reverse Polarity Necessary to switch OFF BTS7080-2EPA output during Loss of Ground RPD 47 kΩ Output polarization (pull-down) Ensures polarization of BTS7080-2EPA outputs to distinguish between Open Load and Short to VS in OFF Diagnosis ROL 1.5 kΩ Output polarization (pull-up) Ensures polarization of BTS7080-2EPA output during Open Load in OFF diagnosis COUT 10 nF Protection of BTS7080-2EPA ou tput during ESD events and BCI T1 BC 807 Switch the battery voltage for Open Load in OFF diagnosis CVS 100 nF Filtering of voltage sp ikes on the battery line CVSGND 47 nF Buffer capacitor for fast transient See Table 5 (P_4.3.0.7) for the boundary conditions A placeholder on PCB layout is recommended DZ2 33 V TVS Diode Transient Voltage Suppressor diode Protection during Overvoltage and in case of Loss of Battery while driving an inductive load CVS2 – Filtering / buffer capacitor located at VBAT connector RSENSE 1.2 kΩ SENSE resistor RIS_PROT 4.7 kΩ Protection during Overvoltage, Reverse Polarity, Loss of Ground Value to be tuned according to microcontroller specifications DZ1 7 V Z-Diode Protection of microcontroller during Overvoltage RADC 4.7 kΩ Protection of microcontroller ADC input during Overvoltage, Reverse Polarity, Loss of Ground Value to be tuned according to microcontroller specifications C SENSE 220 pF Sense signal filtering A time constant (RADC * CSENSE) longer than 1 µs is recommended RGND 47 Ω Protection in case of Overvoltage and Loss of Battery while driving inductive loads

Data Sheet 55 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V

• For further information you may contact http://www.infineon.com/

Data Sheet 56 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Package Outlines Figure 44 PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package Outline Figure 45 PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil ,1'(; 0$; 67$1'2)) & [ 0$5.,1* 6($7,1* 3/$1( &23/$1$5,7< s s s rr s $% & s %27720 9,(: s s [ [ s *$8*( 3/$1( FRSSHU VROGHU PDVN VWHQFLO DSHUWXUHV

Data Sheet 57 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Package Outlines Green product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages

Data Sheet 58 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V

Revision History

Table 25 BTS7080-2EPA - List of changes Revision Changes Figure 19) P_7.5.7.12 updated (added in Note or Test Condition: see Figure 21; deleted unnecessary space in Symbol: |dVOUT / dt | → |dVOUT / dt|) P_8.7.7.6 updated (added in Note or Test Condition: see Figure 26) P_9.7.7.1 updated (added in Note or Test Condition: see Figure 34) P_7.5.7.11 updated (added in Note or Test Condition: see Figure 19) Figure 1, Figure 43 updated Chapter 1 updated (or LED equivalent → or equivalent electronic loads (e.g. LED modules)) P_4.3.0.7 added Table 24 updated Chapter 5.1 updated (added: see Chapter 10 for the complete application setup overview) 1.04, 2019-06-26 Chapter 9.2 updated (2 V → V DS(OLOFF)) General: updated (ReverSave™ → ReverseON) Chapter 1 updated ((inserted headline "Product Validation"), (Qualified in accordance with AEC Q100 grade 1 → Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.)) General: updated Product Name (PROFET™+2 → PROFET™+2 12V) Page 1: updated figure product Table 24 updated punctuation Chapter 9.3.1 updated (typo) Page 1: updated (Package PG-TSDSO-14-22 → Package PG-TSDSO-14) Figure 29 updated Figure 44 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package Outline → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package Outline) Figure 45 updated (PG-TSDSO-14-22 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil → PG-TSDSO-14 (Thin (Slim) Dual Small Outline 14 pins) Package pads and stencil) Table 1 updated ((Symbol: I VS(SLEEP) → IVS(SLEEP)_85), (Parameter: Minimum Overvoltage protection (TJ = 25 °C) → Minimum Overvoltage protection (TJ ≥ 25 °C)) P_9.6.0.6 updated (Note or Test Condition: removed unnecessary line-break)

Data Sheet 59 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V 1.03, 2018-06-14 Chapter 7.4.1 updated chapter title (PROFET → PROFET™) Table 12 updated table title (PROFET → PROFET™) Chapter 8.6.1 updated chapter title (PROFET → PROFET™) Table 16 updated table title (PROFET → PROFET™) Chapter 9.5.1 updated chapter title (PROFET → PROFET™) Table 21 updated table title (PROFET → PROFET™) Table 1 updated (RDS(ON) → RDS(ON)_150), (VDS(CLAMP) → VDS(CLAMP)_25) Chapter 8.5.2 updated phrasing P_7.5.7.14 Table subheading "Switching Energy" added P_7.5.7.15 Table subheading "Switching Energy" added Chapter 6.4 added conditions Chapter 7.5 added conditions P_7.5.7.14 updated (Test condition: add "See Figure") P_7.5.7.15 updated (Test condition: add "See Figure") Chapter 8.7 added conditions Chapter 9.6 added conditions P_9.7.7.27 updated (Test condition: add "See Figure") P_9.7.7.29 updated (Test condition: add "See Figure") 1.02, 2017-11-17 Table 6 footnote updated ("Specified RthJA value is" removed) Figure 17 symbol updated (V IS(CLAMP) → VSIS(CLAMP)) 1.01, 2017-10-24 Figures updated (straight lines for signals th at are crossing, points for connections; typos, capitalization/lower case printing) Typos and misspelling corrected according to style guidelines, inconsistencies among document resolved P_4.1.0.36 updated (symbol: I DI → IDI(REV)) P_5.4.0.5 symbol updated (IDI → IDI(H)) P_5.4.0.6 symbol updated (IDI → IDI(L)) Chapter 7.3.3 updated Table 24 updated (RDSEL included) 1.00, 2017-08-24 Data Sheet available Table 25 BTS7080-2EPA - List of changes Revision Changes

Data Sheet 60 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V Table of Contents

Data Sheet 61 Rev. 1.06 2019-10-30 BTS7080-2EPA PROFET™+2 12V

All referenced product or service names and trademarks are the property of their respective owners. Edition 2019-10-30 Published by Infineon Technologies AG

81726 Munich, Germany

© 2019 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference Z8F65710359 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. Please read the Important Notice and Warnings at the end of this document