BTS70012-1ESP

BTS70012-1ESP INFINEON | Alldatasheet

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Technical content

Data Sheet Rev. 1.20 www.infineon.com 1 2022-12-16 BTS70012-1ESP

1 Overview

• Suitable for driving 31.3 A resistiv e, inductive and capacitive loads
• Replaces electromechanical rela ys, fuses and discrete circuits
• Suitable for driving glow plug, heat ing loads, DC motor and for power distribution Figure 1 BTS70012-1ESP Application Di agram. Further information in Chapter 10 PROFET™ +2 12V 1x 1.4 m Ω Smart High-Side Power Switch Package PG-TSDSO-24 Marking 70012-1ESP PROFET™ +2 12V App_1CH_INTDIO_CVG.emf Microcontroller VDD DZ2 CVS2 Logic Supply Logic GND Power GND VSS GPIO RIN IN GPIO RDEN DEN CVS GND RGND CVSGND ROL RPD COUT0 ZWIRE DZ1 ISADC RADC RIS_PROT RSENSECSENSE Optional Optional Chassis GND VBAT Optional ZWIRE ZLOAD* *See Chapter 1 „Potential Applications“ OUT VS

Data Sheet 2 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Overview Basic Features

• High-Side Switch with Diagn osis and Embedded Protection
• Part of PROFET™ +2 12V Family
• PRO-SIL™ ISO 26262-ready for supporting the integrator in evaluation of hardware element according to ISO 26262:2018 Clause 8-13
• Capacitive Load Switching mode
• ReverseON for low power dissipation in Reverse Polarity
• Switch ON capability while Inve rse Current condition (InverseON)
• Green Product (RoHS compliant) Protection Features
• Absolute and dynamic temperature limi tation with controlled reactivation
• Overcurrent protection (tripp ing) with Intelligent Latch
• Undervoltage shutdown
• Overvoltage protection with ex ternal components (as shown in Figure 39) Diagnostic Features
• Proportional load current sense
• Open Load in ON and OFF state
• Short circuit to ground and battery Product Validation Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.

Description

The BTS70012-1ESP is a Smart High-Side Power Switch, providing protection functions and diagnosis. Table 1 Product Summary Parameter Symbol Values Minimum Operating voltage V S(OP) 4.1 V Minimum Operating voltage (cranking) VS(UV) 3.1 V Maximum Operating voltage VS 28 V Minimum Overvoltage protection (TJ ≥ 25 °C) VDS(CLAMP)_25 35 V Maximum current in OFF mode (TJ ≤ 85 °C) IVS(OFF)_85 2.2 µA Maximum operative current IGND(ON_D) 3.3 mA Typical ON-state resistance (TJ = 25 °C) RDS(ON)_25 1.4 mΩ Maximum ON-state resistance (TJ = 150 °C) RDS(ON)_150 2.47 mΩ Nominal load current (TA = 85 °C) IL(NOM) 31.3 A Minimum overload detection current (TJ = -40°C) IL(OVL0)_-40 187 A Typical current sense ratio at IL = IL(NOM) kILIS 34100

Data Sheet 3 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Block Diagram and Terms

2 Block Diagram and Terms

2.1 Block Diagram

Figure 2 Block Diagram of BTS70012-1ESP IN ESD Protection Input Logic IS DEN Internal Power Supply Bloc k_HEAT1ch.emf GND Circuitry Supply Voltage Mo nitorin g Overvoltage Protection Intelligent Restart Control SENSE Output VS GND OUT Internal Reverse Polarity Protection Channel T Driver Logic Gate Control Chargepump Load Current Sense Overtemperature Overvoltage Clam ping Overcurrent Protection Output Voltage Limitation Voltage Sensor ReverseO N InverseON

Data Sheet 4 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Block Diagram and Terms

2.2 Terms

Figure 3 shows all terms used in this data sheet, with associated convention for positive values. Figure 3 Voltage and Current Convention IIN IDEN IIS VS IGND IL IN DEN IS GND VS OUT VIN VDEN VIS VOUT VDS IVS Te r ms _1CH .e mf VSIS

Data Sheet 5 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 4 Pin Configuration VS GND OUT IN DEN IS OUT OUT OUT OUT Pinout_PROFET1ch_PDH_24.emf exposed pad (bottom) 13n.c. n.c. n.c. OUT OUT OUT OUT OUT OUT OUT n.c. n.c. n.c. n.c. n.c.

Data Sheet 6 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Pin Configuration

3.2 Pin Definitions and Functions

(exposed pad) Supply Voltage Battery voltage 4G N D Ground Signal ground 5I N Input Channel Digital signal to switch ON the channel (“high” active) If not used: connect with a 10 kΩ resistor either to GND pin or to module ground 6D E N Diagnostic Enable Digital signal to enable device diagnosis (“high” active) and to clear the protection latch of channel If not used: connect with a 10 kΩ resistor either to GND pin or to module ground 7I S SENSE current output Analog/digital signal for diagnosis If not used: left open 1-3, 8-12 n.c. Not connected , internally not bonded 13-24 OUT Output Protected high-side power output channel1) 1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow.

Data Sheet 7 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings - General

Table 3 Absolute Maximum Ratings 1) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply pins Power Supply Voltage VS -0.3 – 28 V – P_4.1.0.1 Load Dump Voltage VBAT(LD) – – 35 V suppressed Load Dump acc. to ISO16750-2 (2010). R i = 2 Ω P_4.1.0.3 Supply Voltage for Short Circuit Protection VBAT(SC) 0–2 4 V S e t u p a c c . t o AEC-Q100-012 Rsupply = 10 mΩ Lsupply = 5 µH Rshort = 25 mΩ Lshort = 5 µH P_4.1.0.25 Reverse Polarity Voltage - VBAT(REV) ––1 6 V t ≤ 2 min TA = +25 °C Setup as described in Chapter 10 P_4.1.0.5 Current through GND Pin IGND -50 – 50 mA RGND according to Chapter 10 P_4.1.0.9 Logic & control pins (Digital Input = DI) DI = IN, DEN Current through DI Pin IDI -1 – 2 mA 2) P_4.1.0.14 Current through DI Pin Reverse Battery Condition IDI(REV) -1 – 10 mA 2) t ≤ 2 min P_4.1.0.36 IS pin Voltage at IS Pin VIS -1.5 – VS V IIS = 10 μA P_4.1.0.16 Current through IS Pin IIS -25 – IIS(SAT),M AX mA – P_4.1.0.18

Data Sheet 8 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V General Product Characteristics Notes 1. Stresses above the ones listed he re may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to preven t IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Temperatures Junction Temperature TJ -40 – 150 °C – P_4.1.0.19 Storage Temperature TSTG -55 – 150 °C – P_4.1.0.20 ESD Susceptibility ESD Susceptibility all Pins (HBM) VESD(HBM) -2 – 2 kV HBM 3) P_4.1.0.21 ESD Susceptibility OUT vs GND and VS connected (HBM) VESD(HBM)_OU T ESD Susceptibility all Pins (CDM) VESD(CDM) -500 – 500 V CDM 4) P_4.1.0.23 ESD Susceptibility Corner Pins (pins 1, 12, 13, 24) VESD(CDM)_CR N -750 – 750 V CDM 4) P_4.1.0.24 1) Not subject to production test - specified by design. 2) Maximum VDI to be considered for Latch-Up tests: 5.5 V. 3) ESD susceptibility, Human Body Mode l “HBM”, according to AEC Q100-002. 4) ESD susceptibility, Charged Device Mo del “CDM”, according to AEC Q100-011. Table 3 Absolute Maximum Ratings 1) (continued) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 9 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V General Product Characteristics

4.2 Absolute Maximum Ratings - Power Stages

4.2.1 Power Stages - 1.2 m Ω

4.3 Functional Range

Table 4 Absolute Maximum Ratings - 1.2 m Ω 1) TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Maximum Energy Dissipation Single Pulse EAS – – 525 mJ IL = 2*IL(NOM) TJ(0) = 150 °C VS = 28 V P_4.2.21.1 Maximum Energy Dissipation Repetitive Pulse EAR – – 160 mJ IL = IL(NOM) TJ(0) = 85 °C VS = 13.5 V 1M cycles P_4.2.21.2 Load Current | IL|– – IL(OVL0), MAX A– P_4.2.21.3 Table 5 Functional Range - Supply Voltage and Temperature 1) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply Voltage Range for Normal Operation Lower Extended Supply Voltage Range for Operation VS(EXT,LOW) 3.1 – 6 V 2)3) (parameter deviations possible) P_4.3.0.2 Supply Voltage Range reached after Overload Protection activation leading to “Undervoltage on V S” condition VS(EXT,CVG) –– 3 . 1 V CVSGND is required when the Overload Protection is triggered (see Chapter 8.2) and the observed number of retries is different from what specified in Chapter 8.3.1 P_4.3.0.7

Data Sheet 10 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V General Product Characteristics Note: Within the functional or operatin g range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics tables.

4.4 Thermal Resistance

Note: This thermal data was generated in accord ance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Upper Extended Supply Voltage Range for Operation VS(EXT,UP) 18 – 28 V 3) (parameter deviations possible) P_4.3.0.3 Junction Temperature TJ -40 – 150 °C – P_4.3.0.5 1) Not subject to production test - specified by design. 2) In case of VS voltage decreasing: VS(EXT,LOW),MIN =3 . 1V . I n c a s e o f VS voltage increasing: VS(EXT,LOW),MIN =4 . 1V . 3) Protection functions still operative. Table 6 Thermal Resistance 1) 1) Not subject to production test - specified by design. Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Thermal Characterization Parameter Junction-Top ΨJTOP –0 . 7 1 . 3 K / W 2) 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C, PDISSIPATION = 1 W. P_4.4.0.12 Thermal Resistance Junction-to-Case RthJC –0 . 4 0 . 7 K / W 2) simulated at exposed pad P_4.4.0.13 Thermal Resistance Junction-to-Ambient RthJA – 23.0 – K/W 2) P_4.4.0.14 Table 5 Functional Range - Supply Voltage and Temperature 1) (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 11 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V General Product Characteristics

4.4.1 PCB Setup

Figure 5 1s0p PCB Cross Section Figure 6 2s2p PCB Cross Section Figure 7 PCB setup for thermal simulations Figure 8 Thermal vias on PCB for 2s2p PCB setup 70 µm modeled (traces, cooling area) 1,5 mm 70 µm, 5% metalization* PC B_Z th_1s0p.emf *: means percentual Cu metalization on each layer 70 µm modeled (traces) 35 µm, 90% metalization* 1,5 mm 70 µm, 5% metalization* PCB_Zth_2s2p.emf 35 µm, 90% metalization* *: means percentual Cu metalization on each layer PCB_si m_setup_TS DS O24.emf PCB 1s0p + 600 mm2 cooling PCB 2s2p / 1s0p footprint PCB_2s2p_vias_TSDSO24.emf

Data Sheet 12 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V General Product Characteristics

4.4.2 Thermal Impedance

Figure 9 Typical Thermal Impe dance. PCB setup according Chapter 4.4.1 Figure 10 Thermal Resistan ce on 1s0p PCB with various cooling surfaces 0.1 100 0.0001 0.001 0.01 0.1 1 10 100 1000 ZthJA [K/W] TA = 105 °C Time [s] ZthJA - BTS70012-ESP JEDEC 2s2p JEDEC 1s0p - 600 mm² JEDEC 1s0p - 300 mm² JEDEC 1s0p - footprint 0 100 200 300 400 500 600 RthJA [K/W] TA = 105 °C Cooling area [mm²] RthJA - BTS70012-1ESP JEDEC 1s0p

Data Sheet 13 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Logic Pins

5 Logic Pins

The device has 2 digital pins.

5.1 Input Pin (IN)

The input pin IN activates the output channel. Th e input circuitry is compatible with 3.3V and 5V microcontroller (see Chapter 10 for the complete application setup overview). The electrical equivalent of the input circuitry is shown in Figure 11. In case the pin is not used, it must be connected with a 10 k Ω resistor either to GND pin or to module ground. Figure 11 Input circuitry The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always higher than the voltage needed to ensure a “low” state. Figure 12 Input Threshold voltages and hysteresis GND IN IGND IDI VDI Input_IN_INTDIO.emf VS VS(CLAMP) RGND IDIESD VDI (CLAM P) Input _V DITH_ 2.emf VDI (TH ), MAX VDI (HYS) t VDI VDI (TH ) ,MIN I nternal channel activation signal t 0 x 1 x 0 VDI (T H)

Data Sheet 14 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Logic Pins

5.2 Diagnosis Pin

The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and can be used to reset the latched protection (Protection circuitry not di sabled by DEN). When DEN pin is set to “high”, the diagnosis is enabled (see Chapter 9.2 f o r m o r e d e t a i l s ) . W h e n i t i s s e t t o “ l o w ” , the diagnosis is disabled (IS pin is set to high impedance). The transition from “high” to “low” of DEN pin clears the protection la tch of the channel depending on the logic state of IN pin and DEN pulse length (see Chapter 8.3 for more details). The internal structure of diagnosis pins is the same as the one of input pins. See Figure 11 for more details.

5.3 Electrical Characteristics Logic Pins

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Digital Input (DI) pins = IN, DEN Table 7 Electrical Characteri stics: Logic Pins - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Digital Input Voltage Threshold VDI(TH) 0.8 1.3 2 V See Figure 11 and Figure 12 P_5.4.0.1 Digital Input Clamping Voltage VDI(CLAMP1) –7–V 1) IDI = 1 mA See Figure 11 and Figure 12 1) Not subject to production test - specified by design. P_5.4.0.2 Digital Input Clamping Voltage VDI(CLAMP2) 6.5 7.5 8.5 V IDI = 2 mA See Figure 11 and Figure 12 P_5.4.0.3 Digital Input Hysteresis VDI(HYS) –0 . 2 5 –V 1) See Figure 11 and Figure 12 P_5.4.0.4 Digital Input Current (“high”) IDI(H) 21 0 2 5 µ A VDI = 2 V See Figure 11 and Figure 12 P_5.4.0.5 Digital Input Current (“low”) IDI(L) 21 0 2 5 µ A VDI = 0.8 V See Figure 11 and Figure 12 P_5.4.0.6

Data Sheet 15 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Supply

6 Power Supply

The BTS70012-1ESP is supplied by VS, which is used for the internal logic as well as supply for the power output stage. VS has an undervoltage detection circuit, which prev ents the activation of the power output stage and diagnosis in case the applied voltage is below the undervoltage threshold ( VS < VS(OP)). During power up, the internal power on signal is set when supply voltage (VS) exceeds the minimum operating voltage (VS > VS(OP)).

6.1 Operation Modes

BTS70012-1ESP has the following operation modes in case of VS > VS(OP):

• O F F m o d e
• O N m o d e
• Diagnosis in ON mode
• Diagnosis in OFF mode
• F a u l t
• C L S m o d e The transition between operation modes is determined according to these variables:
• Logic level at IN pin
• PWM signal at IN pin
• Logic level at DEN pin
• Internal latch
• V DS voltage level The truth table in case of VS > VS(OP) is shown in Table 8. The behavior of BTS70012-1ESP as well as some parameters may change in dependence on the operation mode of the device. There are three parameters describing each operation mode of BTS70012-1ESP:
• Status of the output channel
• Status of the diagnosis
• Current consumption at VS pin (measured by I VS in OFF mode, IGND in all other operative modes) Table 8 Operation Mode truth table IN DEN Internal latch IIS Operative Mode Comment 0 0 0 leakage OFF DMOS channel is OFF 0 0 1 leakage OFF DMOS channel is OFF 0 1 0 leakage OFF_DIAG Diagnostic in OFF-mode open load Diagnostic in OFF-mode 0 1 1 fault Diagnostic in OFF-mode 1 0 0 leakage ON DMOS channel is ON, no diagnostic 10 1 l e a k a g e f a u l t D M O S c h a n n e l is switched OFF due to failure 11 0 IIS ON_DIAG DMOS channel is ON and diagnostic

Data Sheet 16 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Supply

6.1.1 OFF mode

When BTS70012-1ESP is in OFF mode, the output channel is OFF. The cu rrent consumption is minimum (see parameter IVS(OFF)). No Overtemperature, Overload protection mechanism and no diagnosis function is active when the device is in OFF mode.

6.1.2 ON mode

ON (IN = High; DEN = Low) mode is the normal operation mode of BTS70012-1ESP. Device current consumption is specified with IGND(ON_D) + IIS(OFF) (measured at GND pin because the current at VS pin includes the load current). Overcurrent and Overtemperature protections are active. No diagnosis function is active.

6.1.3 OFF_Diag mode

T h e d e v i c e i s i n O F F _ D i a g m o d e a s l o n g a s D E N p i n i s s e t t o “ h i g h ” a n d I N p i n i s s e t t o “ l o w ” . T h e o u t p u t channel is OFF. Depending on the load condition, either a fault current IIS(FAULT) or an Open Load in OFF current (IIS(OLOFF)) may be present at IS pin. In such situation, the current consumption of the device is increased.

6.1.4 ON_Diag mode

The device is in ON_Diag mode with current sense function enabled. Device current consumption is specified with IGND(ON_D). Depending on the load condition, either a fault current IIS(FAULT) or IIS current may be present at IS pin.

6.1.5 Fault mode

The device is in Fault mode as soon as a protection event happens which affects that the device switches off due to its protection function. In Fault mode, a IIS(FAULT) signal is present at IS pin during the DEN signal is "high".

6.1.6 CLS mode

The device has a Capacitive Load Switching mode (CLS ) implemented to charge capacitive loads. The CLS mode is entered when an input frequency of fVIN(CLS) with the duty cycle of DCVIN(CLS) is applied at the input pin (for more details see Chapter 7.2.3). The device current consumption in CLS is specified by the parameter IGND(ON_D). 1 1 1 fault fault DMOS channel is switched OFF due to failure fIN(CLS) X 0 leakage CLS DMOS channel is ON in Capacitive Load Switching mode Table 8 Operation Mode truth table IN DEN Internal latch IIS Operative Mode Comment

Data Sheet 17 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Supply

6.2 Undervoltage on VS

Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in ON mode) and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic switches OFF the output channel. As soon as the supply voltage VS is above the operative threshold VS(OP), the channel is sw itched ON again as shown in Figure 13. If the device is in OFF mode and the input is set to “high”, the channel will be switched ON if VS > VS(OP). Figure 13 VS undervoltage behavior t VS(HYS) t VS t PowerSuppl y_UV.vsd x VS(OP) VS(UV) VOUT IN

Data Sheet 18 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Supply

6.3 Electrical Characteristics Power Supply

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω Table 9 Electrical Characteri stics: Power Supply - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. VS pin Power Supply Undervoltage Shutdown VS(UV) 1.8 2.3 3.1 V VS decreasing IN = “high” From VDS ≤ 0.5 V to VDS = VS See Figure 13 P_6.4.0.1 Power Supply Minimum Operating Voltage VS(OP) 2.0 3.0 4.1 V VS increasing IN = “high” From VDS = VS to VDS ≤0.5 V See Figure 13 P_6.4.0.3 Power Supply Undervoltage Shutdown Hysteresis VS(HYS) –0 . 7 –V 1) VS(OP) - VS(UV) See Figure 13 1) Not subject to production test - specified by design. P_6.4.0.6 Breakdown Voltage between GND and VS Pins in Reverse Battery S(REV) 16 – 30 V 1) IGND(REV) = 7 mA TJ = 150 °C P_6.4.0.9

Data Sheet 19 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Supply

6.4 Electrical Characteristics Power Supply - Product Specific

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω

6.4.1 BTS70012-1ESP

Table 10 Electrical Characterist ics: Power Supply BTS70012-1ESP Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Supply Current Consumption in OFF Mode with Loads IVS(OFF)_85 –0 . 2 2 . 2 µ A 1) VS = 18 V VOUT = 0 V IN = DEN = “low” TJ ≤ 85 °C 1) Not subject to production test - specified by design. P_6.5.25.1 Supply Current Consumption in OFF Mode with Loads IVS(OFF)_150 –16 5 µ A VS = 18 V VOUT = 0 V IN = DEN = “low” T J = 150 °C P_6.5.25.2 Operating Current in ON_Diag Mode (Channel ON) IGND(ON_D) –23 . 3 m A VS = 18 V IN = DEN = “high” P_6.5.25.3 Operating Current in OFF_Diag Mode IGND(OFF_D) –1 . 2 1 . 8 m A VS = 18 V IN = “low”; DEN = “high” P_6.5.25.5

Data Sheet 20 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7 Power Stages

The high-side power stage is built using a N-channel vertical Power MOSFET with charge pump.

7.1 Output ON-State Resistance

The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 14 shows the variation of RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured at TJ = 150 °C. Figure 14 RDS(ON) variation factor The behavior in Reverse Polarity is described in Chapter 8.4.1. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 - 4 0 - 3 0 - 2 0 - 1 00 1 02 03 04 05 06 07 08 09 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 RDS(ON) variation factor Junction Temperature (°C) RDS(ON) variation over TJ Typical Reference value: "2" = RDS(ON),MAX @ 150 °C

Data Sheet 21 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7.2 Switching loads

7.2.1 Switching Resistive Loads

When switching resistive loads, the switching times and slew rates shown in Figure 15 can be considered. The switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF. Figure 15 Switching a Resistive Load IN t VOUT VIN(TH) (dV/dt)ON VIN(HYS) PDMOS t t Power St age_Swi tch Res.emf EON EOFF tON tON(DELAY) tOFF(DELAY) -(dV/dt)OFF tOFF 10% of VS 90% of VS 70% of VS 30% of VS 30% of VS 70% of VS

Data Sheet 22 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7.2.2 Switching Inductive Loads

When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device due to overvoltage, a voltage clamp mechanism is implem ented. The clamping structure limits the negative output voltage so that VDS = VDS(CLAMP). Figure 16 shows a concept drawing of the implementation. The clamping structure is available in all operation modes listed in Chapter 6.1. Figure 16 Output Clamp concept During demagnetization of inductive loads, energy has to be dissipated in BTS70012-1ESP. The energy can be calculated with Equation (7.1): (7.1) The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design of the component. Please refer to Chapter 4.2 for the maximum allowed values of EAS (single pulse energy) and EAR (repetitive energy). PowerStage_Clamp_INTDIO_1CH.emf High-side Channel VS RL VOUT I L VDS(CLAMP) IL VS OUT VDS GND VS(CLAMP) VSIS(CLAMP) RSEN SE RGND IS EV DS CLAMP() VS VDS CLAMP()– RL RL I⋅ L æö IL+ln⋅ L RL

Data Sheet 23 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7.2.3 Switching Capacitive Loads

When switching a resistive load with the Capacitive Load Switching (CLS) mode the switching times as well as the Switch-ON Slew Rate will change to tON_CLS, tON_CLS(DELAY), (dV/dt)ON_CLS as shown in Figure 17. The CLS mode is entered by applying a PWM signal at the IN pin with a frequency of fVIN(CLS) and a duty cycle of DCVIN(CLS). During this mode the thermal shut down temperature is reduced to TJ_CLS(DYN) and the device is set to auto- restart. Figure 17 Switching a Resistive Load with CLS mode The CLS mode has to be left after a maximum time of tCLS by setting the input to "high" or "low" state. A transition from the CLS mode to the ON mode will be automatically done when VDS < VDS(OLOFF). Before changing from CLS mode to normal mode, it shall be ensured that there is no short circuit at the output. To distinguish between short circuit and normal load, a current sense measurement shall be performed before leaving CLS mode. If the current meas urement delivers an expected value, the transition from CLS mode to normal mode is possible. If the current measurement deli vers an open load value (n o output current), it has to be assumed that there is either an open load or a short circuit at th e output. Additionally, a short circuit condition could be excluded by an external voltage measurement at the output. IN tVOUT VIN(TH) (dV/dt)ON_CLS VIN(HYS) t tON_CLS 10% of VS 90% of VS 70% of VS 30% of VS tON_CLS(DELAY) tCLS t nACT nCLS_ACT = 1 fVIN(CLS)

Data Sheet 24 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages Figure 18 Switching a Capacitive Load with CLS mode

7.2.4 Output Voltage Limitation

To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while the channel is diagnosed (DEN pin set to “high” - see Figure 19) bringing VDS equal or lower than VDS(SLC), the output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC) even for very small output currents. The VDS increase allows the current sensing circuitry to work more efficiently, providing better kILIS accuracy for output current in the low range. Figure 19 Output Voltage Limitati on activation during diagnosis ONCLS IN t t IL t nCLS_ACT = 1 tCLS nACT t VOUT t Operation Mode VDS(OLOFF) IN IL tDEN VDS VDS(SLC) t t t

Data Sheet 25 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7.3 Advanced Switching Characteristics

7.3.1 Inverse Current behavior

When VOUT > VS, a current IINV flows into the power output transistor (see Figure 20). This condition is known as “Inverse Current”. If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses therefore an increase of overall device temperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output stage is comparable to normal operation in RDS(ON). During Inverse Current condition, the channel remains in ON or OFF state as long as |IL| < |IL(INV)|. With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as |IL| < |IL(INV)| (see Figure 21). Figure 20 Inverse Current Circuitry OUT VS VBAT -ILINV Comp. VOUT > VS Gate Driver Device Logic GND PowerStage_Inverse_HEAT.emf RGND

Data Sheet 26 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages Figure 21 InverseON - Channel behavior in case of applied Inverse Current Note: No protection mechanism like Overtemperature or Overload protection is active during applied Inverse Currents. OFF OFF CASE 2 : Switch is OFFIN t IL t DMOS state t INVERSE NORMALNORMAL ON INVERSE NORMAL IL t DMOS state t ON CASE 1 : Switch is ONIN t NORMAL OFF ON CASE 4 : Switch OFF into Inverse Curren t IN t IL t DMOS state t INVERSE NORMALNORMAL ON INVERSE NORMAL IL t DMOS state t OFF CASE 3 : Switch ON into Inverse Curren t IN t NORMAL OFF ON ON OFF Power St age_InvCurr_INVON.emf

Data Sheet 27 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7.3.2 Cross Current robustness with H-Bridge configuration

When BTS70012-1ESP is used as high-side switch e.g. in a bridge configuration (the refore paired with a low- side switch as shown in Figure 22), the maximum slew rate applied to the output by the low-side switch must be lower than | dVOUT / dt |. Figure 22 High-Side switch used in Bridge configuration IN IN OUT OUT VS PowerStage_ PassiveSlew_P R O F E T1Ch.emf T T M ON (DC) OFF ON ( PWM) OFF Current through Motor Cross Current | dVOUT / dt | VS HSS 1 HSS 2 R/L cable VBAT

Data Sheet 28 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7.4 Electrical Characteristics Power Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω

7.4.1 Electrical Characteristics Power Stages

Table 11 Electrical Characterist ics: Power Stages - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Voltages Drain to Source Clamping Voltage at TJ = -40 °C VDS(CLAMP)_-40 33 36.5 42 V IL = 20 mA TJ = -40°C DEN = “high” See Figure 16 P_7.4.0.4 Drain to Source Clamping Voltage at T J ≥ 25 °C VDS(CLAMP)_25 35 38 44 V 1) IL = 20 mA TJ ≥ 25°C DEN = “high” See Figure 16 1) Tested at TJ = 150°C. P_7.4.0.5 Table 12 Electrical Characteristics: Power Stages Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Timings Switch-ON Delay t ON(DELAY) 10 70 140 μs VS = 13.5 V VOUT = 10% VS See Figure 15 P_7.4.5.13 Switch-ON Delay Capacitive Load Switching tON_CLS(DELAY) 20 550 1000 μs VS = 13.5 V VOUT = 10% VS See Figure 17 P_7.4.5.12 Switch-OFF Delay tOFF(DELAY) 10 50 160 μs VS = 13.5 V VOUT = 90% VS See Figure 15 P_7.4.5.2 Switch-ON Time tON 50 130 210 μs VS = 13.5 V VOUT = 90% VS See Figure 15 P_7.4.5.3 Switch-ON Time Capacitive Load Switching tON_CLS 350 1075 1800 μs VS = 13.5 V VOUT = 90% VS See Figure 17 P_7.4.5.10

Data Sheet 29 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages Switch-OFF Time tOFF 30 100 220 μs VS = 13.5 V VOUT = 10% VS See Figure 15 P_7.4.5.4 Switch-ON/OFF Matching tON - tOFF ΔtSW -85 -10 65 μs VS = 13.5 V P_7.4.5.19 Voltage Slope Switch-ON Slew Rate (d V/dt)ON 0.16 0.27 0.39 V/ μs VS = 13.5 V VOUT = 30% to 70% of VS See Figure 15 P_7.4.5.6 Switch-ON Slew Rate in CLS (d V/dt)ON_CLS 0.008 0.021 0.034 V/ μs VS = 13.5 V VOUT = 30% to 70% of VS See Figure 17 P_7.4.5.11 Switch-OFF Slew Rate -(d V/dt)OFF 0.16 0.27 0.39 V/ μs VS = 13.5 V VOUT = 70% to 30% of VS See Figure 15 P_7.4.5.7 Slew Rate Matching (dV/dt)ON - (dV/dt)OFF Voltages Output Voltage Drop Limitation at Small Load Currents V DS(SLC) 21 0 2 0 m V 1) IOUT = IOUT(OL) = 20 mA P_7.4.5.9 CLS Mode Input Frequency for CLS Mode Activation fVIN(CLS) 22 30 38 kHz 2) DCVIN(CLS) = 50% See Figure 17 P_7.4.5.14 Duty Cycle for CLS Mode Activation DCVIN(CLS) 30% 50% 70% 1) fVIN(CLS) =3 0k H z See Figure 17 P_7.4.5.15 Maximum Time in CLS Mode tCLS – – 100 ms 1) See Figure 18 P_7.4.5.16 Maximum Number of CLS Mode Activations nCLS(ACT) – – 50k 1) See Figure 18 P_7.4.5.17 Thermal Shutdown Temperature in CLS Mode (Dynamic) T J_CLS(DYN) –2 0 –K 1) P_7.4.5.18 1) Not subject to production test - specified by design 2) Functional test only Table 12 Electrical Characteristics: Power Stages (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 30 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages

7.5 Electrical Characteristics - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω 7.5.1 Power Output Stage - 1.2 m Ω Table 13 Electrical Characteristics: Power Stages - 1.2 m Ω Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Output characteristics ON-State Resistance at TJ =2 5° C RDS(ON)_25 –1 . 4 –m Ω 1) TJ = 25 °C P_7.5.23.1 ON-State Resistance at TJ = 150 °C ON-State Resistance in Cranking RDS(ON)_CRAN K ––2 . 9 m Ω TJ = 150 °C VS = 3.1 V P_7.5.23.3 ON-State Resistance in Inverse Current at TJ = 25 °C RDS(INV)_25 –1 . 5 –m Ω 1) TJ = 25 °C VS = 13.5 V IL = -4 A DEN = “low” see Figure 20 P_7.5.23.4 ON-State Resistance in Inverse Current at TJ = 150 °C RDS(INV)_150 ––2 . 9 m Ω TJ = 150 °C VS = 13.5 V IL = -4 A DEN = “low” see Figure 20 P_7.5.23.5 ON-State Resistance in Reverse Polarity at TJ = 25 °C RDS(REV)_25 –2 . 9 –m Ω 1) TJ = 25 °C VS = -13.5 V IL = -4 A see Figure 31 P_7.5.23.6 ON-State Resistance in Reverse Polarity at T J = 150 °C RDS(REV)_150 ––4 . 6 m Ω TJ = 150 °C VS = -13.5 V IL = -4 A P_7.5.23.7 Nominal Load Current IL(NOM) – 31.3 – A 1) TA = 85 °C TJ ≤ 150 °C P_7.5.23.8

Data Sheet 31 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Power Stages Output Leakage Current at TJ ≤ 85 °C IL(OFF)_85 –0 . 2 2 . 2 μA 1) VOUT = 0 V VIN = “low” TA ≤ 85 °C P_7.5.23.9 Output Leakage Current at TJ = 150 °C IL(OFF)_150 ––6 5 μA VOUT = 0 V VIN = “low” TA = 150 °C P_7.5.23.10 Inverse Current Capability IL(INV) – -31.3 – A 1) VS < VOUT IN = “high” see Figure 20 P_7.5.23.11 Voltage Slope Passive Slew Rate (e.g. for Half Bridge Configuration) | dVOUT / dt |– – 1 0 V / μs 1) VS = 13.5 V see Figure 22 P_7.5.23.12 Voltages Drain Source Diode Voltage | VDS(DIODE) | – 550 700 mV IL = -190 mA TJ = 150 °C P_7.5.23.13 Switching Energy Switch-ON Energy EON –1 . 5 –m J 1) VS = 18 V see Figure 15 P_7.5.23.14 Switch-OFF Energy EOFF –1 . 6 5 –m J 1) VS = 18 V see Figure 15 P_7.5.23.15 1) Not subject to production test - specified by design. Table 13 Electrical Characteristics: Power Stages - 1.2 m Ω (continued) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max.

Data Sheet 32 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection

8 Protection

The BTS70012-1ESP is protected agai nst Overtemperature, Overload, Reverse Ba ttery (with ReverseON) and Overvoltage. Overtemperature and Over load protections are wo rking when the device is in ON or ON_Diag mode but not during InverseON and ReverseON functi on. Overvoltage protection works in all operation modes. Reverse Battery protection works when the GND and VS pins are reverse supplied.

8.1 Overtemperature Protection

The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for the channel. An increase of junction temperature TJ above either one of the two thresholds ( TJ(ABS) or TJ(DYN)) switches OFF the overheated channe l to prevent destruction. The ch annel remains switched OFF until junction temperature has reached the “Reactivation” condition described in Table 14. The behavior is shown in Figure 23 (absolute Overtemperature Protection) and Figure 24 (dynamic Overtemperature Protection). TJ(REF) is the reference temperature used for dynamic temperature protection. Figure 23 Overtemperature Protection (Absolute) Over_Temperature_Behavior.emf IL(OVL0 ) IL t TJ IIS DEN Internal latch TJ( ABS) t t t t IN t IIS( FAULT ) IL(NOM) IIS = IL kILIS

Data Sheet 33 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection Figure 24 Overtemperature Protection (Dynamic) When the Overtemperature protection circuitry allows the channel to be switched ON again, the Intelligent Latch strategy described in Chapter 8.3 is followed. IL( OVL ) IL t TJ IIS DEN Internal Latch TJ( ABS) t t t t IN t IIS( FAULT) TJ( D YN ) IL / kILIS TJ(REF)

Data Sheet 34 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection

8.2 Overload Protection

The BTS70012-1ESP is protected in case of Overload or short circuit to ground. Two Overload thresholds are defined (see Figure 25) and selected automatically depending on the voltage VDS across the power DMOS:

• IL(OVL0) when VDS < 13 V
• IL(OVL1) when VDS > 22 V Figure 25 Overload Current Thresholds In order to allow a higher load inrush at low ambien t temperature, Overload th reshold is maximum at low temperature and decreases when TJ increases (see Figure 26). IL(OVL0) typical value rema ins approximately constant up to a junction temperature of +75 °C.

Data Sheet 36 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection

8.3 Protection and Diagnosis in case of Fault

Any event that triggers a protection mechanism (either Overtemperature or Overload) has 2 consequences:

• The channel switches OFF and the internal latch is set to “1”
• If the diagnosis is active for the channel, a current IIS(FAULT) is provided by IS pin (see Chapter 9.2.2 for further details) The channel can be switched ON again if all the protec tion mechanisms fulfill th e ”reactivation” conditions described in Table 14. Furthermore, the device has the intelligen t latch to protect itself against unwanted repetitive reactivation in fault condition.

8.3.1 Intelligent Latch Strategy

At normal condition, when IN is set to “high”, the channel is switched ON. In case of fault condition the output stage latches OFF. There are two ways to de-latch the switch. With IN pin: It is necessary to set the input pin to “low” for a time longer than tDELAY(LR) (“latch reset delay” time) to de-latch the channel. The channel can be al lowed to restart only if the “lat ch” conditions for the protection mechanisms are fulfilled (see Table 14 ). During the “latch reset delay” time, if the input is set to “high” the channel remains switched OFF and the timer tDELAY(LR) is reset. The timer tDELAY(LR) restarts as soon as the input pin is set to “low” again. The intelligent latch strategy is shown in Figure 30 (flowchart) and Figure 28 (timing diagram). With DEN pin: It is possible to “force” a reset of the internal latch without waiting for tDELAY(LR) by applying a pulse (rising edge followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a duration longer than tDEN(LR) to ensure a reset of the internal latch. The timing is shown in Figure 29. Table 14 Protection “Reactivation” Condition Fault condition Switch OFF ev ent “Reactivation” condition Overtemperature TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN) TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN) (including hysteresis) Overload IL ≥ IL(OVL) IL < 50 mA, TJ within TJ(ABS) and TJ(DYN) ranges (including hysteresis)

Data Sheet 38 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection Figure 30 Intelligen t Latch Flowchart Pr otection_PROFET_Flow_PDH.emf Fault (Overtemperature or Overload) Switch channel ON Switch channel OFF yes Latch = 1 IN is "high" yes Wait until IN is "low" then start counting for tDELAY(LR) IN is "low" tDELAY(LR) elapsed Continue latching for tDELAY(LR) yes no no yes Latch = 0 Latch = 1 no yes START Set DEN to „high“ Wait until DEN pulse > t DEN(LR) Latch = 0 DEN pulse > t DEN(LR) Yes nono yes no De-latching with DEN no Reactivation condition fulfilled (TJ and / or ΔT / and / or Overload) no yes

Data Sheet 39 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection

8.4 Additional protections

8.4.1 Reverse Polarity Protection

In Reverse Polarity condition (also known as Reverse Battery), the output stage is switched ON (see parameter RDS(REV)) because of ReverseON feature which limits the power dissipation in the output stage. Each ESD diode of the logic contributes to total power dissipation. The reverse current through the output stage must be limited by the connected load. The current through Digital Input pins has to be limited as well by an external resistor (please refer to the Absolute Maximum Ratings listed in Chapter 4.1 and to Application Information in Chapter 10). Figure 31 shows a typical application including a device with ReverseON. A current flowing into GND pin (-IGND) during Reverse Polarity condition is necessary to ac tivate ReverseON, therefore a resistive path between module ground and device GND pin must be present. Figure 31 Reverse Battery Protection (application example)

8.4.2 Overvoltage Protection

In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistor is still operational and follows the input pin. In addition to the output clamp for inductive loads as described in Chapter 7.2.2, there is a clamp mechanism available for Overvoltage protection for the logi c circuit and the output channel, monitoring the voltage between VS and GND pins (VS(CLAMP)). Protection_RevBatt_HEAT.emf High-side Channel L, C, R Microcontroller -IL -IGND-IIS IDI -VBA T(REV) ReverseON RDI RSEN SE RGND DIDO GND IS GND OUT VS

Data Sheet 40 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection

8.5 Protection against loss of connection

8.5.1 Loss of Battery and Loss of Load

The loss of connection to battery or to the load has no influence on device robustness when load and wire harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be handled. PROFET™ +2 12V devices can handle the indu ctivity of the wire harn ess up to 10 µH with IL(NOM). In case of applications where curren ts and/or the aforementioned indu ctivity are exceeded, an external suppressor diode (like diode DZ2 shown in Chapter 10) is recommended to handle the energy and to provide a well-defined path to the load current.

8.5.2 Loss of Ground

In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin and the microcontroller to ensure a channel switch OFF (as described in Chapter 10). Note: In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground path is available, which could keep the device operational during loss of device ground.

Data Sheet 41 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection

8.6 Electrical Characteristics Protection

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω

8.6.1 Electrical Characteristics Protection

Table 15 Electrical Characteri stics: Protection - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Thermal Shutdown Temperature (Absolute) TJ(ABS) 150 175 200 °C 1)2) See Figure 23 1) Functional test only. 2) Tested at TJ = 150°C only. P_8.6.0.1 Thermal Shutdown Hysteresis (Absolute) THYS(ABS) –3 0 –K 3) See Figure 23 3) Not subject to production test - specified by design. P_8.6.0.2 Thermal Shutdown Temperature (Dynamic) TJ(DYN) –8 0 –K 3) See Figure 24 P_8.6.0.3 Power Supply Clamping Voltage at TJ = -40 °C VS(CLAMP)_-40 33 36.5 42 V IVS = 5 mA TJ = -40 °C See Figure 16 P_8.6.0.6 Power Supply Clamping Voltage at TJ ≥ 25 °C VS(CLAMP)_25 35 38 44 V 2) IVS = 5 mA TJ ≥ 25 °C See Figure 16 P_8.6.0.7 Power Supply Voltage Threshold for Overcurrent Threshold Reduction in case of Short Circuit V S(JS) 20.5 22.5 24.5 V 3) Setup acc. to AEC- Q100-012 Rsupply = 10 mΩ Lsupply = 5 µH Rshort = 25 mΩ Lshort = 5 µH P_8.6.0.8 Table 16 Electrical Characteristics: Protection Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Latch Reset Delay Time after Fault Condition tDELAY(LR) 40 70 100 ms 1) See Figure 28 1) Functional test only. P_8.6.4.1 Minimum DEN Pulse Duration for Latch Reset tDEN(LR) 50 100 150 µs 2) See Figure 29 2) Not subject to production test - specified by design. P_8.6.4.2

Data Sheet 42 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Protection

8.7 Electrical Characteristics Pr otection - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω 8.7.1 Protection Power Output Stage - 1.2 m Ω Table 17 Electrical Characteri stics: Protection - 1.2 mΩ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Overload Detection Current at TJ = -40 °C IL(OVL0)_-40 187 217 248 A 1) TJ = -40 °C dI/dt = 0.4 A/µs see Figure 25 and Figure 26 1) Functional test only. P_8.7.24.1 Overload Detection Current at TJ = 25 °C IL(OVL0)_25 180 209 238 A 2) TJ = 25 °C dI/dt = 0.4 A/µs see Figure 25 and Figure 26 P_8.7.24.7 Overload Detection Current at TJ = 150 °C IL(OVL0)_150 146 170 193 A 2) TJ = 150 °C dI/dt = 0.4 A/µs see Figure 25 and Figure 26 P_8.7.24.8 Overload Detection Current at High VDS IL(OVL1) – 130 – A 2) dI/dt = 0.4 A/µs see Figure 25 2) Not subject to production test - specified by design. P_8.7.24.5 Overload Detection Current Jump Start Condition IL(OVL_JS) – 130 – A 2) VS > VS(JS) dI/dt = 0.4 A/µs see Figure 27 P_8.7.24.6

Data Sheet 43 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Diagnosis

9 Diagnosis

For diagnosis purpose, the BTS70012-1ESP provides a sense current signal ( IIS) at pin IS. In case of disabled diagnostic (DEN pin set to “low”), IS pin becomes high impedance. A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ. Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS pin to the sense current output of other devices, if they are supplied by a different battery feed. See Figure 32 for details as an overview. Figure 32 Diagnosis Block Diagram Diagnosis_HEAT_1CH.emf IIS(FAULT) OUT VS VDS(OLOFF) IIS(OLOFF) IS Output Channel IL / kILIS MUX Latch DEN Overtemperature IS Pin Control Logic IN T RSEN SE

Data Sheet 44 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Diagnosis

9.1 Overview

Table 18 gives a quick reference to the state of the IS pin during BTS70012-1ESP operation.

9.2 Diagnosis in ON state

A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions are fulfilled:

• The power output stage is switched ON with VDS < VDS(OLOFF)
• The diagnosis is enabled
• No fault (as described in Chapter 8.3) is present or was present and not cleared yet (see Chapter 9.2.2 for further details) If a “hard” failure mode is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin. Table 18 SENSE Signal, Function of Application Condition Application Condition Input level DEN level VOUT Diagnostic Output Normal operation “low” “high” ~ GND Z IIS(FAULT) if latch ≠ 0 Short circuit to GND ~ GND Z IIS(FAULT) if latch ≠ 0 Overtemperature Z IIS(FAULT) Short circuit to VS VS IIS(OLOFF) (IIS(FAULT) if latch ≠ 0) Open Load < VS - VDS(OLOFF) > VS - VDS(OLOFF) 1) With additional pull-up resistor. Z IIS(OLOFF) (in both cases IIS(FAULT) if latch ≠ 0) Inverse current VOUT > VS IIS(OLOFF) (IIS(FAULT) if latch ≠ 0) Normal operation “high” ~ VS IIS = IL / kILIS Overcurrent < VS IIS(FAULT) Short circuit to GND ~ GND IIS(FAULT) Overtemperature Z IIS(FAULT) Short circuit to VS VS IIS < IL / kILIS Open Load ~ VS 2) The output current ha s to be smaller than IL(OL). IIS = IIS(EN) Under load (e.g. Output Voltage Limitation condition) ~ VS 3) The output current has to be higher than IL(OL). IIS(EN) < IIS < IL(NOM) / kILIS Inverse current VOUT > VS IIS = IIS(EN) CLS mode “pwm” “high” < VS - VDS(OLOFF) Z All conditions n.a. “low” n.a. Z

9.2.1 Current Sense ( kILIS)

Figure 34. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).

• A well-defined and precise current ( IL(CAL)) is applied at the output during End of Line test at customer side
• The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL))
• Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by ΔkILIS The derating of kILIS after calibration is calculated using the formulas in Figure 33 and it is specified by ΔkILIS Figure 33 ΔkILIS calculation formulas The calibration is intend ed to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H. Figure 34 Current Sense Ratio in Open Load at ON condition Diagnosis_dKILIS.emf IIS ILIL(OL) IIS(OL ) Di agn o s i s_ OLON _adv .em f IIS(EN)

Data Sheet 46 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Diagnosis

9.2.2 Fault Current ( IIS(FAULT))

As soon as a protection event occurs, the value of the internal latch (see Chapter 8.3 for more details) is changed from 0 to 1, and a current IIS(FAULT) is provided by pin IS when DEN is set to “high”. If internal latch is 1, and it is not reset, the current IIS(FAULT) is provided each time the device diagnosis is activated by DEN=High. Figure 35 shows the relation between IIS = IL / kILIS, IIS(SAT) and IIS(FAULT). Figure 35 SENSE behavior - overview

9.3 Diagnosis in OFF state

When a power output stage is in OFF state, the BT S70012-1ESP can measure the drain-source voltage and compare it with a threshold voltage. In this way, us ing some additional external components (a pull-down resistor and a switchable pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to battery. If a Fault co ndition was detected by the device (if internal latch is 1, fault current is provided by IS pin independent of drain-source or output voltage, as long as DEN=High) a current IIS(FAULT) is provided by IS pin each time the channel diagnosis is checked also in OFF state. See Chapter 9.2.2 for further details.

9.3.1 Open Load current ( IIS(OLOFF))

In OFF state, when DEN pin is set to “high”, the VDS voltage is compared with a threshold voltage VDS(OLOFF). If the load is properly connected and there is no short circuit to battery, VDS ~ VS therefore VDS > VDS(OLOFF). When the diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. Figure 36 shows the relationship between IIS(OLOFF) and IIS(FAULT) as functions of VDS. The two currents do not overlap making it always possible to differentiate between Open Load in OFF and Fault condition. Diagn osis_HEAT_IISFAU LT_IISSAT.emf IIS IL IIS (SA T) IIS (FA ULT ) IL / kILI S IL(OVL).min IIS (SA T) .min IIS (FA ULT ) .min IL(OVL).max IIS (FA ULT ) .max IIS (SA T) .max

Data Sheet 48 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Diagnosis

9.4 SENSE Timings

Figure 38 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load change). As a proper signal cannot be established before the load current is stable (therefore before tON), tsIS(DIAG) ≤ 3 × ( tON_max + tsIS(ON)_max ). Figure 38 SENSE Settling / Disabling Timing t t t IL IIS DEN t ONOFF OFF Diagnose_PROFET_SENSE_timings_He at.emf IN tsIS(DI AG) tsI S(LC ) tsIS(O F F)tsIS(ON)tsIS(O F F)

Data Sheet 49 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Diagnosis

9.5 Electrical Characteristics Diagnosis

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω Table 19 Electrical Characteri stics: Diagnosis - General Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SENSE Saturation Current IIS(SAT) 4.4 – 15 mA 1) VSIS = VS - VIS ≥ 2 V See Figure 35 P_9.6.0.1 SENSE Leakage Current when Disabled IIS(OFF) –0 . 0 1 0 . 5 µ A D E N = “ l o w ” VIS = 0 V P_9.6.0.2 SENSE Leakage Current when Enabled at TJ ≤ 85 °C IIS(EN)_85 –0 . 2 1µ A 1) TJ ≤ 85 °C DEN = “high” IL = 0 A See Figure 34 1) Not subject to production test - specified by design. P_9.6.0.3 SENSE Leakage Current when Enabled at TJ = 150 °C IIS(EN)_150 –0 . 2 1µ A TJ = 150 °C DEN = “high” IL = 0 A See Figure 34 P_9.6.0.4 Saturation Voltage in kILIS Operation S - VIS) VSIS_k –0 . 5 1V 1) VS = 6 V IN = DEN = “high” IL ≤ 2 * IL(NOM) P_9.6.0.6 Saturation Voltage in Open Load at OFF Diagnosis (VS - VIS) VSIS_OL –0 . 5 1V 1) VS = 6 V IN = “low” DEN = “high” P_9.6.0.7 Saturation Voltage in Fault Diagnosis S - VIS) VSIS_F –0 . 5 1V 1) VS = 6 V IN = “low” DEN = “high” latch ≠ 0 P_9.6.0.8 Power Supply to IS Pin Clamping Voltage at T J =- 4 0° C VSIS(CLAMP)_- 33 36.5 42 V IIS = 1 mA TJ = -40 °C See Figure 16 P_9.6.0.9 Power Supply to IS Pin Clamping Voltage at T J ≥25 °C VSIS(CLAMP)_25 35 38 44 V 2) IIS = 1 mA TJ ≥ 25 °C See Figure 16 2) Tested at TJ = 150°C. P_9.6.0.10

Data Sheet 50 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Diagnosis

9.5.1 Electrical Characteristics Diagnosis

Table 20 Electrical Characteristics: Diagnosis Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. SENSE Open Load in OFF Current SENSE Open Load in OFF Delay Time tIS(OLOFF)_D 70 185 300 µs VDS < VOL(OFF) from IN falling edge to VIS = RSENSE * 0.9 * IIS(OLOFF),MIN DEN = “high” P_9.6.4.4 Open Load VDS Detection Threshold in OFF State SENSE Settling Time with Nominal Load Current Stable tsIS(ON) –54 0 µ s IL = IL(NOM) DEN from “low” to “high” P_9.6.4.6 SENSE Disable Time tsIS(OFF) –52 0 µ s 1) From DEN falling edge to IIS = IIS(OFF) See Figure 38 1) Not subject to production test - specified by design. P_9.6.4.8 SENSE Settling Time after Load Change tsIS(LC) –52 0 µ s 1) from IL = IL22 to IL = IL23 See Figure 38 P_9.6.4.9 SENSE Settling Time after Load Change with Small Load Current tsIS(LC)_SLC – 500 800 µs 1) DEN = “high” Load Change from IL22 to IL10 P_9.6.4.15

Data Sheet 51 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Diagnosis

9.6 Electrical Characteristics Diagnosis - Power Output Stages

VS = 6 V to 18 V, TJ = -40 °C to +150 °C Typical values: VS = 13.5 V, TJ = 25 °C Typical resistive load connected to the output for testing (unless otherwise specified): RL = 2.1 Ω 9.6.1 Diagnosis Power Output Stage - 1.2 m Ω Table 21 Electrical Characte ristics: Diagnosis - 1.2 mΩ Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Open Load Output Current at IIS = 8 µA IL(OL)_8u 82 – 464 mA IIS = IIS(OL) = 8 µA see Figure 34 P_9.7.26.3 Current Sense Ratio at IL = IL07 kILIS07 -65% 34100 +65% IL07 = 200 mA P_9.7.26.11 Current Sense Ratio at IL = IL10 kILIS10 -65% 34100 +65% IL10 = 700 mA P_9.7.26.14 Current Sense Ratio at IL = IL13 kILIS13 -55% 34100 +55% IL13 = 2 A P_9.7.26.17 Current Sense Ratio at IL = IL17 kILIS17 -40% 34100 +40% IL17 = 7 A P_9.7.26.21 Current Sense Ratio at IL = IL20 kILIS20 -24% 34100 +24% IL20 = 20 A P_9.7.26.24 Current Sense Ratio at IL = IL22 kILIS22 -8% 34100 +8% IL22 = 30 A P_9.7.26.26 Current Sense Ratio at IL = IL23 kILIS23 -8% 34100 +8% 1) IL23 = 35 A P_9.7.26.31 SENSE Current Derating with Low Current Calibration ΔkILIS(OL) -30 0 +30 % 1) IL(CAL) = IL10 IL(CAL)_H = IL13 IL(CAL)_L = IL07 TA(CAL) = 25 °C P_9.7.26.27 SENSE Current Derating with Nominal Current Calibration Δk ILIS(NOM) -5 0 +5 % 1) IL(CAL) = IL22 IL(CAL)_H = IL23 IL(CAL)_L = IL20 TA(CAL) = 25 °C 1) Not subject to production test - specified by design. P_9.7.26.29

Data Sheet 52 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V

Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.

10.1 Application setup

Figure 39 BTS70012-1ESP Application Diagram Note: This is a very simplified example of an applicatio n circuit. The function must be verified in the real application. PROFET™ +2 12V App_1CH_INTD IO_CVG.emf Microcontroller VDD DZ2 CVS2 Logic Supply Logic GND Power GND VSS GPIO RIN IN GPIO RDEN DEN CVS GND RGND CVSGND ROL RPD COUT0 ZWIRE DZ1 ISADC RADC RIS_PROT RSENSECSENSE Optional Optional Chassis GND VBAT Optional ZWIRE ZLOAD* *See Chapter 1 „Potential Applications“ OUT VS

Data Sheet 53 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V

10.2 External Components

10.3 Further Application Information

• Please contact us for information regarding the Pin FMEA
• For further information you may contact http://www.infineon.com/ Table 22 Suggested Component values Reference Value Purpose RIN 4.7 kΩ Protection of the microcontroller during Overvoltage and Reverse Polarity Necessary to switch OFF BTS70012-1ESP output during Loss of Ground RDEN 4.7 kΩ Protection of the microcontroller during Overvoltage and Reverse Polarity Necessary to switch OFF BTS70012-1ESP output during Loss of Ground RPD 47 kΩ Output polarization (pull-down) Ensures polarization of BTS70012-1ESP outputs to distinguish between Open Load and Short to VS in OFF Diagnosis ROL 1.5 kΩ Output polarization (pull-up) Ensures polarization of BTS70012-1ESP output during Open Load in OFF diagnosis COUT 10 nF Protection of BTS70012-1ESP ou tput during ESD events and BCI T1 BC 807 Switch the battery voltage for Open Load in OFF diagnosis CVS 100 nF Filtering of voltage sp ikes on the battery line CVSGND 47 nF Buffer capacitor for fast transient See Table 5 (P_4.3.0.7) for the boundary conditions A placeholder on PCB layout is recommended DZ2 33 V TVS Diode Transient Voltage Suppressor diode Protection during Overvoltage and in case of Loss of Battery while driving an inductive load CVS2 – Filtering / buffer capacitor located at VBAT connector RSENSE 1.2 kΩ SENSE resistor RIS_PROT 4.7 kΩ Protection during Overvoltage, Reverse Polarity, Loss of Ground Value to be tuned according to microcontroller specifications DZ1 7 V Z-Diode Protection of microcontroller during Overvoltage RADC 4.7 kΩ Protection of microcontroller ADC input during Overvoltage, Reverse Polarity, Loss of Ground Value to be tuned according to microcontroller specifications CSENSE 220 pF Sense signal filtering A time constant (RADC + RIS_PROT) * CSENSE longer than 1 µs is recommended RGND 47 Ω Protection in case of Overvoltage and Loss of Battery while driving inductive loads

Data Sheet 54 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Package Outlines Figure 40 PG-TSDSO-24 (Thin (Slim) Dual Small Outline 24 pins) Package drawing

Data Sheet 55 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Package Outlines Figure 41 PG-TSDSO-24 (Thin (Slim) Dual Small Outline 24 pins) Package pads and stencil Green product (RoHS compliant) To meet the world-wide customer requirements for en vironmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages

Data Sheet 56 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V

Revision History

Table 23 BTS70012-1ESP - List of changes Revision Changes 1.20, 2022-12-16 Icon “PRO-SIL™ ISO 26262- ready” added to front page Marking on front page updated (BTS70012-1ESP → 70012-1ESP) Basic Features list updated Figure 9, Figure 10, Figure 13, Figure 26 updated Table 1, Table 8, Table 14, Table 18 updated P_6.4.0.7 removed 1.10, 2020-12-14 Typo fixed (PROFET™+2 → PROFET™ +2) 1.00, 2020-10-16 Data Sheet available

Data Sheet 57 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V Table of Contents

Data Sheet 58 Rev. 1.20 2022-12-16 BTS70012-1ESP PROFET™ +2 12V

All referenced product or service names and trademarks are the property of their respective owners. Edition 2022-12-16 Published by Infineon Technologies AG

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Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference Z8F65710207 IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's comp liance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. Please read the Important Notice and Warnings at the end of this document © 2022 Infineon Technologies AG. All Rights Reserved.