BTS6460SF

BTS6460SF INFINEON | Alldatasheet

Document overview

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Technical content

Rev. 1.0, 2010-04-12 SPOC - BTS6460SF For Advanced Front Light Control SPI Power Controller

Data Sheet 2 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Table of Contents Table of Contents

Data Sheet 3 Rev. 1.0, 2010-04-12

SPOC - BTS6460SF PG-DSO-36-43 BTS6460SF Data Sheet 4 Rev. 1.0, 2010-04-12 For Advanced Front Light Control SPI Power Controller SPOC - BTS6460SF 1O v e r v i e w

Features

• 16 bit serial peripheral interface for control and diagnosis
• Integrated PWM generator
• 3.3 V and 5 V compatible logic pins
• Very low stand-by current
• Enhanced electromagnet ic compatibility (EMC) for bulbs as well as LEDs with increased slew rate
• Stable behavior at under voltage
• Device ground independent from load ground
• Green Product (RoHS-Compliant)
• AEC Qualified

Description

The SPOC - BTS6460SF is a four channel high-side smart power switch in PG-DSO-36-43 package providing embedded protective functions. It is especially designe d to control standard exterior lighting in automotive applications. In order to use the same hardware, the device can be configured to bulb or LED mode for channel 2 and channel 3. As a result, both load types are optimized in terms of switching and diagnosis behavior. It is specially designed to drive exterior lamps up to 65W, 27W and 10W and HIDL. Product Summary Operating Voltage Power Switch VBB 4.5 … 28 V Logic Supply Voltage VDD 3 . 0…5 . 5V Supply Voltage for Load Dump Protection VBB(LD) 40 V Maximum Stand-By Current at 25 °C IBB(STB) 4.5 µA Typical On-State Resistance at Tj = 25 °C channel 0, 1 channel 2, 3 RDS(ON,typ) 3.5 mΩ 11 mΩ Maximum On-State Resistance at Tj = 150 °C channel 0, 1 channel 2, 3 RDS(ON,max) 9m Ω 28 mΩ SPI Access Frequency fSCLK(max) 5M H z

Data Sheet 5 Rev. 1.0, 2010-04-12 Configuration and status diagnosis ar e done via SPI. The SPI is daisy chai n capable. The device provides a current sense signal per channel that is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over load and over temperature flag is provided in the SPI diagnosi s word. A multiplexed switch bypass monitor provides short-circuit to VBB diagnosis. In OFF state a current source can be switched to the output of one selected channel in order to detect an open load. Additionally, there is an integrated PWM generator im plemented, which allows autonomous PWM operation with programmable phase shifts, duty cycles and PWM frequencies. The status diagnosis and the current sense signal is available for each channel. The SPOC - BTS6460SF provides a fail-safe feature via limp home input pin. The power transistors are built by N-channel vertical power MOSFETs with charge pumps. Protective Functions

• Reverse battery protecti on with external components
• Reversave TM - Reverse battery protection by self turn on of all channels
• Short circuit protection
• Over load protection
• Thermal shutdown with latch and dynamic temperature sensor
• Over current tripping
• Over voltage protection
• Loss of ground protection
• Electrostatic discha rge protection (ESD) Diagnostic Functions
• Multiplexed proportional load current sense signal (IS)
• Enable function for current s ense signal configurable via SPI
• High accuracy of current sense signal at wide load current range
• Current sense ratio ( kILIS) configurable for LEDs or bulbs for channel 2 and 3
• Very fast diagnosis in LED mode
• Feedback on over temperature and over load via SPI
• Multiplexed switch bypass monitor provides short circuit to VBB detection
• Integrated, in two steps programmable current source for open load in OFF-state detection Application Specific Functions
• Fail-safe activation via LHI pin

Applications

• High-side power switch for 12 V grounded loads in automotive applications
• Especially designed for standard exterior lighting like high beam, low beam, indicator, parking light and equivalent LEDs
• Load type configuration via SPI (bulbs or LEDs) for optimized load control
• Replaces electromechanical relays, fuses and discrete circuits

Data Sheet 6 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Block Diagram 2B l o c k D i a g r a m Figure 1 Block Diagram SPOC - BTS6460SF limp home control LED mode control 321channel 0 power supply driver logic gate control charge pump clamp for inductive load over current protectionload current sense temperature sensor ESD protection GND SPI current sense multiplexer SO SCLK SI CS switch bypass monitor VBB OUT3 OUT2 OUT1 OUT0 IN2 IN3 IN1 PWM generator VDD LHI ISSY PCLK IS

Data Sheet 7 Rev. 1.0, 2010-04-12

2.1 Terms

Figure 2 shows all terms used in this data sheet. Figure 2 Terms In all tables of electrical characteristics is valid: Channel related symbols without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS0 … VDS3). values in bold letters (e.g. 0) are default values. IDD VDD VSO VIN2 ISI VIN3 ICS VBB IIS IBB VDD SI CS IS VBB VSI VCS VSCLK VIN1 IIN1 IN1 IN2 ISCLK SCLK VIS IIN3 IN3 GND IGND VLHI LHI OUT0 IL0 OUT1 IL1 OUT2 IL2 OUT3 IL3 VOUT3 VOUT2 VDS3 VDS2 VOUT1 VOUT0 VDS1 VDS0 ISO IIN2 Terms_PWM.emf ILHI PCLK IPCLK VPCLK IISSY ISSY VISSY

Data Sheet 8 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Pin Configuration

3 Pin Configuration

3.1 Pin Assignment SPOC - BTS6460SF

Figure 3 Pin Configuration PG-DSO-36-43 (top view) OUT1 OUT2 OUT2 VBB VBB OUT1 OUT1 OUT1 TEST n.c. n.c. GND 18 19 2017 IN3 OUT0 OUT0 OUT0 OUT0 IN1 IN2 VBB VBB GND LHI CS SCLK SI OUT3 OUT3 VBB TEST VBB PCLK VDD ISSY SO IS

Data Sheet 9 Rev. 1.0, 2010-04-12

3.2 Pin Definitions and Functions

1) All VBB pins have to be connected. VBB – Positive power supply for high-side power switch

19 VDD – Logic supply (5 V)

15, 22 GND – Ground connection Parallel Input Pins (integrated pull-down, leave unused pins unconnected)

16 IN1 I Input signal of channel 1 (high active)

17 IN2 I Input signal of channel 2 (high active)

18 IN3 I Input signal of channel 3 (high active)

3, 4, 5, 6 2) All outputs pins of each channel have to be connected. OUT0 O Protected high-side power output of channel 0 31, 32, 33, 34 2) OUT1 O Protected high-side power output of channel 1 29, 30 2) OUT2 O Protected high-side power output of channel 2 7, 8 2) OUT3 O Protected high-side power output of channel 3 SPI, PWM & Diagnosis Pins

14 CS I Chip select of SPI interface (low active); Integrated pull up

13 SCLK I Serial clock of SPI interface

12 SI I Serial input of SPI interface (high active)

11 SO O Serial output of SPI interface

27 PCLK I PWM clock reference signal

21 IS O Current sense output signal

20 ISSY O Current sense synchronization signal

Limp Home Pin (integrated pull-down, pull-down resistor recommended)

10 LHI I Limp home activation signal (high active)

23, 24 n.c. – not connected, internally not bonded 25, 26 TEST – Test pins, internally bonded and pulled down, do not connect

Data Sheet 10 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF

Electrical Characteristics

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Absolute Maximum Ratings 1) Tj = -40 to +150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions min. max. Supply Voltage

4.1.1 Power supply voltage

VBB -0.3 28 V – 4.1.2 Logic supply voltage VDD -0.3 5.5 V –

4.1.3 Reverse polarity voltage according Figure 30 -Vbat(rev) –1 6 V TjStart = 25 °C

t ≤ 2m i n . 2)

4.1.4 Supply voltage for short circuit protection (single

pulse) VBB(SC) V RECU = 20 mΩ l = 0 or 5 m 3) channel 0, 1 0 24 RCable = 6 mΩ/m LCable = 1 µH/m channel 2, 3 0 24 RCable = 16 mΩ/m LCable = 1 µH/m

4.1.5 Supply voltage for lo ad dump protection with

VBB(LD) –4 0 V RI = 2 Ω 4) t = 400 ms 4.1.6 Current through ground pin IGND –2 5 m A t ≤ 2m i n . 4.1.7 Current through VDD pin IDD -25 12 mA t ≤ 2m i n . Power Stages

4.1.8 Load current

IL -IL(LIM) IL(LIM) A 5)

4.1.9 Maximum energy dissipation

EAS mJ 6) Tj(0) = 150 °C channel 0, 1 – 180 IL(0) = 5 A channel 2, 3 – 45 IL(0) = 2 A Diagnosis Pin 4.1.10 Current through sense pin IS IIS -8 8 mA t ≤ 2m i n . Input Pins 4.1.11 Voltage at input pins VIN -0.3 5.5 V – 4.1.12 Current through input pins IIN -0.75 -2.0 0.75 2.0 mA – t ≤ 2m i n . SPI Pins 4.1.13 Voltage at chip select pin VCS -0.3 VDD + 0.3 V – 4.1.15 Voltage at serial input pin VSI -0.3 VDD + 0.3 V – 4.1.17 Voltage at serial clock pin VSCLK -0.3 VDD + 0.3 V – 4.1.19 Voltage at serial out pin VSO -0.3 VDD + 0.3 V –

Data Sheet 11 Rev. 1.0, 2010-04-12 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. PWM Clock and Sense Synchronization Pin 4.1.21 Voltage at PWM clock input pin VPCLK -0.3 VDD + 0.3 V – 4.1.22 Current through PWM clock input pin IPLCK -0.75 -2.0 0.75 2.0 mA – t ≤ 2m i n . 4.1.23 Voltage at sense synchronization pin VISSY -0.3 VDD + 0.3 V – Limp Home Pin

4.1.25 Voltage at limp home input pin

VLHI -0.3 5.5 V – 4.1.26 Current through limp home input pin ILHI -0.75 -2.0 0.75 2.0 mA – t ≤ 2m i n . Temperatures

4.1.27 Junction temperature Tj -40 150 °C–

4.1.28 Dynamic temperature increase while switching ∆Tj –6 0 K –

4.1.29 Storage temperature Tstg -55 150 °C–

4.1.30 ESD susceptibility HBM

OUT pins vs. VBB other pins incl. OUT vs. GND VESD kV HBM 1) Not subject to production test, specified by design. 2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. 3) In accordance to AEC Q100-012 and AEC Q101-006. 4) R I is the internal resistance of the load dump pulse generator. 5) Over current protection is a protection feature. Operatio n in over current protection is considered as “outside” normal operating range. Protection features are not designed for continuous repetitive operation. 6) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse 7) ESD resistivity, HBM according to EIA/JESD 22-A 114B (1.5 kΩ, 100 pF) Absolute Maximum Ratings (cont’d)1) Tj = -40 to +150 °C; all voltages with respect to ground (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions min. max.

Data Sheet 12 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF

4.2 Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

4.2.1 Junction to Soldering Point 1)

1) Not subject to production test, specified by design. RthJSP – – 20 K/W measured to pin 1, 2, 9, 28, 35, 36

4.2.2 Junction to Ambient 1) RthJA –3 5 –K / W 2)

2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer.

Data Sheet 13 Rev. 1.0, 2010-04-12

5 Power Supply

The SPOC - BTS6460SF is supplied by two supply voltages VBB and VDD. The VBB supply line is used by the power switches. The VDD supply line is used by the SPI related circuitry and for driving the SO line. A capacitor between pins VDD and GND is recommended as shown in Figure 30. There is a power-on reset function implemented for the VDD logic power supply. After start-up of the logic power supply, all SPI registers are reset to their default values. The SPI interface including daisy chain function is active as soon as VDD is provided in the specified range independent of VBB. First SPI data are the output register values with TER = 1. Specified parameters are valid for the supply voltage range according VBB(nor) or otherwise specified. For the extended supply voltage range according VBB(ext) device functionality (switchi ng, diagnosis and protection functions) are still given, parameter deviations are possible.

5.1 Power Supply Modes

The following table shows all possible power supply modes for VBB, VDD and the pin LHI.

5.1.1 Stand-by Mode and Device Wake-up Mechanisms

Stand-by mode is entered as soon as the current sense multiplexer ( DCR.MUX) is in default (stand-by) position, the PWM start bit is reset (PCR.PST = 0b) and all input pins are not set. All error latches are cleared automatically in stand-by mode. As soon as stand-by mode is entered, register HWCR.STB is set. To wake -up the device, the current sense multiplexer (DCR.MUX) is programmed different to default (s tand-by) position or the PWM start bit is set (PCR.PST = 1b). The power-on wake up time tWU(PO) has to be considered for both cases. Idle mode parameters are valid, when all channels are switched off, but the current sense multiplexer is not in default position, and VDD supply is available. Note: A transition from operation to stand-by mode does not reset the SPI registers. So, if VDD is present and SPI is programmed, a changing to MUX = 111b does not reset the SPI registers. An activation of the channels via the input pin INx will wake up the device with the former SPI register settings. Power Supply Modes Off Off SPI on Reset Off On via INx Limp Home mode without SPI Normal operation Limp Home mode with SPI 1) SPI read only VDD 0V 0V 5V 5V 0V 0V 0V 5V 5V L H I 0 V5 V0 V5 V0 V 0 V 5 V 0 V 5 V Power stage, protection – – – – – ✓ 2) Channel 1, 2 and/or 3 activated according to the state of INx ✓2) ✓✓ 2) SPI (logic) – – ✓✓ reset reset reset ✓ reset3) 3) SPI reset only with applied VBB voltage Stand-by current – – – – ✓✓ 4) 4) When INx = low – ✓5) 5) When DCR.MUX = 111b, INx = low and PCR.PST = 0b 6) When all channels are in OFF-state and DCR.MUX ≠ 111b 7) Current sense disabled in limp home mode

Data Sheet 14 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Power Supply Activating one of the outputs via the input pi ns (INx = high) will wake-up the de vice out of stand-by mode. The power stages are working without VD D supply according to the table abov e. The output turn-on times will be extended by the stand-by channel wake up time tWU(STCH) as long as no other channel is active. If one channel is active already before channel turn-on times ton (6.5.12) can be considered. Note: In the operation with VDD = 0 V and INx = high a switching off of all input signals will turn the device in stand- by mode. In stand-by mode the error latches are cleared. Limp home (LHI = high) applied for a time longer than tLH(ac) will wake-up the device out of stand-by mode after the power-on wake up time tWU(PO) and it is working without VDD supply. Channels 1, 2 and 3 can be activated via the input pins INx. The error latches can be cleared by a low-high transition at the according input pin.

5.2 Reset

There are several reset trigger implemented in the de vice. They reset the SPI registers including the over temperature latches to their default values. The po wer stages will switch off, if they are activated via the SPI register OUT.n. If the power stages are activated via the parallel input pins they are not affected by the reset signals. The ERR-flags are cleared by those reset triggers. The over temperature protection and latches are functional after a reset trigger. Note: During a reset only the channels 1, 2 and 3 can be activated via the according input pins. The input assigned mode is not available during a reset. The first SPI transmission after any ki nd of reset contains at pin SO the read information from the standard diagnosis, the transmission error bit TER is set. Power-On Reset The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed after wake up time tWU(PO). Reset Command There is a reset command available to reset all register bi ts of the register bank an d the diagnosis registers. As soon as HWCR.RST = 1b, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed after transfer delay time tCS(td). Limp Home Mode The limp home mode will be activated as soon as the pin LHI is set to high for a time longer than tLH(ac). The SPI write-registers are reset with applied VBB voltage. The outputs OUTx can be activated via the input pins also during activated limp home mode. The error latches can be cleare d by a low-high transition at the according input pin. For application example see Figure 30. The SPI interface is operating normally, so the limp home register bit LHI as well as the error flags can be read, but any write command will be ignored.

Data Sheet 15 Rev. 1.0, 2010-04-12

5.3 Electrical Characteristics

Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Electrical Characteristics Power Supply Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

5.3.1 Supply voltage range for normal operation

VBB(nor) 8–1 7 V –

5.3.2 Extended supply volt age range for operation

VBB(ext) 4.5 – 28 1) 1) Not subject to production test, specified by design. V Parameter deviations possible

5.3.3 Stand-by current for whole device with loads IBB(STB)

4.5 µA VDD = 0 V VLHI = 0 V 1) Tj = 25 °C 1) Tj ≤ 85 °C

5.3.4 Idle current for whole device with loads, all

IBB(idle) –7–m A VDD = 5 V DCR.MUX = 110 5.3.5 Logic supply voltage VDD 3.0 – 5.5 V –

5.3.6 Logic supply current IDD

µA VCS = VLHI = 0 V RIS = 2.7 kΩ VIS = 0 V fSCLK = 0 Hz fSCLK = 5 MHz

5.3.7 Logic idle current IDD(idle) –2 5 – µA VCS = VDD

fSCLK = 0 Hz Chip in Standby

5.3.8 Operating current for whole device active IGND – 1 02 5m A fSCLK = 0 Hz

5.3.9 L-input level at LHI pin VLHI(L) 0–0 . 8 V – 5.3.10 H-input level at LHI pin VLHI(H) 1.8 – 5.5 V – 5.3.11 L-input current through LHI pin ILHI(L) 31 2 8 0 µA 1) VLHI = 0.4 V

5.3.12 H-input current through LHI pin ILHI(H) 10 40 80 µA VLHI = 5 V

5.3.13 Power-On reset threshold voltage

VDD(PO) ––2 . 4 V –

5.3.14 Power-On wake up time tWU(PO) ––2 0 0 µs 1)

5.3.15 Stand-by channel wake up time tWU(STCH) ––2 0 0 µs 1)

5.3.16 Limp home acknowledgement time tLH(ac) 5–2 0 0 µs 1)

Data Sheet 16 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Power Supply

5.4 Command Description

Hardware Configuration Register 1) 1) Shaded cells not mentioned in this chapter. W/R 2) 2) W/R Write/Read, RB Register Bank, ADDR Address RB2) ADDR 2) 9876543210 read 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 STB CL write 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 RST CL Field Bits Type Description RST 1 w Reset Command 0 1) Normal operation

1 Execute reset command

1) Bold letters indicate the default values. STB 1 r Stand-by

0 Device is awake

1 Device is in stand-by mode

Data Sheet 17 Rev. 1.0, 2010-04-12

6 Power Stages

The high-side power stages are built by N-channel vert ical power MOSFETs (DMOS) with charge pumps. There are four channels implemented in the device. Channels can be switched on via an input pin (please refer to Section 6.2) or via SPI register OUT.

6.1 Output ON-State Resistance

The on-state resistance RDS(ON) depends on the supply voltage VBB as well as on the junction temperature Tj. Figure 4 shows those dependencies. The behavior in reverse polarity mode is described in Section 8.5. Figure 4 Typical On-State Resistance

6.2 Input Circuit

The outputs of the SPOC - BTS6460SF can be activated either via the SPI register OUT.OUTn or via the dedicated input pins. There are two different ways to use the input pins, the direct drive mode and the assigned drive mode. The default setting is the direct drive mode. To activate the assigned drive mode the register bit ICR.INCG needs to be set. Additionally, there are two ways of using the input pins in combination with the OUT register by programming the ICR.COL parameter.

• ICR.COL = 0b: A channel is switched on either by the according OUT register bit or the input pin.
• ICR.COL = 1b: A channel is switched on by the according OUT register bit only, when the input pin is high. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by the SPI register OUT. VBB = 13.5 V -50 0 50 100 150 Tj [°C] RDS(ON) [mΩ] Channel 0,1 (bulb) Channel 2,3 (bulb) Channel 2,3 (LED) Tj = 25 °C 0 5 10 15 20 25 30 V BB [V] RDS(ON) [mΩ] Channel 0, 1 (bulb) channel 2,3 (bulb) channel 2,3 (LED)

Data Sheet 18 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Power Stages Figure 5 shows the complete input switch matrix. Figure 5 Input Switch Matrix The current sink to ground ensures t hat the input signal is low in case of an open input pin. The zener diode protects the input circuit against ESD pulses.

6.2.1 Input Direct Drive

This mode is the default after the device’s wake up and reset. The input pins activate the channels during normal operation (with default setting of bit ICR.INCG), stand-by mode and limp home mode. Channel 0 can be activated only via the SPI-bit OUT.OUT0 in direct drive mode. The inputs are linked directly to the channels according to: InputMatrix_PWM .emf IN1 INCG Gate Driver 2 Gate Driver 1 Gate Driver 0 Gate Driver 3 OR OUT2 OUT1 OUT0OUT3 OR COL IN2 OR ORIN3 OR PWM Generator ch0 ch1 ch2 ch3 FREQ-values PST ch0 ch1 ch2 ch3 PWM signals OFF/ ON channel 0 FREQ0FREQ1 OR

Data Sheet 19 Rev. 1.0, 2010-04-12

6.2.2 Input Assigned Drive

To activate the assigned drive function the register bit ICR.INCG needs to be set. In this mode all output channels can be activated via the input pins. Channel 2 and 3 are assigned to only one input pin. The following mapping is used:

6.3 Power Stage Output

The power stages are built to be used in high side configuration (Figure 6). Figure 6 Power Stage Output The power DMOS switches with a dedicated slope, which is optimized in terms of EMC emission. Defined slew rates and edge shaping allow lowest EMC emissions during PWM operation at low switching losses. Table 1 Direct Drive Mode Input Pin Assigned channel , if ICR.INCG = 0b IN1 Channel 1 IN2 Channel 2 IN3 Channel 3 Table 2 Assigned Drive Mode Input Pin Assigned channel , if ICR.INCG = 1 b IN1 Channel 0 IN2 Channel 1 IN3 Channel 2, channel 3 Output.emf OUT GND VOUT VBB VDS VBB

Data Sheet 20 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Power Stages

6.3.1 Bulb and LED mode

Channel 2 and channel 3 can be configured in bulb and LED mode via the SPI registers HWCR.LEDn. During LED mode following parameters are changed for an optimize d functionality with LED loads: On-state resistance RDS(ON), switching timings (tdelay(ON), tdelay(OFF), tON, tOFF), slew rates dV/dtON and dV/dtOFF, current protections IL(trip) and current sense ratio kILIS.

6.3.2 Switching Resistive Loads

When switching resistive loads the following switching times and slew rates can be considered. Figure 7 Switching a Load (resistive)

6.3.3 Switching Inductive Loads

When switching off inductive loads wi th high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to cont inue driving the current. To prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implem ented, which limits that nega tive output voltage to a the energy capability, the clamp voltage VDS(CL) increases with the junction temperature Tj and load current IL. Please refer also to Section 8.6. The maximum allowed load inductance is limited.

6.4 Inverse Current Behavior

During inverse currents ( VOUT > VBB) the affected channel stays in ON- or in OFF-state. Fu rthermore, during applied inverse currents no ERR-flag is set. The functionality of unaffected channel s is not influenced by inverse currents applied to other channels (except effects due to junction temperature increase). Influences on the diagnostic function of unaffected channels are possible only for the current sense ratio, please refer to ∆kILIS(IC) (9.8.3). Note: No protection mechanism like temperature protection or current protection is active during applied inverse currents. Inverse currents cause power losses inside the DMOS, which increase the overall device temperature, which could lead to a switch off of the unaffected channels due to over temperature. VOUT t SwitchOn .emf tON tOFF t 90 % of VBB 10 % of VBB 70 % of VBB dV / dtON 30 % of VBB 70% dV / dtOFF 30% tdelay( ON ) tdelay(OFF ) IN / OUTx tON(rise) tOFF (fall)

Data Sheet 21 Rev. 1.0, 2010-04-12

6.5 Electrical Characteristics

Electrical Characteristics Power Stages Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Output Characteristics

6.5.1 On-state resistance RDS(ON) mΩ

channel 0, 1 3.5 IL = 7.5 A 1) Tj = 25 °C Tj = 150 °C channel 2, 3 100 HWCR.LEDn = 0 IL = 2.6 A 1) Tj = 25 °C Tj = 150 °C HWCR.LEDn = 1 IL = 0.6 A 1) Tj = 25 °C Tj = 150 °C

6.5.2 Output clamp VDS(CL) V

channel 0, 1 32 Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 6 A channel 2, 3 32 Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 2 A

6.5.3 Output leakage current per channel in

IL(OFFSTB) µA OUT.OUTn = 0 DCR.MUX = 111 channel 0, 1 – Tj = 25 °C 1) Tj = 85 °C 1) Tj = 105 °C channel 2, 3 – Tj = 25 °C 1) Tj = 85 °C 1) Tj = 105 °C

6.5.4 Output leakage current per channel in idle

IL(OFFidle) µA OUT.OUTn = 0 DCR.MUX ≠ 111 channel 0, 1 – 530 1) Tj = 85 °C 1) Tj = 105 °C Tj = 150 °C channel 2, 3 – 230 1) Tj = 85 °C 1) Tj = 105 °C Tj = 150 °C

Data Sheet 22 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Power Stages

6.5.5 Inverse current capability per channel -IL(IC) A 1) No influences on

switching functionality of unaffected channels, kILIS influence according kILIS(IC) (9.8.3) channel 0, 1 6 – – channel 2, 3 2 – – Input Characteristics 6.5.6 L-input level VIN(L) 0–0 . 8 V – 6.5.7 H-input level VIN(H) 1.8 – 5.5 V – 6.5.8 L-input current IIN(L) 31 2 8 0 µA 1) VIN = 0.4 V

6.5.9 H-input current IIN(H) 10 40 80 µA VIN = 5 V

Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 23 Rev. 1.0, 2010-04-12 Timings 6.5.10 Turn-ON delay to 10% VBB tdelay(ON) µs 1) VBB = 13.5 V channel 0, 1 – 25 – – channel 2, 3 – HWCR.LEDn = 0 HWCR.LEDn = 1 6.5.11 Turn-OFF delay to 90% VBB tdelay(OFF) µs 1) VBB = 13.5 V channel 0, 1 – 75 – – channel 2, 3 – HWCR.LEDn = 0 HWCR.LEDn = 1

6.5.12 Turn-ON time to

90% VBB including turn-ON delay tON µs VBB = 13.5 V DCR.MUX ≠ 111 channel 0, 1 – – 100 RL = 2.2 Ω channel 2, 3 – 100 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω

6.5.13 Turn-OFF time to

10% VBB including turn-OFF delay tOFF µs VBB = 13.5 V channel 0, 1 – – 150 RL = 2.2 Ω channel 2, 3 – 110 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω

6.5.14 Turn-ON rise time from 10% to

90% VBB tON(rise) µs VBB = 13.5 V DCR.MUX ≠ 111 channel 0, 1 – – 55 RL = 2.2 Ω channel 2, 3 – HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω

6.5.15 Turn-OFF fall time from 90% to

10% VBB tOFF(fall) µs VBB = 13.5 V channel 0, 1 – – 55 RL = 2.2 Ω channel 2, 3 – HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 24 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Power Stages

6.5.16 Turn-ON/OFF matching |tON -

tOFF| µs VBB = 13.5 V channel 0, 1 – – 90 RL = 2.2 Ω channel 2, 3 – HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω

6.5.17 Turn-ON slew rate

30% to 70% VBB dV/ dtON V/µs VBB = 13.5 V channel 0, 1 0.2 0.7 2.0 RL = 2.2 Ω channel 2, 3 0.2 0.6 0.9 2.5 2.5 6.0 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω

6.5.18 Turn-OFF slew rate

70% to 30% VBB -dV/ dtOFF V/µs VBB = 13.5 V channel 0, 1 0.2 0.7 2.0 RL = 2.2 Ω channel 2, 3 0.2 0.6 0.9 2.5 2.5 6.0 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω 1) Not subject to production test, specified by design. Electrical Characteristics Power Stages (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 25 Rev. 1.0, 2010-04-12

6.6 Command Description

Output Configuration Registers W/R R B A D D R 9876543210 r / w 00000 0 0 0 0 0 0 OUT3 OUT2 OUT1 OUT0 Field Bits Type Description OUTn n = 3 to 0 nr w Set Output Mode for Channel n

0 Channel n is switched off

1 Channel n is switched on 1)

1) Channel status depends on automatic PWM generator configuration. For more details, please refer to Section 7. HWCR Hardware Configuration Register W/R R B A D D R 9876543210 r / w 10010 0 CLKTRIM CLK 0 LED3 LED2 STB CL Field Bits Type Description LEDn n = 3 to 2 nr w Set LED Mode for Channel n

0 Channel n is in bulb mode

1 Channel n is in LED mode

Inputand Current Source Configuration Register W/R R B A D D R 9876543210 r / w 10001 0 0 0 0 0 0C O L I N C G CSL 0 Field Bits Type Description INCG 2 rw Input Drive Configuration

0 Direct drive mode

1 Assigned drive mode

COL 3 rw Input Combinatorial Logic Configuration

0 Input signal OR-combined with according OUT register bit

1 Input signal AND-combined with according OUT register bit

Data Sheet 26 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Automatic PWM Generator

7 Automatic PWM Generator

The SPOC - BTS6460SF has an automatic PWM generator implemented, which allows to operate the channels in PWM mode with drastically reduced micro controller attention compared to a conventional PWM generation via SPI. After the initializing phase, where different settings are done, the PWM generator works autonomously. The only required information from the micro controller is the PWM duty cycle and the channel states (ON-state or OFF-state). For details about the current sense diagnosis please refer to Chapter 9.

7.1 PWM Setup

The PWM operation mode is available for each output. The register CHCRn.FREQ is used to switch from normal mode to automatic PWM generation mode. With CHCRn.FREQ = 00 b the output state is following the OUTn register value. For details please refer to Figure 5. To start the automatic PWM generation the bit PCR.PST has to be set. For details please refer to Figure 8. The device can be woken up also out of stand-by mode by setting the bit PCR.PST. Therefore, the power-on wake up time tWU(PO) (5.3.14) has to be considered as delay until the automatic PWM generation will start.

7.2 PWM Clock

The output PWM frequency fPWM can be derived from an external clock fPCLK, which is applied at the pin PCLK, or from an internal clock fINT. The source for the PWM clock can be selected by the SPI register HWCR.CLK. Note: For avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated PWM generator (PCR.PST = 0b).

7.2.1 External PWM Clock

The output PWM frequency is generated from the PWM clock input signal fPCLK (applied at the pin PCLK), if HWCR.CLK is set to 0b. The resulting output PWM frequency clock fPWM is: (1) The prescaler is set via the register CHCRn.FREQ according to: For example: with fin =102,400 Hz

• CHCRn.FREQ = 01b: fPWM = 400 Hz
• CHCRn.FREQ = 10b: fPWM = 200 Hz
• CHCRn.FREQ = 11b: fPWM = 100 Hz Note: For avoiding skews it is recommended to change the prescaler setting only during deactivated PWM generator (PCR.PST = 0b). Table 3 Prescaler Setting Prescaler Setting CHCRn.FREQ Resulting Prescaler 00b Normal mode without automatic PWM generation 01b Prescaler 1: fPCLK (or fINT) / 256 10b Prescaler 2: fPCLK (or fINT) / 512 11b Prescaler 4: fPCLK (or fINT) / 1024 fPWM fPCLK

Data Sheet 27 Rev. 1.0, 2010-04-12 The applied clock signal can be monitored via SPI in the standard diagnosis. T he standard diagnosis bit CLE provides the information in device operation mode (not during stand-by), if the applied clock is above or below the threshold fPCLK(TH) according to the following table. The bit CLE will be reset after every successful standard diagnosis readout. The reset of the bit CLE is performed only, if the bit CLE is set. Note: A changing of the HWCR.CLKTRIM will also change the CLE thresholds.

7.2.2 Internal PWM Clock

The SPOC - BTS6460SF provides also an internal clock signal fINT. The internal clock frequency is used by setting the register HWCR.CLK to 1b. For adjusting the clock signal, a trimming of fINT via the SPI register HWCR.CLK_TRIM can be done. fPWM can be decreased or increased in steps of kTRIM. (2)

7.3 PWM Duty Cycle

The PWM duty cycle of each output is defined by the SPI register DCCRn.DC register from 0 to 256. The ON-state duty cycle is (in %): (3) The minimum duty cycle, which can be set (except from 0 %), is according to Equation (3) 0.39 %. The duty cycle of the output voltage depends on the switching times tON, tOFF and the connected load. Th erefore, the observed output duty cycle can differ from the set duty cycle.

7.4 Channel Phase Shift

For optimized EMC performances phase shifts betwe en all channels can be programmed via the SPI register CHCRn.PHS. The phase shifts refer to one common start point. Please refer to Figure 8. Up to eight different phase shifts can be selected. Table 4 External Clock Monitoring External Clock Status CLE Clock Frequency 0b fPCLK > fPCLK(TH) 1b fPCLK < fPCLK(TH) fPWM fINT x kTRIM⋅()± DCPWM DCCRn.DC 100⋅ 256

Data Sheet 28 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Automatic PWM Generator Figure 8 Phase Shifts between Channels

7.5 Daisy Chain Operation with PWM Generator

The SPI of SPOC - BTS6460SF provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS . This allows the usage of only one PWM clock input signal fPCLK. To avoid a synchronous activation of channels of the different devices, device phase shift can be programmed at the register PCR.DPSH.

7.5.1 Activation of S everal SPOC Devices with PWM Generation

For the usage of several SPOC devices in daisy chain configuration with automatic PWM generation the following procedure is recommended:

• Wake up the devices by setting the DCR.MUX ≠ 111b
• Set the PWM frequencies, duty cycles , phase shifts of all channels
• Set the device phase shift for each SPOC device differently
• Activate the automatic PWM generator of all devices by setting PCR.PST within one MCS-frame
• Activate the channels via the SPI registers OUT.OUTn With the next rising edge of the PWM clock signal fPWM the automatic PWM generation will start. Please see Figure 9 for details. Note: If the PWM generator is started during stand-by, the power-on wake up time tWU(PO) (5.3.14) has to be considered as delay until the automatic PWM generation will start. ChannelPhaseShift .emf t VPCLK t PCR.PST t VOUT0 t OUT.OUT0 t VOUT1 t OUT.OUT1 TPCLK DCPWM0 TPWM0 tCh. phase shift1

Data Sheet 29 Rev. 1.0, 2010-04-12 Figure 9 Phase Shifts between Devices

7.5.2 How to resynchronize a Reset SPOC

In case of a reset SPOC device or a SPOC device in stand-by mode the synchronization can be done as follows:

• Set the PWM frequencies, duty cycles, phase shifts of the reset device
• Set the device phase shift for the reset SPOC device
• Deactivate the automatic PWM generation of all SPOC devices in this daisy chain
• With the next SPI transmission activate the automatic PWM generator of all SPOC devices by setting PCR.PST within one MCS-frame
• Activate the channels of the reset SPOC device via the SPI register OUT.OUTn With the next rising edge of the PWM clock signal fPWM the automatic PWM generation will start again synchronously. t VPCLK t PCR.PST t VOUT0 t OUT.OUT0 t OUT.OUT0 DevicePhaseShift.emf t VOUT0 tDev. phase shift1 t PCR.PST DCPWM0 t t VOUT1 tDev. phase shift1 tCh. phase shift1 DCPWM1 Device 1 Device 2 OUT.OUT1

Data Sheet 30 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Automatic PWM Generator

7.6 Electrical Characteristics

Electrical Characteristics Power Stages Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. 7.6.1 External PWM clock threshold fPCLK(TH) 22 – 46 kHz HWCR.CLKTRIM = 100

7.6.2 External PWM clock fPCLK ––2 5 0 k H z –

7.6.3 External PWM clock period tPCLK(P) 4–– µs 1)

1) Not subject to production test, specified by design. Functional test is performed at fPCLK = 250kHz.

7.6.4 External PWM clock high time tPCLK(H) 2–– µs 1)

7.6.5 External PWM clock low time tPCLK(L) 2–– µs 1)

7.6.6 External PWM clock duty cycle range DCPCLK 30 % –7 0 % 1)

7.6.7 Internal PWM clock fINT 75 105 135 kHz HWCR.CLKTRIM = 100

7.6.8 Internal PWM clock trimming step kTRIM –5 % – 2)

2) Not subject to production test, specified by design.

Data Sheet 31 Rev. 1.0, 2010-04-12

7.7 Command Description

Hardware Configuration Register W/R R B A D D R 9876543210 read 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 STB CL write 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 RST CL Field Bits Type Description CLK 5 rw Clock Mode 1)

0 External clock input PCLK is used for PWM mode

1 Internal clock is used for PWM mode

1) For avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated PWM generator (PCR.PST = 0b). CLKTRIM 8:6 rw Internal Clock Trim 000 fINT - 4 kTRIM ... 011 fINT - 1 kTRIM 100 fINT without trimming 101 fINT + 1 kTRIM ... 111 fINT + 3 kTRIM Standard Diagnosis CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TER 0 LHI SBM xC L E x x x x x x x ERR3 ERR2 ERR1 ERR0 Field Bits Type Description CLE 11 r External Clock Status 1) 0 fPCLK > fPCLK(TH) 1 fPCLK < fPCLK(TH) 1) Invalid in stand-by mode

Data Sheet 32 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Automatic PWM Generator CHCRn Channel Configuration Register W/R R B A D D R 9876543210 r / w 110xx 0 0 0 PHSn SYDELn FREQn Field Bits Type Description FREQn n = 0 to 3 1:0 rw PWM Frequency Prescaler Setting for Channel n

00 Normal mode without automatic PWM generation

01 Prescaler 1: fPCLK (or fINT) / 256

10 Prescaler 2: fPCLK (or fINT) / 512

11 Prescaler 4: fPCLK (or fINT) / 1024

n = 0 to 3 3:2 rw Delay of Current Sense Synchronization Signal for Channel n

00 No synchronization signal delay

01 Synchronization signal delay 1: 8 / ( fPCLK (or fINT))

10 Synchronization signal delay 2: 16 / ( fPCLK (or fINT))

11 Synchronization signal delay 3: 24 / ( fPCLK (or fINT))

n = 0 to 3 6:4 rw Channel Phase Shift for Channel n

000 No phase shift

001 Phase shift 1: 32 / ( fPCLK (or fINT))

010 Phase shift 2: 64 / ( fPCLK (or fINT))

...

110 Phase shift 6: 192 / ( fPCLK (or fINT))

111 Phase shift 7: 224 / ( fPCLK (or fINT))

PWM Configuration Register W/R R B A D D R 9876543210 r / w 00111 0 0 0 0 0 0 DCS DPSH PST Field Bits Type Description PST 0 rw Automatic PWM Generation

0 No automatic PWM generation

1 Automatic PWM generation

DPSH 2:1 rw Device Phase Shift

00 No phase shift

01 Phase shift 1: 8 / ( fPCLK (or fINT))

10 Phase shift 2: 16 / ( fPCLK (or fINT))

11 Phase shift 3: 24 / ( fPCLK (or fINT))

DCS 3 rw Single Duty Cycle for all Channels

0 Duty cycle setting of channel 0 used for all channels

1 Individual duty cycle settin g used for each channel

Data Sheet 33 Rev. 1.0, 2010-04-12 DCCRn Duty Cycle Configuration Register W/R R B A D D R 9876543210 r / w 010xx 0 DCn Field Bits Type Description DCn n = 0 to 3 8:0 rw Duty Cycle for Channel n during Automatic PWM Generation

000000000 DC value: 0 (channel off)

000000001 DC value: (1 / 256) * 100

000000010 DC value: (2 / 256) * 100

...

011111111 DC value: (255 / 256) * 100

1xxxxxxxx DC value: 1 (channel 100% on)

Data Sheet 34 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Protection Functions

8 Protection Functions

The device provides embedded protective functions, wh ich are designed to prevent IC destruction under fault conditions described in this data sheet. Fault condit ions are considered as “out side” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation.

8.1 Over Current Protection

The maximum load current IL is switched off in case of exceeding the over current trip level IL(trip) by the device itself. Depending on the total short circuit impedance higher current over shoots may occur. A limited auto-restart function is implemented. The number of restarts is dependent of the VDS voltage. Please refer to following figures for details. Figure 10 Over current protection with latch due to reaching maximum number of retries nretry IL IIS t t t ERR t CurrentTrippingDeltaT_nretry.emf CL = 1 VDS t VDS(Vtrip) IL(trip) over current normal operationIN / OUTx t Tj Tj(startn) + ∆Tj(res) Tj(start1) Tj(start1) + ∆Tj(res) Tj(start2) + ∆Tj(res) n = 1 over load removed Tj(SC) n= nretry * ERR-flag will be reset by standard diagnosis readout during restart Switch off by over current switch off Restart by dynamic temperature sensor Latch OFF due maximum number of retries reached

Data Sheet 36 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Protection Functions

8.2 Over Current Pr otection at high VDS

The SPOC - BTS6460SF provides an over current protection for VDS > VDS(Vtrip) (8.9.5). For VDS > VDS(Vtrip) and IL > IL(Vtrip) during turn on the channel switches off and latches immediately. For details please refer to parameter IL(VTRIP) (8.9.4). The current trip level IL(Vtrip) is below the current trip level IL(trip) at VDS = 7V. The ratio between IL(trip) and IL(Vtrip) is defined by the parameter ∆kTR (8.9.6). The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turn ed on immediately (or according to th e automatic PWM generator setting) after the command HWCR.CL = 1b. Figure 13 Over current protection in case of high VDS voltages

8.3 Over Current Protection for S hort Circuit Type 2 Protection

After activation of the channels without over temperature shutdown and after the delay time tdelay(trip) (8.9.2) the over current protection threshold IL(trip) is reduced to IL(Itrip). The delay time tdelay(trip) is reset by an dynamic temperature sensor or over current shutdown and any IN, OUTx or automatic PWM generator signal transition. In case of a short circuit to GND event with IL > IL(Itrip) (8.9.3), which occurs in the on st ate, the channel is switched off and latched immediately. For more details, please refer to the figure Figure 14. The current trip level IL(Itrip) is below the current trip level IL(trip) at VDS = 7V. The ratio between IL(trip) and IL(Itrip) is defined by the parameter ∆kTR (8.9.6). The over current latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turn ed on immediately (or according to th e automatic PWM generator setting) after the command HWCR.CL = 1b. IL IIS t t t ERR t CurrentTrippingHighVDS.emf CL = 1 VDS t VDS(Vtrip) IL(Vtrip) high VDS over current normal operation over load removed IN / OUTx

Data Sheet 37 Rev. 1.0, 2010-04-12 Figure 14 Shut Down by Over Current due to Short Circuit Type 2

8.4 Over Temperature Protection

Each channel has its own temperature sensor. If the te mperature at the channel exceeds the thermal shutdown temperature Tj(SC), the channel will switch off and latch to prevent destruction (also in case of VDD = 0V). In order to reactivate the channel, the temperature at the ou tput must drop by at leas t the thermal hysteresis ∆Tj and the over temperature latch must be cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immedi ately (or according to the automatic PWM generator setting) after the command HWCR.CL = 1b. Figure 15 Shut Down by Over Temperature

8.4.1 Dynamic Temperature Sensor Protection

Additionally, each channel has its own dynamic temperat ure sensor. The dynamic temperature sensor improves short circuit robustness by limiting sudden increases in the junction temperature. The dynamic temperature sensor turns off the channel if its sudden temperature incr ease exceeds the dynamic tem perature sensor threshold ∆Tj(SW). The number of automatic reactivations is limited by nretry (8.9.7). If this number of retries is exceeded the channel turns off and latches. The re try latch is cleared by SPI command HWCR.CL = 1b. If the input pin or the bit in the SPI register OUT is still set, the channel will be turned on immediately (or according to the automatic PWM generator setting) after the command HWCR.CL = 1b. For the condition n < nretrythe counter of automatic reactivations will be reset by every low to high transition on the input pin or the bit in SPI register OUT. IL IIS t t t ERR t CurrentTrippingLowVDS .emf CL = 1 IL( Itr ip) normal operation over current normal operation over load removed IN / OUTx t > tdelay (trip) IL IIS t t t ERR t OverLoad.emf CL = 1 IN / OUTx CL = 1 IL(trip) t Tj Tj(start1) Tj(start1) + ∆Tj(SW) Tj(SC) Latch OFF due to over temperature Latch OFF due to over temperature

Data Sheet 38 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Protection Functions For automatic PWM generation the coun ter will be reset also in case of du ty cycles < 100% during the off-state. Please refer to Figure 14 for details. Figure 16 Dynamic Temperature Sensor Operations with latch due to reaching maximum number of retries nretry IIS t t ERR t DeltaT_nretry.emf CL = 1 over load normal operationIN / OUTx t Tj n = 1 over load removed Tj(SC) n= nretry * ERR-flag will be reset by standard diagnosis readout during restart Latch OFF due maximum number of retries reached IL t VDS t VDS(Vtrip) IL(trip) Tj(start1) + ∆Tj(res) Tj(start1) + ∆Tj(SW) Switch off by dynamic temperature sensor Restart by dynamic temperature sensor ∆TjSW Tj(startn) + ∆Tj(res) Tj(start1)

Data Sheet 39 Rev. 1.0, 2010-04-12 Figure 17 Dynamic Temperature Sensor Operations with latch due to reaching over temperature Tj(SC) The ERR-flag will be set during dynamic temperature sensor shut down. It can be reset by reading the ERR-flag. If the channel is still in dynamic temperature sensor shut down, the ERR-flag will be set again. During the automatic restart of the channel the ERR-flag can be cleared by reading the ERR-flag. It will be set again as soon as the dynamic temperature sensor is activated again.

8.5 Reverse Polarity Protection

In reverse polarity mode, power dissipation is caused by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse current through the channels has to be limited by the connected loads.The current through the ground pin, sense pin IS, current sense synchronization pin, the logic power supply pin VDD, the SPI pins, input pins, clock input pin and the limp home input pin has to be limited as well (please refer to the maximum ratings listed on Page 10). For reducing the power loss during reverse polarity Reversave TM functionality is implemented for all channels. They are turned on to almost forward condition in reverse polarity condition, see parameter RDS(REV). Note: No protection mechanism like temperature protection or current protection is active during reverse polarity.

8.6 Over Voltage Protection

In the case of supply voltages between VBB(SC) max and VBB(CL) the output transistors are still operational and follow the input or the OUT register. Parameters are not warranted and lifetime is reduced compared to normal mode. In addition to the output clamp for inductive loads as described in Section 6.3, there is a clamp mechanism available for over voltage protection for the logic and all channels. IL IIS t t t ERR t DeltaT_OT.emf CL = 1 VDS t VDS(Vtrip) IL(trip) over load normal operationIN / OUTx t Tj Tj(startn) + ∆Tj(res) Tj(start1) Tj(start1) + ∆Tj(res) Tj(start1) + ∆Tj(SW) n = 1 over load removed Tj(SC) n < nretry * ERR-flag will be reset by standard diagnosis readout during restart Switch off by dynamic temperature sensor Restart by dynamic temperature sensor Latch OFF due to over temperature∆TjSW

Data Sheet 40 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Protection Functions

8.7 Loss of Ground

In case of complete loss of the device ground co nnections, but connected load ground, the SPOC - BTS6460SF securely changes to or stays in OFF-state.

8.8 Loss of VBB

In case of loss of VBB connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or th rough an additional path from VBB to gr ound. For exam ple, a suppre ssor diode is recommended between VBB and GND.

Data Sheet 41 Rev. 1.0, 2010-04-12

8.9 Electrical Characteristics

Electrical Characteristics Protection Functions Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Over Load Protection

8.9.1 Load current trip level IL(trip) A VDS < 7 V

channel 0, 1 71 120 100 Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C channel 2, 3 HWCR.LEDn = 0 Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C 5.5 8.5 HWCR.LEDn = 1 Tj = -40 °C 1) Tj = 25 °C Tj = 150 °C Over Current Protection

8.9.2 Over current tripping activation time tdelay(trip) 7–1 4 m s 1)

8.9.3 Load current trip level after tdelay(trip) IL(Itrip) A

channel 0, 1 40 Tj = -40 °C Tj = 150 °C channel 2, 3 15.5 HWCR.LEDn = 0 Tj = -40 °C Tj = 150 °C 3.8 3.8 HWCR.LEDn = 1 Tj = -40 °C Tj = 150 °C

8.9.4 Load current trip level at high VDS IL(Vtrip) A 1)

channel 0, 1 40 Tj = -40 °C Tj = 150 °C channel 2, 3 15.5 HWCR.LEDn = 0 Tj = -40 °C Tj = 150 °C 3.8 3.8 HWCR.LEDn = 1 Tj = -40 °C Tj = 150 °C

8.9.5 Over current tripping at high VDS

VDS(Vtrip) 1 5 ––V 1)

8.9.6 Current trip at VDS = 7 V to current trip at

VDS = 20 V ratio ∆kTR 1.2 1.5 – 1)

Data Sheet 42 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Protection Functions Over Temperature Protection

8.9.7 Number of automatic retries at over

current or dynamic temperature sensor shut down at low VDS nretry(LV) –3 2 – 1) VDS = 9 V

8.9.8 Number of automatic retries at over

current or dynamic temperature sensor shut down at medium VDS nretry(MV) –8– 1) VDS = 13 V

8.9.9 Thermal shut down temperature Tj(SC) 150 175 195 °C 1)

8.9.10 Thermal hysteresis of thermal shutdown ∆Tj –1 0 –K 1)

8.9.11 Dynamic temperature increase

limitation while switching ∆Tj(SW) –6 0 –K 1)

8.9.12 Dynamic temperature sensor restart ∆Tj(res) –2 0 –K 1)

8.9.13 On-state resistance RDS(REV) mΩ 1) VBB = -13.5 V channel 0, 1 4.7 9.5 IL = -7.5 A Tj = 25 °C Tj = 150 °C channel 2, 3 14.7 29.5 IL = -2.6 A Tj = 25 °C Tj = 150 °C Over Voltage

8.9.14 Over voltage protection

VBB(CL) V VBB to GND 40 55 70 IGND = 5 mA channel 0, 1 32 Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 6 A channel 2, 3 32 Tj = 25 °C IL = 20 mA 1) Tj = 150 °C IL = 2 A 1) Not subject to production test, specified by design. Electrical Characteristics Protection Functions (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 43 Rev. 1.0, 2010-04-12

8.10 Command Description

Hardware Configuration Register W/R R B A D D R 9876543210 read 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 STB CL write 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 RST CL Field Bits Type Description CL 0 rw Clear Latch

0 Thermal and over current latches are untouched

1 Command: Clear all thermal and over current latches

CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TER 0 LHI SBM x CLE x x x x x x x ERR3 ERR2 ERR1 ERR0 Field Bits Type Description ERRn n = 0 to 3 3:0 r Error Flag for Channel n

0 No error

1 Error occurred

Data Sheet 44 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Diagnosis

9 Diagnosis

For diagnosis purpose, the SPOC - BTS6460SF provides a current sense signal at pin IS and the diagnosis word via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. In OFF-state a current source is able to be switched on for a selected channel with the DCR.CSOL bit. This allows open load / short circuit detection to VBB in OFF-state. The current value can be configured to a low or a high value Please refer to Figure 18 for details on diagnosis function: Figure 18 Block diagram: Diagnosis channel 0 load current sense Diagnosis_STD.emf RIS IIS0 current sense multiplexer IS T gate control latch temperature sensor ERR0 OR latch DCR.MUX VBB VDS(SB) SBM DCR. OUT3 OUT2 OUT1 OUT0 VBB CSOL over current protection IL(OL)

Data Sheet 45 Rev. 1.0, 2010-04-12 For diagnosis feedback at different operation modes, please see following table.

9.1 Diagnosis Word at SPI

The standard diagnosis at the SPI in terface provides information about each channel. The error flags, an OR combination of the over temperature flags and the over lo ad monitoring signals are provided in the SPI standard diagnosis bits ERRn. The over load monitoring signals are latched in the erro r flags and cleared each time the standard diagnosis is transmitted via SPI. In detail, they are cleared between the second and third raising edge of the SCLK signal. The over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control block. The over current flags, which cause an channel 0 or 1 driving a too high current to switch off, are latched like the over temperature flags. Those latches are cleared by SPI command HWCR.CL. Please note: The over temperature and over current information is latched twice. When transmitting a clear latch command (HWCR.CL), the error flag is cleared during command transmission of the next SPI frame and ready for latching after the third raising edge of the SCLK signal. As a result, the first standard diagnosis information after a CL command will indicate a failure mode at the previously affected chann els although the th ermal latches have been cleared already. In case of continuous over load, t he error flags are set again immediately because of the over load monitoring signal.

9.2 Load Current Sense Diagnosis

There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI. Table 5 Operation Modes 1) 1) L = low level, H = high level, Z = high impedance, potential d epends on leakage currents and external circuit x = undefined Operation Mode Input Level OUT.OUTn Output Level VOUT Current Sense IIS Error Flag ERRn 2) The error flags are latched until they are tr ansmitted in the standard diagnosis word via SPI SBM DCR.SBM Normal Operation (OFF) L / 0 (OFF-state) GND Z 0 1 Short Circuit to GND GND Z 0 1 Thermal shut down Z Z 0 x Short Circuit to VBB VBB Z 0 0 Open Load Z Z 0 0 3) 3) If the current sense multiplexer is set to Channel 0 to 3 and DRC.CSOL bit set Inverse Current > VBB Z 0 0 4) 4) If the current sense multiplexer is set to Channel 0 to 3 Normal Operation (ON) H / 1 (ON-state) ~ VBB IL / kILIS 00 Short Circuit to GND ~ GND Z 1 1 Dynamic Temperature Sensor shut down Z Z 1 x Over Current shut down Z Z 1 5) 5) The over current latch off flag is set la tched and can be cleared by SPI command HWCR.CL x Thermal shut down Z Z 1 6) 6) The over temperature flag is set latc hed and can be cleared by SPI command HWCR.CL x Short Circuit to VBB VBB < IL / kILIS 00 Open Load VBB Z00 Inverse Current > VBB Z00

Data Sheet 48 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Diagnosis

9.3 Sense Synchronization duri ng Automatic PWM Generation

For performing current sens e measurements there is a current sense synchronization signal at the pin ISSY available. This signal indicates the possible start of VIS measurement. The synchronization signal will be activated after the time tMeasurement delay after channel’s activation. The delay time can be configured via SPI register CHCRn.SYDEL. The current sense synchronization signal is only available during the automatic PWM generation, i.e. the bit PCR.PST is set. Figure 23 shows the functionality of the current sense synchronization signal. Figure 23 Current Sense Synchronization SenseSynchronization.emf t VPCLK t PCR.PST t VOUT0 t OUT.OUT0 t VOUT1 t t VISSY tSynch. delay1 t VIS t DCR.MUX 001 001 000 001 tSynch. delay0 tsIS(ON) OUT.OUT1 tCh. phase shift1

Data Sheet 49 Rev. 1.0, 2010-04-12

9.4 Sense Measurement without Synchronization Signal

The SPOC - BTS6460SF refers all the channel activations to the clock signal fPCLK or fINT. In case of using the external clock fPCLK the state (ON- or OFF-state) is known by the micro controller, which allows a time based processing. In case of micro controller’s loss of the PCLK synchrony the automatic PWM generation can be started again by resetting and setting of the bit PCR.PST. After that the micro controller is synchronous to the automatic PWM generation.

9.5 Automatic Current Sen se Multiplexer Switching

The device provides for current sense measurements a function, which changes the current sense multiplexer sequentially and automatically. The function starts af ter the PWM reference point has passed, which happens each 1024 clock cycles ( fPCLK or fINT). For more details please refer to figure Figure 23. The current sense multiplexer is switched first to the channel 0. When the current sense syn chronization signal at the pin ISSY is finished, the multiplexer is programmed automatically to channel 1 (one clock cycle after the high low transition of the ISSY signal) and so on. Th e current sense syn chronization signal at the pin ISSY will be set for eight clock cycles, if the channel duty cycle is 0 % <DC <100 %. For the scenario, where the channel is continuously on (DC = 100 %) or off ( DC = 0 %), or the tISSY delay > tduty cycle (delay longer than on-state of channel) the sense synchronization signal will be set for nine clock cycles (fPCLK or fINT). Furthermore, to shorten the ISSY burst length for channels continuously in ON- or OFF-state, the ISSY signal will be started 11 clock cycles after the previous ISSY pulse. If the synchronization delay is programmed to 11b the following channel needs at minimum a synchronization delay ≥ = 01b, otherwise the next ISSY signal will be delayed by one period of the following channel. This multiplexer switching loop is done only once after the bit DCR.AMUX is set. After the completed loop the bit will be set to DCR.AMUX = 0b automatically. For more details please refer to Figure 23. The automatic multiplexer switching can be stopped manually by setting the bit DCR.AMUX = 0b. Note: The phase shifts between the channels have to be programmed in ascending order (channel 0 with minimum phase shift, channel 1 with a higher phase shift than channel 0, channel 2 with a higher phase shift than channel 1, ...) to get a short AMUX burst duration. Otherwise the duration for a complete automatic multiplexer cycle will increase until a new PWM reference point has passed and the channel is activated. During the activated AMUX bit any command, which should change the multiplexer, will be ignored. If a channel is switched continuously off, the current sense multiplexer will be switched to high impedance during the sense synchronization pulse.

Data Sheet 50 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Diagnosis Figure 24 Automatic Current Sense Multiplexer Switching

9.6 Switch Bypass Diagnosis

To detect short circuit to VBB, there is a switch bypass monitor implemente d. In case of short circuit between the output pin OUT and VBB in ON-state, the current will flow through the power transistor as well as through the short circuit (bypass) with undefined ratio. As a result, the current sense signal will show lower values than expected by the load current. In OFF-state, the output voltage will stay close to VBB potential which means a small VDS. The switch bypass monitor compares the voltage VDS across the power transistor of that channel, which is selected by the current sense multiplexer ( DCR.MUX) with threshold VDS(SB). The result of comparison can be read in SPI register DCR.SBM or in the standard diagnosis. AutoMUX.emf t VPCLK t PCR.PST t DCR.AMUX t VISSY t VOUT2 tCh. phase shift2 tSynch. delay0 tSynch. high A * t VOUT3 tCh. phase shift3 t VIS tsIS(ON) tISSY delay ON/OFF tSynch. delay2 tSynch. high B * tSynch. high A * tSynch. high B * Ch0 Ch1 Ch2 Ch3 n * 1024 Set to 0 automatically t VOUT0 t VOUT1 tCh. phase shift1 tISSY delay ON/OFF * tSynch. high A = 8 / (fPCLK or fINT) * tISSY delay ON/OFF = 11 / (fPCLK or fINT) * tSynch. high B = 9 / (fPCLK or fINT)

Data Sheet 51 Rev. 1.0, 2010-04-12

9.7 Open Load in OFF-State

For performing a dedicated open load in OFF-state dete ction a current source can be switched in parallel to the DMOS accord ing to the Figure 18. The current source current can be programmed in two steps by the bit ICR.CSL. The following procedure is recommended to use:

• Select the dedicated channel with the multiplexer
• Enable the open load current with the DCR.CSOL bit
• Read the DCR.SBM or the standard diagnosis
• Disable the open load current with the DCR.CSOL bit

Data Sheet 52 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Diagnosis

9.8 Electrical Characteristics

Electrical Characteristics Diagnosis Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Load Current Sense

9.8.1 Current sense ratio kILIS Tj = -40 °C

channel 0, 1: 0.600 A 1.3 A 2.6 A 4.0 A 7.5 A 2190 3990 4690 5130 5490 5840 6140 6350 6430 6480 50010 12510 9210 8510 7710 channel 2, 3 (bulb): HWCR.LEDn = 0 0.300 A 0.600 A 1.3 A 2.6 A 4.0 A 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 3710 2710 2210 2110 2110 channel 2, 3 (LED): HWCR.LEDn = 1 0.050 A 0.150 A 0.300 A 0.600 A 1.0 A 165 300 350 385 400 400 440 450 460 500 1305 675 580 555 555

9.8.2 Current sense ratio

kILIS Tj = 25 °C to 150 °C channel 0, 1: 0.600 A 1.3 A 2.6 A 4.0 A 7.5 A 3120 4420 5030 5130 5490 5840 6140 6350 6430 6480 10960 10010 8660 8240 7710 channel 2, 3 (bulb): HWCR.LEDn = 0 0.300 A 0.600 A 1.3 A 2.6 A 4.0 A 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 2690 2300 2100 2110 2110 channel 2, 3 (LED): HWCR.LEDn = 1 0.050 A 0.150 A 0.300 A 0.600 A 1.0 A 165 300 350 385 400 400 440 450 460 500 805 640 580 555 555

Data Sheet 53 Rev. 1.0, 2010-04-12

9.8.3 Current sense drift of unaffected channel

during inverse current of other channels channel 0, 1 channel 2, 3 (bulb) channel 2, 3 (LED) ∆kILIS(IC) -20 % -20 % -20 % -20 % -20 % -20 % 20 % 20 % 20 % 20 % 20 % 20 % DCR.MUX ≠ 111 IL0, 1 = 7.5 A IL1, 0 (IC) = 7.5 A IL2, 3 (IC) = 2.6 A HWCR.LEDn = 0 IL2, 3 = 2.6 A IL0, 1 (IC) = 7.5 A IL3, 2 (IC) = 2.6 A HWCR.LEDn = 1 IL2, 3 = 0.6 A IL0, 1 (IC) = 7.5 A IL3, 2 (IC) = 2.6 A 9.8.4 Current sense voltage limitation VIS(LIM) 0.9 × VDD VDD 1.1 × VDD V DCR.MUX = 011 IL3 = 2 A RIS = 2.7 kΩ

9.8.5 Maximum steady state current sense

IIS(MAX) 5.5 – – mA 1) VIS = 0 V

9.8.6 Current sense leakage / offset current

channel 0, 1 channel 2, 3 IIS(en) µA IL = 0 A DCR.MUX ≠ 111

9.8.7 Current sense leakage, while diagnosis

IIS(dis) ––1 µA DCR.MUX = 110

9.8.8 Current sense settling time after channel

channel 0, 1 tsIS(ON) ––1 5 0 µs VBB = 13.5 V RIS = 2.7 kΩ RL = 2.2 Ω channel 2, 3 150 100 HWCR.LEDn = 0 RL = 6.8 Ω HWCR.LEDn = 1 RL = 33 Ω

9.8.9 Current sense desettling time after

tdIS(OFF) µs 1) VBB = 13.5 V RIS = 2.7 kΩ HWCR.LEDn = 0 HWCR.LEDn = 1

9.8.10 Current sense settling time after change

channel 0, 1 tsIS(LC) ––3 0 µs 1) VBB = 13.5 V RIS = 2.7 kΩ IL = 7.5 A to 4.0 A channel 2, 3 HWCR.LEDn = 0 IL = 2.6 A to 1.3 A HWCR.LEDn = 1 IL = 0.6 A to 0.3 A Electrical Characteristics Diagnosis (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 54 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Diagnosis

9.8.11 Current sense settling time after current

tsIS(EN) ––2 5 µs RIS = 2.7 kΩ DCR.MUX: 110 -> 000

9.8.12 Current sense settling time after

multiplexer channel change tsIS(MUX) ––3 0 µs RIS = 2.7 kΩ RL0 = 2.2 Ω RL2 = 33 Ω DCR.MUX: 010 -> 000 9.8.13 Current sense deactivation time tdIS(MUX) ––2 5 µs 1) RIS = 2.7 kΩ DCR.MUX: 000 -> 110 Switch Bypass Monitor 9.8.14 Switch bypass monitor threshold VDS(SB) 1.5 – 4 V – Open load in off current source

9.8.15 Current source in OFF-state IL(OL) 100

3.0 450 7.5 µA mA IECR.CSL = 0 IECR.CSL = 1 Current Sense Synchronization Signal 9.8.16 L level signal voltage VISSY(L) 0–0 . 4 V IISSY = -0.5 mA

9.8.17 H level signal voltage VISSY(H) VDD -

0.4 V – VDD V 1) IISSY = 0.5 mA VDD = 4.3 V

9.8.18 Signal enable time tISSY(en) ––4 µs 1) CL = 20 pF

9.8.19 Signal disable time tISSY(dis) ––4 µs 1) CL = 20 pF

1) Not subject to production test, specified by design. Electrical Characteristics Diagnosis (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Data Sheet 55 Rev. 1.0, 2010-04-12

9.9 Command Description

Diagnosis Control Register W/R R B A D D R 9876543210 read 1 0 0 1 1 0 0 0 0 0 AMUX SBM MUX write 1 0 0 1 1 0 0 0 0 0A M U X C S O L M U X Output state OUT.OUTn Field Bits Type Description (OFF-state) MUX 2:0 r/w Set Current Sense Multiplexer Configuration

000 IS pin is high impedance

001 IS pin is high impedance

010 IS pin is high impedance

011 IS pin is high impedance

100 IS pin is high impedance

101 IS pin is high impedance

110 IS pin is high impedance

111 Stand-by mode (IS pin is high impedance)

SBM 3 r Switch Bypass Monitor

0 VDS < VDS(SB)

1 VDS > VDS(SB)

1) Invalid in stand-by mode (ON-state) MUX 2:0 r/w Set Current Sense Multiplexer Configuration

000 Current sense of channel 0 is routed to IS pin

001 Current sense of channel 1 is routed to IS pin

010 Current sense of channel 2 is routed to IS pin

011 Current sense of channel 3 is routed to IS pin

111 Stand-by mode (IS pin is high impedance))

SBM 3 r Switch Bypass Monitor Field Bits Type Description CSOL 3 w Current Source Switch for Open Load Detection

0 OFF

AMUX 4 rw Automatic Current Sense Multiplexer Switching during Automatic PWM Generation

Data Sheet 56 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Diagnosis CHCRn Channel Configuration Register W/R R B A D D R 9876543210 r / w 110xx 0 0 0 PHSn SYDELn FREQn Field Bits Type Description SYDELn n = 0 to 3 3:2 rw Delay of Current Sense Synchronization Signal for Channel n CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TER 0 LHI SBM x CLE x x x x x x x ERR3 ERR2 ERR1 ERR0 Field Bits Type Description ERRn n = 3 to 0 nr Error flag Channel n 0 normal operation 1 failure mode occurred SBM 13 r Switch Bypass Monitor 1) 1) Invalid in stand-by mode

Data Sheet 57 Rev. 1.0, 2010-04-12 ICR Inputand Current Source Configuration Register W/R R B A D D R 9876543210 r / w 10001 0 0 0 0 0 0 COL INCG CSL 0 Field Bits Type Description CSL 1 rw Level for Current Source for Open Load Detection

0 Low level

1 High level

Data Sheet 58 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Serial Peripheral Interface (SPI)

10 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS . A modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred, while the minimum of 16 bit is also taken into consideration. Therefore the interface provides daisy chain capability even with 8 bit SPI devices. Figure 25 Serial Peripheral Interface

10.1 SPI Signal Description

CS - Chip Select: The system micro controller selects the SPOC - BTS6460SF by means of the CS pin. Whenever the pin is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS High to Low transition:

• The requested information is transferred into the shift register.
• SO changes from high impedance state to high or lo w state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration, a high signal indicates a faulty transmission. This information stays available to the first rising edge of SCLK. Figure 26 Combinatorial Logic for TER Flag CS Low to High transition:
• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored.
• Data from shift register is transferred into the addressed register. 14 13 12 11 14 13 12 11MSB MSB SPI_16bit .emf LSB6 5 4 3 2 1 LSB6 5 4 3 2 1 10 9 8 10 9 8 7SO SI CS SCLK time TER.emf SI SPI OR TER 1 SO CS SCLK S SO S SI

Serial Peripheral Interface (SPI) Data Sheet 59 Rev. 1.0, 2010-04-12 SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (S O) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any transition. SI - Serial Input: Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, co ntrol bits followed by data bits. Please refer to Section 10.5 for further information. SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin goes to low state. New data will appear at the SO pi n following the rising edge of SCLK. Please refer to Section 10.5 for further information.

10.2 Daisy Chain Capability

The SPI of SPOC - BTS6460SF provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS . The SI line of one device is connecte d with the SO line of another device (see Figure 27), in order to build a chain. The ends of the chain are connected with the output and input of the master device, MO and MI respectively. The ma ster device provides the master cl ock MCLK which is connected to the SCLK line of each device in the chain. Figure 27 Daisy Chain Configuration In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The bit shifted out occurs at the SO pin. After eight SCLK cyc les, the data transfer for one device has been finished. In single chip configuration, the CS line must turn high to make the devic e accept the transferred data. In daisy chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. When using three devices in daisy chain, three times 16 (or e.g. 16 + 8 +16) bits ha ve to be shifted through the devices. After that, the MCS line must turn high (see Figure 28). SI device 1 SPI SCLK SO CS SI device 2 SPI SCLK SO CS SI device 3 SPI SCLK SO CS MO MI MCS MCLK SPI_DaisyChain .emf

Data Sheet 60 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Serial Peripheral Interface (SPI) Figure 28 Data Transfer in Daisy Chain Configuration

10.3 Timing Diagrams

Figure 29 Timing Diagram SPI Access MI MO MCS MCLK SI device 1 SI device 2 SI device 3 SO device 1 SO device 2 SO device 3 time SPI_DaisyChain2_16bit.emf CS SCLK SI tC S(lead) tCS( td )tCS( la g ) tSCLK( H) tSCLK( L) tSCLK( P) tSI(su) tSI( h) SO tSO( v)tSO(en) tSO(dis) 0.7VDD 0.2VDD 0.7VDD 0.2VDD 0.7VDD 0.2VDD 0.7VDD 0.2VDD SPI Timing.emf

Serial Peripheral Interface (SPI) Data Sheet 61 Rev. 1.0, 2010-04-12

10.4 Electrical Characteristics

Electrical Characteristics Serial Peripheral Interface (SPI) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Input Characteristics (CS, SCLK, SI)

10.4.1 L level of pin

VCS(L) VSCLK(L) VSI(L) 0 – 0.2* VDD V VDD = 4.3 V

10.4.2 H level of pin

VCS(H) VSCLK(H) VSI(H) 0.4* VDD – VDD V VDD = 4.3 V

10.4.3 Pull-up resistor at CS pin RCS 50 120 180 k Ω ICS = 100 µA

10.4.4 Pull-down resistor at pin

50 120 180 k Ω – ISCLK = 100 µA ISI = 100 µA Output Characteristics (SO) 10.4.5 L level output voltage VSO(L) 0–0 . 4 V ISO = -0.5 mA

10.4.6 H level output voltage VSO(H) VDD -

0.4 V – VDD V ISO = 0.5 mA VDD = 4.3 V

10.4.7 Output tristate leakage current ISO(OFF) -10 – 10 µA VCS = VDD

10.4.8 Serial clock frequency fSCLK 0

MHz 1) VDD = 4.3 V 2) VDD = 3.0 V

10.4.9 Serial clock period tSCLK(P) 200

ns 1) VDD = 4.3 V 2) VDD = 3.0 V

10.4.10 S e r i a l c l o c k h i g h t i m e tSCLK(H) 100

ns 1) VDD = 4.3 V 2) VDD = 3.0 V 1 0 . 4 . 1 1 Serial clock low time tSCLK(L) 100 166 ns 1) VDD = 4.3 V 2) VDD = 3.0 V 1 0 . 4 . 1 2 Enable lead time (falling CS to rising SCLK) tCS(lead) 200 333 ns 1) VDD = 4.3 V 2) VDD = 3.0 V 1 0 . 4 . 1 3 Enable lag time (falling SCLK to rising CS) tCS(lag) 200 333 ns 1) VDD = 4.3 V 2) VDD = 3.0 V 1 0 . 4 . 1 4 Transfer delay time (rising CS to falling CS) tCS(td) 200 333 ns 1) VDD = 4.3 V 2) VDD = 3.0 V 1 0 . 4 . 1 5 Data setup time (required time SI to falling SCLK) tSI(su) 20 ns 1) VDD = 4.3 V 2) VDD = 3.0 V 1 0 . 4 . 1 6 Data hold time (falling SCLK to SI)tSI(h) 20 ns 1) VDD = 4.3 V 2) VDD = 3.0 V

Data Sheet 62 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Serial Peripheral Interface (SPI) 1 0 . 4 . 1 7 Output enable time (falling CS to SO valid) tSO(en) 200 333 ns 2) CL = 20 pF VDD = 4.3 V VDD = 3.0 V 1 0 . 4 . 1 8 Output disable time (rising CS to SO tri-state) tSO(dis) 200 333 ns 2) CL = 20 pF VDD = 4.3 V VDD = 3.0 V 1 0 . 4 . 1 9 Output data valid time with capacitive load tSO(v) 100 166 ns 2) CL = 20 pF VDD = 4.3 V VDD = 3.0 V 1) Not subject to production test, specified by design. SPI functional test is performed at fSCLK = 5 MHz. 2) Not subject to production test, specified by design. Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d) Unless otherwise specified: VBB = 8 V to 17 V, VDD = 3.0 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VBB = 13.5 V, VDD = 4.3 V, Tj = 25 °C Pos. Parameter Symbol Limit Values Unit Test Conditions min. typ. max.

Serial Peripheral Interface (SPI) Data Sheet 63 Rev. 1.0, 2010-04-12

10.5 SPI Protocol 16Bit

Note: Reading a register needs two SPI frames. In the first frame the RD command is sent. In the second frame the output at SPI signal SO will contain the requested information. A new command can be executed in the second frame. The standard diagnosis can be accessed either by sending the standard diagnosis read command or it is transmitted after each write command. CS1) 1) The SO pin shows this information between CS hi -> lo and first SCLK lo -> hi transition. 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Write OUT Register S I 100000000000 O U T 3 O U T 2 O U T 1 O U T 0 Read OUT Register S I 000000xxxxxxxxx0 Write Configuration and Control Registers SI 1 x ADDR DATA Read Configuration and Control Registers S I 0x A D D R xxxxxxxxx0 Read Standard Diagnosis S I 0xxxxxxxxxxxxxx1 Standard Diagnosis S O T E R 0 L H I S B M x C L E xxxxxxx E R R 3 E R R 2 E R R 1 E R R 0 Second Frame of Read Command SO TER 1 0 0 0 0 0 x x x x x x OUT3 OUT2 OUT1 OUT0 SO TER 1 x ADDR DATA Field Bits Type Description W/R 15 w 0 Read 1W r i t e RB 14 rw Register Bank

0 Read / write to register bank 0

1 Read / write to register bank 1

TER CS r Transmission Error

0 Previous transmission was successful (modulo 16 clocks received)

1 Previous transmission failed or first transmission after reset

n = 3 to 0 nw Output Control Register of Channel n ADDR 13:10 rw Address Pointer to register for read and write command DATA 9:0 rw Data Data written to or read from register selected by address ADDR ERRn n = 3 to 0 nr Diagnosis of Channel n

0 No failure

1 Over temperature, over load or short circuit

Data Sheet 64 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Serial Peripheral Interface (SPI) CLE 11 r External Clock Status 1) 0 fPCLK > fPCLK(TH) 1 fPCLK < fPCLK(TH) SBM 13 r Switch Bypass Monitor 1) LHI 14 r Limp Home Enable 2)

0 H-input signal at pin LHI

1 L-input signal at pin LHI

1) Invalid in stand-by mode 2) Not latching information, read of LHI-status during falling CS Field Bits Type Description

Serial Peripheral Interface (SPI) Data Sheet 65 Rev. 1.0, 2010-04-12

10.6 Register Overview

Note: A readout of an unused register will return the standard diagnosis. Register Bank 1 B i t 1 51 41 31 21 11 0 9 8 7 6 5 4 3 2 1 0 Name W/R RB ADDR DATA O U T W / R 00000000000 O U T 3 O U T 2 O U T 1 O U T 0 PCR W/R 0 0 1 1 1 0 0 0 0 0 0 DCS DPSH PST DCCR0 W/R 0 1 0 0 0 0 DC0 DCCR1 W/R 0 1 0 0 1 0 DC1 DCCR2 W/R 0 1 0 1 0 0 DC2 DCCR3 W/R 0 1 0 1 1 0 DC3 Field Bits Type Description RB 6 - Read Bit ADDR 5:4 w Address Pointer to register for read and write command DATA 3:0 rw Data Data written to or read from register selected by address ADDR OUTn n = 3 to 0 nr w Set Output Mode for Channel n

1 Channel n is switched on

PST 0 rw Automatic PWM Generation DPSH 6:4 rw Device Phase Shift

01 Phase shift 1: 8 / (

fPCLK (or fINT)) DCS 0 rw Single Duty Cycle for all Channels

1 Individual duty cycle setting used for each channel

n = 0 to 8:0 rw Duty Cycle for Channel n during Automatic PWM Generation ... 1xxxxxxxx DC value: 1 (channel 100% on)

Data Sheet 66 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Serial Peripheral Interface (SPI) Note: A readout of an unused register will return the standard diagnosis. B i t 1 51 41 31 21 11 0 9 8 7 6 5 4 3 2 1 0 Name W/R RB ADDR DATA I C R W / R 10001000000 C O L I N C G C S L 0 HWCR R 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 STB CL W 1 0 0 1 0 0 CLKTRIM CLK 0 LED3 LED2 RST CL D C R R1001100000 AMUX SBM MUX W 1001100000 AMUX CSOL MUX C H C R 0 W / R 11000000 P S H 0 S Y D E L 0 F R E Q 0 C H C R 1 W / R 11001000 P S H 1 S Y D E L 1 F R E Q 1 C H C R 2 W / R 11010000 P S H 2 S Y D E L 2 F R E Q 2 C H C R 3 W / R 11011000 P S H 3 S Y D E L 3 F R E Q 3 Field Bits Type Description CSL 1 rw Level for Current Source for Open Load Detection INCG 2 rw Input Drive Configuration COL 3 rw Input Combinatorial Logic Configuration

0 Normal operation

1 Device is in Standby mode

n = 3 to 2 nr w Set LED Mode for Channel n

Serial Peripheral Interface (SPI) Data Sheet 67 Rev. 1.0, 2010-04-12 CLKTRIM 8:6 rw Internal Clock Trim 000 fINT - 4 kTRIM ... 011 fINT - 1 kTRIM 100 fINT without trimming 101 fINT + 1 kTRIM ... 111 fINT + 3 kTRIM MUX 2:0 rw Set Current Sense Multiplexer Configuration in OFF-state Set Multiplexer Configuration in ON-state SBM 3 r Switch Bypass Monitor CSOL 3 w Current Source Switch for Open Load Detection AMUX 5:4 w Automatic Current Sense Multiplexer Switching (single loop)

0 Automatic current sense multiplexer switching not activated

1 Automatic current sense multiplexer switching activated and

n = 0 to 3 1:0 rw PWM Frequency Prescaler Setting for Channel n n = 0 to 3 3:2 rw Delay of Current Sense Synchronization Signal for Channel n Field Bits Type Description

Data Sheet 68 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Serial Peripheral Interface (SPI) PSHn n = 0 to 3 6:4 rw Channel Phase Shift for Channel n

001 Phase shift 1: 32/ ( fPCLK (or fINT))

... 1) For avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated PWM generator (PCR.PST = 0b). 2) Invalid in stand-by mode Field Bits Type Description

Data Sheet 69 Rev. 1.0, 2010-04-12 Figure 30 Application Circuit Example SPI VBB OUT3 OUT2 OUT1 OUT0 65W 65W 27W 10W ISSY SO SCLK SI CS GND VDD GND Circuit _ PWM.emf VDD 100nF µC e.g. XC2267 VSS VCC Vbat AD 3.9 kΩ 3.9 kΩ 5V 500 Ω 2.7 kΩ 1kΩ 1nF SPI PWM generator PCLK3.9 kΩ GPIO 3.9 kΩ 3.9 kΩ 8kΩ 8kΩ GPIO GPIO IN2 IN3 IN1 WD -O UT 10Ω LHI IS 3.9 kΩGPIO

1 For filtering and protection purposes

2 For increased ISO - pulse r obustness

WD -O UT8k Ω 10kΩ

Data Sheet 70 Rev. 1.0, 2010-04-12 SPOC - BTS6460SF Figure 31 PG-DSO-36-43 (Plastic Dual Small Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). GPS01089 2) Does not include dambar protrusion of 0.05 max. per side 1) Does not include plastic or metal protrusion of 0.15 max. per side 1 18 36 19 0.65 0.33 0.2 2.45 2.65 MAX. 0.1 -0.2 -0.1 0.23 +0.09 0.35 x 45˚ -0.2 1)7.6 10.3 0.7±0.2 8˚ MAX. ±0.3 Index Marking 1)12.8-0.2 18 1 19 36 Index Marking Ejector Mark Bottom View

0.17 M C A-B D 36x

±0.08 2) C D A B Dimensions in mm You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.

Revision History

Data Sheet 71 Rev. 1.0, 2010-04-12 Revision Date Changes 1.0 2010-04-12 Initial Data Sheet

81726 Munich, Germany

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