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Rev. 1.1, 2014-11-24 BTS6110-1SJA Smart High-Side Power Switch

Data Sheet 2 Rev. 1.1, 2014-11-24 BTS6110-1SJA Table of Contents Table of Contents

Data Sheet 3 Rev. 1.1, 2014-11-24 Smart High-Side Power Switch BTS6110-1SJA 1O v e r v i e w Application

  • Side Indicator 2 x R10W + 1 x R2W Basic Features
  • One channel device
  • Very small external reservoir capacitor of 10 µF
  • Electrostatic discha rge protection (ESD)
  • Optimized electromagnetic compatibility
  • Green product (RoHS compliant)
  • AEC qualified Protection Functions
  • Overtemperature protection with limited restart
  • Overvoltage protection without external component Diagnostic Functions
  • Auto-failure detection of a failed main lamp (N -1 diagnosis), signalized by frequency doubling

Description

The BTS6110-1SJA is a single 80 m Ω channel Smart High-Side Power Switch, embedded in a PG-DSO-8-49 package, providing protective functions and diagnosis. It is designed to drive lamps 2 x R10W + 1 x R2W to realize the side indicators function for motorcycle. Table 1 Product Summary Parameter Symbol Value Operating voltage range VS(OP) 9 V ... 16 V Load dump voltage VS(LD) 65 V Maximum ON state resistance at TJ = 150 °C RDS(ON) 200 m Ω Flasher Frequency ; normal operation f4 85 ± 15 cycles / minute 1) 1) With external capacitor CEXT = 10µF Flasher Frequency; loss of a main lamp / typical value f2 f4 * 2.24 Minimum current limitation IL(SC) 20 A

Data Sheet 4 Rev. 1.1, 2014-11-24 BTS6110-1SJA Block Diagram

2 Block Diagram

Figure 1 BTS6110-1SJA Block Diagram

3 Application Information

Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 2 Application Example Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Table 2 Bill of Material Reference Value Purpose CVS 10 nF / min. 100V Reduction of voltage spikes . It is mandatory to place this component to assure correct device behavior. CEXT 10 µF BTS6110-1SJA energy reservoir during ON state. It is mandatory to place this component to assure correct device behavior. Block diagram single .vsd OUT Over Temperature Gate Control VS T Over voltage clamping CAP Input Trigger Over Current Limiter Load Current Sense Internal Power Supply Capacitor loading Management TEST Clock Generation Driver Logic ESD OUT Vs Application example_onedash.vsd CAP CVS CEXT VBAT TEST

Data Sheet 5 Rev. 1.1, 2014-11-24

4 Pin Configuration

4.1 Pin Assignment

Figure 3 Pin Configuration

4.2 Pin Definitions and Functions

4.3 Voltage and Current Definition

Figure 4 shows all terms used in this document, with associated convention for positive values. Figure 4 Voltage and Current Definition Pin Symbol Function 1C A P CAPacitor; Must be connected to OUT via a reservoir capacitor

2 TEST TEST MODE PIN; Must be connected to OUT

3, 4 OUT OUTput; Protected high side power output channel 1) 1) All output pins must be connected toget her on the PCB. PCB traces have to be designed to withstand the maximum current which can flow. 5, 6, 7, 8 VS Voltage Supply; Battery voltage pinout Single SO 8. vsd VS VS VS CAP TEST OUT VS OUT VS CAP OUT VS VCAP I S VDS VOUT IOUT voltage and current convention single .vsd +BAT GND ICAP TEST VTEST ITEST

Data Sheet 6 Rev. 1.1, 2014-11-24 BTS6110-1SJA General Product Characteristics

5 General Product Characteristics

5.1 Absolute Maximum Ratings

  1. Stresses above the ones listed here may cause perma nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Table 3 Absolute Maximum Ratings 1) TJ = -40 °C to +150 °C; (unless otherwise specified) 1) Not subject to production test. Specified by design. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Supply Voltages Supply voltage VS -0.3 – 18 V – P_5.1.1 Reverse polarity voltage - VS(REV) 0 – 16 V t < 120 s TA = 25 °C RL ≥ 6 Ω P_5.1.2 Supply voltage for Load dump protection VS(LD) – – 65 V 2) RI = 2 Ω RL = 6 Ω 2) VS(LD) is setup without the DUT connected to the generator per ISO 7637-1. P_5.1.3 CAP Pin Voltage at CAP pin VCAP -0.3 – 8.0 V – P_5.1.4 Current through CAP pin ICAP -2 – 15 mA – P_5.1.5 TEST Pin Voltage at TEST pin VTEST -0.3 – 1 V – P_5.1.6 Current through TEST pin ITEST -2 – 2 mA – P_5.1.7 Power Stage Load current | IL |– – IL(LIM) A – P_5.1.8 Power dissipation (50% duty cycle) PTOT – – 1.4 W TA = 85 °C TJ < 150 °C P_5.1.9 Voltage at power transistor VDS – – 65 V – P_5.1.10 Temperatures Junction temperature TJ -40 – 150 °C – P_5.1.11 Storage temperature TSTG -55 – 150 °C – P_5.1.12 ESD Susceptibility ESD susceptibility (all pins) VESD -2 – 2 kV 3) HBM 3) ESD susceptibility HBM according to EIA/JESD 22-A 114B P_5.1.13 ESD susceptibility (OUT versus VS) VESD -4 – 4 kV 3) HBM P_5.1.14

General Product Characteristics Data Sheet 7 Rev. 1.1, 2014-11-24

5.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

5.3 Thermal Resistance

5.3.1 PCB set up

Figure 5 PCB Footprint for PG-DSO-8-49 Table 4 Functional Range TJ = -40 °C to +150 °C; (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Nominal operating voltage VNOM 9 13.5 16 V VOUT = 0 V P_5.2.1 Extended operating voltage VS(OP) 8 – 24 V 1) 8 to 18 V: RL = 6 Ω, 18 to 24 V: RL = 12 Ω VDS < 0.7 V 1) Not subject to production test. Specified by design. P_5.2.2 Table 5 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Junction to case (bottom) RthJS – 40 – K/W 1) 1) Not subject to production test. Specified by design. P_5.3.1 Junction to ambient RthJA – 58 – K/W 1) 2) 2) Specified Rthja value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board with thermal vias; The product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35 µm Cu). P_5.3.2 HLG05506 e A B L

Data Sheet 8 Rev. 1.1, 2014-11-24 BTS6110-1SJA General Product Characteristics

5.3.2 Thermal Resistance

Figure 6 Typical Thermal Resistance for FR2 PCB Figure 7 Typical Thermal Resistance for FR4 PCB 100 Zth‐ja [K/W] Time [s] 1s0p‐footprint 1s0p‐100mm² 1s0p‐300mm² 1s0p‐600mm² 100 Zth‐ja [K/W] Time [s] 1s0p‐footprint 1s0p‐100mm² 1s0p‐300mm² 1s0p‐600mm²

Data Sheet 9 Rev. 1.1, 2014-11-24

6 Power Stage

The power stage is built using an N-channel vertical power MOSFET (DMOS) with charge pump.

6.1 Output ON-state Resistance

The ON-state resistance RDS(ON) depends on the junction temperature TJ. Figure 8 shows the dependencies in terms of temperature for the typical ON-state resistanc e. The behavior in reverse polarity is described in Chapter 7.2. Figure 8 Typical ON-state Resistance

6.2 Turn ON/OFF Characteris tics with Resistive Load

A low voltage event at the OUT pin causes the power DMOS to switch ON with a dedicated slope, optimized in terms of Electro Magnetic Emission. Chapter 7.2 shows the typical timing when switching a resistive load. Figure 9 Switching a R esistive Load Timing -40 -20 0 20 40 60 80 100 120 140 16040 100 120 140 160 180 temp [°C] RDS(ON) [mΩ] typical RDS(ON) with VCHI typical RDS(ON) with VCLO BTS6110-1EJA VOUT tRI S E tIN IT tFALL 90% VS 10% VS t Switching times .vsd 30% VS 70% VS dV/ dt ON dV /dt OFF

6.3 Frequency Generator

6.4 Timing Output

Figure 11. Depending on the measurement results, three possible actions will be done (see Chapter 8 for the details diagnosis definition). normal diagnosis keep the power output ON for t1 to run at f4 frequency. A short circuit will latch the device.

Data Sheet 11 Rev. 1.1, 2014-11-24 Figure 11 Frequency Generation Timing

6.5 Output Polarization

The BTS6110-1SJA includes from VS to OUT a pull up resistor RL(OFF). This pull-up resistor compensates the IDIRT leakage current due to the humidity and dust at the handle bar selector. It forces supply voltage VS at the output until a load is connected. The BTS6110-1SJA starts as soon as VDS is detected between VS and OUT by charging the external reservoir capacitor CEXT. Refer to Figure 12. VOUT IOUT SHORT CIRCUIT UNDERLOAD DIAG DIAG DIAG DIAG NOMINAL LOAD T2FAIL tINIT tINIT DIAG frequency generator diag.vsd VOUT IOUT UNDERLOAD DIAG DIAG NOMINAL LOAD tINIT DIAG DIAG T2FAIL

Data Sheet 13 Rev. 1.1, 2014-11-24

6.6 CAP Pin

The BTS6110-1SJA stores the needed energy to keep the DMOS ON during T2 phase, in the capacitor CEXT. This capacitor is loaded initially with IINT while OUT is grounded. IINT is relatively important to reduce tINIT, initialization time. During the next successive activations, th e charging / discharging currents are controlled to ICLOAD and ICUNLOAD whom are significantly lower to improve EMC and capacitor aging. The loading is stopped when the voltage at the capacitor VCHI is reached, and restarted by VCLO. This oscillation provides the reference clock to the flasher functionality. In the case VS - VOUT is below VS(OP), the device doesn’t start. Refer from Equation (1) to Equation (4) and Figure 14 and Figure 15. (1) (2) (3) (4) Figure 14 Capacitor Charge and Discharge Timing tINIT CEXT VS 1V– IINIT ⎛⎞ln××= T2FAIL T4 df×= d ICUNLOAD ICLOAD T4 CEXT RCAP×= Cap_load. vsd VOUT ICAP VCAP IINIT ICUNLOAD VCHI VCLO ICLOAD tINIT t t t

Data Sheet 14 Rev. 1.1, 2014-11-24 BTS6110-1SJA Protection Functions Figure 15 Normal Period T4 Dependency in Regards to Capacitor Value (typical behavior)

7 Protection Functions

The BTS6110-1SJA provides integrated protection func tions. These functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are designed for neither continuous nor repetitive operation.

7.1 Overvoltage Protection

The BTS6110-1SJA is protected against overvoltage. In case of a voltage VS > VS(AZ), if the handle bar selector switch is ON, the ZDS(AZ) will activate the power DMOS and some current will flow, limited by the load.

7.2 Reverse Polarity Protection

In case of reverse polarity, the intrinsic body diodes of the power DMOS causes power dissipation. The current in this intrinsic body diode is limited by the load itself. Figure 16 shows the application schematic. 400 500 600 700 800 900 1000 7 8 9 1 01 11 21 3 T4 [ms] C [uF] Minimum period T4 at 25°C Nominal period T4 Maximum period T4 at 25°C Maximum period T4 in ‐20…85°C Maximum period T4 in ‐40…150°C

Data Sheet 15 Rev. 1.1, 2014-11-24 Figure 16 Reverse Polarity Protection

7.3 Overload Protection

In case of overload, such as high inrush of cold lamp filament, or short circuit to ground, the BTS6110-1SJA offers protection mechanisms.

7.3.1 Current Limitation

At first step, the instantaneous power in the switch is maintained to a safe value by limiting the current to IL(SC). During this time, the DMOS temperature is increasing.

7.3.2 Temperature Limita tion in the Power DMOS

The channel incorporates an absolute ( TJ(SC)) and a dynamic ( TJ(SW)) temperature sensor. Activation of either sensor will cause the overheated channel to switch OFF to prevent destruction. Any protective switch OFF latches the output until the temperature has reac hed an acceptable value. To ensure the lamps to be turned ON, the DMOS restarts after cool down until t1. Figure 17 sketches the situation. The restart takes place for maximum t1 of the flasher in fault condition, around 130ms. If after this time, the device is still in restart conditions, the switch is latched until the OUT voltage goes to HIGH again. OUT VBAT(REV) IOUT(REV) VS T CAP Internal Power Supply LOGIC Reverse Polarity .vsd CEXT VDS(REV) ZDS(AZ) ZDS(AZ)

Data Sheet 16 Rev. 1.1, 2014-11-24 BTS6110-1SJA Diagnostic Functions Figure 17 Overload Protection

8 Diagnostic Functions

For diagnosis purpose, the BTS6110-1SJA measures the load current.

8.1 Load Current Measurement

The BTS6110-1SJA integrates a sense signal called IIS. As long as no “hard” failure mode occurs (current limitation / overtemperature / excessiv e dynamic temperature increase) a proportional signal to the load current (ratio kILIS = IL / IIS) is measured. To reduce current consumption, the diagnosis is only realized periodically. Refer to the Figure 11. The complete sense circuit and diagnostic mechanism is described on Figure 18. In the case VIS < VREF, the device raises an internal fault signal, to double the flashing frequency. Just before the switch ON event, the device measures the supply voltage VS, via a voltage divider. Figure 18 Diagnostic Block Diagram VOUT t IOUT t IL(SC) TDMOS tTA TJ(SC) Intellilatch.vsd IL(NOM) ΔTJ(SW)ΔTJ(SW) ΔTJ(SC) LOAD CURRENT LIMITATION PHASE LATCH Latch Reset: Selector OFF -> ON Normal Operation Sense schematic single.vsd 0 if VIS > VREF 1 if VIS < VREF RIS VS OUT

Data Sheet 17 Rev. 1.1, 2014-11-24

8.2 Under load Current

Figure 19 shows the load current Idf_L considered as a function of the load current in the power DMOS. The blue curve represents the typical current threshold, assuming ideal device. The red curves show the accuracy the device provide accross full temperature range, at a defined current 1). Figure 19 Current Sense for Nominal Load 1) Only Idf_L9 and Idf_L16 are tested in production. T he red curves between these points are specified by design. Underload_new.vsd Idf_L VS Idf_L9 Idf_L16 91 6

Data Sheet 18 Rev. 1.1, 2014-11-24 BTS6110-1SJA

Electrical Characteristics

9 Electrical Characteristics

9.1 Electrical Charact eristics Power Stage

Table 6 Electrical Characteristics: Power Stage VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. ON-state resistance per channel RDS(ON)_150 – – 200 m Ω RL = 6 Ω VCAP = VCHI TJ = 150 °C See Figure 8 P_9.1.1 ON-state resistance per channel RDS(ON)_25 – 80 – m Ω 1) TJ = 25 °C 1) Not subject to production test, specified by design P_9.1.2 Drain to source clamping voltage VDS(AZ) = [VS - VOUT] VDS(AZ) 65 70 75 V IDS = 2 mA P_9.1.3 Output Leakage resistor RRAIN 0.04 0.4 1 k Ω 1) P_9.1.11 Slew rate 30% to 70% VS dV/dtON 0.1 0.25 0.5 V/µs RL = 6 Ω VS = 13.5 V See Figure 9 P_9.1.5 Slew rate 70% to 30% VS Turn-ON time to VOUT = 10 to 90% VS tRISE – 70 1) – µs P_9.1.7 Turn-OFF time to VOUT = 90 to 10% VS tFALL – 70 1) – µs P_9.1.8 Switch ON energy EON – 450 – µJ 1) RL = 6 Ω VOUT = 90% VS VS = 16 V P_9.1.9 Switch OFF energy EOFF – 470 – µJ 1) RL = 6 Ω VOUT = 10% VS VS = 16 V P_9.1.10

Data Sheet 19 Rev. 1.1, 2014-11-24

9.2 Electrical Char acteristics CAP pin

Table 7 Electrical Characteristics: CAP pin VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Load Current Initialization Load current IINIT 3 4.5 10 mA See Figure 14 VS = 9 V P_9.2.1 Charging current ICLOAD 76.4 µA 1) See Figure 14 VCAP = 5.37 V 1) Not subject to production test, specified by design P_9.2.2 Discharging current ICUNLOAD -74.4 µA 1) See Figure 14 VCAP = 5.37 V P_9.2.3 Load current matching ICRATIO = |ICUNLOAD | / ICLOAD 0.97 – 1) See Figure 14 P_9.2.4 Voltage Threshold CAP voltage High threshold VCHI 6.4 V 1) See Figure 14 P_9.2.5 CAP voltage Low threshold VCLO 4V 1) See Figure 14 P_9.2.6 CAP voltage diagnostic threshold VCDIAG 5.37 V 1) See Figure 14 P_9.2.7 CAP voltage threshold Matching VOSC = VCHI - VCLO 2.4 V 1) See Figure 14 P_9.2.8 Flasher duty cycle Device dependency RLOAD = VOSC / ICLOAD – 32 – k Ω 1) See Figure 14 P_9.2.10 Flasher duty cycle Device dependency RUNLOAD = VOSC / ICUNLOAD – 31.6 – k Ω 1) See Figure 14 P_9.2.11 Flasher duty cycle Device dependency RCAP = RUNLOAD + RLOAD 58 63.6 75 k Ω P_9.2.17 Flasher duty cycle Device dependency RCAP_USAGE 58 63.6 70.3 k Ω 1) 2) TJ = -20°C to 85°C P_9.2.19 Flasher duty cycle Device dependency RCAP_AMB 58 63.6 69.2 k Ω 1) 2) TJ = +25°C P_9.2.20 Time Generator Duty Cycle d 45 50 55 % – P_9.2.14 Double frequency factor df = T2FAIL / Initialisation Time tINIT – 30 – ms – 1)2) VS = 9V 2) With a CEXT of 10 µF P_9.2.13 Impedance sensing Time tSCAN – 25 – ms – 1)2) P_9.2.16

Data Sheet 20 Rev. 1.1, 2014-11-24 BTS6110-1SJA

9.3 Electrical Characteristi cs for the Protection Functions

Table 8 Electrical Characteristics: Protection VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Reverse Polarity Drain source diode voltage during reverse polarity VDS(REV) 200 600 700 mV R L = 6 Ω TJ = 150 °C See Figure 16 P_9.3.1 Overload Condition Load current limitation IL(SC) 20 27 36 A 1)VDS = 5 V 1) Test at TJ = -40°C only P_9.3.2 Dynamic temperature increase while switching ∆TJ(SW) –8 0 –K 2) See Figure 17 2) Not subject to production test, specified by design. P_9.3.5 Thermal shutdown temperature TJ(SC) 150 170 2) 2002) °C See Figure 17 P_9.3.3 Thermal shutdown hysteresis ∆TJ(SC) – 30 – K 2) See Figure 17 P_9.3.4

Data Sheet 21 Rev. 1.1, 2014-11-24

9.4 Electrical Character istics Diagnostic Function

Table 9 Electrical Characteristics: Diagnostics VS = 9 V to 16 V, TJ = -40 °C to +150 °C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Load Current Underload Threshold Load current threshold Low battery operation Idf_L9 0.782 0.924 1.067 A VS at 9 V step See Figure 19 P_9.4.1 Load current threshold High battery operation Idf_L16 1.074 1.269 1.464 A VS at 16 V step See Figure 19 P_9.4.2

Data Sheet 22 Rev. 1.1, 2014-11-24 BTS6110-1SJA Package Outlines Figure 20 PG-DSO-8-49 (Plastic Dual Small Outline Package) (RoHS-Compliant) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant. For the soldering of this device the appropriate temperature profile as described in J-STD-020 is to be used. Table 10 Package Classification Value Purpose MSL3 JEDEC humidity category acc. J-STD-020-D 260°C JEDEC classification te mperature acc. J-STD-020-D 0.35 x 45° 1)-0.24 C +0.06 0.19 0.64 ±0.26 ±0.25 0.2 8xM C 1.27 +0.10.41

0.2 M A

-0.06 SEATING PLANE B Index Marking 5-0.2 1) A 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area 1.75 MAX. (1.45) ±0.070.175 B0.1 8° MAX.

Revision History

Data Sheet 23 Rev. 1.1, 2014-11-24 Version Date Changes 1.1 2014-11-24 Chapter 3 - Changed position of the Notes Chapter 5.3 - Removed the hint for exposed pad packages in footnote of table 5 Chapter 6.3 - Minor text change and update of Figure 10 Chatper 6.4 - Minor text change and update of Figure 11 Chatper 6.5 - Typo in text and update of Figure 12 and 13 (typo and headline) Chapter 7.3.2 - Typo in text corrected Chapter 8.2 - Update of Figure 19 VCAP - VOUT = 5.37 V to VCAP = 5.37 V Chapter 10 - Updated package drawing Figure 20 1.0 2014-02-27 Creation of the Document

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© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.