BTS56033-LBA

BTS56033-LBA INFINEON | Alldatasheet

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Technical content

Rev. 2.0, 2014-05-26 BTS56033-LBA SPI Power Controller SPOC™+ 12V

Data Sheet 4 Rev. 2.0, 2014-05-26 Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics of MURATA MANUFACTURING CO., MICROWAVE OFFI CE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Open wave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Sate llite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Sy mbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. T EKTRONIX™ of Tektroni x Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2014-03-27

Data Sheet 5 Rev. 2.0, 2014-05-26 Table of Contents

Data Sheet 6 Rev. 2.0, 2014-05-26

Data Sheet 8 Rev. 2.0, 2014-05-26 List of Tables

/g3 Type Package Marking BTS56033-LBA TSON-24-3 BTS56033-LBA Data Sheet 9 Rev. 2.0, 2014-05-26 BTS56033-LBA 1O v e r v i e w

Features

• 8 bit serial peripheral interface (daisy chain capable SPI) for control and diagnosis
• CMOS compatible parallel input pins for four channels
• Selectable AND- / OR-combination for parallel inputs (PWM control)
• Load type configuration via SPI (bulbs or LEDs) for optimized load control
• Very low stand-by current
• Device ground independent from load ground
• Green Product (RoHS-Compliant)
• AEC Qualified

Description

The BTS56033-LBA is a six channel high-side smart pow er switch in TSON-24-3 package providing embedded protective functions. It is specially designed to control standard exterior lighting in automotive applications. In order to use the same hardware, the device can be configured to bulb or LED mode. As a result, both load types are optimized in terms of switching and diagnosis behavior. It is designed to drive exterior lamps up to 27 W and 10 W, or the equivalent LED light. Configuration and status diagnosis are done via SPI. An 8 bit serial peripheral interface (SPI) is used. The SPI is daisy chain capable. Table 1 Product Summary Operating Voltage Power Switch VS 5.5 … 28 V Logic Supply Voltage VDD 3.8 … 5.5 V Over Voltage Protection VS(AZ,min) 42 V Maximum Stand-By Current at 25 °C IVS(STB) 1µ A Maximum ON State Resistance at Tj = 150 °C 39 mΩ channels RDS(ON,max) 78 mΩ Maximum ON State Resistance at Tj = 150 °C 110 mΩ channels RDS(ON,max) 220 mΩ SPI Access Frequency fSCLK(max) 3M H z

Data Sheet 10 Rev. 2.0, 2014-05-26 The device provides a current sense signal per channel th at is multiplexed to the diagnosis pin IS. It can be enabled and disabled via SPI commands. An over temper ature flag per output is pr ovided in the SPI diagnosis word. A multiplexed switch bypass monitor provides short-circuit to VS diagnosis. 39 mΩ channels can be configured to bulb or LED mode for maximum flexibility. The BTS56033-LBA provides a fail-safe feature via a Limp Home Input (LHI) pin and direct INput pins. The power transistors are built by N-channel vert ical power MOSFETs with c harge pumps. The device is monolithically integrated in SMART technology.

Applications

• High-side power switch for 12 V in automotive or industrial applications such as lighting, heating, motor driving, energy and power distribution
• Especially designed for standard exte rior lighting like position light, tail light, brake light, parking light, license plate light, indicators and equivalent in the LED technology
• Replaces electromechanical relays, fuses and discrete circuits Protective Functions
• Reverse battery protecti on with external components
• Short circuit to ground protection
• Stable behavior at under voltage
• Current limitation
• Absolute and and dynamic temperature sensor
• Thermal shutdown with latch after a limited amount of retries
• Overvoltage protection
• Loss of ground protection
• Electrostatic discha rge protection (ESD) Diagnostic Functions
• Multiplexed proportional load current sense signal (IS)
• Enable function for current s ense signal configurable via SPI
• High accuracy of current sense signal at wide load current range
• Current sense ratio ( kILIS) configurable for LEDs or bulbs
• Very fast diagnosis in LED mode
• Feedback on over temperature via SPI
• Short circuit to VS detection
• Monitoring of I nput pins status Application Specific Functions
• Fail-safe activation via LHI pin and control via input pins
• Enhanced electromagnetic compatibility (EMC) for bulbs as well as LEDs
• LED mode selection available
• SPI with daisy chain capability
• Switch bypass monitoring for detecting short circuit to VS

Data Sheet 11 Rev. 2.0, 2014-05-26 2B l o c k D i a g r a m Figure 1 Block Diagram BTS56033-LBA 65432channel 1 power supply driver logic gate control charge pump clamp for inductive load load current limitationload current sense temperature sensor ESD protection GND SO SCLK SI CS LHI VS OUT4 OUT3 OUT2 OUT1 IN2 IN3 IN1 IS VDD IN4 limp home control SPI current sense multiplexer switch bypass monitor LED mode control OUT6 OUT5 BlockDiagram _ 033 .emf

Data Sheet 12 Rev. 2.0, 2014-05-26

2.1 Terms

Figure 2 shows all terms used in this data sheet, with associated convention for positive values. Figure 2 Voltage and Current Definition In all tables of electrical characteri stics, symbols related to channels without channel number are valid for each channel separately (e.g. VDS specification is valid for VDS1 … VDS6). All SPI register bits are marked as follows: ADDR.PARAMETER (e.g. HWCR.STB) with the exception of the bits in the Diagnosis frames which are marked only with PARAMETER (e.g. VSMON). IDD VDD VSO VIN 2 ISI ICS VS IIS IS VDD SO SI CS IS VS VSI VCS VSC LK VIN 1 IIN 1 IN1 IN2 ISC LK SCLK VIS GND IGND VLHI ILHI LHI OUT1 IL1 OUT2 IL2 OUT3 IL3 OUT4 IL4 VOUT4 VOUT3 VDS4 VDS 3 VOUT2 VOUT1 VDS2 VDS 1 ISO IIN 2 Terms_033 .emf VIN 3 IIN 3 IN3 VIN 4 IIN 4 IN4 OUT5 IL5 VOUT5 OUT6 IL6 VOUT6 VDS 5 VDS6

Data Sheet 13 Rev. 2.0, 2014-05-26

3 Pin Configuration

3.1 Pin Assignment BTS56033-LBA

Figure 3 Pin Configuration TSON-24-3 (top view) OUT3 OUT3 OUT4 OUT1 OUT1 OUT2 OUT2 OUT417 OUT5 OUT5 OUT6 OUT6 CS SCLK SI SO IN2 IN1 IN3 IN4 LHI IS VS exposed pad (bottom ) VDD GND Pinout_033 .emf

Data Sheet 14 Rev. 2.0, 2014-05-26

3.2 Pin Definitions and Functions

25 VS – Positive power supply for high-side power switch

1 GND – Ground connection

2 VDD – Logic supply (5 V)

SPI & Diagnosis Pins

3 SO O Serial output of SPI interface

4 SI I Serial input of SPI interface (“high” active)

5 SCLK I Serial clock of SPI interface (“high” active)

6 CS I Chip select of SPI interface (“lo w” active); Integrated pull up to VDD

12 IS O Current sense output signal

Limp Home Input Pin (integrated pull-down, leave unused Limp Home Input pin unconnected)

7 LHI I Limp home activation signal (“high” active)

Parallel Input Pins (integrated pull-down, leave unused pins unconnected)

8 IN1 I Input signal of channel 1 (“high” active)

9 IN2 I Input signal of channel 2 (“high” active)

10 IN3 I Input signal of channel 3 (“high” active)

11 IN4 I Input signal of channel 4 (“high” active)

23, 24 1) All outputs pins of each channel must be connected together on the PCB. All pins of an output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. OUT1 O Protected high-side power output of channel 1 21, 22 1) OUT2 O Protected high-side power output of channel 2 19, 20 1) OUT3 O Protected high-side power output of channel 3 17, 18 1) OUT4 O Protected high-side power output of channel 4 15, 16 1) OUT5 O Protected high-side power output of channel 5 13, 14 1) OUT6 O Protected high-side power output of channel 6

Electrical Characteristics

Data Sheet 15 Rev. 2.0, 2014-05-26

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Tj = -40 to +150 °C; all voltages with respect to ground Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) 110 mΩ channels: RL = 18 Ω Table 2 Absolute Maximum Ratings 1) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Supply Voltage Power supply voltage Logic supply voltage VDD -0.3 5.5 V – P_4.1.2 Reverse polarity voltage -VS(rev) –1 6 V 2) TjStart = 25 °C t ≤ 2m i n . See Chapter 10 for setup P_4.1.3 Supply voltage for short circuit protection (single pulse) VS(SC) 02 8 V 3) RECU = 20 mΩ l = 0 or 5 m RCable = 16 mΩ/m LCable = 1 µH/m P_4.1.5 Permanent short circuit Number channel activations All channels nRSC1 - 100 k 3) VDD = 5 V tON = 300ms P_4.1.6 Voltage at power transistor VDS –4 2 V – P_4.1.8 Supply voltage for load dump protection VS(LD) –4 2 V 4) RI = 2 Ω t = 400 ms P_4.1.9 Current through ground pin IGND -100 25 mA t ≤ 2m i n . P_4.1.10 Current through VDD pin IDD -25 30 mA t ≤ 2m i n . P_4.1.11 Power Stages Load current |IL| –I L(LIM) A 5) P_4.1.12 Maximum energy dissipation single pulse - 39 mΩ ch. EAS –4 5 m J 6) Tj(0) = 150 °C IL(0) = IL(nom) = P_6.6.17 P_4.1.15 Maximum energy dissipation single pulse - IL(nom) 110 mΩ ch. EAS –2 0 m J 7) Tj(0) = 150 °C IL(0) = IL(nom) = P_6.6.18 P_4.1.16

Data Sheet 16 Rev. 2.0, 2014-05-26 Diagnosis Pin Voltage at sense pin IS VIS -0.3 VS V– P_4.1.24 Current through sense pin IS IIS -10 40 mA t ≤ 2m i n . P_4.1.25 Input Pins Voltage at input pins Current through input pins IIN -0.75 0.75 mA – P_4.1.27 Current through input pins IIN -2.0 10 mA t ≤ 2m i n . P_4.1.28 SPI Pins Voltage at chip select pin Current through chip select pin ICS -0.75 0.75 mA – P_4.1.30 Current through chip select pin ICS -2.0 10 mA t ≤ 2m i n . P_4.1.31 Voltage at serial input pin VSI -0.3 6.0 V – P_4.1.32 Current through serial input pin ISI -0.75 0.75 mA – P_4.1.33 Current through serial input pin ISI -2.0 10 mA t ≤ 2m i n . P_4.1.34 Voltage at serial clock pin VSCLK -0.3 6.0 V – P_4.1.35 Current through serial clock pin ISCLK -0.75 0.75 mA – P_4.1.36 Current through serial clock pin ISCLK -2.0 10 mA t ≤ 2m i n . P_4.1.37 Current through serial output pin SO ISO -0.75 0.75 mA – P_4.1.38 Current through serial output pin SO ISO -10 2.0 mA t ≤ 2m i n . P_4.1.39 Limp Home Input Pin Voltage at Limp Home Input pin Current through Limp Home Input pin ILHI -0.75 0.75 mA – P_4.1.41 Current through Limp Home Input pin ILHI -2.0 10 mA t ≤ 2m i n . P_4.1.42 Temperatures Junction temperature Tj -40 150 °C – P_4.1.45 Dynamic temperature increase while switching Storage temperature Tstg -55 150 °C – P_4.1.47 ESD Susceptibility ESD susceptibility HBM OUT pins vs. VS VESD -4 4 kV 8) HBM P_4.1.48 ESD susceptibility HBM all pins vs. VDD VESD -1.5 1.5 kV 8) HBM P_4.1.54 ESD susceptibility HBM other pins vs. GND incl. OUT pins vs. GND VESD -2 2 kV 8) HBM P_4.1.49 Table 2 Absolute Maximum Ratings 1) (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 17 Rev. 2.0, 2014-05-26 Notes 1. Stresses above the ones listed here may cause perma nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. ESD Resistivity to GND VESD -500 500 V 9) CDM P_4.1.51 ESD Resistivity Pin 1, 12, 13, 24 (corner pins) to GND VESD1, 12, 13, 24 -750 750 V 9) CDM P_4.1.52 1) Not subject to production test, specified by design. 2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip and package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. 3) EOL tests according to AECQ100-012. Thresh old limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer for short-circuit capability at the end of this document. 4) RI is the internal resistance of the load dump pulse generator. 5) Current limitation is a protection fe ature. Protection features are not designed for continuous repetitive operation. 6) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse 7) Pulse shape represents inductive switch off: ID(t) = ID(0) × (1 - t / tpulse); 0 < t < tpulse 8) ESD resistivity, HBM according to ANSI/ESDA/JEDEC JS-001-2010 9) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1 Table 2 Absolute Maximum Ratings 1) (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 18 Rev. 2.0, 2014-05-26

4.2 Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org.

4.2.1 PCB set up

Figure 4 2s2p PCB Cross Section Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Junction to Soldering Point RthJSP –2–K / W 1) Tj(0) = 105 °C measured to pin 25 1) Not subject to production test, specified by design. P_4.2.1 Junction to Ambient RthJA –2 1 –K / W 1)2) Tj(0) = 105 °C 2) Specified RthJA values is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip and package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where applicable, a thermal via array under the package contacted the first inner copper layer. P_4.2.2 1.5mm 70µm 35µm 0.3mm Zth_PCB_2s2p .emf

Data Sheet 20 Rev. 2.0, 2014-05-26 Figure 7 Solder Area / Vias

4.2.2 Thermal Impedance

Figure 8 Typical Thermal Impedance. PCB setup according Figure 6 /g4/g3/g5 /g5 /g5/g4 /g5/g4/g4 /g4/g3/g4/g4/g4/g5 /g4 /g3/g4/g4/g5 /g4 /g3/g4/g5 /g4 /g3/g5 /g5 /g5/g4 /g5/g4/g4 /g5/g4/g4/g4 /g18/g26/g22/g2/g12/g10/g1/g19/g13/g3/g17/g20 /g16/g23/g24/g21/g1/g19/g25/g20 /g11/g16/g15/g7/g8/g4/g6/g6/g14/g11/g27/g2/g11/g16/g15/g7/g7/g4/g6/g5/g14/g11/g27 /g6/g17/g6/g15 /g5/g17/g4/g15/g1/g2/g1/g8/g4/g4/g1/g12/g12/g19 /g5/g17/g4/g15/g1/g2/g1/g7/g4/g4/g1/g12/g12/g19 /g5/g17/g4/g15/g1/g2/g1/g10/g14/g14/g18/g15/g16/g11/g13/g18

Data Sheet 21 Rev. 2.0, 2014-05-26 Figure 9 Typical Thermal Resistance. PCB setup 1s0p /g4/g1 /g4/g6 /g5/g1 /g5/g6 /g6/g1 /g6/g6 /g7/g1 /g1 /g2/g1/g1 /g3/g1/g1 /g4/g1/g1 /g5/g1/g1 /g6/g1/g1 /g7/g1/g1 /g9/g1/g1 /g16/g32/g25/g2/g13/g10/g1/g20/g14/g3/g19/g21 /g12/g30/g30/g27/g26/g29/g24/g1/g22/g31/g23/g22/g1/g20/g28/g28/g34/g21 /g11/g18/g17/g7/g8/g4/g6/g6/g15/g11/g33/g2/g11/g18/g17/g7/g7/g4/g6/g5/g15/g11/g33 /g2/g11/g1/g10

Data Sheet 22 Rev. 2.0, 2014-05-26

5 Power Supply

The BTS56033-LBA is supplied by two voltage sources:

• VS (analog supply voltage)
• VDD (digital supply voltage) The VS supply line is connected to a battery feed and used for the driving circuitry of the power stages, while VDD is used for the SPI logic and for driving SO pin. VS and VDD supply voltages have an undervoltage detection circuit, which prevents the activation of the associated function in case the measured voltage is below the undervoltage threshold. More in detail:
• An undervoltage on VDD supply prevents SPI communication. SPI registers are reset to default values. The retry counters used to protect the channels are reset therefore the channels are in “unlimited restart” mode.
• An undervoltage on VS supply switches OFF all channels, even in Limp Home mode. The channels are enabled again as soon as VS = VS(OP). The voltage at pin VS is also monitored. In case of a negative voltage transient resulting in VS < VSMON with DCR.MUX ≠ “111B”, any SPI command sent by the micro-controller is not accepted (see Chapter 9.5 for further details). An overview of channel behavior according to different VS and VDD supply voltages is shown in Table 4 (the table is valid after a successful supply voltage ramp-up). Table 4 Device capability as function of VS and VDD VDD ≤ VDD(PO) (VDD(PO) = P_5.3.17) VDD > VDD(PO) VS ≤ VSMON (VSMON = P_5.3.12) Channels are OFF Channels are OFF SPI registers reset SPI registers protected SPI communication not available fSCLK = 0 MHz) SPI communication available1) (fSCLK = 3 MHz) 1) SPI response depends on DCR.MUX value. See Chapter 9.5 for further details Limp Home mode not available Limp Home mode not available VSMON < VS ≤ VS(UV) (VS(UV) = P_5.3.2) Channels are OFF Channels are OFF SPI registers reset SPI registers available SPI communication not available fSCLK = 0 MHz) SPI communication available (fSCLK = 3 MHz) Limp Home mode available (channels are OFF) Limp Home mode available (channels are OFF) VS > VS(UV) 2) The undervoltage condition on VS supply must be considered. See Chapter 5.2.1 for further details Channels cannot be controlled by SPI Channels can be switched ON and OFF SPI registers reset SPI registers available SPI communication not available fSCLK = 0 MHz) SPI communication available (fSCLK = 3 MHz) Limp Home mode available Limp Home mode available

Data Sheet 23 Rev. 2.0, 2014-05-26

5.1 Operation modes

BTS56033-LBA has the following operation modes:

• Stand-by mode
• Idle mode
• Ready mode
• Operative mode
• Limp Home mode The transition between operation modes is determined according to these variables:
• logic level at LHI pin
• logic level at INn pins
• DCR.MUX bits state
• OUT.OUTn bits state The state diagram including the possible transitions is shown in Figure 10. The behavior of BTS56033-LBA as well as some parameters may change in dependence from the operation mode of the device. Furthermore, due to the undervoltage detection circuitry which monitors VS and VDD supply voltages, some changes within the same operation mode can be seen accordingly. Figure 10 Operation Mode state diagram There are three parameters describing the behavior of BTS56033-LBA:
• status of output channels
• status of SPI registers
• status of SPI communication It is necessary to set DCR.MUX to a value different from 111 B to command a switch ON of one or more channels. In alternative it is necessary to set the LHI to “high” - in this case the logic state of the Input pins is reflected to the outputs (if there is no undervoltage condition on VS supply). PowerSupply_OpModes .emf DCR.MUX ≠ "111" Power -up Idle DCR.MUX =" 1 1 1 "o r VDD < VDD(P O) or HWCR.RST = " 1" OUT.OUTn = " 1" or INn = "high" OUT.OUTn = " 0" &I N n = " l o w " DCR.MUX ≠"111" DCR.MUX = "111 " or (VDD < VDD( P O ) & INn = "high") or (HWCR.RST= "1" & INn = "high") OUT.OUTn = "1" or INn = "high" OUT.OUTn= "0" or (VDD < VDD (P O)& INn = "low") or HWCR.RST= "1" LHI = "high" LHI = "low" &I N n = " h i g h " LHI = "high " LHI = "high " LHI = "low" &I N n = " l o w " LHI = "high" (VDD < VDD(PO) & INn = „low“) o r (HWCR .RS T= "1" & I Nn = „low“) Operative Ready Limp Home Stand-by Note: Registers which are not mentioned are considered to be in default state

Data Sheet 24 Rev. 2.0, 2014-05-26 Table 5 shows the correlation between device operation modes, VS and VDD supply voltages, and the state of the most important functions (channel status, SPI communication and SPI registers).

5.1.1 Power-up

The Power-up condition is entered when one of the supply voltages ( VS or VDD) is applied to the device. Both supplies are rising until they are above the undervoltage thresholds VS(OP) and VDD(PO) therefore the internal power- on signals are set.

5.1.2 Stand-by mode

When BTS56033-LBA is in Stand-by mode, all outputs are OFF. The SPI registers can be programmed if VDD > VDD(PO). The current consumption is minimum (see parameter IVS(STB)). The circuitry that monitors VS versus the threshold VSMON is disabled, allowing the programmi ng of the registers. Even if one Input pin is set to “high” or if one OUT.OUTn bit is set to “1”, all outputs stay switched OFF.

5.1.3 Idle mode

In Idle mode, the internal supply circuitry is working and the device current consumption is increased. All channels are OFF and a command to switch ON one or more outputs (either via SPI or via Input pins) is accepted and executed, bringing the device into Operative mode. SPI communication is possible. Table 5 Device function in relation to operation modes, VS and VDD voltages Operation Mode Function VS ≤ VSMON VSMON >V S ≤ VS(UV) VS > VS(UV) Stand-by Channels OFF OFF OFF SPI comm. available 1) 1) if VDD > VDD(PO), otherwise not available or in reset available1) available1) SPI registers available 1) available1) available1) Idle Channels OFF OFF OFF SPI comm. available 1) available1) available1) SPI registers available 1) available1) available1) Ready Channels OFF OFF OFF SPI comm. all commands rejected1) available1) available1) SPI registers available 1) available1) available1) Operative Channels OFF OFF follow SPI and/or Input pins SPI comm. all commands rejected1) available1) available1) SPI registers available 1) available1) available1) Limp Home Channels OFF OFF follow Input pins SPI comm. all commands rejected1) available (read-only) available (read-only) SPI registers available (ERR_MUX only)1) available (ERR_MUX only)1) available (ERR_MUX only)1)

Data Sheet 25 Rev. 2.0, 2014-05-26

5.1.4 Ready mode

In Ready mode, one or more outputs received a command to switch ON (either via SPI or via Input pins). Nevertheless all outputs are OFF because of DCR.MUX bits still set to 111B. It is necessary to change the value of those bits to bring the device into Operative mode and switch ON the channels.

5.1.5 Operative mode

Operative mode is the normal operation mode of BTS56033-LBA when no Limp Home condition is set and one or more outputs are switched ON. Device curr ent consumption is specified by parameter IGND. An undervoltage condition on VDD supply voltage brings the device into Stand-by mode (if all Input pins are set to “low”) or into Ready mode (if at least one Input pin is set to “high”).

5.1.6 Limp Home mode

BTS56033-LBA enters Limp Home mode when LHI pin is set to “high”. SPI registers are reset to the default value after tLHI(ac) from the rising edge at pin LHI (see Figure 11 for further details). SPI communication is possible but only in read-only mode (SPI registers can be read but cannot be written, meaning that current sensing is not available). When VS ≤ VSMON the logic state detected at pin LHI is ignored and the device doesn’t enter Limp Home mode. Figure 11 Limp Home Activation as function of VS

5.2 Reset condition

One of the following 3 conditions resets the SPI registers to the default value:

• VDD is not present or below the undervoltage threshold VDD(PO)
• LHI pin is set to “high” and VS > VSMON
• a reset command ( HWCR.RST set to “1”) is executed – ERR_MUX, ERR_COUNTERn and ERRn bits are not cleared by a reset command (for functional safety) In particular, all channels are switched OFF (if the device is not in Limp Home mode with one or more Input pins set to “high”). In case of lack of VDD supply the internal retry counters are disabled therefore all channels are in “unlimited restart” mode. LHI pin LHI bit SPI state tLHI( ac) t < tLHI(ac) ,min tLHI( ac) t < tLHI(ac) ,min PowerSupply_LimpHomeActive. emf Normal operation Reset Normal operation VS VSMON

Data Sheet 26 Rev. 2.0, 2014-05-26

5.2.1 Undervoltage on VS

Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative and the supply voltage drops below the undervoltage threshold VS(UV), the logic switches OFF the channels. As soon as the supply voltage VS is above the minimum operative voltage threshold VS(OP), the channels having either the corresponding Input pin set to “high” or the OUT.OUTn bit set to “1” are switched ON again (as shown in Figure 12). Figure 12 VS undervoltage behavior PowerSupply_ UVRVS.emf t VS(OP ) VS(UV ) VS(H YS ) t VOUT VS

Data Sheet 27 Rev. 2.0, 2014-05-26

5.3 Electrical Characteristics

Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C Typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) 110 mΩ channels: RL = 18 Ω Table 6 Electrical Characteristics Power Supply Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. VS pin Operating voltage power switch VS(OP) 5.5 – 28 1) V VDS < 0.5 V P_5.3.1 Undervoltage shutdown VS(UV) ––4 . 5 V O U T n = O N From VDS < 1 V to ILn =0A (see Figure 12) P_5.3.2 Undervoltage shutdown Hysteresis VS(HYS) –3 5 0 –m V 1) P_5.3.3 Stand-by current for whole device with loads IVS(STB) –0 . 1 1 μA 1) VDD = 0 V VLHI = 0 V Tj = 25 °C P_5.3.7 Stand-by current for whole device with loads IVS(STB) –0 . 1 2 . 5 μA 1) VDD = 0 V VLHI = 0 V Tj = 85 °C P_5.3.8 Stand-by current for whole device with loads IVS(STB) –41 5 μA VDD = 0 V VLHI = 0 V Tj = 150 °C P_5.3.26 Idle current for whole device with loads, all channels off. IVS(idle) –2 . 2 5 5m A VDD = 5 V DCR.MUX = 110B P_5.3.10 Operating current for whole device IGND – 1 01 8m A fSCLK = 0 MHz P_5.3.28 VS threshold for Limp Home validation VDD pin Logic supply voltage VDD 3.8 – 5.5 1) V fSCLK = 3 MHz P_5.3.13 Logic supply current Normal operation IDD –1 2 5 2 2 0 μA fSCLK = 0 MHz VCS = VDD= 5 V DCR.MUX ≠ 111B P_5.3.14 Logic Stand-by current IDD(STB) –3 5 7 0 μA fSCLK = 0 MHz VCS = VDD= 5 V DCR.MUX = 111B P_5.3.16

Data Sheet 28 Rev. 2.0, 2014-05-26 Note: Characteristics show the deviation of parameter at the given supply voltage and junction temperature. Typical values show the typical parameters expected from manufacturing at VS =1 3 . 5V , VDD = 4.3 V and Tj =2 5° C Power-On reset threshold voltage VDD(PO) 2.3 2.75 3.8 V SI = 0 V SCLK = 0 V CS = 0 V SO from 0 to Z P_5.3.17 LHI Input Characteristics L-input level at pin LHI VLHI(L) -0.3 – 1.0 V LHI = 1 (see Chapter 9.6.1) P_5.3.18 H-input level at pin LHI VLHI(H) 2.6 – 6.0 V – P_5.3.19 L-input current through pin LHI ILHI(L) 32 7 7 5 μA VLHI = 1.0 V P_5.3.20 H-input current through pin LHI ILHI(H) 73 0 7 5 μA VLHI = 2.6 V P_5.3.21 Timings Power-On wake up time tWU(PO) –2 0 0 – μs 1) P_5.3.22 Limp Home acknowledgement time tLHI(ac) 5–3 0 μs VDD = 5 V polling of Standard Diagnosis (see Chapter 9.6.1) until LHI = STB = 1 P_5.3.23 Reset command delay time td(RST) ––1 0 0 μs 1) P_5.3.25 1) Not subject to production test, specified by design. Table 6 Electrical Characteristics Power Supply (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 29 Rev. 2.0, 2014-05-26

6 Power Stages

The high-side power stages are built by N-channel vert ical power MOSFETs with charge pumps. There are six channels implemented in the device. Each ch annel can be switched on via SPI register OUT or via an input pin, when available. Channels 2, 3 and 4 provide a load type configuration for bulbs or LEDs in register LGCR (see Chapter 9.7.4). The load type configuration can be changed in ON- as well as in OFF-state.

6.1 Output ON-State Resistance

The ON-state resistance RDS(ON) depends mainly on the junction temperature Tj. Figure 13 shows the variation of RDS(ON) across the whole temperature range. Th e value “1” corresponds to the typical RDS(ON) measured at TJ =2 5 ° C . Figure 13 RDS(ON) variation factor The behavior in reverse polarity mode is described in Chapter 7.

6.2 Input Circuit

There are two ways of using the input pins in combination with the register OUT by programming bit HWCR.COL in register HWCR (see Chapter 9.7.6).

• HWCR.COL = 0: A channel is switched ON either by the according OUT.OUTn bit or by the input pin.
• HWCR.COL = 1: A channel is switched ON by the according OUT.OUTn bit only, when the input pin is “high”. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by the SPI register OUT (see Chapter 9.7.1). The default state (HWCR.COL = 0) is the OR-combination of the input signal and the SPI-bit. In Limp Home Mode (LHI pin set to “high”) the combinatorial logic is switched to OR-mode to enable a channel activation via the input pins only. Figure 14 shows the complete input switch matrix. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 - 4 0 - 2 00 2 04 06 08 0 1 0 0 1 2 0 1 4 0 160 RDS(ON) variation factor Junction Temperature (°C) RDS(ON) variation factor ("1" = RDS(ON) typical @ 25°C)

Data Sheet 30 Rev. 2.0, 2014-05-26 The zener diode protects the input circuit against ESD pu lses. The current sink to ground ensures that the input signal is low in case of an open input pin.

6.3 Input Status Monitor

The level of the input stage can be monitored via the input status monitor. The input status is indicated in the OUT register for the available input pin. After setting the bit SWCR.SWR, the readout the output register OUT shows the state of the input pins. The input status monitor is operational only when BTS56033-LBA is not in stand-by op eration. During stand-by operation this function is not supported. Figure 14 Input Switch Matrix IN1 IN2 Gate Driver 3 Gate Driver 2 Gate Driver 1 Gate Driver 4 OR OUT3 OUT2 OUT1OUT4 OR IIN 1 IIN 2 COL Gate Driver 5 INST OUT5 INST2 INST1 IN3 IN4 OR OR IIN 2 IIN 3 INST3INST4 Gate Driver 6 OUT6 PowerStage _InputMatrix _ 033. emf

Data Sheet 31 Rev. 2.0, 2014-05-26

6.4 Power Stage Output

The power stages are built to be used in high side configuration (Figure 15). The power DMOS switches with a dedicated slope, which is optimized in terms of electromagnetic emission (EME). Defined slew rates allow lowest EME during PWM operation at low switching losses. Figure 15 Power Stage Output

6.4.1 Bulb and LED Mode

Channels 2, 3 and 4 can be configured in bulb a nd LED mode via the SPI initialization registers LGCR when SWCR.SWR = 0. The default state is LGCR.LEDn = 0. During LED mode the following parameters are changed for an optimized functionality with LED loads: ON-state resistance RDS(ON), switching timings (tdelay(ON), tdelay(OFF), tON, tOFF), slew rates dV/dtON and dV/dtOFF, load current protections IL(LIM) and current sense ratio kILIS.

6.4.2 Switching Resistive Loads

When switching resistive loads the following switching times and slew rates can be considered. Figure 16 Switching a Load (resistive) PowerStage _Output . emf OUT GND VOUT VS VDS VS VOUT t PowerStage _SwitchON.emf t 90 % of Vs 10 % of Vs 70 % of Vs dV / dtON 30 % of Vs 70% of Vs dV / dtOFF 30% of Vs tdelay (ON) tdelay( OFF ) IN / OUT.OUTn tON tOFF

Data Sheet 32 Rev. 2.0, 2014-05-26

6.4.3 Switching Inductive Loads

When switching OFF inductive loads wi th high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to cont inue driving the current. To prevent the destruction of the device due to overvoltage, there is a voltage clamp mechanism implem ented which limits that negat ive output voltage to a allowed load inductance is limited.

6.4.4 Switching Channels in Parallel

In case of appearance of a short circuit with channels in parallel driving a single load, BTS56033-LBA output stages are not synchronized in the restart event. When all channels connected to the same load are in temperature limitation, the channel which has cooled down the fastest doesn't wait for the other ones to be cooled down as well to restart. Thus, it is not recommended to use the device with channels in parallel. Note: In case of parallel channel operation, short circuit robustness may be reduced and nRSC1 is not guaranteed any more.

Data Sheet 33 Rev. 2.0, 2014-05-26

6.5 Electrical Characteristics

Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C Typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) 110 mΩ channels: RL = 18 Ω Table 7 Electrical Characteristics Power Stages Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Output Characteristics On-State resistance 39 mΩ ch. RDS(ON) –3 9 –m Ω 1) VS = 9 V to 18 V IL = 2.6 A Tj = 25 °C LGCR.LEDn = 0 P_6.6.9 On-State resistance 39 mΩ ch. RDS(ON) ––7 8 m Ω VS = 9 V to 18 V IL = 2.6 A Tj = 150 °C LGCR.LEDn = 0 P_6.6.10 On-State resistance 39 mΩ ch. in LED mode RDS(ON) –1 3 7 –m Ω 1) VS = 9 V to 18 V IL = 0.6 A Tj = 25 °C LGCR.LEDn = 1 P_6.6.11 On-State resistance 39 mΩ ch. in LED mode RDS(ON) ––2 7 5 m Ω VS = 9 V to 18 V IL = 0.6 A Tj = 150 °C LGCR.LEDn = 1 P_6.6.12 On-State resistance 110 mΩ ch. RDS(ON) –1 1 0 –m Ω 1) VS = 9 V to 18 V IL = 2 A Tj = 25 °C P_6.6.13 On-State resistance 110 mΩ ch. RDS(ON) ––2 2 0 m Ω VS = 9 V to 18 V IL = 2 A Tj = 150 °C P_6.6.14 Nominal load current 39 mΩ ch. (all channels active) IL(nom) –2–A 1) TA = 85 °C Tj < 150 °C P_6.6.17 Nominal load current 110 mΩ ch. (all channels active) IL(nom) –1 . 2 –A 1) TA = 85 °C Tj < 150 °C P_6.6.18 Output clamp VDS(CL) 42 47 54 V IL = 20 mA P_6.6.19

Data Sheet 34 Rev. 2.0, 2014-05-26 Output leakage current per channel Tj ≤ 85°C 39 mΩ ch. IL(OFF) – 0.02 0.5 µA 2) VIN = 0 V or floating OUT.OUTn = 0 Tj ≤ 85°C Stand-by or Idle mode P_6.6.22 Output leakage current per channel Tj ≤ 85°C 110 mΩ ch. IL(OFF) – 0.02 0.5 µA 2) VIN = 0 V or floating OUT.OUTn = 0 Tj ≤ 85°C Stand-by or Idle mode P_6.6.23 Output leakage current per channel Tj = 150°C 39 mΩ ch. IL(OFF) –1 . 3 4 . 5 µ A VIN = 0 V or floating OUT.OUTn = 0 Tj = 150°C Stand-by or Idle mode P_6.6.26 Output leakage current per channel Tj = 150°C 110 mΩ ch. IL(OFF) –0 . 5 4µ A VIN = 0 V or floating OUT.OUTn = 0 Tj = 150°C Stand-by or idle mode P_6.6.27 Input Characteristics L-input level VIN(L) -0.3 – 1.0 V – P_6.6.28 H-input level VIN(H) 2.6 – 6.0 V – P_6.6.29 L-input current IIN(L) 3 2 77 5µ A VIN = 1.0 V P_6.6.30 H-input current IIN(H) 7 3 07 5µ A VIN = 2.6 V P_6.6.31 Timings Turn-ON delay to 10% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. tdelay(ON) 10 30 70 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.36 Turn-ON delay to 10% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. in LED mode tdelay(ON) 3 1 02 5µ s VS = 13.5 V LGCR.LEDn = 1 P_6.6.37 Turn-ON delay to 10% VS (Logical propagation delay from input INn to output OUTn) 110 mΩ ch. tdelay(ON) 10 30 70 µs VS = 13.5 V P_6.6.38 Turn-OFF delay to 90% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. tdelay(OFF) 10 30 70 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.43 Table 7 Electrical Characteristics Power Stages (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 35 Rev. 2.0, 2014-05-26 Turn-OFF delay to 90% VS (Logical propagation delay from input INn to output OUTn) 39 mΩ ch. in LED mode tdelay(OFF) 3 1 02 5µ s VS = 13.5 V LGCR.LEDn = 1 P_6.6.44 Turn-OFF delay to 90% VS (Logical propagation delay from input INn to output OUTn) 110 mΩ ch. tdelay(OFF) 10 30 70 µs VS = 13.5 V P_6.6.45 Turn-ON time to 90% VS 39 mΩ ch. tON 30 75 180 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.50 Turn-ON time to 90% VS 39 mΩ ch. in LED mode tON 10 25 55 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.51 Turn-ON time to 90% VS 110 mΩ ch. tON 30 75 180 µs VS = 13.5 V P_6.6.52 Turn-OFF time to 10% VS 39 mΩ ch. tOFF 30 75 180 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.57 Turn-OFF time to 10% VS 39 mΩ ch. in LED mode tOFF 10 25 55 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.58 Turn-OFF time to 10% VS 110 mΩ ch. tOFF 30 75 180 µs VS = 13.5 V P_6.6.59 Turn-ON/OFF matching 39 mΩ ch. tON - tOFF -30 0 50 µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.68 Turn-ON/OFF matching 39 mΩ ch. in LED mode tON - tOFF -20 0 20 µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.69 Turn-ON/OFF matching 110 mΩ ch. tON - tOFF -30 0 50 µs VS = 13.5 V P_6.6.70 Turn-ON slew rate 30% to 70% VS 39 mΩ ch. dV/ dtON 0.1 0.25 0.5 V/µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.75 Turn-ON slew rate 30% to 70% VS 39 mΩ ch. in LED mode dV/ dtON 0.35 0.88 1.75 V/µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.76 Turn-ON slew rate 30% to 70% VS 110 mΩ ch. Table 7 Electrical Characteristics Power Stages (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 36 Rev. 2.0, 2014-05-26 Turn-OFF slew rate 70% to 30% VS 39 mΩ ch. -dV/dtOFF 0.1 0.25 0.5 V/µs VS = 13.5 V LGCR.LEDn = 0 P_6.6.82 Turn-OFF slew rate 70% to 30% VS 39 mΩ ch. in LED mode -dV/dtOFF 0.35 0.88 1.75 V/µs VS = 13.5 V LGCR.LEDn = 1 P_6.6.83 Turn-OFF slew rate 70% to 30% VS 110 mΩ ch. Output Voltage Drop Output voltage drop limitation at small load currents 39 mΩ ch. in LED mode VDS(NL) - 1 02 5m V IL = 50 mA LGCR.GBRn = 1 P_6.6.94 Output voltage drop limitation at small load currents 110 mΩ ch. VDS(NL) – 1 53 0m V IL = 20 mA P_6.6.95 1) Not subject to production test, specified by design. 2) Tested at Tj = -40 °C Table 7 Electrical Characteristics Power Stages (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 37 Rev. 2.0, 2014-05-26

7 Protection Functions

The device provides embedded protective functions, wh ich are designed to prevent IC destruction under fault conditions described in this data sheet. Fault condit ions are considered as “out side” normal operating range. Protective functions are neither designed for continuous nor for repetitive operation.

7.1 Over Load Protection

The load current IL is limited by the device itself in case of over load or short circuit to ground. 39 m Ω channels have 2 steps of current limitation which are selected automatically depending on the voltage VDS across the power DMOS as show in Figure 17. 110 mΩ channels have 1 step therefore the current limitation threshold is the same across the whole VDS range (see Figure 18). Please note that VOUT = VS - VDS. The current limitation threshold when VDS = 5 V is taken as reference. Current limitation to the value IL(LIM) is realized by increasing the resistance of the output channel, which leads to fast DMOS temperature rise. Figure 17 Typical Current Limitation variation according to VDS voltage 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 4 8 12 16 20 24 28 Current limitation variation factor Drain Source Voltage (V) Current limitation variation ("1" = IL(LIM) @ VDS = 5 V)

Data Sheet 38 Rev. 2.0, 2014-05-26 Figure 18 Typical Current Limitation behavior

7.2 Over Temperature Protection

Each channel incorporates both an absolute Tj(SC) and a dynamic ∆Tj(SW) temperature sensor. An increase of junction temperature Tj above one of the two thresholds ( Tj(SC) or Tj(SW)) switches OFF an overheated channel to prevent destruction. Any protective switch OFF deactiv ates the output until the temperature has reached an acceptable value. Each protective switch OFF event increments the error counter by one. The number of automatic reactivations is limited by nretry. If this number of retries is reached the channel turns OFF and latches OFF. The error information related to the given channel is available on the Standard Diagnosis and Errors Diagnosis. After switching OFF and latching OFF, the only way to switch ON again, is to clear all thermal counters and errors on all channels by setting HWCR.CTC bit to 1. If the channel is active (either OUT.OUTn = 1 or INn = 1) it is turned on immediately after the SPI command. For the condition n < nretry the counter of automatic reactivations is reset by every channel activation if HWCR.RCR bit is set to 1. In Figure 21 the different behavior of retry counters according to HWCR.RCR bit value can be seen. In Limp Home Mode, the thermal counters of the protecti on functions are only operative if VDD is provided in the specified range. Otherwise the counters are not active and all channels are in „unlimited restart“ mode. It is not possible to reset the counters using HWCR.CTC bit as long as the SPI is in Limp Home Mode, even if the VDD is provided. In case of the short circuit to ground, current sense ratio ( kILIS) is deactivated as soon as VDS > VDS(SB) (Switch bypass monitor threshold). Usually a short circuit to ground condition tends to set VDS = VS therefore in most of the cases no current sensing diagnostic is possible in short circuit. The error information related to the given channel are available also on Warnings Diagnosis (ERRn bits). Refer to Figure 19 and Figure 20 for details. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 4 8 12 16 20 24 28 Current limitation variation factor Drain Source Voltage (V) Current limitation variation ("1" = IL(LIM) @ VDS = 5 V)

Data Sheet 39 Rev. 2.0, 2014-05-26 Figure 19 Dynamic Temperature Sensor Operations - Short Circuit Protection_ DynT_SC.emf IN / OUT.OUTn * ERR reset by: HWCR.CTC = 1 t IIS IL(LIM) IL Tj ΔTjSW ΔTjS W ERR_COUNTER 0 1 ... nret ry ERR Internal counter 0 1 0 1 0 1 t t t t t t ΔTjS W ΔTjSW Tj( S C)

Data Sheet 40 Rev. 2.0, 2014-05-26 Figure 20 Dynamic and Absolute Temperature Sensor Operations - Overload Condition IL( LIM) IL t ΔTjSW Tj IIS Protection_DynT_OverLoad .emf IN / OUT.OUTn * ERR reset by: HWCR.CTC = 1 ERR_COUNTER 0 1 ... nret ry ERR Internal counter 0 1 0 1 ΔTjSW ΔTjSW t t t t t t Tj(SC)

Data Sheet 41 Rev. 2.0, 2014-05-26 Figure 21 Different counte r reset according to HWCR.RCR bit value

7.3 Reverse Polarity Protection

In reverse polarity condition, power dissipation is caus ed by the intrinsic body diode of each DMOS channel as well as each ESD diode of the logic pins. The reverse cu rrent through the channels has to be limited by the connected loads.The current through ground pin GND, sense pin IS, logic power supply pin VDD, SPI pins, input pins and Limp Home Input pin has to be limited as well (please refer to the maximum ratings listed on Chapter 4.1). Note: No protection mechanism like temperature protection or current limitation is active during reverse polarity.

7.4 Over Voltage Protection

In the case of supply voltages between VS(SC)max and VS(AZ) the output transistors are still operational and follow the input or the OUT register. Parameters are not warranted and lifetime is reduced compared to nominal voltage supply. In addition to the output clamp for inductive loads as described in Chapter 6.4.3, there is a clamp mechanism available for over voltage protection for the logic and all channels.

7.5 Loss of Ground

In case of complete loss of the device ground connection, but loads connected to ground, the BTS56033-LBA securely changes to or stays in OFF-state. Please refer to Chapter 10 where an application setup is described.

7.6 Loss of VS

In case of loss of VS connection in ON-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from VS to ground. For example, a suppressor diode is recommended between VS and GND. Internal counter IN / OUT.OUTn Protection_RCR. emf 0 1 IL IL( L IM ) t 2 3 4 5 ERR HWCR.RCR 0 (default ) 1 0 1 1 2 0 1 0 1 1 0 t t t t

Data Sheet 42 Rev. 2.0, 2014-05-26

7.7 Electrical Characteristics

Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C typical values: VS = 13.5 V, VDD = 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) 110 mΩ channels: RL = 18 Ω Table 8 Electrical Characteristics Protection Functions Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Over Load Protection Load current limitation 39 mΩ ch. IL(LIM) 25 32 44 A 1) VDS = 5 V LGCR.LEDn = 0 P_7.7.9 Load current limitation 39 mΩ ch. IL(LIM) –1 6 –A 1) VDS = 26 V LGCR.LEDn = 0 P_7.7.10 Load current limitation 39 mΩ ch. in LED mode IL(LIM) 6.5 9 16 A VDS = 5 V Tj = -40 °C LGCR.LEDn = 1 P_7.7.11 Load current limitation 39 mΩ ch. in LED mode IL(LIM) –4 . 5 –A 1) VDS = 26 V LGCR.LEDn = 1 P_7.7.12 Load current limitation 110 mΩ ch. IL(LIM) 9 1 21 6A VDS = 5 V Tj = -40 °C P_7.7.13 Over Temperature Protection Thermal shut down temperature Tj(SC) 150 170 200 °C 1) P_7.7.14 Thermal hysteresis of thermal shutdown Dynamic temperature increase limitation while switching Number of automatic retries at dynamic temperature sensor or over temperature shut down nretry –89 1) P_7.7.17 Reverse Polarity Drain source diode voltage during reverse polarity 39 mΩ ch. VDS(REV) 400 650 800 mV IL = IL(nom) = P_6.6.17 Tj = 150 °C P_7.7.20

Data Sheet 43 Rev. 2.0, 2014-05-26 Drain source diode voltage during reverse polarity 110 mΩ ch. VDS(REV) 400 650 800 mV IL = IL(nom) = P_6.6.18 Tj = 150 °C P_7.7.21 Over Voltage Overvoltage protection VS(AZ) 42 47 54 V IS = 4 mA P_7.7.22 1) Not subject to production test, specified by design. Table 8 Electrical Characteristics Protection Functions (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 44 Rev. 2.0, 2014-05-26

8 Diagnosis

For diagnosis purpose, the BTS56033-LBA provides a current sense signal at pin IS and a diagnosis word via SPI. There is a current sense multiplexer implemented that is controlled via SPI. The sense signal can also be disabled by SPI command. A switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. Please refer to Figure 22 for details. Figure 22 Block Diagram: Diagnosis For diagnosis feedback at different operation modes, please see Table 9. channel 1 load current sense IIS 0 current sense multiplexer T gate control load current limitation latch temperature sensor ERR1 OR latch DCR.MUX OUT4 OUT3 OUT2 OUT1 VS IS VS VDS (S B) SBM DCR. OUT5 OUT6 Diagnosis_ 033 .emf RIS

Data Sheet 45 Rev. 2.0, 2014-05-26

8.1 Diagnosis Word at SPI

Diagnostic information about the status of each channel is provided through SPI. In the Standard Diagnosis the ERR_MUX bit reports if there is a channel which had alr eady enough restarts to reach the maximum allowed number of retries nretry (P_7.7.17). If 2 or more channels are latched OFF due to that, ERR_MUX bits aren't enough to identify which channels are OFF. In such cases, it is possible to get an overview channel by channel using ERR_COUNTERn bits in Errors Diagnosis (see Chapter 9.6.2) It is possible to check if one or more channels had some retries during switching ON, although the limit of nretry was not reached. An overview channel by channel of thermal counter status is available using ERRn bits in Warnings Diagnosis (see Chapter 9.6.3). For both ERR_COUNTERn and ERRn the information on channel n is given at bit n-1 (e.g. bit 0 indicates status of channel 1). Table 9 Operation Modes 1) 1) L = “low” level, H = “high” level, Z = high impedance, potential depends on leakage currents and external circuit. X = undefined. Operation Mode Input Level OUT.OUTn Output Level VOUT Current Sense IIS Error Flag ERR_COUNTERn 2) The over temperature flag is set la tched and can be cleared by setting HWCR.CTC bit to 1. Warning Flag ERRn3) 3) The warning flags are latched until they are reset (see HWCR.RCR description). DCR.SBM bit Normal Operation (Channel OFF)L / 0 (OFF-state) GND Z 0 0 1 Short Circuit to GND GND Z 0 0 1 Thermal shut down Z Z 0 2) 02) X Short Circuit to VS VS Z0 0 0 Open Load Z Z 0 0 X Normal Operation (Channel ON)H / 1 (ON-state) ~VS IL / kILIS 00 0 Current Limitation < VS Z0 0 X Dynamic or Absolute Thermal Limitation → Channel switched OFF ZZ 0 1 X Dynamic or Absolute Thermal Limitation nretry reached → Channel latched OFF ZZ 1 2) 1X Short Circuit to GND ~GND Z 0 0 1 Short Circuit to VS VS < IL / kILIS 00 0 Open Load VS Z0 0 0

Data Sheet 46 Rev. 2.0, 2014-05-26

8.2 Load Current Sense Diagnosis

There is a current sense signal available at pin IS which provides a current proportional to the load current of one selected channel. The selection is done by a multiplexer which is configured via SPI.

8.2.1 Current Sense Signal

The current sense signal (ratio kILIS = IL / IS) is provided during ON-state as long as no failure mode occurs. For dedicated channels the ratio kILIS can be adjusted to the load type (LED or bulb) via SPI register LGCR. The accuracy of the ratio kILIS depends on the load current and temperature. Usually a resistor RIS is connected to the The current sense signal of a channel is not active when the channel is OFF or when the protection functions (current limitation, over temperature or dynamic temperature sensor s) are active. If the maximum number of automatic reactivations nretry is reached (n = nretry), the current sense signal of the affected channel is deactivated until the reset of the counters by setting HWCR.CTC bit to 1. Details about timings between the current sense signal IIS and the output voltage VOUT and the load current IL can be found in Figure 23. Figure 23 Current Sense Signal Timings

8.2.2 Current Sense Multiplexer

There is a current sense multiplexer implemented in th e BTS56033-LBA that routes the sense current of the selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current can also be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, please refer to Figure 24. Diagnosis_ SenseTiming.emf VOUT IIS t t t IL t ON tON tsI S( ON) tsI S( LC) OFF tOFF tdIS (OFF) OFF IN / OUT.OUTn

Data Sheet 47 Rev. 2.0, 2014-05-26 Figure 24 Current Sense Multiplexer Timings

8.2.3 Open Load at ON Diagnosis

If a channel is ON in Open Load condition, a small curr ent can still flow, for exampl e because of humidity. The parameter IL(OL) gives the threshold of recognition for such leakage current. If the voltage measured at the sense resistor RSENSE corresponds to a current IIS(OL) (4 µA), then the curr ent flowing at the output in ON state is within the limits given by IL(OL). Figure 25 shows the sense current behavior once a channel in Open Load at ON condition is selected with the sense current multiplexer. The red curve show a typical product curve. The blue line shows the ideal kILIS ratio. Figure 25 Current Sense Ratio in Open Load at ON condition

8.3 Switch Bypass Monitor Diagnosis

To detect short circuit to VS, there is a switch bypass monitor implemen ted. In case of short circuit between the output pin OUT and VS in ON-state, the current flows th rough the power transistor as well as through the short circuit (bypass) with undefined share between the two. As a result, the current sense signal shows lower values than expected by the load current. In OFF-state, the output voltage remains close to VS potential which leads to a small VDS. The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX). The result of the comparison can be read in SPI register DCR.SBM. Diagnosis_MuxTiming.emf CS IIS t 000DCR.MUX 001110 110 tsI S(E N) ts IS( MU X) tdIS( MUX) t IIS IL IIS(OL ) IL(OL ) IIS(en)

Data Sheet 48 Rev. 2.0, 2014-05-26

8.4 Gate Back Regulation

To increase the current sense accuracy, the Gate Back Regulation (GBR) function is implemented. This function monitors the VDS voltage at the output and if the value is equal to or lower than VDS(NL) the output DMOS gate is partially discharged. This increases output DMOS resistance so that VDS = VDS(NL) even for very small output currents. The VDS increase allows the current sensing circuitry to work with better accuracy, providing tighter kILIS values for output currents in the low range. This function is active by default ( LGCR.GBRn bits set to “1” after a reset). According to output current, GBR function can be left active or disabl ed. Even if left active, Gate Back Regulation circuitry may not be working because the measured VDS is bigger than VDS(NL) (depending on output current, junction temperature, output DMOS resistance). Due to production and temperature vari ations, GBR circuitry can affect kI LIS performance in negative way for some output current values. For this reason, Table 10 and Table 11 indicate for which output currents it is necessary to deactivate GBR (setting the corresponding LGCR.GBRn bit to “0”) to reach the desired current accuracy. If no indication is given, then the GBR function is assumed to be enabled (LGCR.GBRn bit set to “1”). It is recommended to keep GBR circuitry enabled for Open Load at ON diagnosis. The circuitry that controls GBR function can be deactivated with the following SPI command sequence:

• SWCR.SWR = 1 (SPI command: 11001100
• LGCR.GBRn = 0 (SPI command: 1101aaaaB where “aaaa”B is the new value for LGCR.GBRn bits)
• (optional but recommended: SWCR.SWR = 0 (SPI command: 11000100B) GBR cannot be deactivated for 110mΩ channels. Refer to Chapter 9.7 for more details.

Data Sheet 49 Rev. 2.0, 2014-05-26

8.5 Electrical Characteristics

Unless otherwise specified: VS = 7 V to 18 V, VDD = 3.8 V to 5.5 V, Tj = -40 °C to +150 °C Typical values: VS = 13.5 V, VDD= 4.3 V, Tj = 25 °C Typical resistive loads connected to the outputs (unless otherwise specified): 39 mΩ channels: RL = 6.8 Ω (33 Ω when LGCR.LEDn = “1”) 110 mΩ channels: RL = 18 Ω Measurement setup used for kILIS (unless otherwise specified): Channel 2, 3, 4: when IL ≤ 1.3 A the channels are ON at the same time with equal IL, channels 1, 5, 6 have IL = 0 Channel 1, 5, 6: when IL ≤ 1.3 A the channels are ON at the same time with equal IL, channels 2, 3, 4 have IL = 0 When IL ≥ 2.0 A only the measured channel is ON, all other channels have IL = 0 Table 10 Electrical Characteristics Diagnosis kILIS 39 mΩ ch. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition 39 mΩ ch. Current sense ratio IL03 = 300 mA kILIS03 -36 % 2000 +36 % – P_8.5.49 Current sense ratio IL05 = 600 mA kILIS05 -29 % 2000 +29 % – P_8.5.51 Current sense ratio IL07 = 1.3 A kILIS07 -15 % 2000 +15 % – P_8.5.53 Current sense ratio IL09 = 2.6 A kILIS09 -12 % 2000 +12 % – P_8.5.55 Current sense ratio IL10 = 4 A kILIS10 -11 % 2000 +11 % – P_8.5.56 Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition 39 mΩ ch. in LED mode Current sense ratio IL00 = 20 mA kILIS00 -52 % 620 +52 % – P_8.5.57 Current sense ratio IL02 = 150 mA kILIS02 -30 % 570 +30 % – P_8.5.59 Current sense ratio IL03 = 300 mA kILIS03 -15 % 570 +15 % – P_8.5.60 Current sense ratio IL05 = 600 mA kILIS05 -11 % 570 +11 % – P_8.5.62 Current sense ratio IL06 = 1 A kILIS06 -10 % 570 +10 % – P_8.5.63

Data Sheet 50 Rev. 2.0, 2014-05-26 Table 11 Electrical Characteristics Diagnosis kILIS 110 mΩ ch. Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition 110 mΩ ch. Current sense ratio IL00 = 20 mA kILIS00 -50 % 900 +50 % – P_8.5.66 Current sense ratio IL02 = 150 mA kILIS02 -31 % 900 +31 % – P_8.5.68 Current sense ratio IL03 = 300 mA kILIS03 -22 % 900 +22 % – P_8.5.69 Current sense ratio IL07 = 1.3 A kILIS07 -11 % 900 +11 % P_8.5.73 Current sense ratio IL08 = 2 A kILIS08 -11 % 900 +11 % – P_8.5.74 Table 12 Electrical Characteristics Diagnosis Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Sense pin maximum voltage VIS(AZ) 42 47 54 V IIS = 5 mA P_8.5.75 Current Sense Drift Over Current and Temperature per Device Current sense drift over current and temperature per device 39 mΩ ch. ΔkILIS(T) - 8 –8% 1) kILIS09 versus kILIS07 LGCR.LEDn = 0 P_8.5.80 Current sense drift over current and temperature per device 39 mΩ ch. in LED mode ΔkILIS(T) -9.5 – 9.5 % 1) kILIS05 versus kILIS03 LGCR.LEDn = 1 P_8.5.81 Current sense drift over current and temperature per device 110 mΩ ch. ΔkILIS(T) - 8 –8% 1) kILIS07 versus kILIS03 P_8.5.82

Data Sheet 51 Rev. 2.0, 2014-05-26 Current Sense Drift of Unaffected Channel during Inverse Current of other Channels One channel with IL(IC) = - ILn, all other channels with ILn DCR.MUX ≠ <111, 110> and set to sense any of the channels not in Inverse current condition Current sense drift of unaffected channels during inverse current of one channel ΔkILIS(IC) -20 – 20 % 1) IL1 = 1.3 A IL2 = 2.6 A IL3 = 2.6 A IL4 = 2.6 A IL5 = 1.3 A IL6 = 1.3 A P_8.5.85 Sense Pin - Currents Maximum steady state current sense output current 39 mΩ ch. IIS(MAX) 3.8 – 15 mA VIS = 0 V VS ≥ 8V P_8.5.88 Maximum steady state current sense output current 110 mΩ ch. IIS(MAX) 3.8 – 15 mA VIS = 0 V VS ≥ 8V P_8.5.89 Current sense leakage / offset current IIS(en) ––1 μA 1) Tj ≤ 85 °C IL = 0 mA DCR.MUX ≠ <111,110>B P_8.5.118 Current sense leakage / offset current IIS(en) ––3 . 2 μA Tj = 150 °C IL = 0 mA DCR.MUX ≠ <111,110>B P_8.5.90 Open load detection threshold in ON state 39 mΩ ch. IL(OL) ––2 1 . 5 m A IIS(OL) = 4 μA LGCR.LEDn = 0 P_8.5.95 Open load detection threshold in ON state 39 mΩ ch. in LED mode IL(OL) ––7 . 5 m A IIS(OL) = 4 μA LGCR.LEDn = 1 P_8.5.96 Open load detection threshold in ON state 110 mΩ ch. IL(OL) ––9m A IIS(OL) = 4 μA P_8.5.97 Current sense leakage, while diagnosis disabled IIS(dis) –0 . 0 1 1 μA IL2 = 2.6 A DCR.MUX = 110B P_8.5.98 Sense Pin - Timings Current sense settling time after channel activation 39 mΩ ch. tsIS(ON) ––2 5 0 μs VS = 13.5 V RIS = 2.7 kΩ LGCR.LEDn = 0 P_8.5.103 Table 12 Electrical Characteristics Diagnosis (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 52 Rev. 2.0, 2014-05-26 Current sense settling time after channel activation 39 mΩ ch. in LED mode tsIS(ON) ––1 0 0 μs VS = 13.5 V RIS = 2.7 kΩ LGCR.LEDn = 1 P_8.5.104 Current sense settling time after channel activation 110 mΩ ch. tsIS(ON) ––2 5 0 μs VS = 13.5 V RIS = 2.7 kΩ P_8.5.105 Current sense desettling time after channel deactivation tdIS(OFF) ––2 5 μs VS = 13.5 V RIS = 2.7 kΩ P_8.5.106 Current sense settling time after change of load current 39 mΩ ch. tsIS(LC) ––2 5 μs 1) IL = 2.6 A to 1.3 A VS = 13.5 V RIS = 2.7 kΩ LGCR.LEDn = 0 P_8.5.111 Current sense settling time after change of load current 39 mΩ ch. in LED mode tsIS(LC) ––2 5 μs 1) IL = 1.0 A to 0.6 A VS = 13.5 V RIS = 2.7 kΩ LGCR.LEDn = 1 P_8.5.112 Current sense settling time after change of load current 110 mΩ ch. tsIS(LC) --2 5 μs 1) IL = 2.6 A to 1.3 A VS = 13.5 V RIS = 2.7 kΩ P_8.5.113 Current sense settling time after current sense activation tsIS(EN) ––2 5 μs RIS = 2.7 kΩ IL2 = 2.6 A DCR.MUX: 110B → 001B P_8.5.114 Current sense settling time after multiplexer channel change tsIS(MUX) ––2 5 μs RIS = 2.7 kΩ IL2 = 2.6 A IL3 = 4 A DCR.MUX: 001B → 010B P_8.5.115 Current sense deactivation time tdIS(MUX) ––2 5 μs 1) RIS = 2.7 kΩ DCR.MUX: 010B → 110B P_8.5.116 Switch Bypass Monitor Switch bypass monitor threshold 1) Not subject to production test, specified by design. Table 12 Electrical Characteristics Diagnosis (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Serial Peripheral Interface (SPI) Data Sheet 53 Rev. 2.0, 2014-05-26

9 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is transferred by the lines SI a nd SO at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is taken only when a multiple of 8 bit has been transferred. The interface provides daisy chain capability with 8 bit SPI devices. Figure 26 Serial Peripheral Interface

9.1 SPI Signal Description

The system micro controller selects the BTS56033-LBA by means of the CS pin. Whenever the pin is in “low” state, data transfer can take place. When CS is in “high” state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CS “high” to “low” Transition

• The requested information is transferred into the shift register.
• SO changes from high impedance state to “high” or “low” state depending on the signal level at pin SI. Figure 27 Combinatorial Logic for TER Flag 6 5 4 3 2 1 LSB6 5 4 3 2 1CS MSBSO SI CS SCLK time SPI _ 8bit.emf LSBMSB SPI _TER.emf SI SPI OR TER 1 SO CS SCLK S SO SSI

Serial Peripheral Interface (SPI) Data Sheet 54 Rev. 2.0, 2014-05-26 CS “low” to “high” Transition

• Command decoding is only d one, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the command is ignored.
• Data from shift register is transferred into the addressed register. SCLK - Serial Clock This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling edge of SCLK while the serial output (S O) shifts diagnostic information out on the rising edge of the serial clock. It is essential that the SCLK pin is in “low” state when ever chip select CS makes any transition, otherwise the command may be not accepted. SI - Serial Input Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge of SCLK. The input data consists of two parts, co ntrol bits followed by data bits. Please refer to Chapter 9.5 for further information. SO Serial Output Data is shifted out serially at this pi n, the most significant bit first. SO is in high impedance state until the CS pin goes to “low” state. New data will appear at the SO pin following the rising edge of SCLK. Please refer to Chapter 9.5 for further information.

9.2 Daisy Chain Capability

The SPI of BTS56033-LBA provides daisy chain capability. In this configuration several devices are activated by the same CS signal MCS. The SI line of one device is connected with the SO lin e of another device (see Figure 28), in order to build a chain. The end of the chain is connected to the output and input of the master device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line of each device in the chain. Figure 28 Daisy Chain Configuration In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK. The bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device is finished. In single chip configuration, the CS line must turn “high” to make the device acknowledge the transferred data. In daisy chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. When using three devices in daisy chain, three times 8 bits have to be shifted throug h the devices. After that, th e MCS line must turn “high” (see Figure 29). SI device 1 SPI SCLK SO CS SI device 2 SPI SCLK SO CS SI device 3 SPI SCLK SO CS MO MI MCS MCLK SPI_DaisyChain .emf

Serial Peripheral Interface (SPI) Data Sheet 55 Rev. 2.0, 2014-05-26 Figure 29 Data Transfer in Daisy Chain Configuration

9.3 Timing Diagrams

Figure 30 Timing Diagram SPI Access MI MO MCS MCLK SI device 1 SI device 2 SI device 3 SO device 1 SO device 2 SO device 3 time SPI _DaisyChain_2.emf CS SCLK SI tCS( lead) tCS (t d)tCS( lag) tSC LK (H ) tSC LK (L) tSC LK(P ) tSI ( s u) tSI (h) SO tSO(v )tSO(en) tSO (dis ) SPI _Timings.emf VCS ( H) VCS ( L) VSC LK( H ) VSC LK( L) VSI( H ) VSI( L) VSO( H ) VSO( L)

Serial Peripheral Interface (SPI) Data Sheet 56 Rev. 2.0, 2014-05-26

9.4 Electrical Characteristics

Unless otherwise specified: VS = 7 V to 18 V, Tj = -40 °C to +150 °C, VDD = 3 . 8V t o 5 . 5V Typical values: VS = 13.5 V, Tj = 25 °C, VDD = 4.3 V Table 13 Electrical Characteristics Serial Peripheral Interface (SPI) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Input Characteristics (CS, SCLK, SI) - L Level of pin Input Characteristics (CS, SCLK, SI) - H Level of pin CS VCS(H) 2.6 – VDD V VDD = 4.3 V P_9.4.4 SCLK VSCLK(H) 2.6 – VDD V VDD = 4.3 V P_9.4.5 SI VSI(H) 2.6 – VDD V VDD = 4.3 V P_9.4.6 L-input pull-up current at CS pin -ICS(L) 73 0 7 5 μA VDD = 4.3 V VCS = 1.0 V P_9.4.7 H-input pull-up current at CS pin -ICS(H) 32 7 7 5 μA VDD = 4.3 V VCS = 2.6 V P_9.4.8 L-Input Pull-Down Current at Pin SCLK ISCLK(L) 32 7 7 5 μA VSCLK = 1.0 V VDD = 4.3 V P_9.4.9 SI ISI(L) 32 7 7 5 μA VSI = 1.0 V VDD = 4.3 V P_9.4.10 H-Input Pull-Down Current at Pin SCLK ISCLK(H) 73 0 7 5 μA VSCLK = 2.6 V VDD = 4.3 V P_9.4.11 SI ISI(H) 73 0 7 5 μA VSI = 2.6 V VDD = 4.3 V P_9.4.12 Output Characteristics (SO) L level output voltage VSO(L) 0–0 . 5 V ISO = -0.5 mA P_9.4.13 H level output voltage VSO(H) VDD - 0.5 V – VDD V ISO = 0.5 mA VDD = 4.3 V P_9.4.14 Output tristate leakage current ISO(OFF) -1 – 1 μA VCS =VDD VSO = 0 V VSO = VDD P_9.4.15 Timings Enable lead time (falling CS to rising SCLK) tCS(lead) 2 0 0 ––n s – 1) P_9.4.16 Enable lag time (falling SCLK to rising CS) tCS(lag) 2 0 0 ––n s – 1) P_9.4.17 Transfer delay time (rising CS to falling CS) tCS(td) 1–– μs– 1) P_9.4.18

Serial Peripheral Interface (SPI) Data Sheet 57 Rev. 2.0, 2014-05-26 Output enable time (falling CS to SO valid) tSO(en) ––1 μs 1) CL = 50 pF P_9.4.19 Output disable time (rising CS to SO tristate) tSO(dis) ––1 μs 1) CL = 50 pF P_9.4.20 Serial clock frequency fSCLK 0–3M H z – 1) P_9.4.22 Serial clock period tSCLK(P) 3 3 3 ––n s – 1) P_9.4.24 Serial clock “high” time tSCLK(H) 1 5 0 ––n s – 1) P_9.4.26 Serial clock “low” time tSCLK(L) 1 5 0 ––n s – 1) P_9.4.28 Data setup time (required time SI to falling SCLK) tSI(su) 6 5 ––n s – 1) P_9.4.30 Data hold time (falling SCLK to SI) tSI(h) 6 5 ––n s – 1) P_9.4.32 Output data valid time with capacitive load tSO(v) ––1 6 6 n s 1) CL = 50 pF P_9.4.34 1) Not subject to production test, specified by design Table 13 Electrical Characteristics Serial Peripheral Interface (SPI) (cont’d) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Serial Peripheral Interface (SPI) Data Sheet 58 Rev. 2.0, 2014-05-26

9.5 SPI Protocol

The relationship between SI and SO content during SPI communication is shown in Figure 31. SI line represents the frame sent from the µC and SO line is the answer provided by BTS56033-LBA. The “(previous response)” means that the frame sent back depends on the command frame sent from the µC before. Figure 31 Relationship between SI and SO during SPI communication The SPI protocol provides the answer to a command frame only with the next transmission triggered by the µC. Although the biggest majority of commands and frames implemented in BTS56033-LBA can be decoded without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous transmission to decode BTS56033-LBA response frame completely. More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows: Figure 32 Register content sent back to µC There are 3 special situations where the frame sent back to the µC doesn't depend on the previous received frame:

• in case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8), shown in Figure 33
• when BTS56033-LBA logic supply comes out of Power-On reset condition, as shown in Figure 34
• when VS < VSMON and DCR.MUX ≠ 111B, as shown in Figure 35 Figure 33 BTS56033-LBA response after an error in transmission SI SO frame A frame B (previous response) response to frame A frame C response to frame B SPI_SI2SO.emf SI SO write register A read register A Standard diagnostic register A content (new command ) SPI_RWseq.emf (previous response) frame A (error in transmission ) SPI_SO_TER.emf SI SO (new command) Standard diagnostic + TER(previous response )

Serial Peripheral Interface (SPI) Data Sheet 60 Rev. 2.0, 2014-05-26 Table 14 SPI Command Summary Requested Operation Frame sent to SPOC+ (SI pin) Frame received from SPOC+ (SO pin) with the next command Write OUT register 10aaaaaaB where: “aaaaaaB” = new OUT register content 0aaaaaaaB (Standard Diagnosis) Read OUT register 00xx0000B (“xxB” = don't care) 10aaaaaaB (“aaaaaaB” = OUT register content) Write Configuration register 11aabbbbB where: “aaB” = register address “bbbbB” = new register content 0aaaaaaaB (Standard Diagnosis) Read Configuration register 01aa0000B where: “aaB” = register address 11aabbbbB where: “aaB” = register address “bbbbB” = register content Read Standard Diagnosis 0xxx0001B (“xxxB” = don't care) 0aaaaaaaB (Standard Diagnosis) Read Errors Diagnosis 0xxx0011B (“xxxB” = don't care) 00aaaaaaB (Error Diagnosis) Read Warnings Diagnosis 0xxx0101B (“xxxB” = don't care) 00aaaaaaB (Warning Diagnosis)

Serial Peripheral Interface (SPI) Data Sheet 61 Rev. 2.0, 2014-05-26

9.6 SPI Diagnosis Registers

9.6.1 Standard Diagnosis

S O 76543210 D e f a u l t

0 TER LHI STB VSMON ERR_MUX 50H

Field Bits Type Description TER 6r Transmission Error 0B Previous transmission was successful (modulo 8 clocks received) 1B (default) Previous transmission failed or first transmission after reset LHI 5r Limp Home monitor 0B (default) Normal mode operation 1B Limp Home Mode STB 4r Standby mode monitor 0B Normal mode operation 1B (default) Stand-by mode VSMON 3r VS monitor 0B (default) VS always > VSMON since last Standard Diagnosis readout 1B VS < VSMON at least once ERR_MUX 2:0 r Diagnosis of Channel n in error 000B (default) No channel latched off 001B Channel one latched off 010B Channel two latched off 011B Channel three latched off 100B Channel four latched off 101B Channel five latched off 110B Channel six latched off 111B More than one channel latched off

Serial Peripheral Interface (SPI) Data Sheet 62 Rev. 2.0, 2014-05-26

9.6.2 Errors Diagnosis

9.6.3 Warnings Diagnosis

S O 76543210 D e f a u l t

00 ERR_COUNTERn 00H

Field Bits Type Description ERR_COUNTERn n = 6 to 1 5:0 r Diagnosis of Channel n 0B (default) No failure 1B Over temperature counter reached to nretry S O 76543210 D e f a u l t

00 ERRn 00H

Field Bits Type Description ERRn n = 6 to 1 5:0 r Warning Diagnosis of Channel n 0B (default) No failure 1B Over temperature counter > 0

Serial Peripheral Interface (SPI) Data Sheet 63 Rev. 2.0, 2014-05-26

9.7 SPI Configuration Registers

The following table provides an overview on the registers available and the available addressing space.

9.7.1 Output Config uration Register

9.7.2 Input Status Register

9.7.3 Swap Configuration Register

Table 15 Register Overview Register name Register Bank Address SWCR.SWR bit Content OUT 0 (na) 0 Output configuration OUT 0 (na) 1 Input status SWCR 1 00 (na) Swap configuration LGCR 1 01 0 LED mode configuration LGCR 1 01 1 Gate Back Regulation configuration HWCR 1 10 (na) Hardware configuration DCR 1 11 (na) Diagnostic configuration SWCR.SWR = 0 B i t 7 6 543210 Name W = 1 R = 0 R B 543210 D e f a u l t OUT W/R 0 OUT.OUTn 80H SWCR.SWR = 1 B i t 7 6 543210 Name W = 1 R = 0 R B 543210 D e f a u l t OUT R0 LHI 1 OUT.INSTn 90H B i t 7 6 5 4 3210 D e f a u l t Name W = 1 R = 0 RB ADDR 3210 SWCR W/R 1 00 SWCR.SWR 100C 4 H

Serial Peripheral Interface (SPI) Data Sheet 64 Rev. 2.0, 2014-05-26

9.7.4 LED Mode Conf iguration Register

9.7.5 Gate Back Re gulation Register

9.7.6 Hardware Configuration Register

SWCR.SWR = 0 Name W = 1 R = 0 RB ADDR 3 2 1 0 Default LGCR W/R 1 01 LGCR.LEDn 0D 0 H SWCR.SWR = 1 Name W = 1 R = 0 RB ADDR 3 2 1 0 Default LGCR W/R 1 01 LGCR.GBRn 0D E H Name W = 1 R = 0 RB ADDR 3 2 1 0 Default HWCR R1 1 0 HWCR.RCR HWCR.COL HWCR.STB 0E 2 H W1 1 0 HWCR.RCR HWCR.COL HWCR.RST HWCR.CTC -

Serial Peripheral Interface (SPI) Data Sheet 65 Rev. 2.0, 2014-05-26

9.7.7 Diagnosis Control Register

9.7.8 Configuration Re gister Bit Overview

Name W = 1 R = 0 RB ADDR 3 2 1 0 Default DCR R1 1 1 DCR.SBM DCR.MUX F7H W1 1 1 0 DCR.MUX - Field Bits Type Description RB 6r w Register Bank 0B (default) Read / write to OUT register 1B Read / write to other registers OUT.OUTn n = 6 to 1 5:0 rw Output Control Register of Channel n 0B (default) channel is OFF 1B Channel is ON OUT.INSTn n = 4 to 1 3:0 r Input Status Monitor Channel n 0B (default) Input signal is “low” 1B Input signal is “high” LGCR.LEDn n = 4 to 2 3:1 rw Set LED Mode for Channel n 0B (default) Channel n is in bulb mode 1B Channel n is in LED mode LGCR.GBRn n = 4 to 2 3:1 rw Gate Back Regulation for Channel n 0B Gate back regulation for Channel n is forced OFF 1B (default) Gate back regulation for Channel n is active HWCR.CTC 0w Clear Thermal Counter 0B (default) Thermal latches are untouched 1B Command: Clear all thermal latches HWCR.RST 1w Reset Command 0B (default) Normal operation 1B Execute reset command HWCR.STB 1r Standby Mode 0B Device is awake 1B (default) Device is in Standby mode HWCR.COL 2r w Input Combinatorial Logic Configuration 0B (default) Input signal OR-combined with according OUT register bit1) 1B Input signal AND-combined with according OUT register bit HWCR.RCR 3r w Retry Counter Reset 0B (default) Retry Counter is reset only for HWCR.CTC=1 (and VDD reset) 1B Retry Counter is reset for every IN-pin or OUT.OUTn “high” to “low” transition for nretry < nretry,max and also for HWCR.CTC=1 (and VDD reset)

Serial Peripheral Interface (SPI) Data Sheet 66 Rev. 2.0, 2014-05-26 SWCR.SWR 1r w Switch Register 0B (default) OUT.OUTn and LGCR.LEDn can be written and read 1B OUT.INSTn can be read and LGCR.GBRn can be written and read DCR.SBM 3r Switch Bypass Monitor2) 0B VDS < VDS(SB) 1B VDS > VDS(SB) DCR.MUX 2:0 rw Set Current Sense Multiplexer Configuration in OFF-state 000B IS pin is high impedance 001B IS pin is high impedance 010B IS pin is high impedance 011B IS pin is high impedance 100B IS pin is high impedance 101B IS pin is high impedance 110B IS pin is high impedance 111B Stand-by mode (IS pin is high impedance) Set Multiplexer Configuration in ON-state 000B Current sense of channel 1 is routed to IS pin 001B Current sense of channel 2 is routed to IS pin 010B Current sense of channel 3 is routed to IS pin 011B Current sense of channel 4 is routed to IS pin 100B Current sense of channel 5 is routed to IS pin 101B Current sense of channel 6 is routed to IS pin 110B IS pin is high impedance 111B Stand-by mode (IS pin is high impedance)) 1) In Limp Home Mode (LHI pin set to “high”) the combinatorial logic is switched to OR-mode. 2) The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX). Field Bits Type Description

Data Sheet 67 Rev. 2.0, 2014-05-26 The following figure describes a typical operating circui t. It shall not be considered as a warranty of a certain functionality, condition or quality of the device. The Table 16 shows suggested component values and purposes. Figure 36 Application Circuit Example CVDD µC e.g. XC2267 VSS VCC Vbat AD RVDD GPIO WD- OUT CVS1 CADC Z1Z2CVS2 RIN RIN RIN RIN SPI SPI VS IS SO SCLK SI CS GND LHI WD-OUTRLHI VDD GND VDD IN2 IN3 IN1 IN4 OUT4 OUT3 OUT1 OUT5 OUT6 OUT2 RCS RSCL K RSO RSI 10 W 27 W 27 W 27 W 10 W 10 W Application _033 .emf CGND DGND RREC RGN D COUT RSENSE RADC

Data Sheet 68 Rev. 2.0, 2014-05-26 Table 16 Suggested Component Values Reference Value Purpose RVDD 500 Ω Device logic protection (Size 1206 recommended) RIN 8 k Ω Protection of the µC during ov ervoltage, reverse polarity and loss of ground R1 4.7 k Ω Protection resistor for overvoltage, reverse polarity and loss of ground. Value to be tuned with µC specification RIS 2.7 k Ω Sense resistor RADC 1 k Ω µC-ADC voltage spikes filtering RCS 3.9 k Ω Protection of the µC during ov ervoltage and reverse polarity RSCLK 3.9 kΩ Protection of the µC during ov ervoltage and reverse polarity RSO 3.9 k Ω Protection of the µC during ov ervoltage and reverse polarity RSI 3.9 k Ω Protection of the µC during ov ervoltage and reverse polarity RLHI 8 k Ω Protection of the µC during ov ervoltage and reverse polarity CADC 1 nF µC-ADC voltage spikes filtering CVDD 100 nF Logic supply vo ltage spikes filtering CVS1 68 nF Battery voltage spikes filtering CVS2 100 nF Battery voltage spikes filtering COUT 10 nF For improved electrom agnetic compatibility (EMC) CGND 8.2 nF Ground voltage spikes filtering (optional for improved robustness against battery voltage transients) RGND 100 Ω Ground voltage spikes filtering (optional for improved robustness against battery voltage transients) RREC 1 k Ω Ground voltage recycling path (optional for providing a recycle path in case of loss of Battery) Z1 7 V Protection of µC duri ng overvoltage. Zener diode Z2 P6SMB30 Protection of device du ring overvoltage. Zener diode DGND BAS70 Protection of device during reverse polarity. Schottky diode

Data Sheet 69 Rev. 2.0, 2014-05-26 Figure 37 TSON-24-3 Package drawing

Data Sheet 70 Rev. 2.0, 2014-05-26 Figure 38 TSON-24 Package pads and stencil Green Product (RoHS Compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Note: You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.

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© 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Legal Disclaimer for short-circuit capability Infineon disclaims any warranties and liabilities, whether expressed nor implied, for any short-circuit failures below the threshold limit. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.