BTS5180-2EKA

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Rev. 2.1, 2011-09-01 Automotive Power BTS5180-2EKA Smart High-Side Power Switch Dual Channel, 180mΩ PROFET™+ 12V

Data Sheet 2 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Table of Contents Table of Contents

Data Sheet 3 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Table of Contents

BTS5180-2EKA PG-DSO-14-40 EP BTS5180-2EKA Data Sheet 4 Rev. 2.1, 2011-09-01 PROFET™+ 12V Smart High-Side Power Switch BTS5180-2EKA 1O v e r v i e w Application

• Suitable for resistive, indu ctive and capacitive loads
• Replaces electromechanical relays, fuses and discrete circuits
• Most suitable for loads with high inrush current, such as lamps Basic Features
• Two channel device
• Very low stand-by current
• 3.3 V and 5 V compatible logic inputs
• Electrostatic discha rge protection (ESD)
• Optimized electromagnetic compatibility
• Logic ground independent from load ground
• Very low power DMOS leakage current in OFF state
• Green product (RoHS compliant)
• AEC qualified

Description

The BTS5180-2EKA is a 180 m Ω dual channel Smart High-Side Power Switch, embedded in a PG-DSO-14-40 EP, Exposed Pad package, providing protective functions and diagnosis. The power transistor is built by an N-channel vertical power MOSFET with charge pump. The device is integrated in Smart6 technology. It is specially designed to drive lamps up to 1 * 5W, as well as LEDs in the harsh automotive environment. Table 1 Product Summary Parameter Symbol Value Operating voltage range VS(OP) 5 V ... 28 V Maximum supply voltage VS(LD) 41 V Maximum ON state resistance at TJ = 150 °C per channel RDS(ON) 360 mΩ Nominal load current (one channel active) IL(NOM)1 2 A Nominal load current (both channels active) IL(NOM)2 1.5 A Typical current sense ratio kILIS 550 Minimum current limitation IL5(SC) 8 A Maximum standby current with load at TJ = 25 °C IS(OFF) 500 nA

Data Sheet 5 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Overview Diagnostic Functions

• Proportional load current sense for both channels multiplexed
• Open load in ON and OFF
• Short circuit to battery and ground
• Overtemperature
• Stable diagnostic signal during short circuit
• Enhanced kILIS dependency with temperature and load current Protection Functions
• Stable behavior during undervoltage
• Reverse polarity protection with external components
• Secure load turn-off during logic gr ound disconnect with external components
• Overtemperature protection with restart
• Overvoltage protection with external components
• Voltage dependent current limitation
• Enhanced short circuit operation

Data Sheet 6 Rev. 2.1, 2011-09-01 PROFET™+ 12V

2 Block Diagram

Figure 1 Block Diagram for the BTS5180-2EKA Block diagram DxS.vsd Channel 0 VS OUT 0 IN0 T driver logic gate control charge pump load current sense and open load detection over temperature clamp for inductive load over current switch limit forward voltage drop detection voltage sensor GND ESD protection IS DEN Channel 1 DSEL IN1 Control and protection circuit equivalent to channel 0 T VS OUT 1 internal power supply

Data Sheet 7 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Pin Configuration

3 Pin Configuration

3.1 Pin Assignment

Figure 2 Pin Configuration

3.2 Pin Definitions and Functions

1G N D GrouND; Ground connection 2I N 0 INput channel 0; Input signal for channel 0 activation 3D E N Diagnostic ENable; Digital signal to enable/disable the diagnosis of the device 4I S Sense; Sense current of the selected channel

5 DSEL Diagnostic SELection; Digital signal to select the channel to be diagnosed

6I N 1 INput channel 1; Input signal for channel 1 activation 7, 11 NC Not Connected; No internal connection to the chip 8, 9, 10 OUT1 OUTput 1; Protected high side power output channel 11) 1) All output pins of a given channel must be connected together on the PCB. All pins of an output are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow. 12, 13, 14 OUT0 OUTput 0; Protected high side power output channel 01) Cooling Tab VS Voltage Supply; Battery voltage Pinout dual SO14.vsd OUT0 OUT0 OUT0 NC OUT1 OUT1 OUT1 GND IN0 DEN IS DSEL IN1 NC

Data Sheet 8 Rev. 2.1, 2011-09-01 PROFET™+ 12V

3.3 Voltage and Current Definition

Figure 3 shows all terms used in this data sheet, with associated convention for positive values. Figure 3 Voltage and Current Definition VS IN0 IN1 DEN DSEL IS GND OUT0 OUT1 IIN0 IIN1 IDEN IDSEL IIS VS VIN0 VIN1 VDEN VDSEL VIS I S IGND VDS0 VDS1VOUT0 VOUT1 IOUT1 IOUT0 voltage and current convention.vsd

Data Sheet 9 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA General Product Characteristics

4 General Product Characteristics

4.1 Absolute Maximum Ratings

Table 2 Absolute Maximum Ratings 1) TJ = -40°C to +150°C; (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Supply Voltages Supply voltage VS -0.3 – 28 V – P_4.1.1 Reverse polarity voltage - VS(REV) 0–1 6 V t < 2 min TA = 25 °C RL ≥ 12 Ω RGND = 150 Ω P_4.1.2 Supply voltage for short circuit protection VBAT(SC) 0–2 4 V 2) RECU = 20 mΩ RCable= 16 mΩ/m LCable= 1 μH/m, l = 0 or 5 m See Chapter 6 and Figure 53 P_4.1.3 Supply voltage for Load dump protection VS(LD) – – 41 V 3) RI = 2 Ω RL = 12 Ω P_4.1.12 Short Circuit Capability Permanent short circuit IN pin toggles nRSC1 – – 100 k cycles tON = 300ms P_4.1.4 Input Pins Voltage at INPUT pins VIN -0.3 t < 2 min P_4.1.13 Current through INPUT pins IIN -2 – 2 mA – P_4.1.14 Voltage at DEN pin VDEN -0.3 t < 2 min P_4.1.15 Current through DEN pin IDEN -2 – 2 mA – P_4.1.16 Voltage at DSEL pin VDSEL -0.3 t < 2 min P_4.1.17 Current through DSEL pin IDSEL -2 – 2 mA – P_4.1.18 Sense Pin Voltage at IS pin VIS -0.3 – VS V – P_4.1.19 Current through IS pin IIS -25 – 50 mA – P_4.1.20 Power Stage Load current | IL |– – IL(LIM) A – P_4.1.21 Power dissipation (DC) PTOT ––1 . 6 W TA = 85 °C TJ < 150 °C P_4.1.22

General Product Characteristics Data Sheet 10 Rev. 2.1, 2011-09-01 PROFET™+ 12V Notes 1. Stresses above the ones listed here may cause perma nent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection func tions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Maximum energy dissipation Single pulse (one channel) EAS ––3 0 m J IL(0) = 1 A TJ(0) = 150 °C VS = 13.5 V P_4.1.23 Voltage at power transistor VDS – – 41 V – P_4.1.26 Currents Current through ground pin I GND -10 -150 –1 0 mA – t < 2 min P_4.1.27 Temperatures Junction temperature TJ -40 – 150 °C – P_4.1.28 Storage temperature TSTG -55 – 150 °C – P_4.1.30 ESD Susceptibility ESD susceptibility (all pins) VESD -2 – 2 kV 5) HBM P_4.1.31 ESD susceptibility OUT Pin vs. GND and VS connected VESD -4 – 4 kV 5) HBM P_4.1.32 ESD susceptibility VESD -500 – 500 V 6) CDM P_4.1.33 ESD susceptibility pin (corner pins) VESD -750 – 750 V 6) CDM P_4.1.34 1) Not subject to production test. Specified by design. 2) Hardware set-up in accordance to AEC Q100-012 and AEC Q101-006. 3) VS(LD) is setup without the DUT connected to the generator per ISO 7637-1. 4) EOL tests according to AECQ100-012. Thresh old limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer for short-circuit capability on Page 54 of this document. 5) ESD susceptibility HBM according to EIA/JESD 22-A 114B. 6) “CDM” EIA/JESD22-C101 or ESDA STM5.3.1 Table 2 Absolute Maximum Ratings (cont’d)1) TJ = -40°C to +150°C; (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 11 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA General Product Characteristics

4.2 Functional Range

Table 3 Functional Range TJ = -40°C to +150°C; (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Nominal operating voltage VNOM 8 13.5 18 V – P_4.2.1 Extended operating voltage VS(OP) 5–2 8 V 2) VIN = 4.5 V RL = 12 Ω VDS < 0.5 V See Figure 15 P_4.2.2 Minimum functional supply voltage VS(OP)_MIN 3.8 4.3 5 V 1) VIN = 4.5 V RL = 12 Ω From IOUT = 0 A to VDS < 0.5 V; See Figure 15 See Figure 29 P_4.2.3 Undervoltage shutdown VS(UV) 3 3.5 4.1 V 1) VIN = 4.5 V VDEN = 0 V RL = 12 Ω From VDS < 1 V; to IOUT = 0 A See Figure 15 See Figure 30 P_4.2.4 Undervoltage shutdown hysteresis VS(UV)_HYS – 850 – mV 2) – P_4.2.13 Operating current One channel active IGND_1 –3 . 5 6m A VIN = 5.5 V VDEN = 5.5 V Device in RDS(ON) VS = 18 V See Figure 31 P_4.2.5 Operating current All channels active IGND_2 –58m A VIN = 5.5 V VDEN = 5.5 V Device in RDS(ON) VS = 18 V See Figure 32 P_4.2.6 Standby current for whole device with load (ambiente) IS(OFF) –0 . 1 0 . 5 μA 1) VS = 18 V VOUT = 0 V VIN floating VDEN floating TJ ≤ 85 °C See Figure 33 P_4.2.7

General Product Characteristics Data Sheet 12 Rev. 2.1, 2011-09-01 PROFET™+ 12V Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

4.3 Thermal Resistance

4.3.1 PCB set up

Figure 4 2s2p PCB Cross Section Maximum standby current for whole device with load IS(OFF)_150 –22 0 μA VS = 18 V VOUT = 0 V VIN floating VDEN floating TJ = 150 °C See Figure 33 P_4.2.10 Standby current for whole device with load, diagnostic active IS(OFF_DEN) –0 . 6 –m A 2) VS = 18 V VOUT = 0 V VIN floating VDEN = 5.5 V P_4.2.8 1) Test at TJ = -40°C only 2) Not subject to production test. Specified by design. Table 4 Thermal Resistance Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Junction to soldering point RthJS –5–K / W 1) 1) Not subject to production test. Specified by design. P_4.3.1 Junction to ambient Both channels active RthJA –4 0 –K / W 1) 2) 2)Specified Rthja value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip + package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70μm Cu, 2 x 35 μm Cu). Where applicable, a thermal via array under the exposed pad contacts the first inner copper layer. Please refer to Figure 4 and Figure 5. P_4.3.2 Table 3 Functional Range (cont’d)TJ = -40°C to +150°C; (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. 1.5mm 70µm 35µm 0.3mm PCB 2s2p.vsd

Data Sheet 13 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA General Product Characteristics Figure 5 PC Board Top and Bottom View for The rmal Simulation with 600 mm² Cooling Area

4.3.2 Thermal Impedance

Figure 6 Typical Thermal Impedance. PCB set up according Figure 5 thermique SO14.vsd COOLING TAB VS PCB top view PCB bottom view 0.1 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time [sec] Zth-JA [K/W] 2s2p 1s0p - 600 mm² 1s0p - 300 mm² 1s0p - footprint

General Product Characteristics Data Sheet 14 Rev. 2.1, 2011-09-01 PROFET™+ 12V Figure 7 Typical Thermal Resistance. PCB set up 1s0p 0 100 200 300 400 500 600 70030 100Rthja [K/W] Area [mm2]footprint 1s0p

Data Sheet 15 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Power Stage

5 Power Stage

The power stages are built using an N-channel vertical power MOSFET (DMOS) with charge pump.

5.1 Output ON-state Resistance

The ON-state resistance RDS(ON) depends on the supply voltage as well as the junction temperature TJ. Figure 8 shows the dependencies in terms of temperature and supp ly voltage for the typical ON-state resistance. The behavior in reverse polarity is described in Chapter 6.4. Figure 8 Typical ON-state Resistance A high signal at the input pin (see Chapter 8) causes the power DMOS to switch ON with a dedicated slope, which is optimized in terms of EMC emission.

5.2 Turn ON/OFF Characteris tics with Resistive Load

Figure 9 shows the typical timing when switching a resistive load. Figure 9 Switching a R esistive Load Timing Rdson_180.vsd 100 120 140 160 180 200 220 240 260 280 300 320 340 360 -40 -10 20 50 80 110 140 Junction Temperature (Tj) RDS(ON) (mΩ) 100 150 200 250 300 0369 1 2 1 5 1 8 Supply Voltage V S (V) RDS(ON) (mΩ) IN t VOUT tON tON _DELAY tOFF 90% VS 10% VS VIN_H VIN_L t Switching times .vsd tOFF_DELAY 30% VS 70% VS dV/dt ON dV/dt OFF

Data Sheet 16 Rev. 2.1, 2011-09-01 PROFET™+ 12V

5.3 Inductive Load

5.3.1 Output Clamping

When switching OFF inductive loads wit h high side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destr uction of the device by avalanche due to high voltages, there is a voltage clamp mechanism ZDS(AZ) implemented that limits negative output voltage to a certain level (VS - VDS(AZ)). Please refer to Figure 10 and Figure 11 for details. Nevertheless, the maximum allowed load inductance is limited. Figure 10 Output Clamp (OUT0 and OUT1) Figure 11 Switching an Inductive Load Timing VBAT VOUT IL L, RL VS OUT VDS LOGIC IN VIN Output clamp.svg ZDS(AZ) GND ZGND IN VOUT IL VS VS-VDS(AZ) t t t Switching an inductance.vsd

Data Sheet 17 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Power Stage

5.3.2 Maximum Load Inductance

During demagnetization of inductive lo ads, energy has to be dissipated in the BTS5180-2EKA. This energy can be calculated with following equation: (1) Following equation simplifies under the assumption of RL = 0 Ω. (2) The energy, which is converted into heat, is limited by the thermal design of the component. See Figure 12 for the maximum allowed energy dissipation as a function of the load current. Figure 12 Maximum Energy Dissipation Single Pulse, TJ(0) = 150 °C; VS = 13.5V

5.4 Inverse Current Capability

In case of inverse current, meaning a voltage VINV at the OUTput higher than the supply voltage VS, a current IINV will flow from output to VS pin via the body diode of the power transistor (please refer to Figure 13). The output stage follows the state of the IN pin, except if the IN pi n goes from OFF to ON during inverse. In that particular case, the output stage is kept OFF until the inverse current disappears. Nevertheless, the current IINV should not be higher than IL(INV). Otherwise, the second channel can be corrup ted and erratic behavior can be observed. If the affected channel is OFF, the diagnostic will detect an open load at OFF. If the affected channel is ON, the diagnostic will detect open load at ON (the overtemp erature signal is inhibited) . At the appearance of VINV, a parasitic diagnostic can be observed at the unaffected channel. After, the diagnosis is valid and reflects the output state. At VINV vanishing, the diagnosis is valid and reflects the output state. During inverse current, no protection function are available. EV DS AZ() L RL RL ⎛⎞ln IL+××= E 1 2--- LI 1 VS 100 1000 0123 IL [A] EAS [mJ] EAS180.vsd

Data Sheet 18 Rev. 2.1, 2011-09-01 PROFET™+ 12V Figure 13 Inverse Current Circuitry OUT VS VBAT IL(INV)OL comp. inverse current.svg VINV INV Comp. Gate driver Device logic GND ZGND

Data Sheet 19 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Power Stage

5.5 Electrical Charact eristics Power Stage

Table 5 Electrical Characteristics: Power Stage VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. ON-state resistance per channel RDS(ON)_150 180 330 360 m Ω IL = IL4 = 2 A VIN = 4.5 V TJ = 150 °C See Figure 8 P_5.5.1 ON-state resistance per channel RDS(ON)_25 – 180 – m Ω 1) TJ = 25 °C P_5.5.21 Nominal load current One channel active IL(NOM)1 –2–A 1) TA = 85 °C TJ < 150 °C P_5.5.2 Nominal load current All channel active IL(NOM)2 –1 . 5 –A P _ 5 . 5 . 3 Output voltage drop limitation at small load currents VDS(NL) –1 0 2 5 m V IL = IL0 = 30 mA See Figure 34 P_5.5.4 Drain to source clamping voltage VDS(AZ) = [VS - VOUT] VDS(AZ) 41 47 53 V IDS = 20 mA See Figure 11 See Figure 35 P_5.5.5 Output leakage current per channel; TJ ≤ 85 °C IL(OFF) –0 . 1 0 . 5 μA 2) VIN floating VOUT = 0 V TJ ≤ 85 °C P_5.5.6 Output leakage current per channel; TJ = 150 °C IL(OFF)_150 –11 0 μA VIN floating VOUT = 0 V TJ = 150 °C P_5.5.8 Inverse current capability IL(INV) –1 . 5 –A 1) VS < VOUTx P_5.5.9 Slew rate 30% to 70% VS dV/dtON 0.1 0.25 0.5 V/ μs RL = 12 Ω VS = 13.5 V See Figure 9 See Figure 36 See Figure 37 See Figure 38 See Figure 39 See Figure 40 P_5.5.11 Slew rate 70% to 30% VS Slew rate matching dV/dtON - dV/dtOFF ΔdV/dt -0.15 0 0.15 V/ μs P_5.5.13 Turn-ON time to VOUT = 90% VS tON 30 100 230 μs P_5.5.14 Turn-OFF time to VOUT = 10% VS tOFF 30 100 230 μs P_5.5.15 Turn-ON / OFF matching tOFF - tON ΔtSW -50 0 50 μs P_5.5.16 Turn-ON time to VOUT = 10% VS tON_delay 10 35 100 μs P_5.5.17 Turn-OFF time to VOUT = 90% VS tOFF_delay 10 35 100 μs P_5.5.18

Data Sheet 20 Rev. 2.1, 2011-09-01 PROFET™+ 12V Switch ON energy EON –0 . 4 –m J 1) RL = 12 Ω VOUT = 90% VS VS = 18 V See Figure 41 P_5.5.19 Switch OFF energy EOFF –0 . 4 –m J 1) RL = 12 Ω VOUT = 10% VS VS = 18 V See Figure 42 P_5.5.20 1) Not subject to production test, specified by design. 2) Test at TJ = -40°C only Table 5 Electrical Characteristics: Power Stage (cont’d) VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 21 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Protection Functions

6 Protection Functions

The device provides integrated protecti on functions. These functions are designed to prevent the destruction of the IC from fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are designed for neither continuous nor repetitive operation.

6.1 Loss of Ground Protection

In case of loss of the module ground and the load re mains connected to ground, th e device protects itself by automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied on IN pins. In case of loss of device ground, it’s recommended to use input resistors between the microcontroller and the BTS5180-2EKA to ensure switching OFF of channels. In case of loss of module or device ground, a current ( IOUT(GND)) can flow out of the DMOS. Figure 14 sketches the situation. ZGND can be either resistor or diode. Figure 14 Loss of Ground Protection with External Components

6.2 Undervoltage Protection

Between VS(UV) and VS(OP), the undervoltage mechanism is triggered. VS(OP) represents the minimum voltage where the switching ON and OFF can takes place. VS(UV) represents the minimum voltage the switch can hold ON. If the supply voltage is below the undervoltage mechanism VS(UV), the device is OFF (turns OFF). As soon as the supply voltage is above the undervoltage mechanism VS(OP), then the device can be switched ON. When the switch is ON, protection functions are operational. Nevertheless, the diagnosis is not guaranteed until VS is in the VNOM range. Figure 15 sketches the undervoltage mechanism. INx DEN IS ZDESD GND OUTx VS VBATZD(AZ) LOGIC DSEL Loss of ground protection.svg IOUT(GND) ZDS(AZ) RIN RDEN RDSEL RSENSE RIS ZIS(AZ) ZGND

Data Sheet 22 Rev. 2.1, 2011-09-01 PROFET™+ 12V Figure 15 Undervoltage Behavior

6.3 Overvoltage Protection

There is an integrated clamp mechan ism for overvoltage protection (Z D(AZ)). To guarantee this mechanism operates properly in the application, the current in the Zener diode has to be limited by a ground resistor. Figure 16 shows a typical application to withstand overvoltage issues. In case of supply voltage higher than VS(AZ), the power transistor switches ON and the voltage across the logic section is clamped. As a result, the internal ground potential rises to VS - VS(AZ). Due to the ESD Zener diodes, the potential at pin INx, DSEL and DEN rises almost to that potential, depending on the impedance of the conne cted circuitry. In the case the device was ON, prior to overvoltage, the BTS5180-2EKA remains ON. In the case the BTS5180-2EKA was OFF, prior to overvoltage, the power transistor can be activated. In the case the supply voltage is in above VBAT(SC) and below VDS(AZ), the output transistor is still operational and follows the input. If at least one channel is in the ON state, parameters are no longer guaranteed and lifetime is reduced compared to the nominal supply voltage range. This especially impacts the short circuit robustness, as well as the maximum energy EAS capability. ZGND as a resistor (150 Ω) will offer superior results compared to a diode and resistor (1 kΩ). Figure 16 Overvoltage Protecti on with External Components undervoltage behavior.vsd VOUT VS(OP)VS(UV) VS INx DEN IS ZDESD GND OUTx VS VBATZD(AZ) LOGIC DSEL Overvoltage protection.svg ZDS(AZ) IN0 IN1 RIN RDEN RDSEL RSENSE RIS ISOV ZIS(AZ) ZGND

Data Sheet 23 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Protection Functions

6.4 Reverse Polarity Protection

In case of reverse polarity, the intrinsic body diodes of the power DMOS causes power dissipation. The current in this intrinsic body diode is limited by the load itself. Additionally, the current into the ground path and the logic pins has to be limited to the maximum current described in Chapter 4.1 with an external resistor. Figure 17 shows a typical application. RGND resistor is used to limit the current in the Zener protection of the device. Resistors RDSEL, RDEN, and RIN are used to limit the current in the logic of the device and in the ESD protection stage. RSENSE is used to limit the current in the sense transistor which behaves as a diode. The recommended value for RDEN = RDSEL = RIN = RSENSE = 4.7 kΩ. ZGND can be either a 150 Ω resistor or Schottky diode with 1 kΩ resistor in parallel. In case the overvoltage is not considered in the application, RGND can be replaced by a Schottky diode and 1k Ω resistor in parallel. Optionally a capacitor in parallel is recommended for EMC reasons. During reverse polarity, no protection functions are available. Figure 17 Reverse Polarity Protection with External Components

6.5 Overload Protection

In case of overload, such as high inrush of cold lamp filament, or short circuit to ground, the BTS5180-2EKA offers several protection mechanisms.

6.5.1 Current Limitation

At first step, the instantaneous power in the switch is maintained at a safe value by limiting the current to the maximum current allowed in the switch IL(SC). During this time, the DMOS temperature is increasing, which affects the current flowing in the DMOS. The current limitation value is VDS dependent. Figure 18 shows the behavior of the current limitation as a function of the drain to source voltage. INx DEN IS ZDESD GND OUTx VS -VS(REV) ZD(AZ) LOGIC DSEL Reverse Polarity .vsd ZDS(AZ) IN0 RIN RDEN RDSEL RSENSE RIS VDS(REV) Micro controller protection diodes ZIS(AZ) ZGND

Data Sheet 24 Rev. 2.1, 2011-09-01 PROFET™+ 12V Figure 18 Current Limitation (typical behavior)

6.5.2 Temperature Limita tion in the Power DMOS

Each channel incorporates both an absolute ( TJ(SC)) and a dynamic ( TJ(SW)) temperature sensor. Activation of either sensor will cause an overheated channel to switch OFF to prevent destruction. Any protective switch OFF latches the output until the temperature has reached an acceptable value. Figure 19 gives a sketch of the situation. The ΔTSTEP describes the device’s warming, due to the overcurrent in the channel. A retry strategy is implemented such that when the DM OS temperature has cooled down enough, the switch is switched ON again, if the IN pin signal is still high (restart behavior).

Data Sheet 25 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Protection Functions Figure 19 Overload Protection Note: For better understanding, the time scale is not linear. The real timing of this drawing is application dependant and cannot be described.

6.5.3 Short Circuit Appearan ce with Channel in Parallel

The two channels are not synchronized in the restart event. When the two channels are in temperature limitation, the channel which has cooled down the fastest doesn’t wait for the second one to be cooled down as well to restart. Thus, it is not recommended to use the device with channels in parallel. IN t IL t IL(x)SC IIS t0A IIS(FAULT) VDEN t0V TDMOS t ΔTSTEP TA ΔTJ(SW) ΔTJ(SW) ΔTJ(SW) Hard start.vsd tsIS( FAULT) IL(NOM) IL(NOM) / kILIS tsIS(OT _blank ) TJ( SC) tsIS(OFF ) LOAD CURRENT LIMITATION PHASE LOAD CURRENT BELOW LIMITATION PHASE

Data Sheet 26 Rev. 2.1, 2011-09-01 PROFET™+ 12V

6.6 Electrical Characteristi cs for the Protection Functions

Table 6 Electrical Characteristics: Protection VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Loss of Ground Output leakage current while GND disconnected IOUT(GND) –0 . 1 –m A 1) 2) VS = 28 V See Figure 14 1) All pins are disconnected except VS and OUT. 2) Not Subject to production test, specified by design P_6.6.1 Reverse Polarity Drain source diode voltage during reverse polarity VDS(REV) 200 650 700 mV IL = - 1 A TJ = 150 °C See Figure 17 P_6.6.2 Overvoltage Overvoltage protection VS(AZ) 41 47 53 V ISOV = 5 mA See Figure 16 P_6.6.3 Overload Condition Load current limitation IL5(SC) 8 1 11 5A 3)VDS = 5 V See Figure 18 and Figure 43 3) Test at TJ = -40°C only P_6.6.4 Load current limitation IL28(SC) –4–A 2) VDS = 28 V See Figure 18 and Figure 44 P_6.6.7 Short circuit current during over temperature toggling IL(RMS) –2–A 2) VIN = 4.5 V RSHORT = 100 mΩ LSHORT = 5 μH P_6.6.12 Dynamic temperature increase while switching ΔTJ(SW) –8 0 –K 4) See Figure 19 4) Functional test only P_6.6.8 Thermal shutdown temperature TJ(SC) 150 170 4) 200 4) °C 5) See Figure 19 5) Test at TJ = +150°C only P_6.6.10 Thermal shutdown hysteresis ΔTJ(SC) – 20 – K 5) 4) See Figure 19 P_6.6.11

Data Sheet 27 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Diagnostic Functions

7 Diagnostic Functions

For diagnosis purpose, the BTS5180-2EKA provides a combination of digital and analog signals at pin IS. These signals are called SENSE. In case the diagnostic is dis abled via DEN, pin IS becomes high impedance. In case DEN is activated, the SENSE of the channel X is enabled/disabled via associated pin DSEL. Table 7 gives the truth table.

7.1 IS Pin

The BTS5180-2EKA provides a SENSE current written IIS at pin IS. As long as no “hard” failure mode occurs (short circuit to GND / current limitation / ov ertemperature / excessive dynamic tem perature increase or open load at OFF) a proportional signal to the load current (ratio kILIS = IL / IIS) is provided. The complete IS pin and diagnostic mechanism is described on Figure 20. The accuracy of the SENSE depends on temperature and load current. The IS pin multiplexes the current IIS(0) and IIS(1), via the pin DSEL. Thanks to this multiplexing, the matching between kILISCHANNEL0 and kILISCHANNEL1 is optimized. Due to the ESD protection, in connection to VS, it is not recommended to share the IS pin with other devices if these devices are using another battery feed. The consequence is that the unsupplied device would be fed via the IS pin of the supplied device. Figure 20 Diagnostic Block Diagram Table 7 Diagnostic Truth Table DEN DSEL IS 0 don’t care Z 1 0 Sense output 0 IIS(0) 1 1 Sense output 1 IIS(1) Vs IIS0 = IL0 / kILIS DEN IS DSEL Sense schematic.svg IIS1 = IL1 / kILIS ZIS(AZ) IIS(FAULT) FAULT

Data Sheet 28 Rev. 2.1, 2011-09-01 PROFET™+ 12V

7.2 SENSE Signal in Different Operating Modes

Table 8 gives a quick reference for the state of the IS pin during device operation. Table 8 Sense Signal, Function of Operation Mode Operation Mode Input level Channel X DEN 1) 1) The table doesn’t indicate but it is assumed that the appropriate channel is selected via the DSEL pin. Output Level Diagnostic Output Normal operation OFF H Z Z Short circuit to GND ~ GND Z Overtemperature Z Z Short circuit to VS VS IIS(FAULT) Open Load < VOL(OFF) > VOL(OFF) 2) With additional pull-up resistor. Z IIS(FAULT) Inverse current ~ VINV IIS(FAULT) Normal operation ON ~ VS IIS = IL / kILIS Current limitation < VS IIS(FAULT) Short circuit to GND ~ GND IIS(FAULT) Overtemperature TJ(SW) event Z IIS(FAULT) Short circuit to VS VS IIS < IL / kILIS Open Load ~ VS 3) The output current has to be smaller than IL(OL). IIS < IIS(OL) Inverse current ~ VINV IIS < IIS(OL) 4) After maximum tINV. Underload ~ VS 5) The output current has to be higher than IL(OL). IIS(OL) < IIS < IL(nom) / kILIS Don’t care Don’t care L Don’t care Z

Data Sheet 29 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Diagnostic Functions

7.3 SENSE Signal in th e Nominal Current Range

Figure 21 and Figure 22 show the current sense as a function of the load current in the power DMOS. Usually, a pull-down resistor RIS is connected to the IS pin. This resistor has to be higher than 560 Ω to limit the power losses in the sense circuitry. A typical value is 1.2 k Ω. The blue curve represents the ideal SENSE, assuming an ideal kILIS factor value. The red curves show the accuracy the device provides across full temperature range, at a defined current. Figure 21 Current Sense for Nominal Load

7.3.1 SENSE Signal Variat ion as a Function of Temperature and Load Current

In some applications a better accuracy is required around half the nominal current IL(NOM). To achieve this accuracy requirement, a calibration on the application is possible. To avoid multiple calibration points at different load and temperature conditions, the BTS5180-2EKA allows limited derating of the kILIS value, at nominal load current (IL3; TJ = +25 °C). This derating is described by the parameter ΔkILIS. Figure 22 shows the behavior of the SENSE current, assuming one calibration point at nominal load at +25 °C. The blue line indicates the ideal kILIS ratio. The green lines indicate the derating on the parameter across temperature and voltage, assuming one calibration point at nominal temperature and nominal battery voltage. The red lines indicate the kILIS accuracy without calibration. 0.0 1.0 2.0 3.0 4.0 5.0 6.0 IL [A] I IS [m A] KILIS ideal IIS = kilis BTS5180 kilis4 Kilis3 Kilis2 Kilis1 IL

Data Sheet 30 Rev. 2.1, 2011-09-01 PROFET™+ 12V Figure 22 Improved SENSE Accuracy with One Calibration Point

7.3.2 SENSE Signal Timing

Figure 23 shows the timing during settling and disabling of the SENSE. Figure 23 SENSE Settling / Disabling Timing 0 0.5 1 1.5 2 2.5 3 350 400 450 500 550 600 650 700 750 800 IL [A] kILIS BTS5180 Calibration Point VINx t IL t IIS t VDEN t tsIS(ON) tsIS(OFF) tONx 90% of IIS static 90% of I L static tsIS(ON_DEN) tsIS(LC) VINy t ILy t VDSEL t tsIS(chC) current sense settling disabling time.vsd tONxtOFFx tONy

Data Sheet 31 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Diagnostic Functions

7.3.3 SENSE Signal in Open Load

7.3.3.1 Open Load in ON Diagnostic

If the channel is ON, a leakage curr ent can still flow through an open load, for exampl e due to humidity. The parameter IL(OL) gives the threshold of recognition fo r this leakage current. If the current IL flowing out the power DMOS is below this value, the device recognizes a failure , if the DEN (and DSEL) is selected. In that case, the SENSE current is below IIS(OL). Otherwise, the minimum SENSE cu rrent is given above parameter IIS(OL). Figure 24 shows the SENSE current behavior in this area. The red curve shows a typical product curve. The blue curve shows the ideal kILIS ratio. Figure 24 Current Sense Ratio for Low Currents

7.3.3.2 Open Load in OFF Diagnostic

For open load diagnosis in OFF-state, an external output pull-up resistor ( ROL) is recommended. For the calculation of pull-up resistor value, the leakage currents and the open load threshold voltage VOL(OFF) have to be taken into account. Figure 25 gives a sketch of the situation. Ileakage defines the leakage current in the complete application. To reduce the stand-by current of the system, an open load resistor switch SOL is recommended. If the channel x is OFF, the output is no longer pulled down by the load and VOUT voltage rises to nearly VS. This is recognized by the device as an open load. The voltage threshold is given by VOL(OFF). In that case, the SENSE signal is switched to the IIS(FAULT). An additional RPD resistor can be used to pull VOUT to 0V. Otherwise, the OUT pin is floating. This resistor can be used as well for short circuit to battery detection, see Chapter 7.3.4. IIS IL Sense for OL .vsd IL(OL) IIS(OL)

Data Sheet 32 Rev. 2.1, 2011-09-01 PROFET™+ 12V Figure 25 Open Load Detection in OFF Electrical Equivalent Circuit

7.3.3.3 Open Load Diagnostic Timing

Figure 26 shows the timing during either Open Load in ON or OFF condition when the DEN pin is HIGH. Please note that a delay tsIS(FAULT_OL_OFF) has to be respecte d after the falling edge of th e input, when applying an open load in OFF diagnosis request, otherwise the diagnosis can be wrong. Figure 26 SENSE Signal in Open Load Timing OUT VS SOL Vbat VOL(OFF) Ileakage IIS(FAULT) IS ILOFF OL comp. Open Load in OFF.svg ROL ZGNDRIS Rleakage GND RPD VIN tVOUT t IIS t tsIS(LC) 90% of IIIS(FAULT) static tsIS(FAULT_OL_OFF) Error Settling Disabling Time .vsd VS-VOL(OFF) RDS(ON) x IL IOUT Load is present Open load shutdown with load t

Data Sheet 33 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Diagnostic Functions

7.3.4 SENSE Signal with OUT in Short Circuit to VS

In case of a short circuit between the OUTput-pin and the VS pin, all or portion (depending on the short circuit impedance) of the load current will flow thro ugh the short circuit. As a resul t, a lower current compared to the normal operation will flow th rough the DMOS of the BTS5180-2EKA, which can be recognized at the SENSE signal. The open load at OFF detection circuitry can also be used to distinguish a short circuit to VS. In that case, an external resistor to ground RSC_VS is required. Figure 27 gives a sketch of the situation. Figure 27 Short Circuit to Battery Detecti on in OFF Electrical Equivalent Circuit

7.3.5 SENSE Signal in Case of Overload

An overload condition is defined by a current flowing out of the DMOS reaching the current limitation and / or the absolute dynamic temperature swing TJ(SW) is reached, and / or the juncti on temperature reaches the thermal shutdown temperature TJ(SC). Please refer to Chapter 6.5 for details. In that case, the SENSE signal given is by IIS(FAULT) when the diagnostic is selected. The device has a thermal restart behavior, such th at when the overtemperature or the exceed dynamic temperature condition has disappeared, t he DMOS is reactivated if the IN is still at logical leve l one. If the DEN pin is activated, and DSEL pin is selected to the correct channel, SENSE is not toggling with the restart mechanism and remains to IIS(FAULT).

7.3.6 SENSE Signal in Case of Inverse Current

In the case of in verse current, the sense signal of the affected channel will indicate open load in OFF state and indicate open load in ON state. The unaffected channel indicates normal behavior as long as the IINV current is not exceeding the maximum value specified in Chapter 5.4. VS Vbat VOL(OFF) IIS(FAULT) IS OL comp. Short circuit to Vs.svg VBAT OUT GND ZGND RSC_VSRIS

Data Sheet 34 Rev. 2.1, 2011-09-01 PROFET™+ 12V

7.4 Electrical Character istics Diagnostic Function

Table 9 Electrical Characteristics: Diagnostics VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Load Condition Threshold for Diagnostic Open load detection threshold in OFF state VS - VOL(OFF) 4–6V 1) VIN = 0 V VDEN = 4.5 V See Figure 26 P_7.5.1 Open load detection threshold in ON state IL(OL) 5–3 0 m A VIN = VDEN = 4.5 V IIS(OL) = 22 μA See Figure 24 See Figure 46 P_7.5.2 Sense Pin IS pin leakage current when sense is disabled IIS_(DIS) ––1 μA 1) VIN = 4.5 V VDEN = 0 V IL = IL4 = 2 A P_7.5.4 Sense signal saturation voltage VS - VIS (RANGE) 0–3V 3) VIN = 0 V VOUT = VS > 10 V VDEN = 4.5 V IIS = 6 mA See Figure 47 P_7.5.6 Sense signal maximum current in fault condition IIS(FAULT) 61 5 3 5 m A VIS = VIN = VDSEL = 0 V VOUT = VS > 10 V VDEN = 4.5 V See Figure 20 See Figure 48 P_7.5.7 Sense pin maximum voltage VIS(AZ) 41 47 53 V IIS = 5 mA See Figure 20 P_7.5.3 Current Sense Ratio Signal in the Nominal Area, Stable Load Current Condition Current sense ratio IL0 = 50 mA kILIS0 -35 570 +35 % VIN = 4.5 V VDEN = 4.5 V See Figure 21 P_7.5.8 Current sense ratio IL1 = 0.25 A kILIS1 -21 560 +21 % P_7.5.9 Current sense ratio IL2 = 0.5 A kILIS2 -9 560 +9 % P_7.5.10 Current sense ratio IL3 = 1 A Current sense ratio IL4 = 2 A kILIS4 -6 550 +6 % P_7.5.12 kILIS derating with current and temperature ΔkILIS -5 0 +5 % 3) kILIS3 versus kILIS2 See Figure 22 P_7.5.17 Diagnostic Timing in Normal Condition

Data Sheet 35 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Diagnostic Functions Current sense settling time to kILIS function stable after positive input slope on both INput and DEN tsIS(ON) 0–2 5 0 μs 3) VDEN = VIN = 0 to 4.5 V VS = 13.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 = 1 A See Figure 23 P_7.5.18 Current sense settling time with load current stable and transition of the DEN tsIS(ON_DEN) 0–2 0 μs 1) VIN = 4.5 V VDEN = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 = 1 A See Figure 23 P_7.5.19 Current sense settling time to IIS stable after positive input slope on current load tsIS(LC) 0–2 0 μs 1) VIN = 4.5 V VDEN = 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL2 = 0.5 A to IL = IL3 = 1 A See Figure 23 P_7.5.20 Diagnostic Timing in Open Load Condition Current sense settling time to IIS stable for open load detection in OFF state tsIS(FAULT_OL_ OFF) 0–1 5 0 μs 1) VIN = 0V VDEN = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF VOUT = VS = 13.5 V See Figure 26 P_7.5.22 Diagnostic Timing in Overload Condition Current sense settling time to IIS stable for overload detection tsIS(FAULT) 0–2 5 0 μs 1) 2) VIN = VDEN = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF VDS = 5 V See Figure 19 P_7.5.24 Current sense over temperature blanking time tsIS(OT_blank) – 350 – μs 3) VIN = VDEN = 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF VDS = 5 V to 0 V See Figure 19 P_7.5.32 Table 9 Electrical Characteristics: Diagnostics (cont’d) VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 36 Rev. 2.1, 2011-09-01 PROFET™+ 12V Diagnostic disable time DEN transition to IIS < 50% IL /kILIS tsIS(OFF) 0–3 0 μs 1) VIN = 4.5 V VDEN = 4.5 V to 0 V RIS = 1.2 kΩ CSENSE < 100 pF IL = IL3 = 1 A See Figure 23 P_7.5.25 Current sense settling time from one channel to another tsIS(ChC) 0–2 0 μs VIN0 = VIN1 = 4.5 V VDEN = 4.5 V VDSEL = 0 to 4.5 V RIS = 1.2 kΩ CSENSE < 100 pF IL(OUT0) = IL3 = 1 A IL(OUT1) = IL2 = 0.5 A See Figure 23 P_7.5.26 1) DSEL pin select channel 0 only. 2) Test at TJ = -40°C only 3) Not subject to production test, specified by design Table 9 Electrical Characteristics: Diagnostics (cont’d) VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.

Data Sheet 37 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Input Pins

8 Input Pins

8.1 Input Circuitry

The input circuitry is compatible with 3.3 and 5 V microcontrollers. The concept of the input pin is to react to voltage thresholds. An implemented Schmidt trigger avoids any unde fined state if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in a linear or undefined state. The input circuitry is compatible with PWM applications. Figure 28 shows the electrical equivalent input circuitry. In case the pin is not needed, it must be left opened, or must be connected to device ground (and not module ground) via a 4.7kΩ input resistor. Figure 28 Input Pin Circuitry

8.2 DEN / DSEL Pin

The DEN / DSEL pins enable and disable the diagnostic functionality of the device. The pins have the same structure as the Input pins, please refer to Figure 28.

8.3 Input Pin Voltage

The IN, DSEL and DEN use a comparator with hysteresis. The switching ON / OFF takes place in a defined region, set by the thresholds VIN(L) Max. and VIN(H) Min. The exact value where the ON and OFF take place are unknown and depends on the process, as well as the temperature. To avoid cross talk and parasitic turn ON and OFF, a hysteresis is implemented. This ensures a certain immunity to noise. GND IN Input circuitry.vsd

Data Sheet 38 Rev. 2.1, 2011-09-01 PROFET™+ 12V

8.4 Electrical Characteristics

Table 10 Electrical Characteristics: Input Pins VS = 8 V to 18 V, TJ = -40°C to +150°C (unless otherwise specified). Typical values are given at VS = 13.5 V, TJ = 25 °C Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. INput Pins Characteristics Low level input voltage range VIN(L) -0.3 – 0.8 V See Figure 49 P_8.4.1 High level input voltage range VIN(H) 2 – 6 V See Figure 50 P_8.4.2 Input voltage hysteresis VIN(HYS) – 250 – mV 1) See Figure 51 1) Not subject to production test, specified by design P_8.4.3 Low level input current IIN(L) 11 0 2 5 μA VIN = 0.8 V P_8.4.4 High level input current IIN(H) 21 0 2 5 μA VIN = 5.5 V See Figure 52 P_8.4.5 DEN Pin Low level input voltage range VDEN(L) -0.3 – 0.8 V – P_8.4.6 High level input voltage range VDEN(H) 2–6V – P _ 8 . 4 . 7 Input voltage hysteresis VDEN(HYS) – 250 – mV 1) P_8.4.8 Low level input current IDEN(L) 11 0 2 5 μA VDEN = 0.8 V P_8.4.9 High level input current IDEN(H) 21 0 2 5 μA VDEN = 5.5 V P_8.4.10 DSEL Pin Low level input voltage range VDSEL(L) -0.3 – 0.8 V – P_8.4.11 High level input voltage range VDSEL(H) 2–6V – P _ 8 . 4 . 1 2 Input voltage hysteresis VDSEL(HYS) – 250 – mV 1) P_8.4.13 Low level input current IDSEL(L) 11 0 2 5 μA VDSEL = 0.8 V P_8.4.14 High level input current IDSEL(H) 21 0 2 5 μA VDSEL = 5.5 V P_8.4.15

Data Sheet 39 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Characterization Results

9 Characterizati on Results

The characterization have been performed on 3 lots, with 3 devices each. Characterization have been performed at 8 V, 13.5 V and 18 V, from -40°C to 160°C. When no dependency to voltage is seen, only one curve (13,5V) is sketched.

9.1 General Product Characteristics

9.1.1 Minimum Functi onal Supply Voltage

P_4.2.3 Figure 29 Minimum Functional Supply Voltage VS(OP)_MIN = f(TJ)

9.1.2 Undervoltage Shutdown

P_4.2.4 Figure 30 Undervoltage Threshold VS(UV) = f(TJ) 3,8 4,2 4,6 -40 0 40 80 120 160 Junction Temp (°C) VS(OP)_MIN (V) minimum functional supply.vsd Undervoltage_shutdown.vsd 3,25 3,5 3,75 -40 0 40 80 120 160 Junction Temp (°C) VS(UV) (V)

Data Sheet 40 Rev. 2.1, 2011-09-01 PROFET™+ 12V

9.1.3 Current Consumpt ion One Channel active

P_4.2.5 Figure 31 Current Consumption for Whole D evice with Load. One Channel Active IGND_1 = f(TJ;VS)

9.1.4 Current Consumptio n Two Channels active

P_4.2.6 Figure 32 Current Consumption for Whole D evice with Load. Two Channels Active IGND_2 = f(TJ;VS)

9.1.5 Standby Current for Whole Device with Load

P_4.2.7, P_4.2.10 Figure 33 Standby Current for Whole Device with Load. IS(OFF) = f(TJ;VS) Current consumption one channel active.vsd -40 0 40 80 120 160 Junction Temp (°C) I_GND1 (mA) I_GND1 @ 8V I_GND1 @ 13.5V I_GND1 @ 18V Current consumption two channel active.vsd -40 0 40 80 120 160 Junction Temp (°C) I_GND2 (m A) I_GND2 @ 8V I_GND2 @ 13.5V I_GND2 @ 18V

Data Sheet 41 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Characterization Results

9.2 Power Stage

9.2.1 Output Voltage Drop Li mitation at Low Load Current

P_5.5.4 Figure 34 Output Voltage Drop Limitation at Low Load Current VDS(NL) = f(TJ;VS) ; IL = IL(0) = 30mA

9.2.2 Drain to Source Clamp Voltage

P_5.5.5 Figure 35 Drain to Source Clamp Voltage VDS(AZ) = f(TJ) -40 0 40 80 120 160 Junction Temp (°C) VDS(NL) (mV) Output Voltage drop limitation at low load current.vsd -40 0 40 80 120 160 Junction Temp (°C) VDS(AZ) (V) Drain to source clamp voltage.vsd

Data Sheet 42 Rev. 2.1, 2011-09-01 PROFET™+ 12V

9.2.3 Slew Rate at Turn ON

P_5.5.11 Figure 36 Slew Rate at Turn ON d V/dtON = f(TJ;VS), RL = 12 Ω

9.2.4 Slew Rate at Turn OFF

P_5.5.12 Figure 37 Slew Rate at Turn OFF - d V/dtOFF = f(TJ;VS), RL = 12 Ω

9.2.5 Turn ON

P_5.5.14 Figure 38 Turn ON tON = f(TJ;VS), RL = 12 Ω dV_dt_ON.vsd 0,1 0,3 0,5 -40 0 40 80 120 160 Junction Temp (°C) dV/dt_ON (V/µs) dV/dt_ON @ 8V dV/dt_ON @ 13.5V dV/dt_ON @ 18V dV_dt_OFF.vsd 0,1 0,3 0,5 -40 0 40 80 120 160 Junction Temp (°C) dV/dt_OFF (V/µs) dV/dt_OFF @ 8V dV/dt_OFF @ 13.5V dV/dt_OFF @ 18V 130 230 -40 0 40 80 120 160 Junction Temp (°C) t_ON 90% (µs) tON 90%@18V tON 90%@13,5V tON 90%@8V tON_90.vsd

Data Sheet 43 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Characterization Results

9.2.6 Turn OFF

P_5.5.11 Figure 39 Turn OFF tOFF = f(TJ;VS), RL = 12 Ω

9.2.7 Turn ON / OFF matching

P_5.5.16 Figure 40 Turn ON / OFF matching ΔtSW = f(TJ;VS), RL = 12 Ω 130 230 -40 0 40 80 120 160 Junction Temp (°C) t_OFF 10% (µs) tOFF 10%@18V tOFF 10%@13,5V tOFF 10%@8V tOFF_90.vsd delta_t_SW_OFF_ON.vsd -50 -25 -40 0 40 80 120 160 Junction Temp (°C) delta t SW (µs) delta_t_SW @ 8V delta_t_SW @ 13.5V delta_t_SW @ 18V

Data Sheet 44 Rev. 2.1, 2011-09-01 PROFET™+ 12V

9.2.8 Switch ON Energy

P_5.5.19 Figure 41 Switch ON Energy EON = f(TJ;VS), RL = 12 Ω

9.2.9 Switch OFF Energy

P_5.5.20 Figure 42 Switch OFF Energy EOFF = f(TJ;VS), RL = 12 Ω 250 500 750 -40 0 40 80 120 160 Junction Temp (°C) E_ON (µJ) Switch ON energy @ 18V Switch ON energy @ 13,5V Switch ON energy @ 8V 250 500 750 -40 0 40 80 120 160 Junction Temp (°C) E_ON (µJ) Switch ON energy @ 18V Switch ON energy @ 13,5V Switch ON energy @ 8V

Data Sheet 45 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Characterization Results

9.3 Protection Functions

9.3.1 Overload Condition in the Low Voltage Area

P_6.6.4 Figure 43 Overload Condition in the Low Voltage Area IL5(SC) = f(TJ;VS)

9.3.2 Overload Condition in the High Voltage Area

P_6.6.7 Figure 44 Overload Condition in the High Voltage Area IL28(SC) = f(TJ;VS)

Data Sheet 46 Rev. 2.1, 2011-09-01 PROFET™+ 12V

9.4 Diagnostic Mechanism

9.4.1 Current Sense at no Load

Figure 45 Current Sense at no Load IIS = f(TJ;VS), IL = 0

9.4.2 Open Load Detection Threshold in ON State

P_7.5.2 Figure 46 Open Load Detection ON State Threshold IL(OL) = f(TJ;VS) 0,5 1,5 2,5 -40 0 40 80 120 160 Junction Temp (°C) I_IS @ IL = 0mA (µA) Current _sense_0mA.vsd

Data Sheet 47 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Characterization Results

9.4.3 Sense Signal Maximum Voltage

P_7.5.3 Figure 47 Sense Signal Maximum Voltage VS - VIS(RANGE) =f(TJ;VS)

9.4.4 Sense Signal maximum Current

P_7.5.7 Figure 48 Sense Signal Maximum Current in Fault Condition IIS(FAULT) = f(TJ;VS) -40 0 40 80 120 160 Junction Temp (°C) V S - V IS _RANGE (V) VI S_RANGE @ 8V VI S_RANGE @ 13.5V VI S_RANGE @ 18V IIS_FAULT.vsd -40 0 40 80 120 160 Junction Temp (°C) IIS_FAULT (mA) IIS_FAULT @ 8V IIS_FAULT @ 13.5V IIS_FAULT @ 18V

Data Sheet 48 Rev. 2.1, 2011-09-01 PROFET™+ 12V

9.5 Input Pins

9.5.1 Input Voltage Thr eshold ON to OFF

P_8.4.1 Figure 49 Input Voltage Threshold VIN(L) = f(TJ;VS)

9.5.2 Input Voltage Threshold OFF to ON

P_8.4.2 Figure 50 Input Voltage Threshold VIN(H) = f(TJ;VS) Input_pin_low_voltage.vsd 0,5 1,5 -40 0 40 80 120 160 Junction Temp (°C) V_INH(L) (V) I_I N(L) @ 8V I_I N(L) @ 13.5V I_I N(L) @ 18V Input_pin_high_voltage.vsd 0,5 1,5 -40 0 40 80 120 160 Junction Temp (°C) V_INH(H) (V)

Data Sheet 49 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA Characterization Results

9.5.3 Input Voltage Hysteresis

P_8.4.3 Figure 51 Input Voltage Hysteresis VIN(HYS) = f(TJ;VS)

9.5.4 Input Current High Level

P_8.4.5 Figure 52 Input Current High Level IIN(H) = f(TJ;VS) 100 200 300 400 -40 0 40 80 120 160 Junction Temp (°C) V_IN(HYS) (mV) V_I N (H YS) @ 8V V_I N (H YS) 13.5V V_I N (H YS) @ 18V Input_pin_voltage_hysteresis.vsd -40 0 40 80 120 160 Junction Temp (°C) I_INH(H) (µA) Input_pin_high_current.vsd

Application Information

Data Sheet 50 Rev. 2.1, 2011-09-01 PROFET™+ 12V Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 53 Application Diagram with BTS5180-2EKA Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Table 11 Bill of Material Reference Value Purpose RIN 4.7 kΩ Protection of the micro controller during overvoltage, reverse polarity Guarantee BTS5180-2EKA channels OFF during loss of ground RDEN 4.7 kΩ Protection of the micro controller during overvoltage, reverse polarity Guarantee BTS5180-2EKA channels OFF during loss of ground RPD 47 kΩ Polarization of the output Improve BTS5180-2EKA immunity to electromagnetic noise RDSEL 4.7 kΩ Protection of the micro controller during overvoltage, reverse polarity Guarantee BTS5180-2EKA channels OFF during loss of ground RIS 1.2 kΩ Sense resistor OUT OUT OUT OUT A/D Vss Vdd Micro controller IN0 IN1 DEN DSEL IS GND OUT0 OUT1 Vs VBAT CSENSE Application example.svg R/L cable R/L cable R/L cable COUT1 COUT0 RIN RIN RDEN RDSEL RA/D RSENSE RIS RGND VDD RPD RPD CVS ROL D

Data Sheet 51 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA

10.1 Further Application Information

• Please contact us to get the pin FMEA
• Existing App. Notes
• For further information you may visit http://www.infineon.com/profet RSENSE 4.7 kΩ Overvoltage, reverse polarity, loss of ground. Value to be tuned with micro controller specification. ROL 1.5 kΩ Ensure polarization of the BTS5180-2EKA output during open load in OFF diagnostic RA/D 4.7 kΩ Protection of the micro controller during overvoltage, reverse polarity D BAS21 Protection of the BTS518 0-2EKA during reverse polarity RGND 1 kΩ To keep the device GND at a stable potential during clamping Z1 7 V Zener diode Protection of the micro controller during overvoltage Z2 36 V Zener diode Protection of the device during overvoltage T1 BC 807 Switch the battery voltage for open load in OFF diagnostic CSENSE 100 pF Sense signal filtering CVS 100 nF Filtering of the voltage spikes on the battery line COUT0 4.7 nF Protection of the BTS5 180-2EKA during ESD and BCI COUT1 4.7 nF Protection of the BTS5 180-2EKA during ESD and BCI Table 11 Bill of Material (cont’d) Reference Value Purpose

Data Sheet 52 Rev. 2.1, 2011-09-01 PROFET™+ 12V Figure 54 PG-DSO-14-40 EP (Plastic Dual Small Outline Package) (RoHS-Compliant) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Gree n products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). GPS01207 0.2-0.1 8˚ MAX. 0˚...8˚1.27 0.41±0.09 2) A-B0.2 M C 14xD Seating Plane (1.47) 1.7 MAX. Stand Off C C0.08 -0.10.1+0 8˚ MAX. 0˚...8˚ 0.35 x 45˚ 3.9±0.11)

0.1 DC2 x

±0.250.64 6D D ±0.2 0.2 M +0.06 0.19 8˚ MAX. A 814 B C0.1 A-B 2x ±0.18.65 Index Marking 6.4 Bottom View ±0.1 ±0.12.65 14 8 2) Does not include dambar protrusion of 0.13 max. 1) Does not include plastic or metal protrusion of 0.15 max. per side 3) JEDEC reference MS-012 variation BB

Data Sheet 53 Rev. 2.1, 2011-09-01 PROFET™+ 12V BTS5180-2EKA

Revision History

Version Date Parameter Changes 2.0 2010-05-31 Creation of the Data Sheet 2.1 2011-09-01 P_7.5.8 P_7.5.9 P_7.5.10 P_7.5.11 P_7.5.12 P_7.5.17 Updated kilis specification and Figure 22 accordingly change from 550 +/-50% to 570 +/-35%, change from 550 +/-34% to 560 +/-21%, change from 550 +/-13% to 560 +/-9%, change from 550 +/-9% to 560 +/-7.5%, change from 8% to 6% change from 8% to 5% Updated characterisation results; Graphs in chapter 9.3. switched the 18V and 8V graph in “Figure 33) Standby Current for Whole Device with Load. IS(OFF) = f(TJ;VS)” P_4.1.4 specified as max value; adap ted the footnote; updated the Legal Disclaimer

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© 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Legal Disclaimer for short-circuit capability Infineon disclaims any warranties and liabilities, whether expressed nor implied, for any short-circuit failures below the threshold limit. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.