BTN9960LV

BTN9960LV INFINEON | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 31

Technical content

Features

AEC-Q100/Q006 qualified (Grade 1)
Supply voltage range 8 V - 18 V (max up to 40 V)
Path resistance of typ. 9.7 m Ω @ 25°C (max. 18.1 mΩ @ 150°C)
Low quiescent current of max. 3.3 µA @ 85°C
Protection features: overcurrent, undervoltage, overtemperature
Overcurrent detection level of 35 A min
Eight selectable switching slew rates for optimized EME
Status flag diagnosis with feedback of current sense, temperature and slew rate Potential applications
Automotive 12 V brushed DC Motor
Fuel, washer pump Product validation Qualified for automotive applications. Product validation according to AEC-Q100.

Description

The BTN9960LV is an integrated high current half-bridge for motor drive applications. It is part of the MOTIX™ single half-bridge product family containing one p-channel high-side MOSFET and one n-channel low-side MOSFET with an integrated driver IC in one package. Due to the p-channel high-side switch the need for a charge pump is eliminated thus minimizing EME. Interfacing to a microcontroller is made easy by the integrated driver IC which features logic level inputs, diagnosis with current sense, slew rate adjustment, dead time generation and protection against overtemperature, undervoltage, overcurrent and short circuit. The BTN9960LV provides a cost optimized solution for protected high current PWM motor drives with very low board space consumption. M Micro- controller V B A T Reverse polarity protection C 10 100 nF C DC-Link ~1000 µF R 3 10 kΩ D Z1 10 V R 1 1 kΩ R IS 2 kΩ OUT OUT IN ADC C O2V * C 1 100 nF C OUT * C IS INH IN IS VS OUT GND BTN9960LV R 2 1 kΩ *) C O2V , C OUT optional C 11 10 m F V S to optimize EMC Figure 1 Typical application Type Package Marking BTN9960LV PG-HSOF-7-1 (sTOLL) BTN9960 Datasheet Please read the sections "Important notice" and "Warnings" at the end of this document Rev. 1.00 www.infineon.com 2023-03-01

Datasheet 2 Rev. 1.00 2023-03-01

1 Block diagram

The BTN9960LV contains three separate chips in one package: one p-channel high-side MOSFET and one n-channel low-side MOSFET together with a driver IC, forming an integrated high current half-bridge. All three chips are mounted on a common lead frame, using the chip-on-chip and chip-by-chip technology. The power switches utilize vertical MOS technologies to ensure optimum ON-state resistance. Due to the p-channel high- side switch the need for a charge pump is eliminated thus minimizing EME. Interfacing to a microcontroller is made easy by the integrated driver IC which features logic level inputs, diagnosis with current sense, slew rate adjustment, dead time generation and protection against overtemperature, overcurrent, undervoltage and short circuit. The BTN9960LV can be combined with other BTN9960LVs to form an H-bridge or a 3-phase drive configuration. OUT VS VReg Gate driver Offset Fault SR / T CC Overcurrent detection Power on reset IS INH IN GND Cross current protection Gate driver Temperature sensor UV Latch Slew rate generator Current sense Overcurrent detection Logic Figure 2 Block diagram Following figure shows the terms used in this datasheet. BTN9960LV Datasheet Datasheet 3 Rev. 1.00 2023-03-01

VOUT, VDS(LS) VDS(HS) IVS GND IGND IN INH IOUT, IL VSIS IIS , -ID(HS) , -ID(LS) Figure 3 Terms BTN9960LV Datasheet Datasheet 4 Rev. 1.00 2023-03-01

2 Pin configuration

Figure 4 Pin assignment BTN9960LV (top view) Table 1 Pin definitions and functions Pin Symbol I/O Function 1,2 GND – Ground (1)

3 IN I Input

Defines whether high- or low-side switch is activated. An internal pull down resistor is connected to this pin.

4 INH I Inhibit

When set to low device goes in tristate. An internal pull down resistor is connected to this pin.

5 IS O Current sense, temperature sense, slew rate level and diagnostics

6,7 VS – Supply (1) 8 (EP) OUT O Power output of the bridge 1) All terminal pins must be connected together on the PCB. All terminal pins are internally connected together. PCB traces have to be designed to withstand the maximum current which can flow Bold type: pin needs power wiring BTN9960LV Datasheet Datasheet 5 Rev. 1.00 2023-03-01

3 General product characteristics

The device is intended to be used in an automotive environment. The circumstances, how the device environment must look like, are described in this chapter.

3.1 Absolute maximum ratings

Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2 Absolute Maximum Ratings Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Voltages Supply voltage VS -0.3 – 40 V – Drain-source voltage high- side VDS(HS) -40 – – V Tj ≥ 25°C Drain-source voltage high- side VDS(HS) -38 – – V Tj < 25°C Drain-source voltage low-side VDS(LS) – – 40 V Tj ≥ 25°C Drain-source voltage low-side VDS(LS) – – 38 V Tj < 25°C Logic input voltage VIN VINH -0.3 – 5.5 V – Voltage between VS and IS pin VSIS -0.3 – 40 V – Voltage at IS pin VIS -0.3 – 40 V – Currents HS drain current |ID(HS)| – – IOCH0 A Switch active 2) LS drain current |ID(LS)| – – IOCL0 A Switch active 2) Temperatures Junction temperature Tj -40 – 150 °C – Storage temperature Tstg -55 – 150 °C – ESD susceptibility ESD robustness all pins (HBM) |VESD(HBM,local)| – – 2 kV HBM 3) ESD robustness OUT vs GND vs VS (HBM) |VESD(HBM,global)| – – 6 kV HBM 3) ESD robustness all pins (CDM) |VESD(CDM)| – – 500 TC CDM 4) ESD robustness corner pins (CDM) (pins VS, GND, OUT) |VESD(CDM,corner)| – – 750 TC CDM 4) 1) Not subject to production test, specified by design. 2) Maximum applicable single pulse current depends on tpulse. See figure maximum single pulse current. 3) Human body model “HBM” robustness: class 2 according to AEC-Q100-002. BTN9960LV Datasheet Datasheet 6 Rev. 1.00 2023-03-01

4) Charged device model “CDM” robustness: class C2a according to AEC-Q100-011 Rev D. “TC” corresponds to “test condition” according to AEC-Q100-011. Latchup Robustness: class II according to AEC-Q100-04 Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.

3.2 Functional range

The parameters of the functional range are listed in the following table: Table 3 Functional range Parameter Symbol Values Unit Note or condition Min. Typ. Max. Supply voltage range for normal operation VS(nor) 8 – 18 V 1) Extended supply voltage range for operation VS(ext) 4.5 – 40 V Falling VS(ext) Parameter deviation possible 1) Junction temperature Tj -40 – 150 °C 1) 1) Not subject to production test, specified by design.

3.3 Thermal resistance

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to https://www.jedec.org/ Table 4 Thermal resistance Parameter Symbol Values Unit Note or condition Min. Typ. Max. Thermal resistance junction- case, high-side switch Rthjc (HS) = ΔTj(HS)/Pv(HS) RthJC(HS) – 0.5 0.7 K/W 1) Thermal resistance junction- case, low-side switch Rthjc(LS) = ΔTj(LS)/Pv(LS) RthJC(LS) – 0.8 1.1 K/W 1) Thermal resistance junction- ambient RthJA – 19 – K/W 1) 2) 1) Not subject to production test, specified by design. 2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The device (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. BTN9960LV Datasheet Datasheet 7 Rev. 1.00 2023-03-01

Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the electrical characteristics table. BTN9960LV Datasheet Datasheet 8 Rev. 1.00 2023-03-01

4 Block description and characteristics

4.1 Supply characteristics

Table 5 Supply characteristics VS = 8 V to 18 V, Tj = -40°C to 150°C, IL = 0 A, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. General Supply current IVS(on) – 2.3 4.5 mA VINH = 5 V VIN = 0 V or 5 V normal operation DC-mode (no fault condition) according to Table 12 Supply current in SR selection mode IVS(on_SR) – 2.0 3.2 mA VINH = 0 V VIN = 5 V SR selection mode IVS(on_SR) = IVS – IIS (no fault condition) Quiescent current Tj = 150°C IVS(off)_150C – – 75 µA VINH = VIN = 0 V Tj = 150°C Quiescent current at Tj ≤ 85°C IVS(off)_85C – – 5 µA VINH = VIN = 0 V Tj ≤ 85°C 1) Quiescent current Tj ≤ 85°C and VS = 13.5 V IVS(off)_85C_13.5V – – 3.3 µA VINH = VIN = 0 V VS = 13.5 V Tj ≤ 85°C 1) 1) Not subject to production test, specified by design. BTN9960LV Datasheet Datasheet 9 Rev. 1.00 2023-03-01

0 0,2 0,4 0,6 0,8 1 -40 -20 0 20 40 60 80 100 120 140 160 Tj [°C] IVS(off) [µA] VS = 8 V VS = 14 V VS = 18 V Quiescent current IVS(OFF) [µA] Low level voltage IN, INH [V] TJ = -40°C TJ = 25°C TJ = 150°C Typical quiescent current IVS(OFF) vs. junction temperature TJ Typical quiescent current IVS(OFF) vs. Low level voltage IN,INH Figure 5 Typical quiescent current IVS(OFF) characteristics

4.2 Power stages

The power stages of the BTN9960LV consist of a p-channel vertical DMOS transistor for the high-side switch and a n-channel vertical DMOS transistor for the low-side switch. All protection and diagnostic functions are located in a separate driver IC. Both switches allow active freewheeling and thus minimizing power dissipation during PWM control. The ON-state resistance RON is dependent on the supply voltage VS as well as on the junction temperature Tj. The typical ON-state resistance characteristics are shown in Figure 6. 8 9 10 11 12 13 14 15 16 17 18 8 9 10 11 12 13 14 15 16 17 18 TJ = 150°C TJ = 25°C TJ = -40°C TJ = 150°C TJ = 25°C TJ = -40°C Supply voltage VS [V] Supply voltage VS [V] RON(LS) [mW] RON(HS) [mW] Low-side switch High-side switch Typical ON-state resistance vs. supply voltage VSFigure 6 BTN9960LV Datasheet Datasheet 10 Rev. 1.00 2023-03-01

4.2.1 Electrical characteristics – power stages – static

Table 6 Electrical characteristics – power stages – static VS = 8 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. High-side switch – static characteristics ON-state high-side resistance RON(HS) – 6.3 – mΩ IOUT = 15 A; VS = 13.5 V Tj = 25°C 1) ON-state high-side resistance RON(HS) – 9.0 11.8 mΩ IOUT = 15 A; VS = 13.5 V Tj = 150°C ON-state high-side resistance RON(HS) – 9.5 – mΩ IOUT = 15 A; VS = 6 V Tj = 25°C 1) ON-state high-side resistance RON(HS) – 13.5 16.7 mΩ IOUT = 15 A; VS = 6 V Tj = 150°C Leakage current high-side IL(LKHS) – – 1 µA VINH = VIN = 0 V; VOUT = 0 V Tj ≤ 85°C 1) Leakage current high-side IL(LKHS) – – 60 µA VINH = VIN = 0 V; VOUT = 0 V Tj = 150°C Reverse diode forward‑voltage high-side VDS(HS) – 0.9 – V IOUT = -15 A Tj = -40°C 1) 2) Reverse diode forward‑voltage high-side VDS(HS) – 0.85 – V IOUT = -15 A Tj = 25°C 1) 2) Reverse diode forward‑voltage high-side VDS(HS) – 0.7 0.9 V IOUT = -15 A Tj = 150°C 2) Low-side switch – static characteristics ON-state low-side resistance RON(LS) – 3.4 – mΩ IOUT = -15 A; VS = 13.5 V Tj = 25°C 1) ON-state low-side resistance RON(LS) – 5.7 6.3 mΩ IOUT = -15 A; VS = 13.5 V Tj = 150°C ON-state low-side resistance RON(LS) – 5.1 – mΩ IOUT = -15 A; VS = 6 V Tj = 25°C 1) ON-state low-side resistance RON(LS) – 8.6 10.2 mΩ IOUT = -15 A; VS = 6 V Tj = 150°C Leakage current low-side IL(LKLS) – – 1 µA VINH = VIN = 0 V; VOUT = VS Tj ≤ 85°C 1) Leakage current low-side IL(LKLS) – – 30 µA VINH = VIN = 0 V; VOUT = VS Tj = 150°C (table continues...) BTN9960LV Datasheet Datasheet 11 Rev. 1.00 2023-03-01

Table 6 (continued) Electrical characteristics – power stages – static VS = 8 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Reverse diode forward‑voltage low-side -VDS(LS) – 0.9 – V IOUT = 15 A Tj = -40°C 1) 2) Reverse diode forward‑voltage low-side -VDS(LS) – 0.8 – V IOUT = 15 A Tj = 25°C 1) 2) Reverse diode forward‑voltage low-side -VDS(LS) – 0.6 0.8 V IOUT = 15 A Tj = 150°C 2) 1) Not subject to production test, specified by design. 2) Due to active freewheeling, diode is conducting only for a few µs, depending on the selected slew rate SRx.

4.2.2 Switching times

V OUT t t  V OUT t dr(HS) t r(HS) t df(HS) t f(HS)  V OUT 20% 20% 80%80% Figure 7 Definition of switching times high-side ( Rload to GND) BTN9960LV Datasheet Datasheet 12 Rev. 1.00 2023-03-01

V OUT t t  V OUT t df(LS) t f(LS)  V OUT t dr(LS) t r(LS) 20% 20% 80% 80% Figure 8 Definition of switching times low-side ( Rload to VS) Due to the timing differences for the rising and the falling edge there will be a slight difference between the length of the input pulse and the length of the output pulse. It can be calculated using the following formulas for ΔtxS = tIN – tOUT:

ΔtHS = (tdr(HS) + 0.5 tr(HS)) - (tdf(HS) + 0.5 tf(HS))
ΔtLS = (tdf(LS) + 0.5 tf(LS)) - (tdr(LS) + 0.5 tr(LS)) One of 8 different slew rates (SR) can be selected as described in Chapter 4.4.2. After waking up from stand-by mode, the slew rate level SR0 is selected.

4.2.2.1 Electrical characteristics – power stages – dynamic

Table 7 Electrical characteristics – power stages – dynamic Paragraph condition: VS = 13.5 V, Tj = -40°C to 150°C, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse, IOUT > 90 mA freewheeling, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. High-side switch – dynamic characteristics Rise-time of HS for SR0 tr(HS),SR0 0.05 0.25 0.55 µs SR-level = SR0 Rise-time of HS for SR1 tr(HS),SR1 – 0.36 – µs SR-level = SR1 Rise-time of HS for SR2 tr(HS),SR2 – 0.5 – µs SR-level = SR2 Rise-time of HS for SR3 tr(HS),SR3 – 0.83 – µs SR-level = SR3 Rise-time of HS for SR4 tr(HS),SR4 – 1.0 – µs SR-level = SR4 Rise-time of HS for SR5 tr(HS),SR5 0.22 1.25 5.00 µs SR-level = SR5 Rise-time of HS for SR6 tr(HS),SR6 – 2.5 – µs SR-level = SR6 Rise-time of HS for SR7 tr(HS),SR7 – 5.0 – µs SR-level = SR7 Switch-ON delay time HS for SR0 tdr(HS),SR0 2.4 3.6 4.4 µs SR-level = SR0 Switch-ON delay time HS for SR1 tdr(HS),SR1 – 4.1 – µs SR-level = SR1 (table continues...) BTN9960LV Datasheet Datasheet 13 Rev. 1.00 2023-03-01

Table 7 (continued) Electrical characteristics – power stages – dynamic Paragraph condition: VS = 13.5 V, Tj = -40°C to 150°C, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse, IOUT > 90 mA freewheeling, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Switch-ON delay time HS for SR2 tdr(HS),SR2 – 4.6 – µs SR-level = SR2 Switch-ON delay time HS for SR3 tdr(HS),SR3 – 5.9 – µs SR-level = SR3 Switch-ON delay time HS for SR4 tdr(HS),SR4 – 6.8 – µs SR-level = SR4 Switch-ON delay time HS for SR5 tdr(HS),SR5 4.6 8 11.2 µs SR-level = SR5 Switch-ON delay time HS for SR6 tdr(HS),SR6 – 13.2 – µs SR-level = SR6 Switch-ON delay time HS for SR7 tdr(HS),SR7 – 23.3 – µs SR-level = SR7 Fall-time of HS for SR0 tf(HS),SR0 0.05 0.25 0.55 µs SR-level = SR0 Fall-time of HS for SR1 tf(HS),SR1 – 0.36 – µs SR-level = SR1 Fall-time of HS for SR2 tf(HS),SR2 – 0.5 – µs SR-level = SR2 Fall-time of HS for SR3 tf(HS),SR3 – 0.83 – µs SR-level = SR3 Fall-time of HS for SR4 tf(HS),SR4 – 1.0 – µs SR-level = SR4 Fall-time of HS for SR5 tf(HS),SR5 0.22 1.25 5.00 µs SR-level = SR5 Fall-time of HS for SR6 tf(HS),SR6 – 2.5 – µs SR-level = SR6 Fall-time of HS for SR7 tf(HS),SR7 – 5.0 – µs SR-level = SR7 Switch-OFF delay time HS for SR0 tdf(HS),SR0 1.8 2.5 4.2 µs SR-level = SR0 Switch-OFF delay time HS for SR1 tdf(HS),SR1 – 2.8 – µs SR-level = SR1 Switch-OFF delay time HS for SR2 tdf(HS),SR2 – 3.1 – µs SR-level = SR2 Switch-OFF delay time HS for SR3 tdf(HS),SR3 – 3.9 – µs SR-level = SR3 Switch-OFF delay time HS for SR4 tdf(HS),SR4 – 4.4 – µs SR-level = SR4 Switch-OFF delay time HS for SR5 tdf(HS),SR5 3.4 5.0 9.0 µs SR-level = SR5 Switch-OFF delay time HS for SR6 tdf(HS),SR6 – 8.1 – µs SR-level = SR6 (table continues...) BTN9960LV Datasheet Datasheet 14 Rev. 1.00 2023-03-01

Table 7 (continued) Electrical characteristics – power stages – dynamic Paragraph condition: VS = 13.5 V, Tj = -40°C to 150°C, Rload = 2 Ω, 30 µH < Lload < 40 µH (in series to Rload), single pulse, IOUT > 90 mA freewheeling, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Switch-OFF delay time HS for SR7 tdf(HS),SR7 – 14.0 – µs SR-level = SR7 Low-side switch – dynamic characteristics Rise-time of LS for SR0 tr(LS),SR0 0.05 0.25 0.55 µs SR-level = SR0 Rise-time of LS for SR1 tr(LS),SR1 – 0.36 – µs SR-level = SR1 Rise-time of LS for SR2 tr(LS),SR2 – 0.5 – µs SR-level = SR2 Rise-time of LS for SR3 tr(LS),SR3 – 0.83 – µs SR-level = SR3 Rise-time of LS for SR4 tr(LS),SR4 – 1.0 – µs SR-level = SR4 Rise-time of LS for SR5 tr(LS),SR5 0.22 1.25 5.00 µs SR-level = SR5 Rise-time of LS for SR6 tr(LS),SR6 – 2.5 – µs SR-level = SR6 Rise-time of LS for SR7 tr(LS),SR7 – 5.0 – µs SR-level = SR7 Switch-ON delay time LS for SR0 tdf(LS),SR0 2.6 3.6 5.4 µs SR-level = SR0 Switch-ON delay time LS for SR1 tdf(LS),SR1 – 4.1 – µs SR-level = SR1 Switch-ON delay time LS for SR2 tdf(LS),SR2 – 4.6 – µs SR-level = SR2 Switch-ON delay time LS for SR3 tdf(LS),SR3 – 5.9 – µs SR-level = SR3 Switch-ON delay time LS for SR4 tdf(LS),SR4 – 6.8 – µs SR-level = SR4 Switch-ON delay time LS for SR5 tdf(LS),SR5 6.4 8.0 12.7 µs SR-level = SR5 Switch-ON delay time LS for SR6 tdf(LS),SR6 – 13.2 – µs SR-level = SR6 Switch-ON delay time LS for SR7 tdf(LS),SR7 – 23.3 – µs SR-level = SR7 Fall-time of LS for SR0 tf(LS),SR0 0.05 0.25 0.55 µs SR-level = SR0 Fall-time of LS for SR1 tf(LS),SR1 – 0.36 – µs SR-level = SR1 Fall-time of LS for SR2 tf(LS),SR2 – 0.5 – µs SR-level = SR2 Fall-time of LS for SR3 tf(LS),SR3 – 0.83 – µs SR-level = SR3 Fall-time of LS for SR4 tf(LS),SR4 – 1.0 – µs SR-level = SR4 Fall-time of LS for SR5 tf(LS),SR5 0.22 1.25 5.00 µs SR-level = SR5 (table continues...) BTN9960LV Datasheet Datasheet 15 Rev. 1.00 2023-03-01

4.3 Protection functions

The device provides integrated protection functions. These are designed to prevent IC destruction under fault conditions described in the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed to be used for continuous or repetitive operation, with the exception of Undervoltage, overtemperature and overcurrent events are indicated by a fault current IIS(fault) at the IS pin as described in Chapter 4.4.3. The protection functions of the BTN9960LV are prioritized in the following way: Table 8 Protection functions priorities Priority Function Reference 0 (highest) Undervoltage shutdown Chapter 4.3.1 1 Overtemperature protection Chapter 4.3.2 2 Overcurrent protection Chapter 4.3.3

3 Stand-by mode The device only goes into stand-by mode if no fault is present

Datasheet 16 Rev. 1.00 2023-03-01

4.3.1 Undervoltage shutdown with restart

To avoid uncontrolled motion of the driven motor at low voltages the device switches off (output is tri-state), if the supply voltage drops below the switch-OFF voltage VUV(OFF). If a slew rate level SR0 to SR4 is selected, the device will switch off with the selected slew rate in case of an undervoltage detection. For slew rate level SR5 to SR7, the device will switch off with slew rate level SR4 instead. As soon as the supply voltage VS rises above the switch-ON voltage VUV(ON), with a hysteresis of VUV(HY), the output channel of the device follows the IN pin again. The restart is delayed with a time tUVD which protects the device in case the undervoltage condition is caused by a short circuit event (according to AEC-Q100-012). After power-up, the device is starting without waiting for the delay time tUVD. The slew rate level and the undervoltage event are stored in analog latches, which are supplied by the INH or/and IN pin. Thus at least one of the two pins always shall be set high during this undervoltage event, until the presence of the IIS(fault) current, to keep the previously set slew rate level after the undervoltage shutdown. In the case of both INH and IN being 0 during an undervoltage event, a power on reset is performed. In case of an undervoltage event, the fault current IIS(fault) is provided at the IS pin, once the supply voltage rises above VUV(ON) again. The fault signal at the IS pin is reset after tUVD after the supply voltage rises above VUV(ON). This behavior is shown in Figure 9. I IS(fault) t V UV(ON) V UV(OFF) V UV(HY) t V OUT V S INH t IN t t I IS t UVD Current sense (CS)CSCS Figure 9 Timing diagram for undervoltage behavior for load to GND

4.3.2 Overtemperature protection

The device is protected against overtemperature by an integrated temperature sensor. Overtemperature leads to a shutdown of the output stage (both the high-side and low-side switch). This state is latched until the device is reset by a low signal with a minimum length of treset at the INH and IN pin, provided that its temperature has decreased at least the thermal hysteresis ΔT in the meantime. BTN9960LV Datasheet Datasheet 17 Rev. 1.00 2023-03-01

If a slew rate level SR0 to SR4 is selected, the device will switch off with the selected slew rate in case of overtemperature. For slew rate level SR5 to SR7, the device will switch off with slew rate level SR4 instead.

4.3.3 Overcurrent protection

The current in the bridge is measured in both switches. As soon as the current in forward direction in one switch (high-side or low-side) is reaching the limit IOCx, the device goes either into current limitation mode or switches off with latch, depending on the selected SR-level. The corresponding dependencies are described in Table 9. Table 9 Slew rate dependent overcurrent strategies SR-level Mode Note SR0 Current limitation (retry) For details see Chapter 4.3.3.1 SR1 SR2 SR3 SR4 SR5 Switch-OFF with latch Requiring reset of the fault latch For details see Chapter 4.3.3.2SR6 SR7

4.3.3.1 Current limitation

If this mode is selected according to Table 9 and the current in forward direction in one switch (high-side or low-side) has reached the limit IOCx, the affected switch is deactivated and the other switch is activated for tCLS. During that time all changes at the IN pin are ignored. However, during current limitation, the INH pin can still be used to switch both MOSFETs off. After tCLS the switches follow the IN pin again. The fault signal at the IS pin is reset after 1.5 * tCLS. This behavior is shown in Figure 10. t t I IS I OCx0 I L t CLS 1.5 × t CLS I IS(fault) I OCx Figure 10 Timing diagram current limitation (inductive load) For this mode, the MOSFETs are switched off each with the same slew rates (SR-level) as in normal operation. BTN9960LV Datasheet Datasheet 18 Rev. 1.00 2023-03-01

In combination with a typical inductive load, such as a motor, this results in a switched mode current limitation. This method of limiting the current has the advantage of greatly reduced power dissipation in the BTN9960LV compared to driving the MOSFET in linear mode. Therefore it is possible to use the current limitation for a short time without exceeding the maximum allowed junction temperature (e.g. for limiting the inrush current during motor start up). However, the regular use of the current limitation is allowed as long as the specified maximum junction temperature is not exceeded. Exceeding this temperature can reduce the lifetime of the device.

4.3.3.2 Switch-OFF with latch

If this mode is selected according to Table 9 and as soon as the current in forward direction in one switch (high-side or low-side) has reached the limit IOCx, both output stages are shut down. This state is latched until the device is reset by a low signal with a minimum length of treset at the INH and IN pin. This behavior is illustrated in Figure 11. In order to minimize power dissipation, the MOSFETs are switched off each with the same slew rate level SR4. IOCx t IL t reset INH IN t t IOCx0 t OCx(filter) IIS OC fault (latched) IIS(fault) Figure 11 Timing diagram switch-OFF with latch (inductive load)

4.3.4 Short circuit protection

The device provides embedded protection functions against

Output short circuit to ground
Output short circuit to supply voltage
Short circuit of load The short circuit protection is realized by the previously described undervoltage and overcurrent protection in combination with the overtemperature shutdown of the device.

4.3.5 Electrical characteristics – protection functions

Table 10 Electrical characteristics – protection functions VS = 8 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Undervoltage shutdown Switch-ON voltage VUV(ON) – – 5.5 V VS increasing (table continues...) BTN9960LV Datasheet Datasheet 19 Rev. 1.00 2023-03-01

Table 10 (continued) Electrical characteristics – protection functions VS = 8 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Switch-OFF voltage VUV(OFF) 3.8 – 4.5 V VS decreasing ON/OFF hysteresis VUV(HY) – 0.8 – V 1) Overcurrent shutdown Overcurrent detection level high-side IOCH0 35 47 60 A VS = 13.5 V Overcurrent detection level low-side IOCL0 35 47 60 A VS = 13.5 V Thermal shutdown Thermal shutdown junction temperature TjSD 155 175 200 °C 1) Thermal switch-ON junction temperature TjSO 150 – 190 °C 1) Thermal hysteresis ΔT – 7 – K 1) Protection and reset timing Shut-OFF time for HS and LS tCLS – 115 210 µs – Undervoltage recovery delay time tUVD – 115 210 µs – Reset pulse at INH and IN pin (INH & IN low) treset 9 – – µs – 1) Not subject to production test, specified by design.

4.4 Control and diagnostics

The control inputs IN and INH consist of TTL/CMOS compatible Schmitt triggers with hysteresis which control the integrated gate drivers for the MOSFETs. Setting the INH or/and IN pin to high enables the device. When the INH pin is high, one of the two power switches is switched on depending on the status of the IN pin. To deactivate both switches, the INH pin has to be set to low. No external driver is needed. The BTN9960LV can be interfaced directly to a microcontroller, as long as the maximum ratings in Chapter 3.1 are not exceeded.

4.4.1 Dead time generation

In bridge applications it has to be assured that the high-side and low-side MOSFET are not conducting at the same time, connecting directly the battery voltage to GND. This is assured by a circuit in the driver IC, generating a so called dead time between switching off one MOSFET and switching on the other. The dead time generated in the driver IC is dependent on the selected slew rate.

4.4.2 Adjustable slew rate

In order to optimize electromagnetic emission, one of 8 different switching speeds for the MOSFETs can be selected. This selectability allows the user to optimize the balance between emission and power dissipation within his own application. The slew rate adjustment function is only accessible, if no fault is present. BTN9960LV Datasheet Datasheet 20 Rev. 1.00 2023-03-01

In case the device was in stand-by mode previously, the function is available after the device wake-up time twakeup. Therefore the first pulse at pin IN needs to exceed the wake-up time twakeup. When INH = low and IN = high without a fault being present, the device is in SR selection mode with both high-side and low-side MOSFETs being switched off. When the SR selection mode initially is entered, a temperature information is provided as described in Chapter 4.4.3.2 at the IS pin independently from the selected SR-level. Only when IN goes low (falling edge) for a duration of tSR, the next mode is selected when IN rises again. During this transition pulse, the INH pin has to be low permanently. In the next mode, the slew rate won’t be changed, but a current sense signal IIS(SRx) depending on the currently selected SR-level SRx (as further described in Chapter 4.4.3.2) is provided at the IS pin. This allows to validate if the desired SR-level has been selected. For any further transition pulse, the next SR-level will be selected. The newly selected SR-level then will be indicated at the IS pin with the corresponding IIS(SRx). After reaching SR-level SR7, the next selectable SR-level is SR0 again. This procedure is illustrated in Figure 12. The SR selection mode is left if a fault occurs or by setting INH to high. The procedure is shown in the state diagram in Figure 15. The states at pin IN and INH may not transition synchronous in the same direction, therefore a time delay of tlag need to be applied. After stand-by and power-up, the default value for the slew rate is level SR0. After an undervoltage event the selected slew rate level is persistent, under the conditions described in Chapter 4.3.1 with more details. In case an undervoltage event occurs during the slew rate selection mode, the slew rate configuration can not be guaranteed. Therefore slew rate programming need to be repeated once the undervoltage event has disappeared. IN t t IIS IIS(offset) t 0 0 1 7 0 INH tt SR t SR IIS(SR1) t SR IIS(SR2) t SR IIS(SR0) IIS(SR7) ... t SRM IIS(T) IIS(SR0) IIS(SR_step) t Lag Stand- By-Mode t wakeup IIS(CS) Normal operationSlew Rate Selection Mode IIS(SR_step) Figure 12 Slew rate level selection Note: t wakeup is only needed if the device was in stand-by-mode before.

4.4.3 Status flag diagnosis with current and temperature sense capability

The sense pin IS is used as a combined current sense, temperature sense, slew rate level feedback and fault flag output. Further details, in which state which signal is provided by the IS pin is described in Table 11. The IS pin has three different modes of operation:

4.4.3.1 Current sense

In normal operation (current sense mode), with the IN and INH pin being high (for further details see Table 11), a current source is connected to the IS pin, which delivers a current proportional to the forward load current flowing through the active high-side switch. The sense current can be calculated out of the load current by the following equation: IIS = IL / dkILIS + IIS(offset) BTN9960LV Datasheet Datasheet 21 Rev. 1.00 2023-03-01

The other way around, the load current can be calculated out of the sense current by following equation: IL = dkILIS · (IIS – IIS(offset)) The differential current sense ratio dkilis is defined by: dkILIS = (IL2 – IL1) / (IIS(IL2) – IIS(IL1)) If the high-side drain current is zero (ISD(HS) = 0 A) the offset current IIS = IIS(offset) still will be driven. The external resistor RIS determines the voltage per IS output current. The voltage can be calculated by VIS = RIS · IIS. I IS I L I IS(fault) I IS(fault),max I OCx0,maxI OCx0,min I IS(fault),min I IS(CS),max Current sense Figure 13 Sense current vs. load current

4.4.3.2 Temperature sense and slew rate feedback

In slew rate selection mode, with the IN pin being high and the INH being low after the first transition (further details see Chapter 4.4.2) the IS pin provides a constant current IIS(SRx), allowing to distinguish between the different SR-levels. The sense current IIS can be calculated as follows for the slew rate level SRx: IIS(SRx) = IIS(SR0) – x ⋅ IIS(SR_step) To correctly determine all eight slew rate levels, IIS(SR0) and each individual device's IIS(SR_step) have to be calibrated. When initially entering the SR selection mode, a current source is connected to the IS pin, which delivers a current proportional to the junction temperature of the control chip TCC, which is illustrated in Figure 14. The sense current IIS(T) can be calculated out of the junction temperature in Kelvin T[K] by the following equation: IIS(T) = kTIS · TCC Based on the temperature coefficient kTIS, the temperature TCC then calculates as follows: TCC = IIS(T) / kTIS BTN9960LV Datasheet Datasheet 22 Rev. 1.00 2023-03-01

Max. I IS(fault) Min. I IS(fault) dI IS(fault-IS) Highest k TIS value Lowest k TIS value Max. I IS(CS) 0 K k TIS Figure 14 Sense current vs. junction temperature in the initial state of the SR selection mode

4.4.3.3 Fault feedback

In case of a fault condition, according to the truth table (Table 11), the status output is connected to a current source which is independent of the load current and provides IIS(fault). The maximum voltage at the IS pin is determined by the choice of the external resistor and the supply voltage.

4.4.4 Truth table

Device state Inputs Outputs Mode INH IN HSS LSS IS Normal operation 0 0 OFF OFF IIS(offset) See note 2) Device enters stand-by mode after t > tstdby tri state – Device in stand-by mode 1 0 OFF ON IIS(offset) LSS active 1 1 ON OFF CS 3) HSS active Slew rate selection 0 1 OFF OFF IIS(SRx, T) IIS(offset) Slew rate selection mode During INH = IN = low pulse Overtemperature (OT) at HSS or LSS 1 X OFF OFF IIS(fault) Shutdown with latch, fault detected 4) X 1 OFF OFF IIS(fault) Current limitation (CL) mode at HSS or LSS 1 1 OFF ON IIS(fault) Switched mode, fault detected 5) 1 0 ON OFF IIS(fault) Overcurrent (OC) switch-OFF with latch at HSS or LSS

1 X OFF OFF IIS(fault) OC shutdown with latch, fault

detected 4) X 1 OFF OFF IIS(fault) (table continues...) BTN9960LV Datasheet Datasheet 23 Rev. 1.00 2023-03-01

Table 11 (continued) Truth table Undervoltage (UV), VS < VUV(OFF) 1 X OFF OFF * 1) Undervoltage shutdown, fault detected 6) X 1 OFF OFF 1) Sense current present ≤ IIS(offset). 2) The device only goes into stand-by mode if no fault is present. 3) Current sense - high-side (CS): IIS = IL / dkILIS + IIS(offset), for details see Chapter 4.4.3.1. 4) Requires the reset of the fault latch with INH = IN = low for treset to get back to normal operation. 6) When VS > VUV(ON) (rising), the device will return to normal operation after tUVD; Fault signal IIS(fault) is reset after tUVD (see Chapter 4.3.1). Table 12 Switches – states table Inputs Switches 0 = logic LOW OFF = switched off 1 = logic HIGH ON = switched on X = 0 or 1 Normal operation INH IN HSS LSS IS 1 0 OFF ON IIS(offset) 1 1 ON OFF CS Undervoltage INH IN HSS LSS IS

1 X OFF OFF *

Overtemperature & OC with latch INH IN HSS LSS IS

1 X OFF OFF IIS(fault)

SR selection mode – Temperature feedback INH IN HSS LSS IS Current limitation LS INH IN HSS LSS IS

1 X ON OFF IIS(fault)

SR selection mode – Change SR INH IN HSS LSS IS Current limitation HS INH IN HSS LSS IS

1 X OFF ON IIS(fault)0 1 OFF OFF IIS(SRx)

VS > VUV(ON) Unsupplied INH = IN = 0 X 1 OFF OFF * X 1 OFF OFF IIS(fault) after t = tCLS SR - level ≤ 4 & IVS > IOCH0 SR - level ≤ 4 & IGND > IOCL0 VS < VUV(OFF) (decreasing) INH = 1 after t ≥ t wakeup VS > VUV(ON) (increasing) Tj < TjSO & reset fault (IN & INH = 0 for treset ) IN = 1 after t ≥ t wakeup INH = 0 & IN = 1 INH = 1 IN = New SR - level: SR a à SR b INH = IN = 0 for t = tstdby INH = 1 All states (except Standby) VS < VUV(OFF) (decreasing) All states INH = IN = 0 for t ≥ tstdby

0 X OFF OFF IIS(fault)

X 1 OFF OFF IIS(fault) after t = tUVD VS < VUV(OFF) (decreasing) All states Tj > TjSD Tj > TjSD or SR - level > 4 & (IVS > IOCH0 or IGND > IOCL0 ) after t = tCLS SR selection mode – Current SR feedback INH IN HSS LSS IS 0 1 OFF OFF I IS(SRx) 0 1 OFF OFF IIS(T) INH = 1 New SR - level: SR a à SR b :transition pulse IN = IN = *: IIS IIS(offset) -: No output, high impedance Figure 15 Simplified state diagram BTN9960LV Datasheet Datasheet 24 Rev. 1.00 2023-03-01

4.4.5 Electrical characteristics – control and diagnostics

Table 13 Electrical characteristics – control and diagnostics VS = 8 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Control inputs (IN and INH) High level voltage INH, IN VINH(H) VIN(H) – 1.6 2.1 V – Low level voltage INH, IN VINH(L) VIN(L) 1.0 1.3 – V – Low level voltage INH, IN for VS < 8 V VINH(L)_UV(OFF) VIN(L)_UV(OFF) 0.4 – – V VS = 4.5 V, falling VS Input voltage hysteresis VINH(HYS) VIN(HYS) – 300 – mV 1) Input current high level IINH(H) IIN(H) 25 50 80 µA VIN = VINH = 5.5 V Input current low level IINH(L) IIN(L) 3 6 10 µA VIN = VINH = 1.0 V Slew rate selection Slew rate level selection pulse time tSR 0.5 – 80 µs See Figure 12 Slew rate selection mode settling time tSRM 1 – – µs See Figure 12 Wake-up time twakeup – – 5 µs After stand-by 1) Lag time between IN/INH state change tlag 0.5 – – µs 1) Time to enter stand-by mode tstdby 100 – 300 µs After both INH and IN transitioned from high to low Sense current for SR-level SR0 IIS(SR0) 1.8 2.15 2.5 mA SR-level = SR0 Current sense step between two SR-levels IIS(SR_step) 150 190 230 µA – Current sense Differential current sense ratio in static on-condition dkILIS = dIL/dIIS BTN9960 dkILIS 21.7 28.9 36.1 103 1 A ≤ IL < IOCH0 VS = 13.5 V RIS = 2 kΩ Sense current in fault condition IIS(fault) 2.51 2.75 3.25 mA VS = 13.5 V (table continues...) BTN9960LV Datasheet Datasheet 25 Rev. 1.00 2023-03-01

Table 13 (continued) Electrical characteristics – control and diagnostics VS = 8 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition Min. Typ. Max. Maximum analog sense current in normal operational condition IIS(CS) – – 2.5 mA VS = 13.5 V; in CS mode 1) Isense leakage current IISL – – 1 µA VINH = VIN = 0 V RIS = 2 kΩ Isense offset current IIS(offset) 30 300 600 µA VINH = 5 V VIN = 0 V or ISD(HS) = 0 A RIS = 2 kΩ Temperature sense at 25°C IIS(T)_25°C – 1.2 – mA IIS(T) Tj = 25°C RIS = 2 kΩ Temperature coefficient for temperature sense kTIS 3.16 3.72 4.28 µA/K 1) 1) Not subject to production test, specified by design. BTN9960LV Datasheet Datasheet 26 Rev. 1.00 2023-03-01

5 Application information

Note: The following information is given as a hint for the implementation of the device only and cannot be regarded as a description or warranty of a certain functionality, condition or quality of the device. M C 10 100 nF C 11 10 µFR 11 1 k Ω R 12 1 k Ω R 1IS 2 k Ω I/OI/O C 1O2V * C 1OUT * C 2O2V * C 2OUT * C 20 100 nF R 2IS 2 k Ω I/OA/D R 22 1 k Ω R 21 1 k Ω A/D V S Reverse polarity protection C 1 100 nF C 2ISC 1IS Microcontroller INH IN IS VS OUT GND BTN9960LV INH IN IS VS OUT GND BTN9960LV C DC_LINK ~1000 µF *) C 1O2V , C 1OUT , C 2O2V ,C 2OUT optional to otpimize EMC C 21 10 µF V BAT Figure 16 Application circuit: H-bridge with two BTN9960LV Note: This is a simplified example of an application circuit. The function must be verified in the real application. To stabilize the supply voltage VS in PWM operation or in over current limitation a sufficient dimensioned low ESR electrolytic capacitor CDC-Link is needed. It prevents destructive voltage peaks and drops. The supply voltage ripple at the device between VS pin and GND must be kept below 1 V peak-to-peak and the capacitors need to be sized accordingly. Therefore the ceramic capacitors C10/C11 respectively C20/C21 must be placed close to the device pins VS and GND. The traces should be kept as short as possible to minimize stray inductance. The value of the capacitors must be verified in the real application to ensure low ripple and transients at the VS pin. The digital inputs IN and INH need to be protected against over-currents (e.g. caused by induced voltage spikes) by a series resistor of typical 1 kΩ. M Micro- controller V B A T Reverse polarity protection C 10 100 nF C DC-Link ~1000 µF R 3 10 kΩ D Z1 10 V R 1 1 kΩ R IS 2 kΩ OUT OUT IN ADC C O2V * C 1 100 nF C OUT * C IS INH IN IS VS OUT GND BTN9960LV R 2 1 kΩ *) C O2V , C OUT optional to optimize EMC C 11 10 m F V S Figure 17 Application circuit: single half-bridge with load (motor) connected to GND Note: This is a simplified example of an application circuit. The function must be verified in the real application. The applicable PWM frequency for which the output signal at OUT pin tracks the control signal at IN pin depends on:

Desired duty cycle range of the output OUT (e.g. 20% to 80%)
Selected slew rate for the output OUT BTN9960LV Datasheet

Datasheet 27 Rev. 1.00 2023-03-01

Switch-ON and switch-OFF delay times of HS / LS switches ( tdr(HS), tdf(LS), tdf(HS), tdr(LS)), depending on slew rate
Rise-time and fall-time of HS / LS switch ( tr(HS), tf(LS), tf(HS), tr(LS)), depending on slew rate BTN9960LV Datasheet

Datasheet 28 Rev. 1.00 2023-03-01

6 Package

Figure 18 PG-HSOF-7 (sTOLL) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further package information, please visit our website: https://www.infineon.com/packages BTN9960LV Datasheet Datasheet 29 Rev. 1.00 2023-03-01

7 Revision history

1.0 2023-03-01 Initial release BTN9960LV Datasheet Datasheet 30 Rev. 1.00 2023-03-01

All referenced product or service names and trademarks are the property of their respective owners. Edition 2023-03-01 Published by Infineon Technologies AG

81726 Munich, Germany

© 2023 Infineon Technologies AG All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference IFX-whc1633080961359 Important notice The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Warnings Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.

Summary

MOTIX™ single half-bridge with integrated driver IC Rev. 1.00 2023-03-01

Description

MOTIX™ single half-bridge with integrated driver IC Rev. 1.00 2023-03-01

Source title BTN9960LV Datasheet(PDF) - Infineon Technologies AG

Read BTN9960LV online.

BTN9960LV INFINEON | Alldatasheet

Document overview

Technical content

Features

Description

1 Block diagram

2 Pin configuration

3 IN I Input

4 INH I Inhibit

5 IS O Current sense, temperature sense, slew rate level and diagnostics

3 General product characteristics

3.1 Absolute maximum ratings

3.2 Functional range

3.3 Thermal resistance

4 Block description and characteristics

4.1 Supply characteristics

4.2 Power stages

4.2.1 Electrical characteristics – power stages – static

4.2.2 Switching times

4.2.2.1 Electrical characteristics – power stages – dynamic

4.3 Protection functions

3 Stand-by mode The device only goes into stand-by mode if no fault is present

4.3.1 Undervoltage shutdown with restart

4.3.2 Overtemperature protection

4.3.3 Overcurrent protection

4.3.3.1 Current limitation

4.3.3.2 Switch-OFF with latch

4.3.4 Short circuit protection

4.3.5 Electrical characteristics – protection functions

4.4 Control and diagnostics

4.4.1 Dead time generation

4.4.2 Adjustable slew rate

4.4.3 Status flag diagnosis with current and temperature sense capability

4.4.3.1 Current sense

4.4.3.2 Temperature sense and slew rate feedback

4.4.3.3 Fault feedback

4.4.4 Truth table

1 X OFF OFF IIS(fault) OC shutdown with latch, fault

1 X OFF OFF *

1 X OFF OFF IIS(fault)

1 X ON OFF IIS(fault)

1 X OFF ON IIS(fault)0 1 OFF OFF IIS(SRx)

0 X OFF OFF IIS(fault)

4.4.5 Electrical characteristics – control and diagnostics

5 Application information

6 Package

7 Revision history

81726 Munich, Germany

BTN9960LV specifications and overview.

More parts from the same family.