BTM9011EP

BTM9010EP INFINEON | Alldatasheet

Document overview

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• PDF pages: 46

Technical content

Features

• Path resistance of typ. 175 m Ω at 25°C
• Pulse current: - 5.2 A for t pulse ≤ 1 s at 85°C - 4.2 A for t pulse ≤ 10 s at 85°C
• Supply voltage range from 7 V to 18 V
• Extended supply voltage range from 4.5 V to 40 V
• Current limitation of min. 10 A
• Slew rate selection
• Protection and diagnostics: overcurrent, undervoltage, overtemperature, open load detection, current sense, cross current protection
• Status flag diagnosis with feedback of current sense
• SPI interface in BTM9011EP
• Half-bridge mode
• Green product (RoHS compliant)
• ISO ready Potential applications
• Automotive unidirectional and bidirectional brushed DC motors
• Door modules
• Mirror modules
• Body control modules
• Other inductive or resistive loads in the automotive field Product validation
• Qualified for automotive applications
• Product validation according to AEC-Q100 Product description MOTIX™ BTM9010EP/BTM9011EP integrated full-bridge IC is an integrated full-bridge for automotive motor drive applications. This monolithic device is implemented in BCD technology, and assembled in PG-TSDSO-14 which has an exposed pad to ensure better thermal performance. The device provides intelligent protection features against overtemperature, undervoltage, overcurrent, short circuit and crosscurrent. Moreover, the device also provides current sense and open load diagnostic as diagnosis features. The information of the output current and the error flag is presented at IS pin. BTM9010EP/BTM9011EP Datasheet Datasheet Please read the sections "Important notice" and "Warnings" at the end of this document 1.0 www.infineon.com 2024-06-30

Protection and Diagnostics GND V S Pull down Pull down Power stageInternal Supply Charge pump Power supply MUX M OUT A OUTB μC BTM9010EP SDI1 BTM9011EP SCLK SDO1 CS SDI2 BTM9011EP SCLK SDO2 CS SDI3 BTM9011EP SCLK SDO3 μC SDISDI SDOSDO CSCS SCLKSCLK CS VDDIOVDDIO VDD_EXT Device 1 Device 2 Device 3 M M M Product type Package Marking BTM9010EP PG-TSDSO-14 BTM9010 BTM9011EP PG-TSDSO-14 BTM9011 BTM9010EP/BTM9011EP Datasheet Product description Datasheet 2 1.0 2024-06-30

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1 Device comparison

This table summarizes the differences between BTM9010EP and BTM9011EP . HW variant (BTM9010EP) SPI variant (BTM9011EP) Package PG-TSDSO-14 PG-TSDSO-14 Digital interface INA, INB, SEL, PWM SDI, SCLK, CS, SDO Path resistance 175 mΩ at 25°C 175 mΩ at 25°C Current limitation Min. 10 A Min. 10 A Overcurrent protection Error flag at IS pin; Latched Error flag at IS pin; OCx bit latched in the status byte; Dedicate bit for each half-bridge Slew rate selection 2 configurable slew rate levels:

• Selected via input sequence
• Read out at IS pin 2 configurable slew rate levels:
• Selected via SR bit in the control byte
• Read out the control byte at SDO pin Undervoltage shutdown No sense current flowing out from IS pin; No error flag; Unlatched No sense current flowing out from IS pin; No error flag; UV bit set but unlatched in the status byte Overtemperature protection Error flag at IS pin; Unlatched Error flag at IS pin; TSDx bit set but unlatched in the status byte; Dedicate bit for each half-bridge Open load detection Error flag at IS pin; Unlatched Error flag at IS pin; OL bit set but unlatched in the status byte Current sense Provided at IS pin Provided at IS pin Enter to standby mode All inputs (INA, INB, SEL and PWM) are set to Low EN bit is set to Low BTM9010EP/BTM9011EP Datasheet

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2 Block diagram

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3 Pin configuration

3.1 HW variant

1 OUTA

2 INA

3 GND

4 GND

5 GND

6 INB

7 OUTB 8 OUTB

9 PWM

10 SEL

14 OUTA

Figure 2 Pin configuration Table 1 Pin definitions and functions Pin Symbol Function 1, 14 OUTA Power output of the half-bridge A. All OUTA pins should be externally connected together.

2 INA Input control combine with INB and PWM, refer to operative condition table

3, 4, 5 GND Power ground. All ground pins should be externally connected together.

6 INB Input control combine with INA and PWM, refer to operative condition table

7, 8 OUTB Power output of the half-bridge B. All OUTB pins should be externally connected together.

9 PWM Input control combine with INA and PWM, refer to operative condition table

10 SEL Current sense selection pin

11, 12 VS Power supply. All VS pins should be externally connected together.

13 IS Current sense and error flag pin

EDP – Exposed die pad. For cooling and EMC purposes only. Not usable as electrical ground. Electrical ground must be provided by pins 3, 4 and 5. It is recommended to connect the EDP to ground. BTM9010EP/BTM9011EP Datasheet Datasheet 7 1.0 2024-06-30

3.2 SPI variant

2 SDI

6 SCLK

9 SDO

Figure 3 Pin configuration Table 2 Pin definitions and functions Pin Symbol Function 1, 14 OUTA Power output of the half-bridge A; All OUTA pins should be externally connected together.

2 SDI Serial data input with internal pull down

3, 4, 5 GND Power ground; All ground pins should be externally connected together.

6 SCLK Serial clock input with internal pull down

7, 8 OUTB Power output of the half-bridge B; All OUTB pins should be externally connected together.

9 SDO Serial data output with open drain

10 CS Chip select input with internal pull down

11, 12 VS Power supply; All VS pins should be externally connected together. EDP – Exposed die pad; For cooling and EMC purposes only; Not usable as electrical ground; Electrical ground must be provided by pins 3, 4 and 5. It is recommended to connect the EDP to ground. BTM9010EP/BTM9011EP Datasheet Datasheet 8 1.0 2024-06-30

4 General product characteristics

The device is intended to be used in an automotive environment.

4.1 Absolute maximum ratings

Stress above the absolute maximum ratings listed in this chapter may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3 Absolute maximum rating Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Voltages Supply voltage VS -0.3 – 40 V – P_GPC_01_1 Output voltage VOUTX -0.3 – VS + 0.3 V – P_GPC_01_02 Voltage of logic pins VINA / VSDI, VINB / VSCKL, VSEL / VCS, VPWM / VSDO -0.3 – VS + 6 V Note: Max. 40 V P_GPC_01_03 Current sense pin VIS -0.3 – 40 V – P_GPC_01_15 Voltage between VS and IS pin VSIS -0.3 – 40 V – P_GPC_01_04 Temperatures Junction temperature Tj -40 – 150 °C – P_GPC_01_09 Storage Temperature Tstg -55 – 150 °C – P_GPC_01_10 ESD susceptibility all pins (HBM) VESD(HBM, local) -2 – 2 kV HBM1) P_GPC_01_11 ESD susceptibility OUT vs GND, VS vs GND (HBM) VESD(HBM, global) -4 – 4 kV HBM1) P_GPC_01_12 ESD susceptibility all pins (CDM) VESD(CDM) -500 – 500 V CDM2) P_GPC_01_13 ESD susceptibility corner pins (CDM) VESD(CDM, corner) -750 – 750 V CDM2) P_GPC_01_14 1) ESD susceptibility, human body model (HBM), according to AEC Q100-002 (1.5 kΩ, 100 pF). 2) ESD susceptibility, charged device model (CDM), according to AEC Q100-011. BTM9010EP/BTM9011EP Datasheet Datasheet 9 1.0 2024-06-30

4.2 Functional range

The parameters of the functional range are listed in the table below: Table 4 Functional range Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Supply voltage range for normal operation VS(nor) 7 – 18 V – P_GPC_02_01 Extended supply voltage range for operation VS(ext) 4.5 – 40 V – P_GPC_02_02 Junction temperature Tj -40 – 150 °C – P_GPC_02_03 HS / LS continous drain current ID(HS) ID(LS) -3.4 – 3.4 A 1) Tamb = 85°C P_GPC_02_04 HS / LS pulsed drain current Ipulse(HS) Ipulse(LS) -4.2 – 4.2 A 1) tpulse ≤ 10 s Tamb = 85°C P_GPC_02_05 HS / LS pulsed drain current Ipulse(HS) Ipulse(LS) -5.2 – 5.2 A 1) tpulse ≤ 1 s Tamb = 85°C P_GPC_02_06 HS / LS pulsed drain current Ipulse(HS) Ipulse(LS) -9.2 – 9.2 A 1) tpulse ≤ 250 ms Tjunc = 25°C 2) P_GPC_02_07 Input voltage range for normal operation VINA(nor) / VSDI(nor), VINB(nor) / VSCLK(nor), VSEL(nor) / VCS(nor), VPWM(nor) 1) Based on thermal simulation using 2s2p with 600 mm2 Cu (70 μm) 2) This pulsed drain current is defined for the inrush current when the load is at cold temperature TLoad = - 40°C

4.3 Thermal resistance

This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, please go to JEDEC webpage. Table 5 Thermal resistance Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Junction to ambient RthJA – 33 – K/W 1) P_GPC_03_01 Junction to case RthJC – 2 – K/W – P_GPC_03_02 BTM9010EP/BTM9011EP Datasheet Datasheet 10 1.0 2024-06-30

1) According to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board. The product (chip and package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

4.4 Current consumption

Table 6 Current consumption VS = 7 V to 18 V, Tj = -40°C to 150°C, IL = 0 A, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Supply current in standby mode IVS_STB – – 5 μA VINA = VINB = 0 V; VSEL = 0 V; VPWM = 0 V; -40°C ≤ Tj ≤ 85°C; VS = 13.5 V P_GPC_04_01 Supply current in standby mode IVS_STB – – 20 μA VINA = VINB = 0 V; VSEL = 0 V; VPWM = 0 V; Tj = 150°C; VS = 13.5 V P_GPC_04_03 Supply current in normal mode IVS(ON) – 3 5 mA In normal operation mode: VINA = 5 V, VINB = 0 V or VINA = 0 V, VINB = 5 V; VSEL = X; VPWM = 0 V or VPWM = 5 V; No load is connected P_GPC_04_04 BTM9010EP/BTM9011EP Datasheet Datasheet 11 1.0 2024-06-30

5 Digital logic

INA is in general to control the high-side switch of the half-bridge A. INB is in general to control the high-side switch of the half-bridge B. PWM is used to control the low-side switches when the high-side is off. Please be informed that there are a few exceptions listed in the operative condition table to cover all use cases. Please check the input patterns refer to the Table 7. Table 7 Operative condition Input pattern Current sense/ Error flag MOSFET status Bridge mode INA INB PWM SEL IS HSA LSA HSB LSB 0 0 0 0 Hi-Z off off off off pull-down resistance is connected; outputs are grounded 1) 0 0 0 1 error flag: short to GND off off off off pull-up resistance is connected short to GND diagnosis 0 0 1 0 current sense: LSB off on off on slow decay/break LS 0 0 1 1 current sense: LSA off on off on slow decay/break LS 0 1 0 0 current sense: HSB off off on off fast decay HSB/off 0 1 0 1 error flag: open load off off on off fast decay HSB/open load diagnosis; pull-down resistance at OUTA is connected 0 1 1 0 current sense: HSB off on on off forward 0 1 1 1 current sense: LSA off on on off forward 1 0 0 0 error flag: open load on off off off fast decay HSA/open load diagnosis; pull-down resistance at OUTB is connected 1 0 0 1 current sense: HSA on off off off fast decay HSA/off 1 0 1 0 current sense: LSB on off off on reverse 1 0 1 1 current sense: HSA on off off on reverse 1 1 0 0 current sense: HSB on off on off slow decay/break HS 1 1 0 1 current sense: HSA on off on off slow decay/break HS 1 1 1 0 current sense: LSB off off off on Half-bridge A in tri-state 1 1 1 1 current sense: LSA off on off off Half-bridge B in tri-state Note: For SPI variant the inputs in the table are mapped to the dedicate bits in SPI protocol. For SPI variant when EN bit is set to 0, the device will enter to standby mode. 1) VSEL ≤ 0.25 V. Table 8 Fault conditions Digital input pins IS Comment INA INB PWM SEL 0 0 0 1 IIS(FAUL T) Short to GND is detected (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 12 1.0 2024-06-30

Table 8 (continued) Fault conditions Digital input pins IS Comment INA INB PWM SEL 0 0 1 0/1 IIS(FAUL T) Error flagged; low side A/B latched off in OC condition 0 1 0 0 IIS(FAUL T) Error flagged; high side B latched off in OC condition 0 1 0 1 IIS(FAUL T) Open load is detected 0 1 1 0/1 IIS(FAUL T) Error flagged; high side B or low side A latched off in OC condition 1 0 0 0 IIS(FAUL T) Open load is detected 1 0 0 1 IIS(FAUL T) Error flagged; high side A latched off in OC condition 1 0 1 0 IIS(FAUL T) Error flagged; high side A or low side B latched off in OC condition 1 1 0 0 IIS(FAUL T) Error flagged; high side A/B latched off in OC condition 1 1 1 0 IIS(FAUL T) Error flagged; low side B latched off in OC condition 1 1 1 1 IIS(FAUL T) Error flagged; low side A latched off in OC condition Note: For SPI variant the inputs in the table are mapped to the dedicate bits in SPI protocol. The error flags can be read out either at IS pin or via SDO pin.

5.1 Control inputs

Table 9 Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Low level voltage INA / SDI, INB / SCLK, SEL / CS, PWM VINA(L) / VSDI(L), VINB(L) / VSCLK(L), VPWM(L), VSEL(L) / VCS(L) High level voltage INA / SDI, INB / SCLK, SEL / CS, PWM VINA(H) / VSDI(H), VINB(H) / VSCLK(H), VPWM(H), VSEL(H) / VCS(H) (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 13 1.0 2024-06-30

Table 9 (continued) Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Input voltage hysteresis VINA(HYS) / VSDI(HYS), VINB(HYS) / VSCLK(HYS), VSEL(HYS) / VCS(HYS), VPWM(HYS) Input current low level IINA(L) / ISDI(L), IINB(L) / ISCLK(L), IPWM(L), ISEL(L) / IPWM(L) 2 4 6 μA VINA / VSDI = VINB / VSCLK = VPWM = VSEL / VPWM = 1.0 V Refer to Figure 4 P_INP_01_04 Input current high level IINA(H) / ISDI(H), IINB(H) / ISCLK(H), IPWM(H), ISEL(H) / IPWM( – 10 20 μA VINA / VSDI = VINB / VSCLK = VPWM = VSEL / VPWM = 2.1 V Refer to Figure 4 P_INP_01_05 1) When VINA, VINB, VPWM, or VSEL(L) is higher than 0.8 V, the devices will enter the normal operation mode from the standby mode, and consume higher quiescent current. BTM9010EP/BTM9011EP Datasheet Datasheet 14 1.0 2024-06-30

6 Power stages

6.1 Functional description

The power stage of the BTM9010EP / BTM9011EP consists of two half-bridges. All protection and diagnostic functions are applicable for each half-bridge. The on-state resistance RON dependents mainly on the junction temperature Tj. The typical on-state resistance characteristics are shown in Figure 5 Figure 5 Typical ON-state resistance vs. supply voltage VS

6.2 Switching time

t t  V OUTx t dr(HS) t r(HS) t df(HS) t f(HS)  V OUTx 20% 20% 80%80% t r(HS),total t f(HS),total Figure 6 Definition of HS switching time without cross current protection time BTM9010EP/BTM9011EP Datasheet Datasheet 15 1.0 2024-06-30

t t t df(LS) t f(LS) t dr(LS) t r(LS) 20% 20% 80% 80% ΔV OUTx ΔV OUTx t f(LS),total t r(LS),total Figure 7 Definition of LS switching time without cross current protection time HS switch on delay in active freewheeling Passive freewheeling INx V OUTx Active freewheeling Passive freewheeling V S + V f V S V S + 50% ˣ V f V f t t Figure 8 HS switch on delay in active freewheeling For SPI variant the INx signal in the figure is mapped to the input bits in SPI protocol. The INx will be updated at the CS falling edge.

6.3 Slew rate selection

6.3.1 HW variant

The slew rate is selected via input toggling as shown in Figure 9. If more then one input signal is high, the next slew rate level will be selected when:

• All input signals are pulled down for the duration 0.5 µs ≤ tSLS ≤ 5 µs
• At least one input signal is pulled up after tSLS expired BTM9010EP/BTM9011EP Datasheet

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At least one input high At least one input high SEL INA INB PWM 0.5μs ≤ t SLS ≤ 5µs Fast slew rate level All inputs low t SLS At least one input high 0.5μs ≤ t SLS ≤ 5µs Slow slew rate level All inputs low Slow slew rate level IS IIS(fault) CS CS CS Slew rate feedback Slew rate feedback Figure 9 Slew rate selection The slow slew rate is selected by default after power up. As shown in Figure 10 when all input signals are pulled down, the selected slew rate can be detected at IS pin before the standby mode blanking time is expired:

• Fast slew rate is selected, if the fault current IIS(FAUL T) is present at IS pin
• Slow slew rate is selected, if no current is present at IS pin t SLS At least one input high At least one input high SEL INA INB PWM 0.5μs ≤ t SLS ≤ 5µs Slow slew rate level All inputs low t SLS At least one input high 0.5μs ≤ t SLS ≤ 5µs Slow slew rate level All inputs low Fast slew rate level IS IIS(fault) CS CS CS Slew rate feedback Slew rate feedback t standby Figure 10 Slew rate detection

6.3.2 SPI variant

The slew rate level is selected via the SR bit in the data byte sent to SDI:

• The fast slew rate is selected if the SR bit is set to 1
• The slow slew rate is selected if the SR bit is set to 0 The slew rate is reset to the slow slew rate level by default after power up. The slew rate level is read out in the control byte via SDO when the SDO_SEL is set to 0.

6.4 Electrical characteristics

Table 10 Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. On-state high-side resistance RON(HS) – – 160 mΩ IOUT = 2.5 A; VS = 6 V; Tj = 150°C P_PS_01_01 (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 17 1.0 2024-06-30

Table 10 (continued) Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. On-state high-side resistance RON(HS) – 87.5 – mΩ IOUT = 2.5 A; VS = 6 V; Tj = 25°C P_PS_01_25 On-state low-side resistance RON(LS) – – 160 mΩ IOUT = 2.5 A; VS = 6 V; Tj = 150°C P_PS_01_02 On-state low-side resistance RON(LS) – 87.5 – mΩ IOUT = 2.5 A; VS = 6 V; Tj = 25°C P_PS_01_26 Fast HS switch on delay time tdr1(HS) 0.3 0.6 1.1 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_04 Slow HS switch on delay time tdr2(HS) 0.5 1 1.5 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_23 Fast HS switch off delay time tdf1(HS) 0.9 1.9 3.0 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_05 Slow HS switch off delay time tdf2(HS) 1.4 3.4 7.0 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_22 Fast HS rise time tr1(HS) 0.35 0.6 1.1 μs VOUTx from 20% to 80% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_06 Slow HS rise time tr2(HS) 0.5 1.1 1.8 μs VOUTx from 20% to 80% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_20 Fast HS fall time tf1(HS) 0.07 0.25 0.5 μs VOUTx from 80% to 20% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_07 Slow HS fall time tf2(HS) 0.15 0.7 1.5 μs VOUTx from 80% to 20% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_21 Fast LS switch on delay time tdf1(LS) 0.3 0.55 0.9 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_08 Slow LS switch on delay time tdf2(LS) 0.5 1 1.5 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_16 (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 18 1.0 2024-06-30

Table 10 (continued) Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Fast LS switch off delay time tdr1(LS) 1.0 1.8 2.6 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_09 Slow LS switch off delay time tdr2(LS) 1.5 3.4 7.1 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_17 Fast LS rise time tr1(LS) 0.15 0.4 0.7 μs VOUTx from 20% to 80% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_10 Slow LS rise time tr2(LS) 0.3 0.8 1.6 μs VOUTx from 20% to 80% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_18 Fast LS fall time tf1(LS) 0.15 0.45 0.7 μs VOUTx from 80% to 20% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_11 Slow LS fall time tf2(LS) 0.3 0.8 1.5 μs VOUTx from 80% to 20% of VS; RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_19 Fast cross current protection time tcross1 2.5 3.3 5 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_12 Slow cross current protection time tcross2 4.5 7 9.5 μs RLoad = 5.6 Ω; VS = 13.5 V P_PS_01_24 Free wheeling diode forward voltage Vf – 0.8 0.9 V |IOUT| = 2 A; Tj = 150°C P_PS_01_13 Slew rate selection time tSLS 0.5 – 5 μs – P_PS_01_15 BTM9010EP/BTM9011EP Datasheet Datasheet 19 1.0 2024-06-30

7 Protection and diagnostics

7.1 HW variant

Both high-side and low-side switches are capable to detect an open load condition in their activated state.

7.1.1 Undervoltage shutdown

If the supply voltage drops below VUV(OFF) as shown in Figure 11, the device will

• Switch off the MOSFETs actively
• Keep the charge pump on
• Provide no output at current sense pin Note: If the supply voltage drops below the power off reset voltage VS_POFFR, the charge pump will be deactivated, and the slew rate will be set to default value. If VS rises above VUV(ON) as shown in Figure 11, the device will resume normal operation. When the supply voltage rises above VUV(ON), the sense current IS will be present at the IS pin when the switch on delay and the current sense recovery time tIS expires. t V UV(ON) V UV(OFF) V UV(HY) VS INx t OUTx t t dr(HS) t IS I IS(FAULT) CSCS t dr(HS) + t ISD Figure 11 Timing diagram for undervoltage behavior

7.1.2 Overtemperature protection

This device is protected against overtemperature by the integrated temperature sensors. Overtemperature leads to a switch off of the output stages including the high-side and low-side switches. If the temperature sensor reaches TjSD for a duration longer than tOTF, the device behaves as follows

• Switch off both high-side and low-side MOSFETs in dedicated half-bridge
• Keep the charge pump on
• Keep the switches off until the device resumes the normal operation when the junction temperature decreases below the threshold
• Provide IIS(fault) at IS pin The device resumes normal functionality once the temperature drops below thermal switch on junction temperature TjSO BTM9010EP/BTM9011EP Datasheet

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7.1.3 Overcurrent protection

7.1.3.1 Short circuit of output to supply or ground

The high-side switches are protected against short to ground whereas the low-side switches are protected against short to supply. If the current within the switch exceeds the corresponding overcurrent detection threshold ISD_xx, the device will

• Enter into an overcurrent condition
• Start the overcurrent shutdown filter time tdOC_xx
• Limit the current to the current limitation ILIM_xx When the overcurrent shutdown is triggered, the device will
• Latch off
• Provide IIS(fault) at IS pin
• Switch on the MOSFETs by input pulse (PWM, INA and INB) as shown in Figure 14 tdOC_HS t OUTx short to GND short condition on high-side switch IHSx ISD_HS ILIM_HS - I SD_HS ILIM_HS ON VS Figure 12 High-side switch short circuit and overcurrent protection tdOC_LS t OUTx short to supply short condition on low-side switch ILSx ISD_LS ILIM_LS - I SD_LS ILIM_LS ON VS VS Figure 13 Low-side switch short circuit and overcurrent protection The high-side current limitation is always higher than the low-side current limitation. BTM9010EP/BTM9011EP Datasheet

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7.1.3.2 Recovery to normal operation

As shown in Figure 14 the recovery will be controlled by the input patterns. tdOC_XX t IL (LSA) ISD_XX ILIM_LS - I SD_LS ILIM_XX PWM SEL IS INA IIS(fault) tIS_BLK Figure 14 Recovery of short circuit and overcurrent protection by input pattern

7.1.4 Cross current protection

The high-side and low-side MOSFETs are ensured never to be simultaneously “ON” to avoid cross currents. This is achieved by integrating delays in the driver stage of the power outputs to create a cross current protection time between switching off one of the MOSFETs and switching on the adjacent MOSFET within the half-bridge. The cross current protection time, tcross1 and tcross2, as shown in Figure 15 and Figure 16, have been specified to ensure that the switching slopes do not overlap with each other. This prevents a cross conduction event. BTM9010EP/BTM9011EP Datasheet Datasheet 22 1.0 2024-06-30

Half-bridge APrevious State à New State HSA ON à HSA OFF LSA OFF à LSA OFF Case 1: HS switch off delay time INA V OUTA t t t df(HS) t f(HS)  V OUTx 80% t f(HS),total VS GND 20% OUTA VS Half-bridge APrevious State à New State HSA OFF à HSA OFF LSA OFF à LSA ON Case 2: LS switch on delay time without cross current protection time PWM V OUTA t t t df(LS) t f(LS)  V OUTx 80% t f(LS),total VS GND 20% VS INB = 0 PWM = 0 INA = 0 INB = 0 OUTA VS Half-bridge APrevious State à New State HSA ON à HSA OFF LSA OFF à LSA ON Case 3: LS switch on delay time with cross current protection time V OUTA t t cross + t df(LS) t f(LS)  V OUTx 80% t f(LS),total VS GND 20% VS INB = 0 INA t PWM = 1 Figure 15 Half-bridge outputs switching times: high-side to low-side transition BTM9010EP/BTM9011EP Datasheet Datasheet 23 1.0 2024-06-30

Previous State à New State HSA OFF à HSA OFF LSA ON à LSA OFF Case 1: LS switch off delay time PWM V OUTA t t t dr(LS) t r(LS)  V OUTx 80% t r(LS),total VS GND 20% OUTA VS Half-bridge A Previous State à New State HSA OFF à HSA ON LSA OFF à LSA OFF Case 2: HS switch on delay time without cross current protection time INB V OUTA t t t dr(HS) t r(HS)  V OUTx 80% t r(HS),total VS GND 20% VS INA = 0 INB = 0 INA = 1 PWM = 1 Previous State à New State HSA OFF à HSA ON LSA ON à LSA OFF Case 3: HS switch on delay time with cross current protection time INA V OUTA t t t cross + t dr(HS) t r(HS)  V OUTx 80% t r(HS),total VS GND 20% INB = 1 PWM t OUTA VS Half-bridge A SEL = 0 SEL = 0 SEL = 0 Figure 16 Half-bridge outputs switching times: low-side to high-side transition

7.1.5 Open load detection

In the following conditions this device provides open load detection without any external pull-down resistance, and the error flag will be present at IS pin.

• Open load at OUTA
• Open load at OUTB
• Short to GND at OUTA and / or OUTB Table 11 Open load diagnostic Digital input pins OUTA OUTB IS Comment INA INB PWM SEL 1 0 0 0 High Low IIS(FAUL T) Open load at OUTA or OUTB 0 1 0 1 Low High IIS(FAUL T) Open load at OUTA or OUTB (table continues...) BTM9010EP/BTM9011EP Datasheet

Datasheet 24 1.0 2024-06-30

Table 11 (continued) Open load diagnostic Digital input pins OUTA OUTB IS Comment INA INB PWM SEL 0 0 0 1 Low Low IIS(FAUL T) Short to GND INA = 0 INB = 1 PWM = 0 SEL = 1 OUTA = Low OUTB = High OUTA OUTB VBAT M OFF Low High ON OFFOFF Internal pull-down OUTA OUTB VBAT M ON High Low INA = 1 INB = 0 PWM = 0 SEL = 0 OUTA = High OUTB = Low OFF OFFOFF Internal pull-down OUTA OUTB VBAT M OFF Low Low INA = 0 INB = 0 PWM = 0 SEL = 1 OUTA = Low OUTB = Low OFF OFFOFF Internal pull-up 20k Internal pull-up 20k Figure 17 Example of open load detection and short to GND

7.1.6 Current sense

In normal operation (refer to Table 7) a current source is connected to IS pin to provide a current proportional to the forward current flowing through the switch selected by SEL pin as shown in Figure 18: Figure 18 Sense current vs. load current BTM9010EP/BTM9011EP Datasheet Datasheet 25 1.0 2024-06-30

7.2 SPI variant

Both high-side and low-side switches are capable of detection an open load in their activated state.

7.2.1 Undervoltage shutdown

If the supply voltage drops below VUV(OFF) as shown in Figure 19, the device will

• Switch off the MOSFETs actively
• Keep the charge pump on
• Provide no output at current sense pin
• Set UV bit to 1 If VS rises above VUV(ON) as shown in Figure 19, the device behaves as follows:
• Resume normal operation
• Clear the UV bit in the status byte When the supply voltage rises above VUV(ON), the sense current IS will be present at the IS pin when the switch on delay and the current sense recovery time tIS expires. t V UV(ON) V UV(OFF) V UV(HY) VS INx t OUTx t t dr(HS) t IS I IS(FAULT) CSCS t dr(HS) + t ISD Set UV bit to 1 Clear UV bit Figure 19 Timing diagram for undervoltage behavior

7.2.2 Overtemperature protection

This device is protected against overtemperature by the integrated temperature sensors. Overtemperature leads to switch off of the output stages including the high-side and low-side switches. If the temperature sensor reaches TjSD for a duration longer than tOTF, the device behaves as follows

• Switch off both high-side and low-side MOSFETs in dedicated half-bridge
• Keep the charge pump on
• Keep the switches off until the device resumes the normal operation when the junction temperature decreases below the threshold
• Provide IIS(fault) at IS pin
• Set the dedicate overtemperature error flag TSDx bit to 1 When the temperature drops below thermal switch on junction temperature TjSO, the device behaves as follows:
• Resume normal operation
• Clear TSDx bit in the status byte BTM9010EP/BTM9011EP Datasheet

Datasheet 26 1.0 2024-06-30

7.2.3 Overcurrent protection

7.2.3.1 Short circuit of output to supply or ground

The high-side switches are protected against short to ground whereas the low-side switches are protected against short to supply. If the current flowing through the switch exceeds the corresponding overcurrent detection threshold ISD_xx, the device will

• Enter into an overcurrent condition
• Start the overcurrent shutdown filter time tdOC_xx
• Limit the current to the current limitation ILIM_xx When the overcurrent shutdown is triggered, the device will
• Latch off
• Provide IIS(fault) at IS pin
• Switch on the MOSFETs by input pulse (PWM, INA and INB) as shown in Figure 22
• Set dedicated OCx bit to 1 tdOC_HS t OUTA short to GND short condition on high-side switch IHSx ISD_HS ILIM_HS - I SD_HS ILIM_HS ON VS Set OCA to 1 Half-bridge A Figure 20 Short circuit between OUTA and GND to trigger overcurrent protection tdOC_LS t OUTA short to supply short condition on low-side switch ILSx ISD_LS ILIM_LS - I SD_LS ILIM_LS ON VS VS Half-bridge A Set OCA to 1 Figure 21 Short circuit between OUTA and VS to trigger overcurrent protection The high-side current limitation is always higher than the low-side current limitation. BTM9010EP/BTM9011EP Datasheet

Datasheet 27 1.0 2024-06-30

7.2.3.2 Recovery to normal operation

As shown in Figure 22 the recovery will be controlled by the input bits in the control byte. When the input bits to switch on the MOSFET is sent to the device, it behaves as follows:

• Recovery to normal operation
• Switch on the related MOSFET
• Clear the OCx bit tdOC_XX t IL (LSA) ISD_XX ILIM_LS - I SD_LS ILIM_XX PWM SEL IS INA IIS(fault) SEL Set OCA to 1 Clear OCA bit Figure 22 Recovery of short circuit and overcurrent protection by input bits

7.2.4 Open load detection

In the following conditions this device provides open load detection without any external pull-down resistance, and the error flag will be present at IS pin and OL bit in the status byte.

• Open load at OUTA
• Open load at OUTB
• Short to GND Table 12 Open load diagnostic Input bits in the control byte OUTA OUTB IS OL bit Comment INA INB PWM SEL 1 0 0 0 High Low IIS(FAUL T) 1 Open load at OUTA or OUTB 0 1 0 1 Low High IIS(FAUL T) 1 Open load at OUTA or OUTB 0 0 0 1 Low Low IIS(FAUL T) 1 Short to GND BTM9010EP/BTM9011EP Datasheet

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INA = 0 INB = 1 PWM = 0 SEL = 1 OUTA = Low OUTB = High OUTA OUTB VBAT M OFF Low High ON OFFOFF Internal pull-down OUTA OUTB VBAT M ON High Low INA = 1 INB = 0 PWM = 0 SEL = 0 OUTA = High OUTB = Low OFF OFFOFF Internal pull-down OUTA OUTB VBAT M OFF Low Low INA = 0 INB = 0 PWM = 0 SEL = 1 OUTA = Low OUTB = Low OFF OFFOFF Internal pull-up 20k Internal pull-up 20k OL = 1 OL = 1 OL = 1 Figure 23 Example of open load detection and short to GND

7.2.5 Current sense

In normal operation (refer to Table 7) a current source is connected to IS pin to provide a current proportional to the forward current flowing through the switch selected by SEL bit as shown in Figure 24: Figure 24 Sense current vs. load current BTM9010EP/BTM9011EP Datasheet Datasheet 29 1.0 2024-06-30

7.2.6 Cross current protection

The high-side and low-side MOSFEs are ensured never to be simultaneously “ON” to avoid cross currents. This is achieved by integrating delays in the driver stage of the power outputs to create a cross current protection time between switching off one of the MOSFETs and switching on the adjacent MOSFET within the half-bridge. The cross current protection time, tcross1 and tcross2, as shown in Figure 25 and Figure 26, have been specified to ensure that the switching slopes do not overlap with each other. This prevents a cross conduction event. OUTA VS Half-bridge APrevious State à New State HSA ON à HSA OFF LSA OFF à LSA OFF Case 1: HS switch off delay time INA V OUTA t t t df(HS) t f(HS)  V OUTx 80% t f(HS),total VS GND 20% OUTA VS Half-bridge APrevious State à New State HSA OFF à HSA OFF LSA OFF à LSA ON Case 2: LS switch on delay time without cross current protection time PWM V OUTA t t t df(LS) t f(LS)  V OUTx 80% t f(LS),total VS GND 20% VS INB = 0 PWM = 0 INA = 0 INB = 0 OUTA VS Half-bridge APrevious State à New State HSA ON à HSA OFF LSA OFF à LSA ON Case 3: LS switch on delay time with cross current protection time V OUTA t t cross + t df(LS) t f(LS)  V OUTx 80% t f(LS),total VS GND 20% VS INB = 0 INA t PWM = 1 Figure 25 Half-bridge outputs switching times: high-side to low-side transition BTM9010EP/BTM9011EP Datasheet Datasheet 30 1.0 2024-06-30

Previous State à New State HSA OFF à HSA OFF LSA ON à LSA OFF Case 1: LS switch off delay time PWM V OUTA t t t dr(LS) t r(LS)  V OUTx 80% t r(LS),total VS GND 20% OUTA VS Half-bridge A Previous State à New State HSA OFF à HSA ON LSA OFF à LSA OFF Case 2: HS switch on delay time without cross current protection time INB V OUTA t t t dr(HS) t r(HS)  V OUTx 80% t r(HS),total VS GND 20% VS INA = 0 INB = 0 INA = 1 PWM = 1 Previous State à New State HSA OFF à HSA ON LSA ON à LSA OFF Case 3: HS switch on delay time with cross current protection time INA V OUTA t t t cross + t dr(HS) t r(HS)  V OUTx 80% t r(HS),total VS GND 20% INB = 1 PWM t OUTA VS Half-bridge A SEL = 0 SEL = 0 SEL = 0 Figure 26 Half-bridge outputs switching times: low-side to high-side transition

7.3 Electrical characteristics

Table 13 Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Switch on voltage VUV(ON) – – 5.0 V VS increasing P_PRO_01_01 Switch off voltage VUV(OFF) 3.0 – 4.5 V VS decreasing P_PRO_01_02 On/off hysteresis VUV(HY) – 0.4 – V – P_PRO_01_03 (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 31 1.0 2024-06-30

Table 13 (continued) Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Current sense recovery time tIS 1 4 10 μs – P_PRO_01_04 VS power on reset VS_POR 3.8 – – V VS increasing P_PRO_01_28 VS power off reset VS_POFFR – 2.0 V VS decreasing P_PRO_01_29 VS power on / off hysteresis VS_POR_HY – 0.02 – V VS_POR - VS_POFFR P_PRO_01_30 Thermal shutdown Thermal shutdown junction temperature TjSD 155 175 200 °C – P_PRO_01_05 Thermal switch on junction temperature TjSO 150 – 190 °C – P_PRO_01_06 Thermal hysteresis ΔT – 12 – K – P_PRO_01_07 Overcurrent shutdown HS/LS overcurrent detection threshold IOC_HS IOC_LS 7.5 10 13.5 A – P_PRO_01_09 HS/LS current limitation ILIM_HS ILIM_LS 10.0 14.0 19.5 A – P_PRO_01_10 HS/LS overcurrent shutdown filter time tdOC_HS tdOC_LS 5 7 11 µs – P_PRO_01_11 Open load detection Open load detection current IOLD 2.5 4 5.5 mA Input patterns: INA = 1, INB = 0, PWM = 0, SEL = 0; INA = 0, INB = 1, PWM = 0, SEL = 0; P_PRO_01_12 Open load detection filter time tD_OL 5 – – µs Input patterns: INA = 1, INB = 0, PWM = 0, SEL = 0; INA = 0, INB = 1, PWM = 0, SEL = 1; INA = 0, INB = 0, PWM = 0, SEL = 1 P_PRO_01_13 (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 32 1.0 2024-06-30

Table 13 (continued) Electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Short to ground detection voltage VSTG 0.7 – 1.25 V – P_PRO_01_27 Current sense High-side current sense ratio Kilis1(HS) 2010 2250 2490 – IOUT = 2.5 A P_PRO_01_14 High-side current sense ratio Kilis2(HS) 1320 2300 3300 – IOUT = 0.4 A P_PRO_01_15 Low-side current sense ratio Kilis1(LS) 2010 2250 2490 – IOUT = 2.5 A P_PRO_01_16 Low-side current sense ratio Kilis2(LS) 1410 2860 4310 – IOUT = 0.4 A P_PRO_01_17 Max. analog sense current IIS(CS) – – 5.5 mA In normal operation condition P_PRO_01_18 Error sense current IIS(FAUL T) 5.9 7.2 8.6 mA In fault condition P_PRO_01_19 Timing Input reset time for HS latched faults tRST_HS 300 – – ns VINX = 5 V to 0 V; HSX is in fault condition P_PRO_01_20 Input reset time for LS latched faults tRST_LS 300 – – ns VPWM = 5 V to 0 V; LSX is in fault condition P_PRO_01_21 Standby mode blanking time tstandby – – 50 μs – P_PRO_01_22 Current sense blank time for slow slew rate tIS_BLK 1.5 – 10 µs IIS from 0 to 40%; Rload = 5.6 Ω; Vs = 13.5 V P_PRO_01_23 Current sense blank time for fast slew rate tIS_BLK 1.0 – 8.5 µs IIS from 0 to 40%; Rload = 5.6 Ω; Vs = 13.5 V P_PRO_01_24 Recovery time from latched fault trec 7 – 25 µs – P_PRO_01_25 BTM9010EP/BTM9011EP Datasheet Datasheet 33 1.0 2024-06-30

8 Serial peripheral interface - SPI

8.1 SPI description

The control input word is read via the serial data input pin SDI, which is synchronized with the clock input SCLK provided by microcontroller. The output word appears synchronously at the serial data output pin SDO, see Figure 27. The transmission cycle begins when the chip is selected by the input CS (chip select), active high. After the CS input returns from high to low, the word that has been read is interpreted according to the content. The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus. The state of SDI is shifted into the input flip-flop with every falling edge on SCLK. The state of SDO is shifted out after every rising edge on SCLK. The SPI of the device is daisy chain capable. 7 76 5 4 3 2 1 EN 6 6 5 4 3 2 CS low to high: SDI is enabled. Status information transferred to output shift register CS high to low: data from shift register is transferred to output functions SDI: will accept data on the falling edge of SCLK signal SDO will change state on the rising edge of SCLK signal Actual status Actual data New data New status SDO SDI CS SCLK time time time time GEFGEF 6 MSB LSB MSB LSB 1 EN SDO _SEL SDO _SEL Figure 27 SPI data transfer timing A SPI communication consists of 8-bit frames as shown in Figure 28:

• SDI receives the data byte
• If SDO_SEL = 0, SDO transmits the global error flag and the Control byte
• If SDO_SEL = 1, SDO transmits the global error flag and the Status byte BTM9010EP/BTM9011EP Datasheet

Datasheet 34 1.0 2024-06-30

SDO_ SEL INA INB PWM SEL SEN_ EN SR EN 7 6 5 4 3 2 1 0 SDI MSB Control Byte SDO_ SEL INA INB PWM SEL SEN_ EN SR EN 7 6 5 4 3 2 1 0 SDO MSB Time MSB is sent first in SPI message LSB LSB Status Byte SDO_ SEL OCA OCB OL UV TSDA TSDB EN 7 6 5 4 3 2 1 0 MSB LSB SDO_SEL = 0 SDO_SEL = 1 Figure 28 SPI response

8.2 Global error flag

The global error flag (GEF) bit is reported on SDO between the CS rising edge and the first SCLK rising edge. With global error flag the device is possible to have a quick diagnostic without any SPI clock pulse in following conditions:

• Overcurrent of half-bridge A
• Overcurrent of half-bridge B
• Open load
• Undervoltage
• Thermal shut down BTM9010EP/BTM9011EP Datasheet

Datasheet 35 1.0 2024-06-30

High ImpedanceHigh Impedance Figure 29 Global error flag - Diagnostic with 0 - clock cycle

8.3 Control byte

The control byte is sent to the device via SDI pin:

• Enable (EN bit): - EN is set to 1 to enable the device - EN is set to 0 to disable the device (default)
• Slew rate selection (SR bit): - SR is set to 1 to select the fast slew rate level - SR is set to 0 to select the slow slew rate level (default)
• Current sense enable (SEN_EN bit): - SEN_EN is set to 1 to enable the current sense - SEN_EN is set to 0 to disable the current sense (default)
• Current sense select (SEL bit): - SEL is set to 1 to provide the sensing current of half-bridge A at IS pin - SEL is set to 0 to provide the sensing current of half-bridge B at IS pin (default) - Combine with other input bits the error flags of open load and short to GND are provided to the IS pin (refer to Table 7)
• PWM (PWM bit): Combine with INA, INB and SEL bit to select the operative mode (refer to Table 7)
• INB (OCB bit): Combine with INA, SEL and PWM bit to select the operative mode (refer to Table 7)
• INA (OCA bit): Combine with INB, SEL and PWM bit to select the operative mode (refer to Table 7)
• Read out byte select (SDO_SEL bit): - SDO_SEL is set to 1 to read out the status byte at SDO pin - SDO_SEL is set to 0 to read out the control byte at SDO pin (default)

8.4 Status byte

The SDO shifts out the status register during the SCLK cycles to provide an overview of the device status shown in Table 14 as following:

• Current operation mode of the device (EN bit): standby mode or normal operation mode
• Thermal shut down (TSDB bit): overtemperature shutdown of half-bridge B BTM9010EP/BTM9011EP Datasheet

Datasheet 36 1.0 2024-06-30

• Thermal shut down (TSDA bit): overtemperature shutdown of half-bridge A
• Undervoltage of VS (UV bit): VS undervoltage shutdown
• Open load (OL bit): open load detection
• Overcurrent of half-bridge B (OCB bit): overcurrent protection of half-bridge B
• Overcurrent of half-bridge A (OCA bit): overcurrent protection of half-bridge A
• Read out byte (SDO_SEL bit): control byte or status byte Note: The global error flag is a logic OR combination of error flags in the status byte: GEF = (TSDB) OR (TSDA) OR (UV) OR (OL) OR (OCB) OR (OCA). Table 14 Failure reported in the global status byte and global error flag Type of error Failure reported in the global status byte Global error flag Thermal shut down of half-bridge A TSDA = 1 1 Thermal shut down of half-bridge B TSDB = 1 1 Undervoltage of VS UV = 1 1 Open load OL = 1 1 Overcurrent of half-bridge A OCA = 1 1 Overcurrent of half-bridge B OCB = 1 1 No error TSD = 0 UV = 0 OL = 0 OCA = 0 OCB = 0

8.5 SPI timing

To ensure a correct SPI communication, the following conditions have to be fulfilled:

• SCLK must be low for a minimum tBEF before CS rising edge and tlead or tlead_EN after CS rising edge
• SCLK must be low for a minimum tlag before CS falling edge and tBEH after CS falling edge CS SCLK SDI tCSLtlag tSCLKH tSCLKL tpCLK SDO V CS(H) + 0.2 V

0.8 V DD_EXT

0.2 V DD_EXT

tSDI_setup tSDO_hold tENSDO tVASDO tDISSDO twakeup is needed when the device is in standby mode twakeup is not needed when the device is in normal operation modetwakeup tBEF V CS(L) - 0.2 V V SCLK(H) + 0.2 V V SCLK(L) - 0.2 V V SDI(H) + 0.2 V V SDI(L) - 0.2 V 3.0 V < V DD_EXT < 5.5 V SDO is connected to a pull up resistance of 2.2 k tlead Figure 30 SPI timing parameters BTM9010EP/BTM9011EP Datasheet Datasheet 37 1.0 2024-06-30

8.6 Daisy chain

In daisy chain configuration the SDO pin of the microcontroller is connected to a slave SDI. The first slave SDO is connected to the next slave SDI in the chain. The SDO of the final device in the chain is connected to the SDI pin of the microcontroller. In daisy chain configuration, the microcontroller SCLK is connected to all the slave CS inputs as shown in Figure 31. In the daisy chain an external VDDIO supply and a pull-up resistance is needed to drive the push-pull stage of the SDO pins. For the last device in the daisy chain no external resistance is required if the microcontroller has an internal pull- up resistance connected to it's SDI pin. SDI1 BTM9011EP SPI SCLK SDO1 CS SDI2 BTM9011EP SPI SCLK SDO2 CS SDI3 BTM9011EP SPI SCLK SDO3 Microcontroller SDI SDO CS SCLK CS VDDIO VDD_EXT Device 1 Device 2 Device 3 The pull-up resistor needs to be adjusted based on the required max. SPI frequency. 500Ω-2kΩ 500Ω-2kΩ 500Ω-2kΩ Figure 31 Daisy chain configuration with three BTM9011EP devices The BTM9011EP operates as a 8-bit shift register. The microcontroller must send the data bytes in reverse order as shown in Figure 32:

• The data byte for the device 3 is sent first.
• Then data byte for the device 2 is sent.
• Then data byte for the device 1 is sent. The SDI of the microcontroller, which is connected to SDO of the last device in the daisy chain, receives:
• A logic OR combination of all Global Error Flags (GEF) at the beginning of the SPI frame, between CS rising edge and the first SCLK rising edge.
• The status byte or the control byte of each BTM9011EP in reverse order: The status byte 3 or the control byte 3 corresponding to the device 3 is received first, followed by the status byte 2 or the control byte 2 corresponding to the device 2, and finally the status byte 1 or the control byte 1 corresponding to the device 1 is received. BTM9010EP/BTM9011EP Datasheet

Datasheet 38 1.0 2024-06-30

MCU SDO = SDI1 0 CS Time SDI2 = SDO1 Status Byte 1 or Control Byte 1 DATA3 DATA 2GEF1 SDI3 = SDO2 Status Byte 2 or Control Byte 2 OR GEF1/2 DATA 3 MCU SDI = SDO3 OR GEF1/2/3 Status Byte 3 or Control Byte 3 Status Byte 1 or Control Byte 1 Status Byte 2 or Control Byte 2 Status Byte 1 or Control Byte 1 SCLK 0 8 CLOCK CYCLES 8 CLOCK CYLES DATA 3 DATA 2 DATA 1

8 CLOCK CYCLES

Figure 32 SPI frame in daisy chain configuration with three BTM9011EP devices

8.7 Electrical characteristics SPI

Table 15 SPI electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. SPI frequency Maximum SPI frequency fSPI,max – – 4 MHz – P_SPI_01_01 Delay from CS rising edge to first rising edge of SCLK SPI interface wake- up time tWAKEUP – – 20 μs – P_SPI_01_02 SPI interface (SDI, SCLK, CS) Pull down resistor at pin CS, SDI and SCLK RCS, RPD_SDI, RPD_SCLK, 100 250 300 kΩ – P_SPI_01_07 (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 39 1.0 2024-06-30

Table 15 (continued) SPI electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. Input capacitance at pin CS, SDI and SCLK Input interface, logic outputs MISO High output voltage level VSDO(H) VDD_EX T - 0.4 – – V RPULL_UP = 2.2 kΩ; VDD_EXT = 5 V P_SPI_01_09 Low output voltage level VSDO(L) – – 0.6 V RPULL_UP = 2.2 kΩ; VDD_EXT = 5 V P_SPI_01_10 Tri-state leakage current ISDOLK -10 – 10 μA VCS = VDD_EXT;

0 V < VSDO < VDD_EXT;

RPULL_DOWN = 200 kΩ P_SPI_01_11 Tri-state input capacitance Data input timing SCLK period tpCLK 250 – – ns – P_SPI_01_13 SCLK high time tSCLKH 0.45 * tpCLK – 0.55 * tpCLK ns – P_SPI_01_14 SCLK low time tSCLKL 0.45 * tpCLK – 0.55 * tpCLK ns – P_SPI_01_15 SCLK low before CS high CS setup time tlead 250 – – ns – P_SPI_01_17 SCLK setup time tlag 250 – – ns – P_SPI_01_18 SCLK low after CS low SDI setup time tSDI_setup 100 – – ns – P_SPI_01_20 SDI hold time tSDI_hold 50 – – ns – P_SPI_01_21 Input signal rise time at pin SDI, SCLK, CS Input signal fall time at pin SDI, SCLK, CS Minimum CS low time (table continues...) BTM9010EP/BTM9011EP Datasheet Datasheet 40 1.0 2024-06-30

Table 15 (continued) SPI electrical characteristics VS = 7 V to 18 V, Tj = -40°C to 150°C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or condition P-Number Min. Typ. Max. GEF valid time tGEF_VAL – – 250 * n ns n = no. of devices in the same daisy chain; P_SPI_01_30 Data output timing SDO rise time trSDO – 50 250 ns CLoad = 50 pF; Rpullup = 2.2 kΩ; Max. values depends on Rpullup P_SPI_01_25 SDO fall time tfSDO – 50 110 ns CLoad = 50 pF; Rpullup = 2.2 kΩ P_SPI_01_26 SDO enable time after CS rising edge tENSDO – – 80 ns – P_SPI_01_27 SDO disable time after CS tDISSDO – – 200 ns – P_SPI_01_28 SDO valid time for VDD_EXT = 5 V tVASDO – – 110 ns VSDO < 0.2 * VDD_EXT, VSDO > 0.8 * VDD_EXT Cload = 50 pF P_SPI_01_29 BTM9010EP/BTM9011EP Datasheet Datasheet 41 1.0 2024-06-30

9 Application Information

The following simplified application figure is given as a hint for the implementation of the device only and is not regarded as a description or warranty of a certain functionality, condition or quality of the device. The function of the described circuits must be verified in the applications. Microcontroller I/O I/O I/OI/O VS OUTA GND B TM9010 EP C VS VS OUTB GND LSBLSA HSBHSA M R INB R PWM R INA INA PWM SEL INB IS R SEL A/D R ISC IS Reverse polarity protection V BAT C DC_LINK R FILT Figure 33 Application figure of BTM9010EP BTM9010EP/BTM9011EP Datasheet Datasheet 42 1.0 2024-06-30

μC SDI SDO CS SCLK CS VDDIO V DD_EXT Device 1 Device 2 Device 3 M M M A/D IS IS IS Reverse polarity protection V B A T CDC_LINK GND GND GND GND CDC_LINK CDC_LINK V S O U T A OUTB V S O U T A OUTB V S O U T A OUTB CIS RIS Rpull_up Rpull_up Rpull_up RSDO RCS RSCLK RSDI CVSCVSCVS

• The pull up resistor needs to be adjusted based on the required max. SPI frequency.· No pull up resistance is needed for the last device in the daisy chain in the SDI pin of the microcontroller has the internal pull up resistance. RFITL Figure 34 Application figure of BTM9011EP in daisy chain BTM9010EP/BTM9011EP Datasheet

Datasheet 43 1.0 2024-06-30

Figure 35 Package dimension BTM9010EP/BTM9011EP Datasheet Datasheet 44 1.0 2024-06-30

11 Datasheet revision history

Revision number Date of release Description of changes 1.00 2024-06-30 Datasheet BTM9010EP/BTM9011EP Datasheet Datasheet 45 1.0 2024-06-30

All referenced product or service names and trademarks are the property of their respective owners. Edition 2024-06-30 Published by Infineon Technologies AG

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