BTM7700G

BTM7700G INFINEON | Alldatasheet

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Data Sheet, Rev. 1.0, June 2007 Automotive Power

Data Sheet 1 Rev. 1.0, 2007-06-12 BTM7700G Table of Contents

BTM7700G PG-DSO-28-22 BTM7700G Data Sheet 1 Rev. 1.0, 2007-06-12 TrilithIC BTM7700G

1 Overview

Features

• Quad D-MOS switch driver
• Free configurable as bridge or quad-switch
• Optimized for DC motor management applications
• L o w RDS ON High side: 110 mΩ typ. @ 25°C, 280 mΩ max. @ 150°C Low side: 80 mΩ typ. @ 25°C, 200 mΩ max. @ 150°C
• Peak current: typ. 9.5 A @ 25 °C
• Very low quiescent current: typ. 5 µA @ 25 °C
• Small outline, enhanced power PG-DSO-package
• Operates up to 40 V
• PWM frequencies up to 1 kHz
• Load and GND-short-circuit-protection
• Overtemperature shut down with hysteresis
• Undervoltage detection with hysteresis
• Status flag diagnosis
• Internal clamp diodes
• Isolated sources for external current sensing
• Green Product (RoHS compliant)
• A E C Q u a l i f i e d

Description

The BTM7700G is part of the TrilithIC family containing three dies in one package: One double high-side switch and two low-side switches. The drains of these three vertical DMOS chips are mounted on separated lead frames. The sources are connected to individual pins, so the BTM7700G can be used in H-bridge- as well as in any other configuration. The double high-side switch is manufactured in SMART SIPMOS® technology which combines low RDS ON vertical DMOS power stages with CMOS circuitry for control, protection and diagnosis. To achieve low RDS ON and fast switching performance, the low-side switches are manufactured in S-FET logic level technology.

Data Sheet 2 Rev. 1.0, 2007-06-12 BTM7700G

2 Pin Configuration

2.1 Pin Assignment

Figure 1 Pin Assignment BTM7700G (Top View)

28 DL1

25 DL1

27 SL1

26 SL1

24 DHVS

23 SH1

22 SH1

21 SH2

20 SH2

19 DHVS

18 DL2

15 DL2

16 SL2

17 SL2

4N.C. 3DL1 2IL1 6GND 7IH1 8ST 9IH2 10DHVS DL2 N.C. DL2 IL2 HS-Leadframe LS-Leadframe LS-Leadframe

Data Sheet 3 Rev. 1.0, 2007-06-12 Pins written in bold type need power wiring. Table 1 Pin Definitions and Functions Pin No. Symbol Function 1, 3, 25, 28 DL1 Drain of low-side switch1, leadframe 11) 1) To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe.

2 IL1 Analog input of low-side switch1

4 N.C. not connected 5, 10, 19, 24 DHVS Drain of high-side switches and power supply voltage, leadframe 21)

6 GND Ground

7 IH1 Digital input of high-side switch1

8 ST Status of high-side switches; open Drain output

9 IH2 Digital input of high-side switch2

11 N.C. not connected 12, 14, 15, 18 DL2 Drain of low-side switch2, leadframe 31)

13 IL2 Analog input of low-side switch2

16,17 SL2 Source of low-side switch2 20,21 SH2 Source of high-side switch2 22,23 SH1 Source of high-side switch1 26,27 SL1 Source of low-side switch1

Data Sheet 4 Rev. 1.0, 2007-06-12 BTM7700G

2.2 Terms

HS-Source-Current Named during Short Circuit Named during Leakage-Cond. ISH1,2 ISCP H IDL LK SH2 DHVS ST IL1 GND IH1 SL2 5,10,19,24 20,21 16,17 RO1 RO2 Biasing and Protection 22,23 1,3,25,28 IH2 IL2 26,27 12,14,15,18 SL1 DL2 SH1 DL1 IGND ILKCL VS=12V CL 100µF CS 470nF IFH1,2 IS ISH2 IDL2 ISH1 IDL1 IDL LK 2 IDL LK 1 VDSL1 -VFL1 VDSL2 -VFL2 -VFH2 VDSH2 -VFH1 VDSH1 VUVON VUVOFF ISL2ISL1 ISCP L 1 ISCP L 2 VIL2 VIL th 2 VIL1 VIL th 1 VST VSTL VSTZ VIH1 VIH2 Gate Driver Gate Driver Diagnosis IST IST LK IIH1 IIH1 IIL1 IIL2

Data Sheet 5 Rev. 1.0, 2007-06-12

3 Block Diagram

Figure 3 Block Diagram BTM7700G SH2 DHVS ST IL1 GND IH1 SL2 IH2 IL2 SL1 DL2 SH1 DL1 5,10,19,24 20,21 16, 17 RO1 RO2 Biasing and ProtectionDiagnosis Driver OUT IN

0 L L

22, 23 1,3,25,28 26, 27 12,14,15,18

Data Sheet 1 Rev. 1.0, 2007-06-12

4 Circuit Description

4.1 Input Circuit

The control inputs IH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into the necessary form for driving the power output stages. The inputs are protected by ESD clamp-diodes. The inputs IL1 and IL2 are connected to the gates of the standard N-channel vertical power-MOS-FETs.

4.2 Output Stages

The output stages consist of an low RDSON Power-MOS H-bridge. In H-bridge configuration, the D-MOS body diodes can be used for freewheeling when communicating inductive loads. If the high-side switches are used as single switches, positive and negative voltage spikes which occur when driving inductive loads are limited by integrated power clamp diodes.

4.3 Short Circuit Protection

The outputs are protected against short circuit to ground and short circuit over load An internal OP-Amp controls the Drain-Source-Voltage by comparing the DS-Voltage-Drop with an internal reference voltage. Above this trip point the OP-Amp reduces the output current depending on the junction temperature and the drop voltage.

4.4 Overtemperature Protection

The high-side switches also incorporate an over temperature protection circuit with hysteresis which switches off the output transistors and sets the status output to low.

4.5 Undervoltage Lockout

When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis. The high-side output transistors are switched off if the supply voltage VS drops below the switch off value VUVOFF.

4.6 Status Flag

The status flag output is an open drain output with zener-diode which requires a pull-up resistor, as shown in the application circuit in Figure 4 “Application Example BTM7700G” on Page 15. Various errors as listed in the table “Diagnosis” are reported by switching the open drain output ST to low.

Data Sheet 2 Rev. 1.0, 2007-06-12 BTM7700G Table 3 Truth table and Diagnosis (valid only for the High-Side-Switches) Flag IH1 IH2 SH1 SH2 ST Remarks Inputs Outputs Normal operation; identical with functional truth table L L H H L H L H stand-by mode switch2 active switch1 active both switches active Overtemperature high-side switch1 0 X X L L X X detected Overtemperature high-side switch2 X X X X L L detected Overtemperature both high-side switches 0 X X L L L L L L detected detected Under voltage X X L L 1 not detected Inputs: Outputs: Status: 0 = Logic LOW Z = Output in tristate condition 1 = No error 1 = Logic HIGH L = Output in sink condition 0 = Error X = don’t care H = Output in source condition X = Voltage level undefined

Data Sheet 3 Rev. 1.0, 2007-06-12

5 Electrical Characteristics

5.1 Absolute Maximum Ratings

Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. Absolute Maximum Ratings1) – 40 °C < Tj < 150 °C 1) Not subject to production test; specified by design Pos. Parameter Symbol Limit Values Unit Remarks min. max. High-Side-Switches (Pins DHVS, IH1,2 and SH1,2) 5.1.1 Supply voltage VS – 0.3 42 V –

5.1.2 Supply voltage for full short circuit

VS(SCP) – 28 V

5.1.3 HS-drain current2)

2) Single pulse IS – 7 3) 3) Internally limited A TA = 25°C; tP < 100 ms

5.1.4 HS-input current IIH – 5 5 mA Pin IH1 and IH2

5.1.5 HS-input voltage VIH – 10 16 V Pin IH1 and IH2

5.1.6 Status pull up voltage VST – 0.3 5.4 V 5.1.7+ Status Output current IST – 5 5 mA Pin ST

5.1.8 Low-Side-Switches (Pins DL1,2, IL1,2 and SL1,2)

5.1.9 Drain-Source-Clamp voltage VDSL 55 – V VIL = 0 V; ID ≤ 1 mA

Tj = 25°C

5.1.10 LS-drain current2) IDL – 7 6 A TA = 25°C; tP < 100 ms

5.1.11 – 8 A TA = 25°C; tP < 10 ms 5.1.12 – 18 A TA = 25°C; tP < 1 ms

5.1.13 LS-input voltage VIL – 20 20 V Pin IL1 and IL2

5.1.14 Junction temperature Tj – 40 150 °C –

5.1.15 Storage temperature Tstg – 55 150 °C –

ESD Protection4) 4) ESD susceptibility HBM according to EIA/JESD22-A114-B (1.5k Ω, 100pF) 5.1.16 Input LS-Switch VESD – 0.3 kV

5.1.17 Input HS-Switch VESD – 1 kV

5.1.18 Status HS-Switch VESD – 2 kV

5.1.19 Output LS and HS-Switch VESD – 8 kV all other pins connected

Data Sheet 4 Rev. 1.0, 2007-06-12 BTM7700G

5.2 Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table

5.3 Thermal Resistance

Pos. Parameter Symbol Limit Values Unit Remarks min. max.

5.2.20 Supply voltage VS VUVOFF 42 V After VS rising above

5.2.21 Input voltage HS VIH – 0.3 15 V – 5.2.22 Input voltage LS VIL – 0.3 20 V –

5.2.23 Status output current IST 0 2 mA –

5.2.24 Junction temperature Tj – 40 150 °C –

Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.

5.3.25 LS-junction to soldering point1)

1) Not subject to production test, specified by design. RthJSP – – 20 K/W measured to pin 3 or 12

5.3.26 HS-junction to soldering point1) RthJSP – – 20 K/W measured to pin 19

5.3.27 Junction to Ambient1)

RthJA = Tj(HS) / (P(HS)+ P(LS)) RthJA – 36 – K/W 2) 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Data Sheet 5 Rev. 1.0, 2007-06-12

5.4 Electrical Characteristics

ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V unless otherwise specified Pos. Parameter Symbol Limit Values Unit Test Condition min. typ. max. Current Consumption HS-switch

5.4.28 Quiescent current IS – 5 9 µA IH1 = IH2 = 0 V

Tj = 25 °C – – 13 µA IH1 = IH2 = 0 V

5.4.29 Supply current;

IS – 1 2.5 mA IH1 or IH2 = 5 V VS = 12 V

5.4.30 Supply current;

IS – 2 5 mA IH1 and IH2 = 5 V VS = 12 V

5.4.31 Leakage current of

ISH LK – – 6 µA VIH = VSH = 0 V VS = 12 V

5.4.32 Leakage current through logic GND

in free wheeling condition ILKCL = IFH + ISH – – 10 mA IFH = 3 A VS = 12 V Current Consumption LS-switch

5.4.33 Input current IIL – 10 100 nA VIL = 20 V;

VDSL = 0V

5.4.34 Leakage current of low-side switch IDL LK – – 10 µA VIL = 0 V

VDSL = 40V Under Voltage Lockout HS-switch 5.4.35 Switch-ON voltage VUVON – – 4.8 V VS increasing 5.4.36 Switch-OFF voltage VUVOFF 1.8 – 3.5 V VS decreasing

5.4.37 Switch ON/OFF hysteresis VUVHY – 1 – V VUVON – VUVOFF

5.4.38 Inverse diode of high-side switch;

VFH – 0.8 1.2 V IFH = 3 A

5.4.39 Inverse diode of low-side switch;

VFL – 0.8 1.2 V IFL = 3 A

5.4.40 Static drain-source on-resistance of

RDS ON H – 110 – mΩ ISH = 1 A; VS = 12 V Tj = 25 °C – 200 280 mΩ ISH = 1 A; VS = 12 V Tj = 150 °C

5.4.41 Static drain-source

on-resistance of low-side switch RDS ON L – 80 – mΩ ISL = 1 A; VIL = 5 V Tj = 25 °C – 140 200 mΩ ISL = 1 A; VIL = 5 V Tj = 150 °C

Data Sheet 6 Rev. 1.0, 2007-06-12 BTM7700G Short Circuit of high-side switch to GND

5.4.42 Initial peak SC current

tdel = 100 µs; VS = 12 V; VDSH = 12V ISCP H 9 11 13 A Tj = – 40 °C 5.5 7 9 A Tj = + 150 °C Short Circuit of high-side switch to VS

5.4.43 Output pull-down-resistor RO 12 22 50 kΩ VDSL = 3 V

Thermal Shutdown1)

5.4.44 Thermal shutdown junction

Tj SD 155 180 190 °C –

5.4.45 Thermal switch-on junction

Tj SO 150 170 180 °C –

5.4.46 Temperature hysteresis ∆Τ – 10 – °C ∆Τ = TjSD – TjSO

Status Flag Output ST of high-side switch

5.4.48 Leakage current IST LK – – 10 µA VST = 5 V

5.4.49 Zener-limit-voltage VST Z 5.4 – – V IST = 1.6 mA Switching times of high-side switch1)

5.4.50 Turn-ON-time to 90% VSH tON – 75 160 µs RLoad = 12 Ω

VS = 12 V5.4.51 Turn-OFF-time to 10% VSH tOFF – 60 160 µs 5.4.52 Slew rate on 10 to 30% VSH dV/dtON – – 1.9 V/µs 5.4.53 Slew rate off 70 to 40% VSH -dV/dtOFF – – 2.7 V/µs Switching times of low-side switch1)

5.4.54 Turn-ON Delay Time td(on) – 5 – ns resistive load

ISL= 3A; VDSL=12V VIL = 5V; RG = 16Ω

5.4.55 Rise Time tr – 22 – ns

5.4.56 Switch-OFF Delay Time td(off) – 13 – ns

5.4.57 Fall Time tf – 18 – ns

Gate charge of low-side switch1)

5.4.58 Input to source charge QIS – 1 – nC ISL = 3 A; VDSL=12 V

5.4.59 Input to drain charge QID – 3 – nC ISL = 3 A; VDSL=12 V

5.4.60 Input charge total QI – 7 15 nC ISL = 3 A; VDSL=12 V

VIL = 0 to 5 V 5.4.61 Input plateau voltage V(plateau) – 2.8 - V ISL = 3 A; VDSL=12 V 1)Not subject to production test; specified by design ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V unless otherwise specified Pos. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Data Sheet 7 Rev. 1.0, 2007-06-12 Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specified mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Control Inputs of high-side switches IH 1, 2 5.4.62 H-input voltage VIH High – – 2.5 V –

5.4.63 L-input voltage VIH Low 1 – – V –

5.4.64 Input voltage hysteresis VIH HY – 0.3 – V –

5.4.65 H-input current IIH High 15 30 60 µA VIH = 5 V

5.4.66 L-input current IIH Low 5 – 20 µA VIH = 0.4 V 5.4.67 Input series resistance RI 2.7 4 5.5 kΩ – 5.4.68 Zener limit voltage VIH Z 5.4 – – V IIH = 1.6 mA Control Inputs IL1, 2 1) Not subject to production test; specified by design ISH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V < VS < 18 V unless otherwise specified Pos. Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Data Sheet 1 Rev. 1.0, 2007-06-12

6 Application Information

Note: The following simplified application examples are given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. The function of the described circuits must be verified in the real application Figure 4 Application Example BTM7700G SH2 DHVS ST IL1 GND IH1 SL2 5,10,19,24 20,21 16,17 TLE 4278G VS=12V D01 Z39 CS 10µF CD 47nF D I Q Reset Watchdog CQ 22µF VCCWD R GND µP RO1 RO2 Biasing and Protection M 22,23 1,3,25,28 IH2 IL2 26,27 12,14,15,18 SL1 DL2 SH1 DL1 RQ 100 kΩ RS 10 kΩ Gate Driver Gate Driver Diagnosis XC866

Green Product (RoHS compliant) Data Sheet 1 Rev. 1.0, 2007-06-12

7 Package Outlines

Figure 5 PG-DSO-28-22 (Plastic Transistor Single Outline Package) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). 11 4 1528 18.1-0.4 Index Marking 2.45 -0.1 7.6 10.3 ±0.3 -0.2 0.2 2.65 max -0.2 1.27 0.23 +0.09 0.1 0.4 0.35 x 45˚ +0.8 +0.150.35 2) 8˚ max 0.2 28x 2) Does not include dambar protrusion of 0.05 max per side 1) Does not include plastic or metal protrusions of 0.15 max rer side GPS05123 Dimensions in mm For further information on alternative packages, please visit our website: http://www.infineon.com/packages.

Data Sheet 1 Rev. 1.0, 2007-06-12

8 Revision History

Rev. Date Changes 1.0 2007-06-12 Initial Version

81726 Munich, Germany

© 6/25/07 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.