BSS84 NEXPERIA | Alldatasheet

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Technical content

Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. use http://www.nexperia.com salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e -mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

1.1 General description

transistor in a small Surface-Mounted Device (SMD) plastic package.

1.2 Features

1.3 Applications

1.4 Quick reference data

Table 1. Product overview

BSS84_6 © NXP B.V. 2008. All rights reserved. Table 2. Pinning

1 G gate

2 S source

3 D drain

Table 3. Ordering information Table 4. Marking codes

BSS84_6 © NXP B.V. 2008. All rights reserved. [1] Device mounted on a Printed-Circuit Board (PCB). Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

BSS84_6 © NXP B.V. 2008. All rights reserved. [1] Mounted on a PCB, vertical in still air. Table 6. Thermal characteristics

BSS84_6 © NXP B.V. 2008. All rights reserved. Table 7. Characteristics Tj=2 5°C unless otherwise specified.

BSS84_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 16 December 2008 6 of 11 NXP Semiconductors BSS84 P-channel enhancement mode vertical DMOS transistor Tj=2 5°CT j=2 5°C Fig 4. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 5. Drain-source on-state resistance as a function of drain current; typical values Tj=2 5°C; VDS = −10 V (1) I D = −130 mA; VGS = −10 V (2) ID = −20 mA; VGS = −2.4 V Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 7. Normalized drain-source on-state resistance factor as a function of junction temperature 0 -2 -10 -12 -600 -200 -400 mld197 -4 -6 -8 VDS (V) VGS = -10 V -7.5 V -6 V -5 V -4 V -3 V -2.5 V ID (mA) mld198 -10 -102 -103 ID (mA) R DSon (W ) VGS = -2.5 V -3 V -7.5 V -10 V -5 V-4 V 0 -2 -4 -10 -600 -200 -400 mld196 ID (mA) VGS (V) 0.6 1.0 1.4 1.8 0 50 100 150-50 Tj (°C) mld194 (1) (2) R DSon R DSon(25°C)

BSS84_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 16 December 2008 7 of 11 NXP Semiconductors BSS84 P-channel enhancement mode vertical DMOS transistor 8. Test information ID = −1 mA; VDS =V GS VGS = 0 V; f = 1 MHz Fig 8. Gate-source threshold voltage as a function of junction temperature Fig 9. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 0.6 0.8 1.0 1.2 0 50 100 150 mld195 -50 Tj (°C) VGSth VGSth(25°C) -10 -20 -30 mld191 C (pF) VDS (V) C iss C oss C rss Fig 10. Switching time test circuit Fig 11. Input and output waveforms mld189 50 Ω VDS = −40 V ID 0 V −10 V mbb690 10 % 90 % 90 % 10 % ton toff OUTPUT INPUT

BSS84_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 16 December 2008 8 of 11 NXP Semiconductors BSS84 P-channel enhancement mode vertical DMOS transistor 9. Package outline Fig 12. Package outline SOT23 (TO-236AB) UNIT A 1 max. bp cD E e1 H E Lp Qw v REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 04-11-04 06-03-16 IEC JEDEC JEITA mm 0.1 0.48 0.38 0.15 0.09 3.0 2.8 1.4 1.2 0.95 e 1.9 2.5 2.1 0.55 0.45 0.10.2 DIMENSIONS (mm are the original dimensions) 0.45 0.15 SOT23 TO-236AB bp D e A Lp Q detail X H E E w M v M A B AB 0 1 2 mm scale A 1.1 0.9 c X Plastic surface-mounted package; 3 leads SOT23

BSS84_6 © NXP B.V. 2008. All rights reserved. Table 8. Revision history

  • Table 5 “Limiting values”: Ptot figure reference updated BSS84_5 20081209 Product data sheet - BSS84_4 BSS84_4 20070717 Product data sheet - BSS84_3 BSS84_3 20030804 Product specification - BSS84_2 BSS84_2 19970618 Product specification - BSS84_1 BSS84_1 19950407 Product specification - -

BSS84_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 16 December 2008 10 of 11 NXP Semiconductors BSS84 P-channel enhancement mode vertical DMOS transistor 11. Legal information

11.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

11.2 Definitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

11.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values —Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data —The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

11.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 12. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

P-channel enhancement mode vertical DMOS transistor © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 December 2008 Document identifier: BSS84_6 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 13. Contents