BSP130 NEXPERIA | Alldatasheet

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Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. use http://www.nexperia.com salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e -mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

Product specification Supersedes data of 1997 Jun 23

2001 Dec 11

N-channel enhancement mode vertical D-MOS transistor age M3D087

2001 Dec 11 2

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130

FEATURES

  • Direct interface to C-MOS, TTL, etc.
  • High-speed switching
  • No secondary breakdown.

APPLICATIONS

  • Line current interruptor in telephone sets
  • Relay, high-speed and line transformer drivers.

DESCRIPTION

N-channel enhancement mode vertical D-MOS transistor in a SOT223 package. PINNING - SOT223 PIN DESCRIPTION 1 gate 2 drain 3 source 4 drain Fig.1 Simplified outline and symbol. Marking codeBSP130. handbook, halfpage MAM054 123 Top view s d g QUICK REFERENCE DATA LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm2. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage (DC) − 300 V ID drain current (DC) − 350 mA Ptot total power dissipation T amb ≤ 25 °C − 1.5 W VGSO gate-source voltage open drain −± 20 V R DSon drain-source on-state resistance ID = 250 mA; VGS =1 0V − 6 Ω VGSoff gate-source cut-off voltage ID = 1 mA; VDS =V GS 0.8 2 V SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage (DC) − 300 V VGSO gate-source voltage (DC) open drain −± 20 V ID drain current (DC) − 350 mA IDM peak drain current − 1.4 A Ptot total power dissipation T amb ≤ 25 °C; note 1 − 1.5 W Tstg storage temperature −55 +150 °C Tj junction temperature − 150 °C

2001 Dec 11 3

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 THERMAL CHARACTERISTICS Note 1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm2. STATIC CHARACTERISTICS Tj = 25°C unless otherwise specified. SYMBOL PARAMETER VALUE UNIT R th j-a thermal resistance from junction to ambient; note 1 83.3 K/W SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS drain-source breakdown voltage ID =1 0µA; VGS = 0 300 −− V IGSS gate-source leakage current V GS = ±20 V; VDS =0 −−± 100 nA VGSth gate-source threshold voltage I D = 1 mA; VDS =V GS 0.8 − 2V R DSon drain-source on-state resistance ID = 20 mA; VGS = 2.4 V − 4.8 10 Ω ID = 250 mA; VGS =1 0V − 3.7 6 Ω IDSS drain-source leakage current V DS = 240 V; VGS =0 −− 100 nA  Yfs transfer admittance I D = 250 mA; VDS = 25 V 200 690 − mS C iss input capacitance V DS = 25 V; VGS = 0; f = 1 MHz − 100 120 pF C oss output capacitance V DS = 25 V; VGS = 0; f = 1 MHz − 21 30 pF C rss feedback capacitance V DS = 25 V; VGS = 0; f = 1 MHz − 10 15 pF Switching times (see Figs2 and3) ton turn-on time I D = 250 mA; VDD =5 0V ; VGS =0t o1 0V − 61 0 n s toff turn-off time I D = 250 mA; VDD = 50 V; VGS = 10 to 0 V − 46 60 ns

2001 Dec 11 4

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 Fig.2 Switching times test circuit. handbook, halfpage MBB691 50 Ω VDD = 50 V ID 10 V 0 V Fig.3 Input and output waveforms. handbook, halfpage MBB692 10 % 90 % 90 % 10 % ton toff OUTPUT INPUT Fig.4 Power derating curve. handbook, halfpage 0 50 100 Tj (°C) Ptot (W) 200 1.5 0.5 150 MRC218 handbook, halfpage250 01 0 3 0 100 150 200 MLD765 VDS (V) C (pF) C rss C oss C iss Fig.5 Capacitance as a function of drain-source voltage; typical values. VGS = 0; f = 1 MHz; Tj=2 5°C.

2001 Dec 11 5

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 handbook, halfpage 1.2 0.8 VDS (V) ID (A) 0.4 48 1 2 MLD766 4 V 3.5 V 3 V 2 V 5 V 2.5 V VGS = 10 V Fig.6 Typical output characteristics. Tj=2 5°C. handbook, halfpage 01 0 1.2 0.4 0.8 ID (A) VGS (V) 468 MLD767 Fig.7 Typical transfer characteristics. VDS = 10 V; Tj=2 5°C. handbook, halfpage30 MLD768 10−1 11 0 ID (A) R DSon (Ω ) 3 V 3.5 V 4 V 10 V 2.5 V 5 V VGS = 2 V Fig.8 Drain-source on-state resistance as a function of drain current; typical values. Tj=2 5°C. handbook, halfpage 02 1 0 VGS (V) R DSon (Ω ) MLD769 Fig.9 Drain-source on-state resistance as a function of gate-source voltage; typical values. VDS = 100 mV; Tj=2 5°C.

2001 Dec 11 6

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 Fig.10 Transient thermal resistance from junction to ambient as a function of pulse time. handbook, full pagewidth102 R th j-a (K/W) 10−1 MRC221 10−5 10−4 10−3 10−2 10−1 1 tp (s) 10 10 2 103 tp tp T P t Tδ = δ = 0.5 0.75 0.2 0.1 0.05 0.01 0.02 handbook, halfpage MLD773 10 10 2 10-3 10-2 10-1

1031 VDS (V)

(A) tp T P t tp Td = DC (1) 1 ms 10 ms 100 ms 100 ms tp = 10 ms Fig.11 SOAR curve. δ = 0.01; Tamb =2 5°C. (1) RDSon limitation.

2001 Dec 11 7

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 handbook, halfpage −50 0 (1) (2) Tj (°C) k 50 150 1.5 0.5 100 MLD771 Fig.12 Temperature coefficient of drain-source on-state resistance; typical values. Typical RDSon ; (1) ID = 250 mA; VGS =1 0V . (2) ID = 20 mA; VGS = 2.4 V. k R DS(on) at Tj handbook, halfpage -50 0 Tj (°C) k 50 150 1.25 100 0.75 0.5 0.25 MLD772 Fig.13 Temperature coefficient of gate-source threshold voltage; typical values. Typical VGSth at 1 mA. k V GS th() at Tj

2001 Dec 11 8

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 PACKAGE OUTLINE UNIT A 1 bp cD E e1 H E Lp Qy wv REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ mm 0.10 0.01 1.8 1.5 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 2.3 e 4.6 7.3 6.7 1.1 0.7 0.95 0.85 0.1 0.10.2 DIMENSIONS (mm are the original dimensions) SOT223 SC-73 97-02-28 99-09-13 w Mbp D e A Lp Q detail X H E E v M A AB B c y 0 2 4 mm scale A X 13 2 Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223

2001 Dec 11 9

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 DATA SHEET STATUS Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was DATA SHEET STATUS (1) PRODUCT STATUS (2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

2001 Dec 11 10

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 NOTES

2001 Dec 11 11

Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BSP130 NOTES

© Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Printed in The Netherlands 613510/03/pp12 Date of release:2001 Dec 11 Document order number: 9397 750 09064