BF543 SIEMENS | Alldatasheet
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Technical content
Silicon N Channel MOS FET Triode BF 543 Preliminary Data
- For RF stages up to 300 MHz preferably in FM applications
- IDSS = 4 mA,gfs = 12 mS ESD: Electrostatic discharge sensitive device, observe handling precautions! Maximum Ratings Type Ordering Code (tape and reel) Marking Package 1)Pin Configuration BF 543 Q62702-F1372LDs SOT-23 1 2 3 G D S Thermal Resistance Junction - ambient2) Rth JA ≤ 450 K/W Parameter Symbol Values Unit Drain-source voltage VDS 20 V Drain current ID 30 mA Gate-source peak current ± IGSM 10 Total power dissipation,TA ≤ 60 ˚C Ptot 200 mW Storage temperature range Tstg – 55 … + 150 ˚C Channel temperature Tch 150 Ambient temperature range TA – 55 … + 150 1) For detailed information see chapter Package Outlines. 2) Package mounted on alumina 15 mm× 16.7 mm × 0.7 mm. 07.94
Electrical Characteristics
atTA = 25 ˚C, unless otherwise specified. UnitValues V nA Parameter Drain-source breakdown voltage ID = 10µA, –VGS = 4 V Gate-source breakdown voltage ± IGS = 10 mA,VDS = 0 Gate cutoff current ± VGS = 6 V,VDS = 0 Symbol V(BR)DS ±V(BR)GSS ± IGSS min. typ. max. mADrain current VDS = 10 V,VGS = 0 IDSS 2.0 4 6.0 VGate-source pinch-off voltage VDS = 10 V,ID = 20µA – VGS(p) – 0.7 1.5 DC Characteristics mSForward transconductance VDS = 10 V,ID = 4 mA,f= 1 kHz gfs 9.5 12 – pFGate-1 input capacitance VDS = 10 V,ID = 4 mA,f= 1 MHz C gss – 2.7 – fFReverse transfer capacitance VDS = 10 V,ID = 4 mA,f= 1 MHz C dg –1 8 – dBPower gain (test circuit) VDS = 10 V,ID = 4 mA,f= 200 MHz G G = 2 mS,G L = 0.5 mS G p –2 2 – pFOutput capacitance VDS = 10 V,ID = 4 mA,f= 1 MHz C dss – 0.9 – Noise figure (test circuit) VDS = 10 V,ID = 4 mA,f= 200 MHz G G = 2 mS,G L = 0.5 mS F –1– AC Characteristics BF 543
Total power dissipationPtot =f (TA ) Gate transconductancegfs= f (V GS ) VDS = 10 V,IDSS = 4 mA,f= 1 kHz Typ. output characteristicsID =f (V DS ) Drain currentID = f (V GS ) VDS = 10 V
Gate input capacitance Cgss = f (V GS ) VDS = 10 V, IDSS = 4 mA,f= 1 MHz Reverse transfer capacitance C dg =f (V DS ) VGS = 0, IDSS = 4 mA, f= 1 MHz Output capacitanceC dss =f (V DS ) VGS = 0, IDSS = 4 mA,f= 1 MHz Gate 1 input admittancey11s VDS = 10 V, IDSS = 4 mA, VGS = 0 (source circuit)
Gate 1 transconductancey21s VDS = 10 V,IDSS = 4 mA, VGS = 0 (source circuit) Output admittancey22s VDS = 10 V,IDSS = 10 mA, VGS = 0 (source circuit) Test circuit for power gainG p and noise figureF f= 200 MHz,G G = 2 mS,G L = 0.5 mS