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Supersedes data of 2000 Mar 29
2010 Sep 16
BF1202; BF1202R; BF1202WR N-channel dual-gate PoLo MOS-FETs
2010 Sep 16 2
NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR
FEATURES
Short channel transistor with high forward transfer admittance to input capacitance ratio Low noise gain controlled amplifier Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization.
APPLICATIONS
VHF and UHF applications with 3 to 9 V supply voltage, such as digital and analogue television tuners and professional communications equipment.
DESCRIPTION
Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1202, BF1202R and BF1202WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. PINNING Marking code legend: * = - : made in Hong Kong * = p : made in Hong Kong * = t : made in Malaysia PIN DESCRIPTION 1s o u r c e 2d r a i n 3g a t e 2 4g a t e 1 handbook, 2 columns Top view MSB014 Fig.1 Simplified outline (SOT143B). BF1202 marking code: LD* handbook, 2 columns Top view MSB035 Fig.2 Simplified outline (SOT143R). BF1202R marking code: LE* lfpage Top view MSB842 Fig.3 Simplified outline (SOT343R). BF1202WR marking code: LE* QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage 10 V ID drain current 30 mA Ptot total power dissipation 200 mW yfs forward transfer admittance 25 30 40 mS Cig1-ss input capacitance at gate 1 1.7 2.2 pF Crss reverse transfer capacitance f = 1 MHz 15 30 fF F noise figure f = 800 MHz 1.1 1.8 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 105 dBV Tj operating junction temperature 150 C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling.
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1. T s is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage 10 V ID drain current 30 mA IG1 gate 1 current 10 mA IG2 gate 2 current 10 mA Ptot total power dissipation BF1202; BF1202R T s 113 C; note 1 200 mW BF1202WR T s 119 C; note 1 200 mW Tstg storage temperature 65 +150 C Tj operating junction temperature 150 C SYMBOL PARAMETER VALUE UNIT Rth j-s thermal resistance from junction to soldering point BF1202; BF1202R 185 K/W BF1202WR 155 K/W handbook, halfpage 05 0 (1)(2) Ts (°C) Ptot (mW) 100 200 250 200 150 150 100 MCD951 Fig.4 Power derating curve. (1) BF1202WR. (2) BF1202; BF1202R.
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR STATIC CHARACTERISTICS Tj =2 5 C unless otherwise specified. Note 1. R G1 connects G1 to VGG =5V . DYNAMIC CHARACTERISTICS Common source; Tamb =2 5 C; VG2-S =4V ; VDS =5V ; ID = 12 mA; unless otherwise specified. Note 1. Measured in Fig.21 test circuit. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)DSS drain-source breakdown voltage V G1-S =V G2-S =0 ; ID =1 0 A1 0 V V(BR)G1-SS gate 1-source breakdown voltage V G2-S =V DS =0 ; IG1-S =1 0m A 6 V V(BR)G2-SS gate 2-source breakdown voltage V G1-S =V DS =0 ; IG2-S =1 0m A 6 V V(F)S-G1 forward source-gate 1 voltage V G2-S =V DS =0 ; IS-G1 =1 0m A 0 . 5 1 . 5 V V(F)S-G2 forward source-gate 2 voltage V G1-S =V DS =0 ; IS-G2 =1 0m A 0 . 5 1 . 5 V VG1-S(th) gate 1-source threshold voltage V G2-S =4V ; VDS =5V ; ID =1 0 0A0 . 3 1 . 0 V VG2-S(th) gate 2-source threshold voltage V G1-S =5V ; VDS =5V ; ID =1 0 0A0 . 3 1 . 2 V IDSX drain-source current VG2-S =4V ; VDS =5V ; RG1 =1 2 0k; note 1 81 6 m A IG1-SS gate 1 cut-off current VG2-S =V DS =0 ; VG1-S =5V 50 nA IG2-SS gate 2 cut-off current VG1-S =V DS =0 ; VG2-S =4V 20 nA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; T j =2 5 C 2 53 04 0m S Cig1-ss input capacitance at gate 1 f = 1 MHz 1.7 2.2 pF Cig2-ss input capacitance at gate 2 f = 1 MHz 1 pF Coss output capacitance f = 1 MHz 0.85 pF Crss reverse transfer capacitance f = 1 MHz 15 30 fF F noise figure f = 10.7 MHz; G S =2 0m S ; BS =0 91 1 d B f=4 0 0M H z ; YS =Y So p t 0.9 1.5 dB f=8 0 0M H z ; YS =Y So p t 1.1 1.8 dB Gtr power gain f = 200 MHz; GS =2m S ; BS =B So p t; GL = 0.5 mS; BL =B Lo p t 34.5 dB f=4 0 0M H z ; GS =2m S ; BS =B So p t; GL =1m S ; BL =B Lo p t 30.5 dB f=8 0 0M H z ; GS = 3.3 mS; BS =B So p t; GL =1m S ; BL =B Lo p t 26.5 dB Xmod cross-modulation input level for k = 1%; fw =5 0M H z ; funw =6 0M H z ; n o t e1 at 0 dB AGC 90 dB V at 10 dB AGC 92 dBV at 40 dB AGC 100 105 dBV
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 0.4 0.8 1.2 1.6 VG1-S (V) ID (mA) MCD952 VG2-S = 4 V 2.5 V 3.5 V
3 V 2 V
1.5 V 1 V Fig.5 Transfer characteristics; typical values. VDS =5V . Tj =2 5 C. handbook, halfpage 01 0 VDS (V) ID (mA) 648 MCD953 VG1-S = 1.5 V 1.4 V 1.2 V 1.3 V 1.1 V 1 V 0.9 V Fig.6 Output characteristics; typical values. VG2-S =4V . Tj =2 5 C. handbook, halfpage 0 2.5 100 0.5 1 1.5 2 VG1-S (V) IG1 (μA) MCD954 VG2-S = 4 V 3.5 V 3 V 2.5 V 2 V 1.5 V 1 V Fig.7 Gate 1 current as a function of gate 1 voltage; typical values. VDS =5V . Tj =2 5 C. VDS =5V . Tj =2 5 C. handbook, halfpage ID (mA) 42 0 81 21 6 MCD955 yfs (mS) 3.5 V 2.5 V 3 V 2 V VG2-S = 4 V Fig.8 Forward transfer admittance as a function of drain current; typical values. VDS =5V . Tj =2 5 C.
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 05 0 10 20 30 40 IG1 (μA) ID (mA) MCD956 Fig.9 Drain current as a function of gate 1 current; typical values. VDS =5V ; VG2-S =4V . Tj =2 5 C. handbook, halfpage VGG (V) 23 4 MCD957 ID (mA) Fig.10 Drain current as a function of gate 1 supply voltage (= VGG); typical values. VDS =5V ; VG2-S =4V ; Tj =2 5 C. RG1 =1 2 0k (connected to VGG); see Fig.21. handbook, halfpage 0246 VGG = VDS (V) ID (mA) MCD958 RG1 = 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 220 kΩ 180 kΩ Fig.11 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. VG2-S =4V ; Tj =2 5 C. RG1 connected to VGG; see Fig.21. handbook, halfpage 0246 MCD959 VG2-S (V) ID (mA) 4.5 V 4 V 3 V VGG = 5 V 3.5 V VDS =5V ; Tj =2 5 C. RG1 =1 2 0k (connected to VGG); see Fig.21. Fig.12 Drain current as a function of gate 2 voltage; typical values.
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage 0246 MCD960 VG2-S (V) IG1 (μA) 4 V 3.5 V 3 V 4.5 V VGG = 5 V Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. VDS =5V ; Tj =2 5 C. RG1 =1 2 0k (connected to VGG); see Fig.21. handbook, halfpage 012 4 −50 −10
3 VAGC (V)
(dB) −20 −30 −40 MCD961 Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. VDS =5V ; VGG =5V ; RG1 = 120 k; f = 50 MHz; Tamb =2 5 C. handbook, halfpage gain reduction (dB) 10 50 120 110 100 20 30 40 MCD962 Vunw (dBμV) Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; Fig.21. VDS =5V ; VGG =5V ; RG1 = 120 k; f= 50 MHz; funw =6 0M H z ; Tamb =2 5 C. handbook, halfpage gain reduction (dB) 10 50 20 30 40 MCD963 ID (mA) Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. VDS =5V ; VGG =5V ; RG1 = 120 k; f = 50 MHz; Tamb =2 5 C.
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage MCD964 f (GHz) Yis (mS) 102 103 102 10−1 bis gis Fig.17 Input admittance as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 2m A ; Tamb =2 5 C. handbook, halfpage MCD965 f (MHz) 102 103 103 102 −103 −102 −10 yrs (μS) ϕrs (deg) ϕrs yrs Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 2m A ; Tamb =2 5 C. handbook, halfpage 102 −102 −10 MCD966 10 102 103 f (MHz) yfs (mS) ϕfs (deg)yfs ϕfs Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 2m A ; Tamb =2 5 C. handbook, halfpage MCD967 bos f (MHz) Yos (mS) 102 103 10−2 10−1 gos Fig.20 Output admittance as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 2m A ; Tamb =2 5 C.
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, full pagewidth DUT 4.7 nF 10 kΩ MGS315 4.7 nF ≈2.2 μH 4.7 nF RL 50 Ω VGG VAGC VDS RGEN 50 Ω VI 50 Ω 4.7 nF RG1 Fig.21 Cross-modulation test set-up. Table 1 Scattering parameters: VDS =5V ; VG2-S =4V ; ID =1 2m A ; Tamb =2 5 C Table 2 Noise data: VDS =5V ; VG2-S =4V ; ID =1 2m A ; Tamb =2 5 C f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) Fmin (dB) opt Rn ()(ratio) (deg) 400 0.9 0.805 28.5 50 800 1.1 0.725 47.2 40
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR PACKAGE OUTLINES UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.1 0.9 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 HE y w v Q 2.5 2.1 0.45 0.15 0.55 0.45 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143B 04-11-16 06-03-16 0 1 2 mm scale Plastic surface-mounted package; 4 leads SOT143B D HE E AB v M A X A Lp Q detail X c y w M e B bp
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR UNIT A REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.1 0.9 max 0.1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 HE y w v Q 2.5 2.1 0.55 0.25 0.45 0.25 e 1.9 1.7 Lp 0.1 0.10.2 bp 0.48 0.38 DIMENSIONS (mm are the original dimensions) SOT143R SC-61AA 04-11-16 06-03-16 0 1 2 mm scale Plastic surface-mounted package; reverse pinning; 4 leads SOT143R D HE E AB v M A X A Lp Q detail X c y w M e B bp
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT343R D A Lp Q detail X c HE E v M A AB 0 1 2 mm scale X Plastic surface-mounted package; reverse pinning; 4 leads SOT343R w M B 97-05-21 06-03-16 bp UNIT max bp cD Eb1 HE Lp Qw v mm 0.11.1 0.8 0.4 0.3 0.25 0.10 0.7 0.5 2.2 1.8 1.35 1.15 e 2.2 2.01.3 0.2 y 0.10.21.15 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.23 0.13 A e y
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR DATA SHEET STATUS Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DISCLAIMERS Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
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NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for the marking codes and the package outline drawings which were updated to the latest version. Printed in The Netherlands R77/03/pp 15 Date of release: 2010 Sep 16