BF1102

BF1102 PHILIPS | Alldatasheet

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Technical content

Preliminary specification 1999 Jul 08 DISCRETE SEMICONDUCTORS BF1102 Dual N-channel dual gate MOS-FET ook, halfpage MBD128

1999 Jul 08 2

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102

FEATURES

• Two low noise gain controlled amplifiers in a single package
• Specially designed for 5 V applications
• Superior cross-modulation performance during AGC
• High forward transfer admittance
• High forward transfer admittance to input capacitance ratio.

APPLICATIONS

• Gain controlled low noise amplifier for VHF and UHF applications such as television tuners and professional communications equipment.

DESCRIPTION

The BF1102 is a combination of two equal dual gate MOS-FETs with shared source and gate 2 leads. The source and substrate are interconnected. An internal bias circuit enables DC stabilization and a very good cross-modulation performance at 5 V supply voltage. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. PINNING - SOT363 PIN DESCRIPTION 1 gate 1 (1) 2 gate 2 (1,2) 3d r a i n ( 1 ) 4d r a i n ( 2 ) 5 source (1,2) 6 gate 1 (2) Fig.1 Simplified outline and symbol. Marking code: W1. handbook, halfpage MBL029 AMP1 d (1)g1 (1) d (2)g1 (2) AMP2 g2 (1, 2) s (1, 2) 13 2 456 QUICK REFERENCE DATA Note 1. T s is the temperature at the soldering point of the source lead. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per MOS-FET unless otherwise specified VDS drain-source voltage −− 7V ID drain current (DC) −− 40 mA Ptot total power dissipation T s ≤ 102 °C; note 1 −− 200 mW yfs forward transfer admittance I D =1 5m A − 43 − mS Cig1-s input capacitance at gate 1 I D =1 5m A − 2.8 − pF Crss reverse transfer capacitance f = 1 MHz − 30 − fF F noise figure f = 800 MHz −− 2.8 dB Xmod cross-modulation input level for k = 1% at 40 dB AGC 100 −− dBµV Tj operating junction temperature −− 150 °C CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.

1999 Jul 08 3

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET unless otherwise specified VDS drain-source voltage − 7V ID drain current (DC) − 40 mA IG1 gate 1 current −± 10 mA IG2 gate 2 current −± 10 mA Ptot total power dissipation T s ≤ 102 °C − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − +150 °C SYMBOL PARAMETER VALUE UNIT Rth j-s thermal resistance from junction to soldering point 240 K/W Fig.2 Power derating curve. handbook, halfpage 0 50 100 200 250 200 MGS359 150 150 100 Ts (°C) Ptot (mW)

1999 Jul 08 4

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 STATIC CHARACTERISTICS Tj =2 5 °C unless otherwise specified. Notes 1. R G1 connects gate 1 to VGG =5V . DYNAMIC CHARACTERISTICS Common source; Tamb =2 5 °C; VG2-S =4V ; VDS =5V ; ID = 15 mA; unless otherwise specified. Notes 1. Not used MOS-FET: V G1-S =0 ; VDS =0 . 2. Measured in test circuit of Fig.17. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET unless otherwise specified V(BR)DSS drain-source breakdown voltage V G1-S =V G2-S =0 ; ID =1 0 µA7 − V V(BR)G1-SS gate-source breakdown voltage V GS =V DS =0 ; IG1-S =1 0m A 6 1 5 V V(BR)G2-SS gate-source breakdown voltage V GS =V DS =0 ; IG2-S =5m A 6 1 5 V V(F)S-G1 forward source-gate voltage V G2-S =V DS =0 ; IS-G1 = −10 mA 0.5 1.5 V V(F)S-G2 forward source-gate voltage V G1-S =V DS =0 ; IS-G2 = −10 mA 0.5 1.5 V VG1-S(th) gate-source threshold voltage V DS =5V ; VG2-S =4V ; ID =2 0 µA0 . 3 1 V VG2-S(th) gate-source threshold voltage V DS =5V ; VG1-S =4V ; ID =2 0 µA0 . 3 1 . 2 V IDSX drain-source current V G2-S =4V ; VDS =5V ; RG = 120 kΩ; note 1 12 20 mA IG1-S gate cut-off current V G1-S =5V ; VG2-S =V DS =0 − 50 nA IG2-S gate cut-off current V G2-S =5V ; VG1-S =V DS =0 − 20 nA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per MOS-FET unless otherwise specified (note 1) yfs forward transfer admittance T j =2 5 °C 3 64 35 0m S Cig1-ss input capacitance at gate 1 f = 1 MHz 2 2.8 3.6 pF Cig2-ss input capacitance at gate 2 f = 1 MHz −− 7p F Coss output capacitance f = 1 MHz − 1.6 2.5 pF Crss reverse transfer capacitance f = 1 MHz − 30 50 fF F noise figure f = 800 MHz; Y S =Y So p t − 22 . 8 d B Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw =5 0M H z ; funw =6 0M H z ; ( n o t e2 ) 85 −− dBµV input level for k = 1% at 40 dB AGC; fw =5 0M H z ; funw =6 0M H z ; ( n o t e2 ) 100 −− dBµV

1999 Jul 08 5

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 ALL GRAPHS FOR ONE MOS-FET Fig.3 Transfer characteristics; typical values. VDS =5V . Tj =2 5 °C. handbook, halfpage MGS360 VG1-S (V) 2.5 V 2 V 1.5 V 1 V 3.5 V 3 V VG2-S = 4 V ID (mA) Fig.4 Output characteristics; typical values. VG2-S =4V . Tj =2 5 °C. handbook, halfpage 01 0 MGS361 24 6 8 VDS (V) ID (mA) 1.4 V 1.3 V 1.2 V 1.1 V 1 V VG1-S = 1.5 V Fig.5 Gate 1 current as a function of gate 1 voltage; typical values. VDS =5V . Tj =2 5 °C. handbook, halfpage 160 120 0.5 2.5 MGS362 1 1.5 2 IG1 (µA) VG1-S (V) 2.5 V 2 V 3.5 V 3 V VG2-S = 4 V Fig.6 Forward transfer admittance as a function of drain current; typical values. VDS =5V . Tj =2 5 °C. handbook, halfpage 01 0 3 0 MGS363 ID (mA) |yfs| (mS)

3.5 V 3 V

VG2-S = 4 V 2.5 V 2 V

1999 Jul 08 6

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 Fig.7 Drain current as a function of gate 1 current; typical values. VDS =5V ; VG2-S =4V ; Tj =2 5 °C. handbook, halfpage 02 0 6 0 MGS364 ID (mA) IG1 (µA) Fig.8 Drain current as a function of gate 1 supply voltage (= VGG); typical values. VDS =5V ; VG2-S =4V ; Tj =2 5 °C. RG1 =1 2 0kΩ (connected to VGG); see Fig.17. handbook, halfpage MGS365 23 5 4 ID (mA) VGG (V) Fig.9 Drain current as a function of gate 1 (= V GG) and drain supply voltage; typical values. VG2-S =4V ; Tj =2 5 °C. RG1 connected to VGG; see Fig.17. handbook, halfpage 01 0 MGS366 2468 ID (mA) VGG = VDS (V) RG1 = 47 kΩ 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 180 kΩ 220 kΩ VDS =5V ; Tj =2 5 °C. RG1 =1 2 0kΩ (connected to VGG); see Fig.17. Fig.10 Drain current as a function of gate 2 voltage; typical values. handbook, halfpage 02 6 MGS367 VG2-S (V) ID (mA) 4.5 V 4 V 3.5 V 3 V VG1-S = 5 V

1999 Jul 08 7

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 Fig.11 Gate 1 current as a function of gate 2 voltage; typical values. VDS =5V ; Tj =2 5 °C. RG1 =1 2 0kΩ (connected to VGG); see Fig.17. handbook, halfpage MGS368 26 4 IG1 (µA) VG2-S (V) 4.5 V 4 V 3.5 V 3 V VG1-S = 5 V Fig.12 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values. VDS =5V ; VGG =5V ; fw =5 0M H z ; funw =6 0M H z ; Tamb =2 5 °C; RG1 =1 2 0kΩ (connected to VGG); see Fig.17. handbook, halfpage 02 0 6 0 120 110 100 MGS369 Vunw (dBµV) gain reduction (dB)

1999 Jul 08 8

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 Fig.13 Input admittance as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 5m A ; Tamb =2 5 °C. handbook, halfpage MGS370 102 10−1 10 10 2 103 f (MHz) yis (mS) bis gis Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 5m A ; Tamb =2 5 °C. handbook, halfpage MGS371 102 103 −ϕ rs (deg) 103 102 10 10 2 103 f (MHz) |yrs| (µS) ϕrs |yrs| Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 5m A ; Tamb =2 5 °C. handbook, halfpage MGS372 102 −ϕ fs (deg) 102 1010 10 10 2 103 f (MHz) |yfs| (mS) ϕfs |yfs| Fig.16 Output admittance as a function of frequency; typical values. VDS =5V ; VG2 =4V . ID =1 5m A ; Tamb =2 5 °C. handbook, halfpage MGS373 10−1 10 10 2 103 f (MHz) yos (mS) bos gos

1999 Jul 08 9

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 Fig.17 Cross-modulation test set-up (for one MOS-FET). handbook, full pagewidth DUT 4.7 nF 10 kΩ MGS315 4.7 nF ≈2.2 µH 4.7 nF RL 50 Ω VGG VAGC VDS RGEN 50 Ω VI 50 Ω 4.7 nF RG1

1999 Jul 08 10

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 PACKAGE OUTLINE REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT363 SC-88 wBMbp D e pin 1 index A Lp Q detail X HE E v M A AB y 01 2 m m scale c X 13 2 456 Plastic surface mounted package; 6 leads SOT363 UNIT A1 max bp cD E e1 HE Lp Qy wv mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.10.2 DIMENSIONS (mm are the original dimensions) 0.45 0.15 0.25 0.15 A 1.1 0.8 97-02-28

1999 Jul 08 11

Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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