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Technical content

Product speciﬁcation File under Discrete Semiconductors, SC07

1995 Apr 25

BF1100; BF1100R Dual-gate MOS-FETs

1995 Apr 25 2

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R

FEATURES

Specially designed for use at 9 to 12 V supply voltage
Short channel transistor with high forward transfer admittance to input capacitance ratio
Low noise gain controlled amplifier up to 1 GHz
Superior cross-modulation performance during AGC.

APPLICATIONS

VHF and UHF applications such as television tuners and professional communications equipment.

DESCRIPTION

Enhancement type field-effect transistor in a plastic microminiature SOT143 or SOT143R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. PINNING CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. PIN SYMBOL DESCRIPTION 1 s, b source 2 d drain 2 gate 2 4g 1 gate 1 Fig.1 Simplified outline (SOT143) and symbol. BF1100 marking code: M56. handbook, halfpage Top view MAM124 s,b d Fig.2 Simplified outline (SOT143R) and symbol. BF1100R marking code: M57. handbook, halfpage Top view MAM125 - 1 s,b d QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage −− 14 V ID drain current −− 30 mA Ptot total power dissipation −− 200 mW Tj operating junction temperature −− 150 °C yfs forward transfer admittance 24 28 33 mS C ig1-s input capacitance at gate 1 − 2.2 2.6 pF C rs reverse transfer capacitance f=1M H z − 25 35 fF F noise ﬁgure f = 800 MHz − 2 − dB

1995 Apr 25 3

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Note 1. Device mounted on a printed-circuit board. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 14 V ID drain current − 30 mA IG1 gate 1 current −± 10 mA IG2 gate 2 current −± 10 mA Ptot total power dissipation see Fig.3 BF1100 up to T amb =5 0°C; note 1− 200 mW BF1100R up to T amb =4 0°C; note 1− 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − +150 °C Fig.3 Power derating curves. handbook, halfpage 0 50 100 200 250 200 MLD155 150 150 100 Ptot (mW) T ( C)amb o BF1100R BF1100 Fig.4 Forward transfer admittance as a function of junction temperature; typical values. 50 0 50 150 MLD156 100 Y fs (mS) T ( C)j o

1995 Apr 25 4

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R THERMAL CHARACTERISTICS Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj=2 5°C; unless otherwise speciﬁed. Notes 1. R G1 connects gate 1 to VGG = 9 V; see Fig.27. 2. R G1 connects gate 1 to VGG = 12 V; see Fig.27. SYMBOL PARAMETER CONDITIONS VALUE UNIT R th j-a thermal resistance from junction to ambient note 1 BF1100 500 K/W BF1100R 550 K/W R th j-s thermal resistance from junction to soldering point note 2 BF1100 T s =9 2°C 290 K/W BF1100R T s =7 8°C 360 K/W SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)G1-SS gate 1-source breakdown voltage VG2-S =V DS = 0; IG1-S = 1 mA 13.2 20 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S =V DS = 0; IG2-S = 1 mA 13.2 20 V V(F)S-G1 forward source-gate 1 voltage V G2-S =V DS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage V G1-S =V DS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S =4V ; VDS =9V ; ID =2 0µA 0.3 1 V VG2-S =4V ; VDS =1 2V ; ID =2 0µA 0.3 1 V VG2-S(th) gate 2-source threshold voltage VG1-S =4V ; VDS =9V ; ID =2 0µA 0.3 1.2 V VG1-S =4V ; VDS =1 2V ; ID =2 0µA 0.3 1.2 V IDSX drain-source current V G2-S =4V ; VDS =9V ; R G1 = 180 kΩ ; note 1 81 3 m A VG2-S =4V ; VDS =1 2V ; R G1 = 250 kΩ ; note 2 81 3 m A IG1-SS gate 1 cut-off current V G2-S =V DS = 0; VG1-S =1 2V − 50 nA IG2-SS gate 2 cut-off current V G1-S =V DS = 0; VG2-S =1 2V − 50 nA

1995 Apr 25 5

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R DYNAMIC CHARACTERISTICS Common source; Tamb =2 5°C; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj=2 5°C VDS = 9 V 24 28 33 mS VDS = 12 V 24 28 33 mS C ig1-s input capacitance at gate 1 f = 1 MHz VDS =9V − 2.2 2.6 pF VDS =1 2V − 2.2 2.6 pF C ig2-s input capacitance at gate 2 f = 1 MHz VDS =9V − 1.6 − pF VDS =1 2V − 1.4 − pF C os drain-source capacitance f = 1 MHz VDS =9V − 1.4 1.8 pF VDS =1 2V − 1.1 1.5 pF C rs reverse transfer capacitance f = 1 MHz VDS =9V − 25 35 fF VDS =1 2V − 25 35 fF F noise ﬁgure f = 800 MHz; G S =G Sopt; BS =B Sopt VDS =9V − 2 2.8 dB VDS =1 2V − 2 2.8 dB Fig.5 Gain reduction as a function of the AGC voltage; typical values. f = 50 MHz. Tj=2 5°C. handbook, halfpage0 01234 V (V)AGC gain reduction (dB) MLD157 (1) RG = 250 kΩ to VGG =1 2V (2) RG = 180 kΩ to VGG =9V fw = 50 MHz; funw = 60 MHz; Tamb =2 5°C. Fig.6 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.27. handbook, halfpage 100 110 120 (1) (2) 10 20 30 40 50 Vunw (dBµV) gain reduction (dB) MLD158

1995 Apr 25 6

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R Fig.7 Output characteristics; typical values. VG2-S =4V . Tj=2 5°C. handbook, halfpage 41 6 MLD159 81 2 ID (mA) V (V)DS 1.3 V 1.2 V 1.1 V 1.0 V 0.9 V V = 1.4 VG1 S Fig.8 Transfer characteristics; typical values. VDS = 9 to 12 V. Tj=2 5°C. handbook, halfpage 0.4 2.0 MLD160 0.8 1.2 1.6 ID (mA) V (V)G1 S V = 4 V2.5 V 2 V 1.5 V 1 V G2 S 3 V Fig.9 Gate 1 current as a function of gate 1 voltage; typical values. VDS = 9 to 12 V. Tj=2 5°C. handbook, halfpage 0123 250 200 150 100 MLD161 IG1 (µA) V (V)G1 S 3 V 2.5 V 2 V 3.5 V V = 4 VG2 S Fig.10 Forward transfer admittance as a function of drain current; typical values. VDS = 9 to 12 V. Tj=2 5°C. handbook, halfpage 10 20 30 MLD162 yfs (mS) I (mA)D 3 V 2.5 V 2 V V = 4 VG2 S 3.5 V

1995 Apr 25 7

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R Fig.11 Drain current as a function of gate 1 current; typical values. VDS = 9 to 12 V. VG2-S =4V . Tj=2 5°C. handbook, halfpage 02 0 4 0 8 0 60 MLD163 I (µA)G1 ID (mA) Fig.12 Drain current as a function of gate 1 supply voltage (= VGG ) and drain supply voltage; typical values; see Fig.27. VG2-S =4V . R G1 connected to VGG . Tj=2 5°C. handbook, halfpage 48 1 6 MLD164 V = V (V)GG DS ID (mA) R = 100 kΩG1 147 kΩ 180 kΩ 205 kΩ 249 kΩ 301 kΩ 402 kΩ 511 kΩ Fig.13 Drain current as a function of gate 1 voltage (= VGG ); typical values; see Fig.27. VDS = 9 V; VG2-S =4V . R G1 = 180 kΩ (connected to VGG ); Tj=2 5°C. handbook, halfpage 02 4 1 0 86 MLD165 V (V)GG ID (mA) VDS = 12 V; VG2-S =4V . R G1 = 250 kΩ (connected to VGG ); Tj=2 5°C. Fig.14 Drain current as a function of gate 1 voltage; (= VGG ); typical values; see Fig.27. handbook, halfpage 048 1 2 MLD166 V (V)GG ID (mA)

1995 Apr 25 8

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R Fig.15 Gate 1 current as a function of gate 2 voltage; typical values. VDS =9V . R G1 = 180 kΩ (connected to VGG ). Tj=2 5°C. handbook, halfpage 0246 MLD167 IG1 (µA) V (V)G2 S 8 V 7 V 6 V 5 V 4 V V = 9 VGG Fig.16 Gate 1 current as a function of gate 2 voltage; typical values. VDS =1 2V . R G1 = 250 kΩ (connected to VGG ). Tj=2 5°C. handbook, halfpage 0246 MLD168 IG1 (µA) V (V)G2 S 11 V 10 V 9 V 8 V 7 V V = 12 VGG Fig.17 Drain current as a function of the gate 2 voltage; typical values; see Fig.27. VDS =9V . R G1 = 180 kΩ (connected to VGG ). Tj=2 5°C. handbook, halfpage 0246 MLD169 ID (mA) 8 V 7 V 6 V 5 V 4 V V = 9 VGG V (V)G2 S VDS =1 2V . R G1 = 250 kΩ (connected to VGG ). Tj=2 5°C. Fig.18 Drain current as a function of the gate 2 voltage; typical values; see Fig.27. handbook, halfpage 0246 MLD170 ID (mA) 11 V 10 V 9 V 8 V 7 V V = 12 VGG V (V)G2 S

1995 Apr 25 9

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R Fig.19 Input admittance as a function of frequency; typical values. VDS = 9 V; VG2 =4V . ID = 10 mA; Tamb =2 5°C. handbook, halfpage 103 MLD172 10210 10 1 10 2 yis (mS) f (MHz) bis gis VDS = 9 V; VG2 =4V . ID = 10 mA; Tamb =2 5°C. Fig.20 Reverse transfer admittance and phase as a function of frequency; typical values. 103 MLD173 10210 10 3 10 2 yrs 10 3 (µS) f (MHz) yrs rs (deg) ϕ rsϕ Fig.21 Forward transfer admittance and phase as a function of frequency; typical values. VDS = 9 V; VG2 =4V . ID = 10 mA; Tamb =2 5°C. 103 MLD174 10210 10 2 yfs (mS) yfs f (MHz) fs (deg) ϕ fsϕ Fig.22 Output admittance as a function of frequency; typical values. VDS = 9 V; VG2 =4V . ID =10 mA; Tamb =2 5°C. handbook, halfpage 103 MLD175 10210 10 1 10 2 yos (mS) f (MHz) bos gos

1995 Apr 25 10

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R Fig.23 Input admittance as a function of frequency; typical values. VDS = 12 V; VG2 =4V . ID = 10 mA; Tamb =2 5°C. handbook, halfpage 103 MLD176 10210 10 1 10 2 yis (mS) f (MHz) bis gis Fig.24 Reverse transfer admittance and phase as a function of frequency; typical values. VDS = 12 V; VG2 =4V . ID = 10 mA; Tamb =2 5°C. 103 MLD177 10210 10 3 10 2 yrs 10 3 (µS) f (MHz) yrs rs (deg) ϕ rsϕ Fig.25 Forward transfer admittance and phase as a function of frequency; typical values. VDS = 12 V; VG2 =4V . ID = 10 mA; Tamb =2 5°C. 103 MLD178 10210 10 2 yfs (mS) yfs f (MHz) fs (deg) ϕ fsϕ Fig.26 Output admittance as a function of frequency; typical values. VDS = 12 V; VG2 =4V . ID = 10 mA; Tamb =2 5°C. handbook, halfpage 103 MLD179 10210 10 1 10 2 yos (mS) f (MHz) bos gos

1995 Apr 25 11

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R Fig.27 Cross-modulation test set-up. For VGG =V DS = 9 V, RG = 180 kΩ . For VGG =V DS = 12 V, RG = 250 kΩ. handbook, full pagewidth DUT VAGC 4.7 nF 10 kΩ MGC420 4.7 nF 450 nH C3 12 pF R L 50 Ω≈ VGG V DS R GEN V I 4.7 nF R GΩ Ω

1995 Apr 25 12

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R Table 1 Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID =1 0m A Table 2 Noise data: VDS = 9 V; VG2-S = 4 V; ID =1 0m A Table 3 Scattering parameters: VDS = 12 V; VG2-S = 4 V; ID =1 0m A Table 4 Noise data: VDS = 12 V; VG2-S = 4 V; ID =1 0m A f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) Fmin (dB) Γopt rn (ratio) (deg) 800 2.00 0.67 43.9 0.89 f (MHz) s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) f (MHz) Fmin (dB) Γopt rn (ratio) (deg) 800 2.00 0.66 43.3 0.97

1995 Apr 25 13

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R PACKAGE OUTLINES Fig.28 SOT143. Dimensions in mm. handbook, full pagewidth MBC845 max o max o max o 1.1 max 0.75 0.60 0.150 0.090 0.1 max M0.1 AB0 0.10.48 TOP VIEW 1.4 1.2 2.5 max 3.0 2.8 M0.2 ABA B 1.9 0.10.88 1.7 Fig.29 SOT143R. Dimensions in mm. handbook, full pagewidth MBC844 max o max o max o 1.1 max 0.40 0.25 0.150 0.090 0.1 max 1.4 1.2 2.5 max 3.0 2.8 A B 1.9 M0.2 A M0.1 B TOP VIEW 0.48 0.38 0.88 0.78 1.7

1995 Apr 25 14

Philips Semiconductors Product speciﬁcation Dual-gate MOS-FETs BF1100; BF1100R DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. Data Sheet Status Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

Product Information

BF1100 specifications and overview.

Summary

Dual-gate MOS-FETs 1995 Apr 25

Description

Dual-gate MOS-FETs 1995 Apr 25

Source title BF1100 Datasheet(PDF) - NXP Semiconductors

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