BD85506F

Rohm

High Efficiency / Low Standby Power 2-Channel Secondary Side Synchronous Rectification Control IC

Manufacturer: Rohm

Document: 37 Pages / 2Mb

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PDF pages: 37

Technical content

Features

 Internal FET Abnormality D etection Function for Secondary Side Synchronous Rectification.  Internal Overvoltage Detection Circuit (OVP) . (Externally adjustable, high accuracy: 2 %)  Efficiency Improvement by FET OFF Threshold Voltage is Adjustable.  Source of each FET c an be individually monitored.  Internal Standby Mode Automatic Determination Function.  Internal Multipurpose Comparator . (It can also b e used as a shunt regulator)  With the Slow Start Function, i t is possible to set the FET Abnormality Detection Function at startup and the during the start of Switching Operation  Wide Input Voltage R ange 5.0 V to 32 V  D1, D2 P in 120 V (Max) Breakdown Voltage  Flow Compatible SOP14 Package Key Specifications  Input Voltage Range: 5.0 V to 32 V  Operating Circuit Current (SW Stopped Mode): 800 µA(Typ)  Standby Circuit Current : 300 µA(Typ)  Drain Monitor Pin Absolute Voltage: 120 V(Max)  Operating Temperature Range: -40 °C to +105 °C Package W(Typ) x D(Typ) x H(Max) SOP14 8.70 mm x 6.20 mm x 1.71 mm

Applications

Isolated LLC Type AC/DC Power Supply. Adapter, TV, Printer, Office Equipment, etc. Typical Application Circuits (Remark) The values in the datasheet are typical unless otherwise specified. Datasheet

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 SH_OUT SH_IN REG SS TH VCC AGND OVP Pin Configuration Pin Descriptions Pin No. Pin Name Function

1 VCC Power supply input pin

2 REG Regulator output pin for driver

3 SH_IN Multi-purpose comparator input pin/ENABLE input pin

4 SH_OUT Multi-purpose comparator output pin/FAIL output pin when abnormality is detected

5 AGND Analog GND

6 TH FET OFF Threshold setting pin

7 SS Mask time setting pin of drive and FET abnormality detection function at start up.

8 D2 Channel 2 Drain signal input pin

9 S2 Channel 2 Source signal input pin

10 G2 Channel 2 Gate drive signal output pin

11 OVP Overvoltage detection setting pin

12 G1 Channel 1 Gate drive signal output pin

13 S1 Channel 1 Source signal input pin

14 D1 Channel 1 Drain signal input pin

(TOP VIEW) Pin Configuration

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 0.8V COMP OUT GND Primary Side Controller PC2: Latch Protection -120mV S Q R Driver SH_OUT SET COMP RESET COMP Auto Standby Block AGND SH_IN VCC OVP Driver 120V Clamper SS TH OFF Threshold Block LDO Block TSD OVP COMPS QD FET OPEN COUNTER REG 2.5mA CSS ROVP RTH 20k 0.5V FET Abnormal Protection Block CREG 120V Clamper 50µA CVCC PC1 PC2 PC1: FeedBack 300k 0.4V ENABLE COMP 0.5V SS COMP S Q D 2ch Synchronous Rectification Controller Block VCC_UVLO Block SYSTEM ON/OFF RVCC Block Diagram

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 SET COMP ON ONG1 -120mV RESET COMP ON -120mV -6mV VOUT -6mV ON I_FET1 -6mV -6mV -120mV -6mV VOUT I_FET2 -6mV-6mV-6mV ON -120mV G2 0V ON ON Description of Blocks 1. SET COMP Block Monitors D1 and D2 pin voltages and outputs a signal to turn ON the FET by detecting -120 mV or less. 2. RESET COMP Block Monitors D1 and D2 pin voltages and outputs a signal to turn OFF the FET by detecting a voltage greater than the set voltage at the TH pin. 3. OFF Threshold Block Sets the D1 and D2 voltages to turn OFF the FET by setting the TH pin resistance. (D1 and D2 become the same setting) The ON/OFF sequence of secondary side synchronous rectification is shown below. (Shown in the example below is for setting the TH pin to 200 kΩ, -6 mV setting)

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 200µs 4096pulse STATE STANDBY ACTIVE ACTIVE Description of Blocks – continued 4. Auto Standby Block By detecting the presence or absence of the D1 and D2 pin pulses, the synchronous rectification operation is automatically operated or stopped, respectively. If a pulse is not detected on the D1 and D2 pins within 200 µs, the chip enters its standby state and the synchronous rectification operation is stopped. After a total of 4096 pulses is detected on the D1 and D2 pins, the chip becomes active and resumes the synchronous rectification action. 5.COMP Block This is a multipurpose comparator. It can be used as a comparator in various voltage detection applications such as set temperature monitoring and voltage monitoring. It can also be used as a low -consumption shunt regulator via feedback operation. 6. ENABLE COMP Block This comparator is for turning ON or OFF the synchronous rectification. When the SH_IN pin goes below or equal to 0.4 V, the SS pin capacitor is discharged and the synchronous rectification operation, G pin OPEN detection, and D pin OPEN detection functions are also stopped. 7. OVP Block This is the overvoltage detection block for the output voltage. Since the lower 20 kΩ resistor is built-in, the detection voltage can be adjusted by connecting a resistor between the detection node and the OVP pin. After OVP is detected, a FAIL signal (constant current sink of 2.5 mA) is output from the SH_OUT pin. When the OVP release voltage is reached or when VCC_UVLO is detected, the constant current sink from SH_OUT is stopped. 8. LDO Block This is the IC internal power supply generation block. The driver power supply is output at the REG pin, and stable operation is obtained by connecting a ceramic capacitor on its output. 9. SS COMP Block Slow start block that sets the operation start time for startup, synchronous rectification, G pin OPEN detection, and D pin OPEN detection functions. When VCC UVLO has been cancelled, a constant current of 50µA is output from the SS pin and its capacitor is charged. When the SS pin voltage reaches at least 0.5V, the following operation takes place: (a) If the SH_IN pin voltage≥0.4 V then the SS pin capacitor continues charging. Synchronous rectification and G, D pin OPEN detection functions start operating. (b) If the SH_IN pin voltage < 0.4 V then the SS pin capacitor discharges. Charging of the SS pin capacitor starts again after the SH_IN pin voltage≥0.4 V. If the SS pin reaches SS≥0.5V, synchronous rectification and G and D pin OPEN detection functions start operating. For more details, refer to "The SS pin discharge function by SH_IN voltage" in "Application Part Selection Method". 10. FET Abnormal Protection Block This block is for the detection of any of the abnormal FET conditions listed below. (a) One of the G1 and G2 pins is OPEN and the FET is Body Diode rectified; (b) One of the D1 and D2 pins is OPEN and the FET is Body Diode rectified; (c) One of the S1 and S2 pins is set to OPEN, and the OFF timing of the FET is abnormal. When detecting these conditions, the FAIL signal (constant current sink of 2.5 mA) is output from the SH_OUT pin. For details of each abnormality detection operation, refer to "Abnormality detection function" of "Application circuit".

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Absolute Maximum Ratings (Ta=25 °C) Parameter Symbol Rating Unit VCC Pin VMAX_VCC -0.3 to +40 V OVP Pin VMAX_OVP -0.3 to +40 V SH_IN Pin VMAX_SH_IN -0.3 to +40 V SH_OUT Pin VMAX_SH_OUT -0.3 to +VCC V G1, G2 Pin VMAX_G1, VMAX_G2 -0.3 to +15 V D1, D2 Pin VMAX_D1, VMAX_D2 +120(Note 1) V REG Pin VMAX_REG -0.3 to +15 V SS Pin VSS -0.3 to +5.5 V TH Pin VMAX_TH -0.3 to +5.5 V Maximum Junction Temperature Tjmax +150 °C Storage Temperature Range Tstg -55 to +150 °C Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in de terioration of the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing board size and copper area so as not to exceed the maximum junction temperature rating. (Note 1) When negative voltage is applied, current flows through the ESD protection element. A current limiting resistor is required for D1 and D2 pins so that the current through these pins is 6 mA or less. Thermal Resistance (Note 2) Parameter Symbol Thermal Resistance (Typ) Unit 1s(Note 4) 2s2p(Note 5) SOP14 Junction-to-Ambient θJA 166.5 108.1 °C/W Junction-to-T op Characterization Parameter(Note 3) ΨJT 26 22 °C/W (Note 2) Based on JESD51-2A (still air). (Note 3) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface of the component package. (Note 4) Using a PCB board based on JESD51-3. (Note 5) Using a PCB board based on JESD51-7. Layer Number of Measurement Board Material Board Size Single FR-4 114.3 mm x 76.2 mm x 1.57 mmt Top Copper Pattern Thickness Footprints and Traces 70 μm Layer Number of Measurement Board Material Board Size 4 Layers FR-4 114.3 mm x 76.2 mm x 1.6 mmt Top 2 Internal Layers Bottom Copper Pattern Thickness Copper Pattern Thickness Copper Pattern Thickness Footprints and Traces 70 μm 74.2 mm x 74.2 mm 35 μm 74.2 mm x 74.2 mm 70 μm

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Power Supply Voltage Range VCC 5.0 20 32 V Operating Temperature Topr -40 +25 +105 °C VCC Capacitor Range(Note 6) CVCC 2.2 4.7 - µF VCC Resistor Range RVCC 100 200 - Ω TH Resistor Range RTH 12 200 330 kΩ REG Capacitor Range(Note 6) CREG 0.47 1.0 2.2 µF (Note 6) Determine a capacitance value considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and others

Electrical Characteristics

(Unless otherwise specified VCC=20 V, VSH_IN=0.6 V, Ta=25 °C) Parameter Symbol Min Typ Max Unit Conditions Circuit Current Item Switching Operation Circuit Current ION 0.5 1 2 mA fsw=50 kHz Switching State Gx=OPEN Standby Circuit Current ISTB 180 300 480 μA Standby State Switching Stopped Circuit Current IACT 450 800 1400 μA Switching Stop State Circuit Current at VCC UVLO Detection IOFF 120 180 300 μA VCC=3.5 V VCC UVLO BLOCK VCC UVLO Threshold Voltage 1 VUVLO1 4.1 4.5 4.9 V VCC Sweep Up VCC UVLO Threshold Voltage 2 VUVLO2 3.9 4.3 4.7 V VCC Sweep Down Slow Start BLOCK Slow Start Completion Voltage VSS 0.4 0.5 0.6 V VSS=0 V→1 V, VSH_IN=0.6 V Slow Start Charge Current ISS -60 -50 -40 µA VSS=0.3 V, VSH_IN=0.6 V Synchronous Rectifier Controller BLOCK GATE ON Threshold Voltage VGON -180 -120 -60 mV VDx=+300 mV→-600 mV GATE OFF Threshold Voltage VGOFF -10 -6 -1 mV VDx=-600 mV→+300 mV RTH=200 kΩ Standby State Automatic Detection BLOCK Standby State Detection Time tSTB 100 200 300 µs D1, D2 Stop Pulse Number of Waiting State Release Pulses PACT - 4096 - Pulse D1, D2 total Pulse Number DRAIN Monitor BLOCK D1, D2 Pin Sink Current ID_SINK 120 270 450 μA VDx=120 V D1, D2 Pin Source Current ID_SO -8 -5 -1 μA VDx=-0.6 V→-0.05 V Driver BLOCK REG Pin Output Voltage VREG 11 12 13 V Switching Stop State REG Pin Maximum Output Current IMAX_REG 20 - - mA VCC=20 V, VREG=0 V High Side FET ON Resistance RHONR 0.7 1.5 3.0 Ω IOUT= -10 mA Low Side FET ON Resistance RLONR 0.5 0.9 1.6 Ω IOUT= +10 mA G1, G2 Pin Turn On Delay Time tDELAY_ON - 90 - ns VDx=5 V→-0.3 V G1, G2 Pin Turn Off Delay Time tDELAY_OFF - 100 - ns VDx=-0.3 V→5 V (Gx, Dx, Sx means x = 1 or 2)

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Electrical Characteristics – continued (Unless otherwise specified VCC=20 V, VSH_IN=0.6 V, Ta=25 °C) Parameter Symbol Min Typ Max Unit Conditions COMP BLOCK Reference Voltage VSH_REF 0.792 0.8 0.808 V Reference Voltage Temperature Change VSHTEMP - -8 - mV Ta=25 °C→105 °C Reference Input Current ISH_IN -0.2 0 +0.2 μA VSH_IN=2 V SH_OUT Pin Current at SH_IN=L ISH_OUT 5 10 20 μA VSH_OUT=20 V, VSH_IN=0 V SH_OUT Sink Current ISH_SINK 10 - - mA VSH_IN=0.85 V, VSH_OUT=5.0 V Abnormality Detection BLOCK Overvoltage Detection Voltage VOVP_TH1 20.58 21.0 21.42 V ROVP=820 kΩ VCC Sweep Up Overvoltage Release Voltage VOVP_TH2 9 10 11 V ROVP=820 kΩ VCC Sweep Down G Pin OPEN Detection Voltage VGOP_TH -405 -325 -245 mV VDx=0 mV→-500 mV G Pin OPEN Detection Timing tGOP 2 2.5 3.5 µs G Pin OPEN Count Complete Pulse Number PGOP - 2048 - Pulse D1 and D2 Pin Number of Pulses D Pin OPEN Detection Voltage VDOP_TH 1.7 2.0 2.3 V VDx=3 V→1 V D Pin OPEN Count Complete Pulse Number PDOP - 128 - Pulse Dx Pin Connected Number of Pulses. S Pin OPEN Detection Voltage VSOP_TH 200 300 400 mV VSx=0 mV→500 mV SH_OUT Sink Current at Abnormality Mode ISH_OUT_PRO 1.2 2.5 4.2 mA VSH_OUT=5 V, VSH_IN=0.6 V REG Pin Discharge Resistance RREG_DIS 1.2 2.2 3.2 kΩ VREG=1 mA (Gx, Dx, Sx means x = 1 or 2)

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 OUT GND SH_IN VCC REG Primary Side Controller PC1 BD85506F PC1 PC1: FeedBack SS Timing Chart The startup sequence is shown below. (1) Primary side controller starts, pulses input to pins D1, D2 secondary side. (2) VCC(=VOUT)Voltage is boosted. (3) When VCC reaches 4.5 V, V CC_UVLO is released and SS pin capacitor starts charging. (4) After VCC_UVLO is released, Startup REG outputs by inputting four pulses to D1 and D2. (5) When SS reaches 0.5 V, if SH_IN≥0.4 V, SR control, Gate Open detection and Drain Open detection functions start. (1) Primary side controller starts, pulses input to pins D1, D2 secondary side. (2) VCC(=VOUT)Voltage is boosted (3) When VCC reaches 4.5 V, VCC_UVLO is released and SS pin capacitor starts charging. (4) After VCC_UVLO is released, Startup REG outputs by inputting four pulses to D1 and D2. (5) When SS reaches 0.5 V, if SH_IN<0.4 V, SS pin capacitor discharges. (6) When SH_IN reaches 0.4 V, SS pin capacitor starts charging again. (7) After reaching SS ≥0.5 V, SR control, Gate Open detection and Drain Open detection functions start. Startup Sequence SH_IN≥0.4 V at SS≥0.5 V Startup Sequence SH_IN<0.4 V at SS≥0.5 V (3) (2) (5) (1) (4) VCC 4.5 V REG 12 V SS 0.5 V Gate Open Detection Drain Open Detection ACTSTOP SH_IN 0.4 V SH_IN≥0.4 V (3) (2) (5) (6) (7) (4) (1) VCC 4.5 V REG 12 V SS 0.5 V ACTSTOP SH_IN 0.4 V SH_IN<0.4 V 0.5 V Gate Open Detection Drain Open Detection

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Application Examples 1. Abnormality Detection Function In secondary side synchronous rectification, if the connection between the IC and the FET becomes OPEN due to mounting failure or similar conditions wherein the FET cannot be driven, and even if the FET cannot be operated through switching, the FET can still be rectified by its body diode and output. However, when a heavy load is applied, the power loss increases in the body diode, causing abnormal heat generation. In order to prevent this abnormal heat generati on, the safety of the circuit can be secured by the FET abnormality detection function built-in this IC. (Body diode rectification operation is a failure mode which is difficult to detect because both voltage and current are output normally) In addition, OVP comparators and multipurpose comparators are also built-in, so it is possible to detect abnormality on the secondary side. List of Abnormality Detection Function and Purpose No. Abnormality Detection Function Name Detection State Abnormal Operation Detection Purpose

1 G Pin OPEN

Either G1 or G2 in is disconnected from secondary side SR FET FET body diode rectification due to stoppage of FET drive Prevent abnormal heat generation of rectifier FET

2 D Pin OPEN

disconnected from secondary side SR FET FET body diode rectification due to stoppage of FET drive Prevent abnormal heat generation of rectifier FET

3 S Pin OPEN

disconnected from secondary side SR FET Reverse FET current due to off threshold fluctuation FET destruction protection

4 OVP Detection Overvoltage Abnormal boost up Breakdown voltage

5 COMP Detection multi-purpose - -

Detection method and return method of each abnormality detection function (Gx, Dx, Sx means x = 1 or 2) No Abnormality Detection Function Name Detection Condition Mask Condition of Abnormality Detection Action of after Confirming Abnormality Detection Reset Condition *2.5 µs after Gx=ON *Dx voltage <-0.325 V *SS<0.5 V *Total D1+D2 =2048 pulse continuously *2.5 mA sink from SH_OUT VCC_UVLO detection Detection Dx<2.0 V *SS<0.5 V *Continuous detection while Dx=128 pulse *2.5 mA sink from SH_OUT *Driver stop *SS discharge *REG discharge VCC_UVLO detection Detection Sx>0.3 V Continuous for 9 µs *2.5 mA sink from SH_OUT *Driver stop *SS discharge *REG discharge VCC_UVLO detection

4 OVP

setting voltage Continuous for 25 µs *2.5 mA sink from SH_OUT *SS, REG discharge and SR stop Reach OVP cancel voltage or VCC UVLO detection

5 COMP

Detection SH_IN>0.8 V - *Sink current from SH_OUT Restore

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 FET GATE2 I_FET2D2 FET GATE1 I_FET1 2.5µs 2.5µs -0.325V 2.5µs 2.5µs (C) (B) Abnormality Detection Function – continued (1) Detection method of G1, G2 OPEN When one of the G1 and G2 pins of the IC becomes OPEN or when the parts connected to the FET are disconnected, and even if the FET cannot be operated through switching, the FET will still be able to output normally through Body diode rectification operation. However, when heavy load is applied, the power loss at body diode increases and may cause abnormal heat generation. This condition can be detected through the G pin OPEN detection function. Below is a block diagram with an example for G pin OPEN detection operation. Example of abnormality detection operation Circuit configuration: A circuit that causes the PC2 to latch and stop on the primary side after detection of abnormality. Abnormal condition: G1 is OPEN. A: G1=OPEN B: The FET is always turned OFF and its body diode performs rectification. When I_FET1 flows, the voltage between the Drain and Source of the FET becomes Vf. C: D1 voltage is monitored after 2.5 µs from the time G1 turns ON. Detected G1 OPEN state at less than -0.325 V. D: G1 OPEN detection confirmed when 2048 pulses are continuously detected. (Count resets when D1 voltage becomes -0.325 V or more even at 1 pulse) E: Sinks the current from SH_OUT and stops the primary side via the photo coupler (PC2). (In case of G pin OPEN detection, synchronous rectification operation is not stopped) (A) (B) (E) (C) (D) OUT GND S Q R Driver SH_OUT SH_IN VCC Driver S QD GATE OPEN COUNTER REG 2.5µs ONE SHOT PULSE 2.5mA -0.325V GATE OPEN_DETECT COMP UVLO UVLO UVLO SR CONTROLLER 2.5µsIN OUT SELECTOR SELECTOR BODY DIODE I_FET1 Primary Side LLC Controller PC2: Latch Protection PC1: FeedBack I_FET2 PC2 PC1 120V Clamper 120V Clamper

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 OUT GND Driver SH_OUT SH_IN VCC Driver DRAIN OPEN COUNTER REG 2.5mA 2.0V DRAIN OPEN_DETECT COMP UVLO UVLO UVLO SR CONTROLLER SELECTOR SELECTOR BODY DIODE I_FET1 Primary Side LLC Controller PC2: Latch Protection PC1: FeedBack I_FET2 PC1 2.0V CH2 CH1 S Q R 120V Clamper 120V Clamper D Q RS SS PC2 (A) (D) (C) (B) FET GATE1 D1SH_OUT D2 2.0V REG SS REG SS 128pulse (A) (B) (C) (D) Abnormality Detection Function – continued (2) Detection method of D1, D2 OPEN Likewise, if one of the D1 and D2 pins of the IC becomes OPEN or when the parts connected to the FET are disconnected, the FET cannot be operated through switching, causing abnormal heat generation. But this IC is able to detect such abnormalities through its D pin OPEN detection function. Below is a block diagram with an example for D pin OPEN detection operation. Example of abnormality detection operation Circuit configuration: A circuit that causes the PC2 to latch and stop on the primary side after detection of abnormality. Abnormal condition: D1 is OPEN. A: No signal input when D1 = OPEN. B: D1<2.0 V, chip detects D1 OPEN and starts counting. C: D1 OPEN detection is confirmed when D1<2.0 V continuously when the input pulse count at D2 reaches 128. (Count resets when D1 becomes 2.0 V or more even at 1 pulse) D: Sinks the current from SH_OUT and stops the primary side via the photo coupler (PC2). Synchronous rectification drive is stopped, discharging the REG and SS pin capacitor.

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 OUT GND Driver SH_OUT SH_IN VCC Driver REG 2.5mA UVLO UVLO SELECTOR SELECTOR I_FET1 Primary Side LLC Controller PC2: Latch Protection PC1: FeedBack I_FET2 PC1 S Q R 120V Clamper 120V Clamper D Q RS SS SET COMP -0.12V RESET COMP -6mV At TH=200kΩ GND -0.3V SOURCE COMP 9µs DELAY SELECTOR Vf UVLO PC2 Circuit Current (A) (D) (B) (C) -6 mV→+Vf Regarding Abnormality Detection Function – continued (3) Detection method of S1, S2 OPEN When either S1 or S2 pin becomes OPEN, the S pin voltage rises by +Vf due to the circuit current. Therefore, since the reference voltage of RESET COMP is also +Vf, it is not able to turn OFF the FET, which may lead to breakdown due to FET reverse current. With this IC, S pin OPEN detection function prevents this FET from being destroyed, ensuring safety of the circuit. Below is a block diagram with an example for S pin OPEN detection operation. Example of abnormality detection operation Circuit configuration: A circuit that causes the PC2 to latch and stop on the primary side after detection of abnormality. Abnormal state: When S1 is set to OPEN. A: When S1=OPEN, S1 voltage increases for +Vf when G1=H. The voltage becomes S1≥0.3 V. (OFF threshold= - 6 mV should also add +Vf. G1 cannot be turned off) B: S1 OPEN is detected and counting starts. C: After 9 µs of continuous detection, the S1 open state is confirmed. D: Sinks the current from SH_OUT and stops the primary side via the photo coupler (PC 2). Synchronous rectification drive is stopped, discharging the REG and SS pin capacitors. In the S1, S2 OPEN state, FET may be destroyed by current backflow. This is the system to stop the switching operation quickly. Therefore, there is no pulse count, and the protection function is independent of the slow start function. (C) (B) (A) (D) FET GATE1 I_FET1D1,S1 T>9µs SH_OUT S1=0.3V

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 OUT GND Driver SH_OUT VCC Driver I_FET1 Primary Side LLC Controller PC2: Latch Protection PC1: FeedBack I_FET2 PC1 120V Clamper 120V Clamper OVP COMP 2.5mA OVP 0.5V/0.25V 20k 25µs Delay REG UVLO SS SR CONTROLLER + 0.5V/0.45V PC2 (A) (E) (C) (F) (D) VOUT Shunt Regulator REF SH_OUT sink CurrentSSFET GATE1 0.45V (A) (C) (B) (E) (D) (F) Regarding Abnormality Detection Function – continued (4) Detection method of overvoltage (OVP) It is possible to detect when overvoltage has occurred due to abnormal feedback operation. The accuracy is within 2 %, with high precision, and the mask period is set to 25 µs. Overvoltage detection can be set only by adjusting the upper resistance since the lower resistor is built-in. Below is a block diagram with an example of OVP detection operation. Example of abnormality detection operation Circuit configuration: A circuit that causes the PC2 to latch and stop on the primary side after detection of abnormality. Abnormal state: When abnormally boosted. A: The lower resistor of the shunt regulator shorts to GND. B: The output voltage abnormally boosts. C: The OVP detection voltage is reached. D: OVP state is confirmed if abnormality persists for 25 µs. E: Stops the primary side by current sink from SH_OUT, and discharges REG and SS pin capacitors. F: SR Driver is stopped when SS voltage reach SS≤0.45 V. OVP detection has hysteresis, and it is canceled with 1/2 of the OVP detection voltage. However, if VCC_UVLO is detected first, VCC_UVLO takes precedence and OVP detection is canceled. OVP detection is controlled independently of the slow start function.

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Regarding Abnormality Detection Function – continued (5) Multipurpose COMP detection method The multipurpose comparator can use the SH_IN pin as an input pin. In the example below, it forms a circuit that detects temperature abnormality of a set using a positive characteristic thermistor. Below is a block diagram with an example of detection operation by COMP. Example of abnormality detection operation Circuit configuration: A positive characteristic thermistor is used as a heat detecting element. An example of a circuit is also shown for latching stop on the primary side by PC2 after detection of abnormality. Abnormal condition: Abnormal heat generation. A: The temperature rises and the positive characteristic thermistor resistance value rises. The SH_IN voltage rises. B: The SH_IN pin voltage reaches 0.8 V or more. C: Comparator output drives the photo coupler (PC2) and stops the primary side. The detection precision of COMP is as high as 1 %, there is no mask period and no hysteresis. Since the SH_IN pin is also used as ENABLE, input setting should be made so that SH_IN≥0.48 V during normal operation. And COMP is controlled independently of the slow start function. (C) (B) (A) OUT GND Driver SH_OUT Driver I_FET1 Primary Side LLC Controller PC2: Latch Protection PC1: FeedBack I_FET2 PC1 120V Clamper 120V Clamper SH_IN REG 0.8V COMP SS 50µA 0.4V ENABLE COMP SR CONTROLLER VCC PC2

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 OUT GND SH_IN OVP REG Primary Side Controller BD85506F PC1 PC2 PC2: Latch Protection PC1: FeedBack VCC SH_OUT VOUT SH_IN DRAIN2 I_SH_OUT Sink Current GATE2 DRAIN1 GATE1 0.6V SS 4.3V 0.35V (A) (C) (B) (E) (G) (F) (D) 2.Setting After Abnormality Detection Depending on the application, operation after abnormality detection can be in any of the following: latch protection, auto restart protection, judgment only signal output, or unused. These application circuits and operation methods will be explained in the following sections. (1) Example of latch protection application If there is a latch stop protection function on the primary side, the circuit sends a signal to the primary side via the photo coupler and stops the primary side. Below is a latch protection application circuit and a sequence example. G2 Example of OPEN protection operation sequence A: G2 is OPEN. B: Count for G2 OPEN detection state. C: Count of 2048 pulses completes. D: Constant current sink from SH_OUT. E: VOUT drops with primary side latch stop by PC2. F: SH_IN≤0.35 V, discharge SS and REG. G: VCC_UVLO is detected at VCC ≤ 4.3 V and secondary side stops. Primary side latched due to drive PC2 after detection

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 OUT GND SH_OUT SH_IN VCC OVP REG Primary Side Controller PC1 BD85506F PC1 PC1: FeedBack OUT GND SH_OUT SH_IN VCC OVP REG Primary Side Controller PC1 BD85506F PC1 SHUNT REGULATORPC1: FeedBack VOUT VCC SH_IN DRAIN2 SS GATE2 DRAIN1 GATE1 0.5V 0.5V VCC=4.3V 0.6V 0.6V VCC=4.3V I_SH_OUT VCC=4.5V VCC=4.5V 0.35V 0.35V 2.5mA 2.5mA (C) (B) (A) (F) (E) (I) (H) (G) (J) (D) Setting After Abnormality Detection – continued (2) Auto restart application example In this method, function does not stop completely after abnormality detection. In the detection period, the output toggles between ON and OFF, and if the state returns to normal, the circuit resumes normal operation after detection of UVLO. Below are examples of application circuits and sequence examples for auto restart protection. (Below is an example of use of the primary side control IC which completely stops when current is forcibly passed to the feedback photo coupler PC1) Example for G2 OPEN protection operation sequence A: G2 is OPEN. B: Count for G2 OPEN detection state starts. C: Count of 2048 pulses completes. D: Constant current sink from SH_OUT. E: PC1 stops primary side and VOUT drops. F: VCC holds voltage by Diode and capacitor and secures stop time (heat dissipation time). G: SH_IN≤0.35 V, discharge SS and REG. H: VCC≤VCC_UVLO is detected at 4.3 V. SH_OUT Sink current stops, primary side restarts. I: VCC≥4.5 V, Releases VCC_UVLO and starts SS charging. J: SS reaches 0.5 V, synchronous rectification, G, D pin open detection function, operation starts. Return to B. Example of auto restart application circuit when COMP is used as shunt regulator. Example of auto restart application circuit when using an external shunt regulator. For this application, COMP cannot be used as protection

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 SS + SS_COMP 50µA 0.5V SR Controller D1,2 G1,2 VOUT 4.5V SS 0.5V SH_IN 0.4V Selection of External Components 1. SS Pin Setting Set the operation start time of the G pin OPEN detection, D pin OPEN detection, and secondary side synchronous rectification at the startup time by the capacitance value connected to the SS pin. When the SH_IN pin voltage reaches VCC≥4.5 V, charging starts with a constant current of 50 µA to the SS pin capacitor. When the SS pin voltage VSS≥0.5 V is reached, secondary side synchronous rectification operation and G, D pin OPEN detection function start operating. The formula for setting SS time tSS and capacitance CSS is 𝑡𝑆𝑆(𝑠) 0.5(𝑉) [F] As an example, the capacitance value for canceling slow start after 5 ms: 5×10−3(𝑠) 0.5(𝑉) = 0.5 [µF] In addition, it is also effective to connect a pull-down resistor to make the slow start time longer. The slow start time for this is expressed by the following formula. 𝐶𝑠𝑠 = − 𝑡𝑆𝑆(𝑠) 𝑅𝑆𝑆(𝛺)×𝑙𝑛(1− 𝑉𝑆𝑆(𝑉) 𝑅𝑆𝑆(𝛺)×𝐼𝑆𝑆(𝐴)) [F] Calculation example The CSS capacitance for tSS=140 ms, RSS=20 kΩ, VSS=0.5 V, ISS=50 µA is: 𝐶𝑠𝑠 = − 0.14(𝑠) ≅ 10 [µF] However, please set the resistance value of RSS so as to exceed the slow start completion voltage VSS taking to account tolerances of values. Pull Down Resistor

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 0 50 100 150 200 250 300 350 GATE OFF Threshold Voltage VGOFF [mV] TH Pin Resistor R TH [kΩ] OUT GND SH_OUT OVP - OVP BLOCK2.5mA20k ROVP 0.5V ONG1 0V -120mV -120mV VOUT ON I_FET1 Application Part Selection Method – continued 2. OVP Pin Setting Since the lower resistor (20 kΩ) is built-in the OVP pin, it is possible to set the detection voltage by adjusting the resistance between the detection node and OVP pin. After OVP detection, current sinks from SH_OUT. OVP detection theoretical voltage formula 𝑅𝑂𝑉𝑃 = 𝑉𝑂𝑉𝑃_𝑇𝐻1(𝑉) Calculation example The set resistance value ROVP when VOVP_TH1 = 20 V is 𝑅𝑂𝑉𝑃 = 20(𝑉) 3. TH Pin Setting By adjusting the resistance at the TH pin, the OFF threshold voltage of secondary side synchronous rectification can be changed. The relationship between the GATE OFF threshold voltage VGOFF and the adjustment resistor RTH is as follows. 𝑉𝐺𝑂𝐹𝐹 = 12(𝑚𝑉) − 45×𝑅𝑇𝐻(𝑘𝛺) (300(𝑘𝛺)+𝑅𝑇𝐻(𝑘𝛺)) [mV] Calculation example The set GATE OFF Threshold value VGOFF when RTH = 200 kΩ is 𝑉𝐺𝑂𝐹𝐹 = 12(𝑚𝑉) − 45×200𝑘𝛺 OFF Threshold Be careful that OFF threshold accuracy changes depending on the resistor value

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 SS SS COMP 50µA 0.5V SR Controller 0.8V COMP SH_OUT 0.4V SH_IN OUT GND RUP RDOWN 0.5V OVP ROVP 20k 2.5mA OVP ENABLE COMP VOUT VCC Application Part Selection Method – continued 4. SH_IN Pin Setting The SH_IN pin is the input pin of the multipurpose comparator with 0.8 V reference and SH_OUT as the output. Typical uses are: A. Overvoltage detection (double detection together with the OVP pin); B. Circuit overheat detection; and C. Shunt Regulator However, since the SH_IN pin is also used as the ENABLE function, it is necessary to input a voltage to the SH_IN pin greater than or equal to 0.48 V (Max) during normal operation. (1) For overvoltage detection Normally, the OVP pin is used for overvoltage detection, but double detection can be made by using multipurpose COMP for additional safety improvement. The method on how to set values is shown below. The setting of the resistance dividers RUP and RDOWN when the output voltage is VOUT and the overvoltage output to be detected is VSH_OVP are as follows. 𝑅𝑈𝑃 = 𝑅𝐷𝑂𝑊𝑁 (𝑘𝛺) × (𝑉𝑆𝐻_𝑂𝑉𝑃(𝑉)−𝑉𝑆𝐻_𝑅𝐸𝐹(𝑉)) 𝑉𝑆𝐻_𝑅𝐸𝐹(𝑉) [kΩ] However, during normal operation, the SH_IN pin voltage VSH_IN must satisfy the following conditions. 𝑉𝑆𝐻_𝐼𝑁 = 0.48𝑉 ≤ 𝑉𝑂𝑈𝑇 (𝑉) × 𝑅𝐷𝑂𝑊𝑁(𝑘𝛺) (𝑅𝑈𝑃 (𝑘𝛺)+𝑅𝐷𝑂𝑊𝑁(𝑘𝛺)) [V] Calculation example When setting VOUT=24 V for normal operation and VSH_OVP=28.8 V for OVP detection voltage, the RUP resistance value when RDOWN=12 kΩ is: 𝑅𝑈𝑃 = 12(𝑘𝛺) × (28.8(𝑉)−0.8(𝑉)) 0.8(𝑉) = 420 [kΩ] Also, the SH_IN pin voltage during stable operation is 𝑉𝑆𝐻_𝐼𝑁 = 24(𝑉) × 12(𝑘𝛺) The above values meet the condition for operation.

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 SS SS COMP 50µA 0.5V SR Controller 0.8V COMP SH_OUT 0.4V SH_IN OUT GND 0.5V OVP 20k 2.5mA OVP ENABLE COMP VCC RUP RDOWN ROVP VOUT RPOS SH_IN Pin Setting – continued (2) For overheating detection By using a positive characteristic thermistor for resistance division at the SH_IN pin, circuit overheat detection is possible. The characteristics of the positive temperature coefficient thermistor are almost constant resistance value at around room temperature. But when a certain temperature (Curie point) is exceeded, the resistance value increases sharply. It is possible to detect the temperature by using this characteristic. If the output voltage during normal operation is V OUT, the positive characteristic thermistor resistance value of the temperature to be detected is RPOS1, and the lower resistance value of the resistor divider is RDOWN, the upper resistance value RUP is set as shown below. 𝑅𝑈𝑃 = 𝑉𝑂𝑈𝑇 (𝑉) × (𝑅𝐷𝑂𝑊𝑁(𝑘𝛺)+𝑅𝑃𝑂𝑆1(𝑘𝛺)) 𝑉𝑆𝐻_𝑅𝐸𝐹(𝑉) − (𝑅𝐷𝑂𝑊𝑁 (𝑘𝛺) + 𝑅𝑃𝑂𝑆1(𝑘𝛺)) [kΩ] However, the following condition must be satisfied for the positive characteristic thermistor resistance value RPOS2 at the normal temperature and the SH_IN pin voltage VSH_IN. 𝑉𝑆𝐻_𝐼𝑁 = 0.48(𝑉) ≤ 𝑉𝑂𝑈𝑇(𝑉) × 𝑅𝐷𝑂𝑊𝑁(𝑘𝛺)+𝑅𝑃𝑂𝑆2(𝑘𝛺) (𝑅𝑈𝑃(𝑘𝛺)+𝑅𝐷𝑂𝑊𝑁(𝑘𝛺)+𝑅𝑃𝑂𝑆2(𝑘𝛺)) [V] Calculation example For example, using Murata PRF15BB102RB6RC (Note 7) as a positive characteristic thermistor: (Note 7) Please refer to the data sheet published by Murata Co. for product information. When setting the positive characteristic thermistor temperature to detect at 115 °C, During normal operation VOUT=24 V, The positive characteristic thermistor resistance value at the detection temperature of 115 °C is RPOS1=10 kΩ The RUP resistance value when RDOWN=22 kΩ is 𝑅𝑈𝑃 = 24(𝑉) × (22(𝑘𝛺)+10(𝑘𝛺)) Also, the positive characteristic thermistor resistance value at 25 °C is RPOS2=0.5 kΩ (Min) in consideration of tolerances, 𝑉𝑆𝐻_𝐼𝑁 = 0.48(𝑉) ≤ 24(𝑉) × 22(𝑘𝛺)+0.5(𝑘𝛺) This meets the condition.

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 SS SS COMP 50µA 0.5V SR Controller 0.8V COMP SH_OUT 0.4V SH_IN OUT GND RUP RDOWN 0.5V OVP ROVP 20k 2.5mA OVP ENABLE COMP VOUT RFB1 RFB2 CFB1 CFB2 VCC SH_IN Pin Setting – continued (3) As a shunt regulator Connecting a feedback resistor to the SH_IN pin makes it usable as a shunt regulator. Since the current consumption from SH_OUT is as small as 10 µA, it is possible to reduce standby power consumption at no load. In normal operation, the output voltage is VOUT, the feedback resistance divides RUP, RDOWN values are as follows. 𝑅𝑈𝑃 = 𝑅𝐷𝑂𝑊𝑁 (𝑘𝛺) × (𝑉𝑂𝑈𝑇(𝑉)−𝑉𝑆𝐻_𝑅𝐸𝐹(𝑉)) 𝑉𝑆𝐻_𝑅𝐸𝐹(𝑉) [kΩ] Calculation example The RUP resistance value when VOUT=24 V in normal operation and the lower side resistance RDOWN is 80 kΩ, 𝑅𝑈𝑃 = 80(𝑘𝛺) × (24(𝑉)−0.8(𝑉)) 0.8(𝑉) = 2320 [kΩ] However, it is necessary to reset the phase compensation of RFB1, RFB2, CFB1, and CFB2. Therefore, it is recommended to check with FRA or other instruments, to ensure that the oscillation margin is enough after setting.

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 SS + SS COMP 50µA 0.5V 0.8V COMP SH_OUT 0.4V SH_IN OUT GND 0.5V OVP 20k 2.5mA OVP ENABLE COMP VOUT S QD VCC_UVLO G OPEN Protection Counter D OPEN Protection Counter SR_ON/OFF S QD S QD ENABLE VCC VCC 4.5V SS 0.5V SH_IN 0.4V SH_IN≥0.4V STOP ACTSTATE ENABLE COMP OUTPUT VCC 4.5V SS 0.5V SH_IN 0.4V SH_IN<0.4V 0.5V STOP ACTSTATE ENABLE COMP OUTPUT Application Part Selection Method – continued 5.The SS pin discharge function by SH_IN voltage When the SH_IN pin is set to 0.4 V or less, the SS pin capacitor is discharged. With this function, synchronous rectification and G, D pin OPEN protection can be stopped arbitrarily by an external signal. However, this function cannot be used as a reset after error detection. Also, at startup, a large amount of rush current flows and operation may become unstable. Therefore, after set voltage had been reached (SH_IN voltage≥0.4 V), SR control and G, D pin OPEN detection starts operation. If SS≥0.5 V, when SH_IN≥0.4 V, it is judged that the set output has been reached and the SS pin capacitor continues charging. But if SS≥0.5 V, when SH_IN<0.4 V, it is judged that the set voltage has not been reached and the SS pin capacitor is discharged. And when the voltage reaches SH_IN≥0.4 V, charging of the SS pin capacitor restarts. In the case of SH_IN≥0.4 V at SS≥0.5 V, Startup sequence In the case of SH_IN<0.4 V at SS≥0.5 V, Startup sequence

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 I/O Equivalence Circuits 1pin VCC / 2pin REG / 9pin S2 / 10pin G2 12pin G1 / 13pin S1 3pin SH_IN / 4pin SH_OUT 6pin TH 7pin SS 11pin OVP 8pin D2 / 14pin D1 SR block 2.REG 13.S1 1.VCC 12.G1 5.AGND 10.G2 9.S2 3.SH_IN 5.AGND 4.SH_OUT 1.VCC Internal REF 6.TH 5.AGND 7.SS 5.AGND Internal REG 11.OVP 5.AGND 14.D1 5.AGND SR block 8.D2

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Layout Notes (1) The VCC line may malfunction under the influence of switching noise. Therefore, it is recommended to connect the noise suppression capacitor CVCC (2.2 µF or more including temperature characteristics, DC bias characteristics, and tolerances) and resistor RVCC (100 Ω or more) between near by the VCC pin and the AGND pin. At this time, the supply voltage drops due to the RVCC resistance, but please set the resistance value so that the FET Driver voltage can be sufficiently secured. (2) The SH_IN pin is a high-impedance line. Layout its wiring as short as possible and make sure it does not run parallel to a switching line. (3) The TH pin is OFF threshold setting pin. When the OFF timing is affected by switching, it is recommended to connect resistor RTH to the TH Pin and AGND as near to the TH pin as possible. (4) The SS pin is the slow start time setting pin. It is recommended that the capacitor CSS is connected as closest to the AGND line as possible. (5) Since the synchronous rectification controller IC needs to accurately monitor the VDS generated in the FET, ensure to connect the D1 and D2 pins of the IC to the Drain of the FET and the S1 and S2 pins to the Source of the FET independently. It is recommended to set the DRAIN monitoring point of the FET considering the influence of the parasitic inductor due to the substrate wiring of the current path. (6) It is recommended that the GND of the different parts connected to the IC is connected to the output GND through independent wiring. (7) Because the Drain wiring is a switching line, it should be wired as short as possible and be wire thinly. (8) Since the D1 and D2 pins detect a very small voltage, it may toggle between ON and OFF depending on the surge voltage. Therefore, it is recommended to connect a filter circuit as a measure to absorb surge. Value setting reference example(Note 8): Schottky barrier diode D1 D2: RB751G-40 (ROHM) FET turn off filter resistance RDRAIN1 RDRAIN2: 0.3 k to 2 kΩ Drain pin current limit resistor RDRAIN3 RDRAIN4: 150 Ω (Note 8) Constants are reference values and not guaranteed values. Please verify on the actual application and set optimum values for the constants. OUT GND Primary Side Controller SH_OUT SH_IN REG TH SS VCC AGND OVP FAIL RDRAIN2 RDRAIN4 RDRAIN1 RDRAIN3 CVCC RTH CSS CREG RVCC (5) (3) (5) (5) (5) (6) (8) (8) (7) (4) (2) (1) (6)

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Operational Notes 1. Reverse Connection of Power Supply Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins. 2. Power Supply Lines Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. Ground Voltage Except for pins the output and the input of which were designed to go below ground, ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. Ground Wiring Pattern When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small -signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance. 5. Recommended Operating Conditions The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics. 6. Inrush Current When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 7. Testing on Application Boards When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage. 8. Inter-pin Short and Mounting Errors Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground , power supply and output pin . Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 9. Unused Input Pins Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is eno ugh to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power supply or ground line.

Regarding the Input Pin of the IC

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Figure 9. Example of monolithic IC structure temperature and the decrease in nominal capacitance due to DC bias and others .

Thermal Shutdown Circuit (TSD)

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Over Current Protection Circuit (OCP)

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

Ordering Information

F:SOP14 Packaging and forming specification E2: Embossed tape and reel Marking Diagram SOP14(TOP VIEW) B D 8 5 5 0 6 F Part Number Marking LOT Number Pin 1 Mark

TSZ02201-0F2F0A200310-1-2 © 2018 ROHM Co., Ltd. All rights reserved. 22.Aug.2018 Rev.001 www.rohm.com TSZ22111 • 15 • 001 Physical Dimension and Packing Information (UNIT: mm) PKG: SOP14 Drawing No.: EX113-5001 (Max 9.05 (include.BURR))

Revision History

Date Rev. Changes 22.Aug.2018 001 New Release

Notice-PGA-E Rev.004 © 2015 ROHM Co., Ltd. All rights reserved. Notice Precaution on using ROHM Products 1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment, OA equipment, telecommunicat ion equipment, home electronic appliances, amusement equipment, etc.). If you intend to use our Products in devices requiring extremely high reliability ( such as medical equipment (Note 1), transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life , bodily injury or serious damage to property ( “Specific Applications”), please consult wit h the ROHM sales representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific Applications. (Note1) Medical Equipment Classification of the Specific Applications JAPAN USA EU CHINA CLASSⅢ CLASSⅢ CLASSⅡb CLASSⅢ CLASSⅣ CLASSⅢ 2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsi bilities, adequate safety measures including but not limited to fail -safe design against the physical injury, damage to any property, which a failure or malfunction of our Products may cause. The following are examples of safety measures: [a] Installation of protection circuits or other protective devices to improve system safety [b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. Our Products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified below . Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any special or extraordinary environments or conditions . If you intend to use our Products under any special or extraordinary environments or conditions (as exemplified below), your independent v erification and confirmation of product performance, reliability, etc, prior to use, must be necessary: [a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents [b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust [c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves [e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items [f] Sealing or coating our Products with resin or other coating materials [g] Use of our Products without cleaning residue of flux (Exclude cases where no -clean type fluxes is u sed. However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] Use of the Products in places subject to dew condensation 4. The Products are not subject to radiation-proof design. 5. Please verify and confirm characteristics of the final or mounted products in using the Products. 6. In particular, if a transient load ( a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on -board mounting is strongly recommended. Avoid applying power exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect product performance and reliability. 7. De-rate Power Dissipation d epending on ambient temperature. When used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8. Confirm that operation temperature is within the specified range described in the product specification. 9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. Precaution for Mounting / Circuit board design 1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. In principle, the reflow solder ing method must be used on a surface -mount products, the flow soldering method must be used on a through hole mount products. If the flow soldering method is preferred on a surface -mount products , please consult with the ROHM representative in advance. For details, please refer to ROHM Mounting specification

Notice-PGA-E Rev.004 © 2015 ROHM Co., Ltd. All rights reserved. Precautions Regarding Application Examples and External Circuits 1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the Products and external components, including transient characteristics, as well as static characteristics. 2. You agree that application notes, reference designs, and associated data and information contained in this document are presented only as guidance for Products use . Therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. Precaution for Electrostatic This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper caution in your manufacturing process and stor age so that voltage exceeding the Products maximum rating will not be applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control). Precaution for Storage / Transportation 1. Product performance and soldered connections may deteriorate if the Products are stored in the places where: [a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2 [b] the temperature or humidity exceeds those recommended by ROHM [c] the Products are exposed to direct sunshine or condensation [d] the Products are exposed to high Electrostatic 2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is exceeding the recommended storage time period. 3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads may occur due to excessive stress applied when dropping of a carton. 4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of which storage time is exceeding the recommended storage time period. Precaution for Product Label A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only. Precaution for Disposition When disposing Products please dispose them properly using an authorized industry waste company. Precaution for Foreign Exchange and Foreign Trade act Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign trade act, please consult with ROHM in case of export. Precaution Regarding Intellectual Property Rights 1. All information and data including but not limited to application example contained in this document is for reference only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party regarding such information or data. 2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the Products with other articles such as components, circuits, systems or external equipment (including software). 3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the Products, subject to the terms and conditions herein. Other Precaution 1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM. 2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of ROHM. 3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the Products or this document for any military purposes, including but not limited to, the development of mass-destruction weapons. 4. The proper name s of companies or products described in this document are trademarks or registered trademarks of ROHM, its affiliated companies or third parties.

Notice – WE Rev.001 © 2015 ROHM Co., Ltd. All rights reserved. General Precaution 1. Before you use our Products, you are requested to caref ully read this document and fully understand its contents. ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of an y ROHM’s Products against warning, caution or note contained in this document. 2. All information contained in this documen t is current as of the issuing date and subject to change without any prior notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales representative. 3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties resulting from inaccura cy or errors of or concerning such information.

Minimum Package Quantity 2500 Packing Type Taping Constitution Materials List inquiry RoHS Yes BD85506F - Web Page

Product Information

BD85506F specifications and overview.

Summary

High Efficiency / Low Standby Power 2-Channel Secondary Side Synchronous Rectification Control IC

Description

High Efficiency / Low Standby Power 2-Channel Secondary Side Synchronous Rectification Control IC

Source title BD85506F Datasheet(PDF) - Rohm

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