Driver IC

BD64547MUV

Rohm

System Motor Driver

Manufacturer: Rohm

Document: 39 Pages / 1Mb

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Document overview

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PDF pages: 39

Technical content

Features

◼ Low ON-resistance Output H-Bridge Driver (2ch) ◼ Built-in Regular Current Chopping Function ◼ Over-current Protection (OCP) in H-Bridge Driver ◼ 3-line Serial Type Interface ◼ SWREG (CH1) with Built-in P-ch Power DMOS FET ◼ High Efficiency SWREG Function ◼ Soft Start Function in SWREG ◼ Over-current Protection (OCP) in SWREG ◼ Output Under Voltage Protection (UVLO) in SWREG ◼ SWREG Enable Function ◼ Thermal Shutdown Function (TSD) ◼ Power ON Reset ◼ VBB Drop Detection Function ◼ Ultra-thin Type, High Heat Dissipation Package

Applications

◼ Inkjet printers ◼ Photo printers etc. Key Specifications ◼ Input Voltage Range 9.0 V to 45.0 V ◼ Motor Rated Output Current 2.0 A/Phase ◼ SWREG1 Output Current Range 0 A to 2.0 A ◼ SWREG2 Output Current Range 0 A to 1.4 A ◼ Operating Temperature Range -25 °C to +85 °C ◼ Standby Current 100 µA (Max) Package W (Typ) x D (Typ) x H (Max) VQFN048V7070 7.0 mm x 7.0 mm x 1.0 mm Typical Application Circuit OUTAP VBBA OUTAM RNFA RNFAS OUTBP VBBB OUTBM RNFB RNFBS LOGIC 4bit DAC (1/10) RNFAS VREFA VREFB SWOUT1 VBBSW1 PRE DRIVER PRE DRIVER SLEEP ENBA,ENBB CLK,STB(LD),DAT ID0,ID1,ID2 RSTIN ENBSW1 ENBSW2 PWM GND TSD OCP Clock internal reg. FB1 OSC R S QDAC for soft start SWOUT2 VINSW2PRE DRIVER FB2 OSC R S QDAC for soft start PGNDSW2 BOOT COMP FB1 FB2 OCPDET UVDET RESET UVDETIN UVP MODE internal reg. Regulator Internal reg. 4bit DAC (1/5or1/10) RNFBS Datasheet

16.Nov.2020 Rev.006 TSZ22111 • 15 • 001 BD64547MUV © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com OUTAP VBBA OUTAM RNFA RNFAS OUTBP VBBB OUTBM RNFB RNFBS LOGIC 4bit DAC (1/5or1/10) RNFAS VREFA 2 VREFB SWOUT1 VBBSW1 PRE DRIVER PRE DRIVER ENBSW1 ENBSW2 PWM GND TSD OCP Clock internal reg. FB1 OSC R S QDAC for soft start SWOUT2 VINSW2PRE DRIVER FB2 OSC R S QDAC for soft start PGNDSW2 BOOT COMP FB1 FB2 OCPDET UVDET RESET UVDETIN UVP MODE internal reg. Regulator 16 361 41 SLEEP ENBA,ENBB CLK,STB(LD),DAT ID0,ID1,ID2 RSTIN to 10 10 3 3 Iinternal reg. 4bit DAC (1/5or1/10) RNFBS RESET UVDET SWOUT1 SWOUT1 VREFA VREFB GND 1 2 3 4 5 6 7 RSTIN SLEEP UVDETIN CLK STB(LD) DAT 2536 35 34 33 SWOUT2 VINSW2 VINSW2 FB2 GND PWM OCPDET VBBSW1 VBBSW1 OUTBM RNFBS 9 10 ID1 ID2 PGNDSW2 SWOUT2 30 29 28 27 OUTBP OUTAP VBBA RNFA RNFAS MODE ENBSW1 ENBSW2 OUTAM PGNDSW2 ENBA ENBB FB1 GND RNFB VBBB ID0 COMP BOOT GND EXP-PAD Pin Configuration Block Diagram Pin Description No. Pin Name I/O Function No. Pin Name I/O Function

1 GND - Ground 25 PGNDSW2 - SWREG2 power ground

2 VREFA I H-Bridge A output current setting 26 OUTAM O H-Bridge A output (-)

3 VREFB I H-Bridge B output current setting 27 RNFAS I H-Bridge A input pin of current

4 SLEEP I Sleep mode setting 28 RNFA O H-Bridge A current detection

5 ENBA I H-Bridge A enable input 29 VBBA - H-Bridge A power supply (42 V)

6 ENBB I H-Bridge B enable input 30 OUTAP O H-Bridge A output (+)

7 CLK I Serial CLK input 31 OUTBP O H-Bridge B output (+)

8 STB(LD) I Serial STB(LD) input 32 VBBB - H-Bridge B power supply (42 V)

9 DAT I Serial DAT input 33 RNFB O H-Bridge B current detection

10 ID0 I ID 0 setting 34 RNFBS I H-Bridge B input pin of current

11 ID1 I ID 1 setting 35 OUTBM O H-Bridge B output (-)

12 ID2 I ID 2 setting 36 GND - Ground

13 ENBSW1 I SWREG1 enable input 37 VBBSW1 - SWREG1 power supply (42 V)

14 ENBSW2 I SWREG2 enable input 38 VBBSW1 - SWREG1 power supply (42 V)

15 PWM I SWREG2 PWM compulsion 39 SWOUT1 O SWREG1 output

16 GND - Ground 40 SWOUT1 O SWREG1 output

17 COMP I/O SWREG2 phase compensation 41 GND - Ground

18 FB2 I SWREG2 feedback 42 FB1 I SWREG1 feedback

19 VINSW2 - SWREG2 power supply (5 V) 43 OCPDET O OCP detection

20 VINSW2 - SWREG2 power supply (5 V) 44 UVDET O VBB drop detection

21 BOOT I SWREG2 H-side Nch booster 45 RESET O Reset output

22 SWOUT2 O SWREG2 output 46 RSTIN I Reset input

23 SWOUT2 O SWREG2 output 47 MODE I H-Bridge mode setting

24 PGNDSW2 - SWREG2 power ground 48 UVDETIN I UVDET setting

EXP-PAD - The EXP-PAD is connect to GND. - - - - [TOP VIEW]

16.Nov.2020 Rev.006 TSZ22111 • 15 • 001 BD64547MUV © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com Absolute Maximum Ratings (Ta = 25 °C) Parameter Symbol Limit Unit VBB Applied Voltage(Note 1)(Note 2) VBB -0.4 to +50.0 V Motor Output Voltage(Note 3) VMOUT -0.4 to +50.0 V SWOUT1 Voltage VSWOUT1 -0.4 to +50.0 V VINSW2 Applied Voltage(Note 1) VINSW2 -0.4 to +7.0 V SWOUT2 Voltage VSWOUT2 -0.4 to +7.0 V Logic Input Voltage(Note 4) VLI -0.4 to +5.5 V Logic Output Voltage(Note 5) VLO 5.5 V RNF Voltage (DC) VRNF(DC) 0.55 V RNF Voltage (peak)(Note 6) VRNF(peak) 2.5 V Power Dissipation(Note 7) Pd 4.83 W Motor Output Current (DC)(Note 1) IOMAXMT(DC) 2.0 A/Phase SWOUT1 Output Current (DC)(Note 1) IOMAXSW1(DC) 2.2 A SWOUT1 Output Current (peak)(Note 1)(Note 6) IOMAXSW1(peak) 2.4 A SWOUT2 Output Current (DC)(Note 1) IOMAXSW2(DC) 1.5 A SWOUT2 Output Current (peak)(Note 1)(Note 6) IOMAXSW2(peak) 1.65 A Storage Temperature Range Tstg -55 to +150 °C Maximum Junction Temperature Tjmax 150 °C Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins o r an open circuit between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the absolute maximum ratings. Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in de terioration of the properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with power dissipation taken into con sideration by increasing board size and copper area so as not to exceed the maximum junction temperature rating. (Note 1) Must not exceed Pd and Tj = 150 °C (Note 2) Supply = VBBA, VBBB, VBBSW1 (Note 3) Motor Output = OUTAP , OUTAM, OUTBP, OUTBM (Note 4) Logic Input = SLEEP, ENBA, ENBB, CLK, STB(LD), DAT, ID0, ID1, ID2, ENBSW1, ENBSW2, PWM, RSTIN, MODE (Note 5) Logic Output = OCPDET, UVDET, RESET (Note 6) peak = 1 μs (Note 7) When mounted on a 4-layer recommended board (74.2 mm x 74.2 mm x 1.6 mm), reduce by 37.3 mW/°C when Ta ≥ 25 °C Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Operating Temperature Topr -25 - +85 °C VBB Applied Voltage(Note 8)(Note 9) VBB 9.0 - 45.0 V CLK Max Operating Frequency fCLOCK - 40 - MHz SWREG1 Output Voltage Setting VOUT1 3.0 - 13.0 V SWREG2 Output Voltage Setting VOUT2 0.8 - 3.6 V SWREG1 Output Current(Note 10) ISW1 0 - 2.0 A SWREG2 Output Current(Note 10) ISW2 0 - 1.4 A VINSW2 Applied Voltage VINSW2 3.0 - 5.5 V (Note 8) When VBB is under POR, H-Bridge, SWREG and circuit protection are disabled. (Note 9) Supply = VBBA, VBBB, VBBSW1 (Note 10) Must not exceed Pd and Tj = 150 °C

16.Nov.2020 Rev.006 TSZ22111 • 15 • 001 BD64547MUV © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com Electrical Characteristics (Unless otherwise specified VBB = 42 V, Ta = 25 °C) Parameter Symbol Specification Unit Conditions Min Typ Max [Overall] Circuit Current (Standby)(Note 1) IBBST - 20 100 µA SLEEP = L, ENBSW1 = H Circuit Current (Active)(Note 1) IBB - 8.5 13.0 mA SLEEP = H, ENBSW1 = L VINSW2 Current IINSW2 - 0 10 µA POR Threshold Voltage H VPORH 6 7 8 V VBB Input timing POR Hysteresis Voltage VPORHY 0.5 1.0 1.5 V [H-Bridge] Output ON-Resistance (H-side) RONH - 0.75 1.05 Ω IOUT = 1 A Output ON-Resistance (L-side) RONL - 0.45 0.75 Ω IOUT = 1 A Built-in Diode Forward Voltage (H-side) VFH - 1.0 1.3 V IOUT = 1 A Built-in Diode Forward Voltage (L-side) VFL - 1.0 1.3 V IOUT = 1 A [Current Control] VREF Voltage Range VVREF 0 - 3.7 V VREF Input Current IVREF -1 0 +1 µA VVREF = 3.3 V RNF Input Current IRNF 5 15 30 µA VREF to RNFS Offset Voltage VOFST(Note 2) -4 0 +4 % VVREF = 2 V, DAC = 15, MODE = H, M [Control Logic 1 (DAT, CLK, STB(LD), ENBA, ENBB, SLEEP , RSTIN, ID0, ID1, ID2)] H Level Input Voltage 1 VIN1H 2.0 - - V L Level Input Voltage 1 VIN1L - - 0.8 V Input Current 1 IIN1 15 33 50 µA Input Voltage = 3.3 V [Control Logic 2 (ENBSW1, ENBSW2, PWM)] H Level Input Voltage 2 VIN2H 2.0 - - V L Level Input Voltage 2 VIN2L - - 0.8 V Input Current 2 IIN2 -18 -9 -3 µA Input Voltage = 0 V [Control Logic 3 (MODE)] Input Voltage H VIN3H 4.0 - - V Input Voltage M VIN3M 2.0 - 3.0 V Input Voltage L VIN3L - - 1.0 V Input Current IIN3 -85 -50 -30 µA Input Voltage = 0 V [Switching Regulator 1 Block] FB1 Threshold Voltage VFBSW1 0.99 1.00 1.01 V Output ON-Resistance RONSW1 - 0.65 0.85 Ω ISWOUT1 = 1 A FB1 Pin Current IFBSW1 -0.1 0 +0.1 µA VFB1 = 1 V FB1 Low Input Voltage VFBUVP1 0.71 0.75 0.79 V Common with RESET detection [Switching Regulator 2 Block] FB2 Threshold Voltage VFBSW2 0.792 0.800 0.808 V Output ON-Resistance (H-side) RONHSW2 - 0.20 0.26 Ω ISWOUT2 = 1 A Output ON-Resistance (L-side) RONLSW2 - 0.20 0.26 Ω ISWOUT2 = 1 A FB2 Pin Current IFBSW2 -0.1 0 +0.1 µA VFB2 = 0.8 V FB2 Low Input Voltage VFBUVP2 0.28 0.40 0.52 V [RESET, UVDET, OCPDET] Low Output Voltage VOD - - 0.2 V IOUT = 1 mA RESET Output Delay Time tRST 40 50 60 ms RSTIN Minimum Input Pulse Width tRSTIN - - 13 µs Refer to P .7 1.4 UVDET Base Voltage VUV 0.552 0.600 0.648 V UVDET Hysteresis Voltage VUVHYS - 0.05 - V (Note 1) Total current value of the VBBA, VBBB, VBBSW1 pins. (Note 2) VOFST = ((VVREF × Current_Ratio / α) – VRNFS) / (VVREF × Current_Ratio / α), α = 5 (MODE = M), 10 (MODE = H)

© 2015 ROHM Co., Ltd. All rights reserved. parts. Be certain to evaluate these values with respect to the actual intended application. Figure 1. BD64547MUV Recommended Range of External Components Circuit diagram

1 Pin Connections when H-Bridge is Not in Use

The pin processing shown in the table below is recommended. ENBx(Note 1) VREFx(Note 1) RNFx(Note 1) RNFxS(Note 1) OUTxP(Note 1) OUTxM(Note 1) Ach OPEN or GND GND GND OPEN Bch OPEN or GND GND GND OPEN (Note 1) x = A, B The overcurrent protection may fail if VREFx and RNFx / RNFxS are left OPEN. (However, there is no problem even if Voltage is applied to the VREFx pin only when ENBx is Low and output is open with no serial input.)

2 Pin Connections when SWREG is Not in Use

The pin processing shown in the table below is recommended. ENBSWx(Note 2) FBx(Note 2) SWOUTx(Note 2) COMP BOOT VINSW2 1ch OPEN GND OPEN - - - 2ch OPEN GND OPEN OPEN OPEN OPEN (Note 2) x = 1, 2

3 Condition of the MODE pin

M 100 kΩ Pull Down L GND (Don't use) (use a Pull Down resistor of 100 kΩ with ±5 % accuracy or tolerance.)

4 Active Condition of Logic Input Pins

Logic input pins Active condition Non-active condition (OPEN case) DAT, CLK, STB(LD), ENBA, ENBB, SLEEP , RSTIN, ID0, ID1, ID2 H (2.0 V or more) L (0.8 V or less) ENBSW1, ENBSW2, PWM L (0.8 V or less) H (2.0 V or more)

5 Condition of the SLEEP pin

Logic input pins Data accept mode Power save mode SLEEP H (2.0 V or more) L (0.8 V or less) When SLEEP = L, ENBSW1 = H and ENBSW2 = H, the condition is stand-by. The IC switches to power save mode. In this case, RESET output (P .7), Thermal shutdown (P .24), over-current (P .24) and output under voltage protection turn OFF.

13 H-Bridge Driver

Figure 2. Explanation of Circuit Operation

1 Overall

1.1 Power supply (VBB) input

1.2 Control Logic Input

PWM is implemented with a Schmitt trigger, with hysteresis.

1.3 Power-On RESET Function

A Power-On RESET circuit is built-in for VBB. When VBB rises to VPORH level (7.0 V (Typ)) or higher at the time of power ON, SWREG1 activates by a soft start. power-down to turn all outputs OFF with VPORH-VPORHY (1.0 V (Typ)) and reset the serial ports.

1.4 Reset Timing, VBB Drop Detection Function

RESET output table is shown below (Values at the table are all typical. VBB has hysteresis).

7.0 V or more

0.75 V or more H L

0.75 V or more L H (50 ms after detection)

2 H-Bridge

2.1 Power Save Mode

When the SLEEP = L, H-Bridge will cause the circuit to enter standby state , with only SWREG1 and SWREG2 active. Serial ports are reset in power save mode. SLEEP pin Mode L Power Save Mode H Normal (active) Mode Be sure driver outputs are in the OFF state when switching modes with the SLEEP pin.

2.2 ID Setting

Setting the identification code of the device with the ID0, ID1 and ID2 pins. ID pin is always monitored. ID2 ID1 ID0 Identification code (D20, D19, D18) L L L Driven by Serial interface 2 L L H 1 (001) L H L 2 (010) L H H 3 (011) H L L 4 (100) H L H 5 (101) H H L 6 (110) H H H 7 (111) Don’t care Don’t care Don’t care All IC reply (000) Identification code 1, 3, 5, 7 is triggered in the falling edge of CLK only, identification code 2, 4, 6 and serial interface 2 is triggered in the rising edge of CLK only.

2.3 MODE Setting

The MODE pin changes the drive mode of H-Bridge as follows. MODE Pin state H-Bridge-A H-Bridge-B H OPEN or 5 V DC motor ×2 or Stepping motor (VREF voltage splitting ratio α = 10) M 100 kΩ pull down DC motor ×2 or Stepping motor (VREF voltage splitting ratio α = 5) L GND Don’t use

2 H-Bridge ― continued

2.4 Serial Interface 1

to the identification code in the L area of STB(LD) signal. The data of the shift register appoints a device code in D20, D19, and D18. Figure 3. Serial Port Write Timing of Serial Interface 1

2.5 Serial Data Allotment (Serial Interface 1)

D14 Word Select 0 = 1 1 D15 Word Select 1 = 1 1 D16 Word Select 2 = 1 1 D17 Word Select 3 = 1 1 D18 - - D19 - - D20 - - D17 Word Select 3 D16 Word Select 2 D15 Word Select 1 D14 Word Select 0 Word Select 1 1 1 1 WORD A 0 0 0 0 WORD B 0 0 0 1 WORD C 0 0 1 0 WORD D 0 0 1 1 Rohm Reserved 0 1 0 0 WORD E 0 1 0 1 WORD F 0 1 1 0 WORD G 0 1 1 1 WORD H Rohm Reserved denotes a special mode -setting port for inspection at shipment. If the Word Select 3, 2, 1, and 0 are set to “0,0,1,1” by mistake, it may cause malfunctions. Therefore, be careful NOT to implement this setting.

2.5 Serial Data Allotment (Serial Interface 1) ― continued

(H-Bridge-A Specific) Initial DAT WORD C (H-Bridge-B Specific) Initial DAT WORD D H-Bridge-A-B General Initial DAT D0 Blank Time LSB 0 Blank Time LSB 0 Internal PWM Mode for H-Bridge-B 0 D1 Blank Time MSB 0 Blank Time MSB 0 External PWM Mode for H-Bridge-B 0 D2 Off Time LSB 0 Off Time LSB 0 Phase for H-Bridge-B 0 D3 Off Time Bit1 0 Off Time Bit1 0 DAC LSB for H-Bridge-B 0 D4 Off Time Bit2 0 Off Time Bit2 0 DAC Bit1 for H-Bridge-B 0 D5 Off Time Bit3 0 Off Time Bit3 0 DAC Bit2 for H-Bridge-B 0 D6 Off Time MSB 1 Off Time MSB 1 DAC MSB for H-Bridge-B 0 D7 Fast Decay Time LSB 0 Fast Decay Time LSB 0 Internal PWM Mode for H-Bridge-A 0 D8 Fast Decay Time Bit1 0 Fast Decay Time Bit1 0 External PWM Mode for H-Bridge-A 0 D9 Fast Decay Time Bit2 0 Fast Decay Time Bit2 0 Phase for H-Bridge-A 0 D10 Fast Decay Time MSB 0 Fast Decay Time MSB 0 DAC LSB for H-Bridge-A 0 D11 Sync. Rect. Control 0 Sync. Rect. Control 0 DAC Bit1 for H-Bridge-A 0 D12 Sync. Rect. Enable 0 Sync. Rect. Enable 0 DAC Bit2 for H-Bridge-A 0 D13 Don’t care - Don’t care - DAC MSB for H-Bridge-A 0 D14 Word Select 0 = 0 0 Word Select 0 = 1 1 Word Select 0 = 0 0 D15 Word Select 1 = 0 0 Word Select 1 = 0 0 Word Select 1 = 1 1 D16 Word Select 2 = 0 0 Word Select 2 = 0 0 Word Select 2 = 0 0 D17 Word Select 3 = 0 0 Word Select 3 = 0 0 Word Select 3 = 0 0 D18 ID Bit0 - ID Bit0 - ID Bit0 - D19 ID Bit1 - ID Bit1 - ID Bit1 - D20 ID Bit2 - ID Bit2 - ID Bit2 -

16.Nov.2020 Rev.006 TSZ22111 • 15 • 001 BD64547MUV © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com (H-Bridge-A Specific) Initial DAT WORD F (H-Bridge-B Specific) Initial DAT D0 EN A PWM Cycle Time LSB 0 EN B PWM Cycle Time LSB 0 D1 EN A PWM Cycle Time Bit1 0 EN B PWM Cycle Time Bit1 0 D2 EN A PWM Cycle Time Bit2 0 EN B PWM Cycle Time Bit2 0 D3 EN A PWM Cycle Time Bit3 0 EN B PWM Cycle Time Bit3 0 D4 EN A PWM Cycle Time Bit4 0 EN B PWM Cycle Time Bit4 0 D5 EN A PWM Cycle Time Bit5 0 EN B PWM Cycle Time Bit5 0 D6 EN A PWM Cycle Time Bit6 0 EN B PWM Cycle Time Bit6 0 D7 EN A PWM Cycle Time Bit7 0 EN B PWM Cycle Time Bit7 0 D8 EN A PWM Cycle Time Bit8 0 EN B PWM Cycle Time Bit8 0 D9 EN A PWM Cycle Time Bit9 0 EN B PWM Cycle Time Bit9 0 D10 EN A PWM Cycle Time Bit10 0 EN B PWM Cycle Time Bit10 0 D11 EN A PWM Cycle Time Bit11 0 EN B PWM Cycle Time Bit11 0 D12 EN A PWM Cycle Time MSB 0 EN B PWM Cycle Time MSB 0 D13 Don’t care - Don’t care - D14 Word Select 0 = 0 0 Word Select 0 = 1 1 D15 Word Select 1 = 0 0 Word Select 1 = 0 0 D16 Word Select 2 = 1 1 Word Select 2 = 1 1 D17 Word Select 3 = 0 0 Word Select 3 = 0 0 D18 ID Bit0 - ID Bit0 - D19 ID Bit1 - ID Bit1 - D20 ID Bit2 - ID Bit2 - WORD G (H-Bridge-A Specific) Initial DAT WORD H (H-Bridge-B Specific) Initial DAT D0 EN A PWM On Time LSB 0 EN B PWM On Time LSB 0 D1 EN A PWM On Time Bit1 0 EN B PWM On Time Bit1 0 D2 EN A PWM On Time Bit2 0 EN B PWM On Time Bit2 0 D3 EN A PWM On Time Bit3 0 EN B PWM On Time Bit3 0 D4 EN A PWM On Time Bit4 0 EN B PWM On Time Bit4 0 D5 EN A PWM On Time Bit5 0 EN B PWM On Time Bit5 0 D6 EN A PWM On Time Bit6 0 EN B PWM On Time Bit6 0 D7 EN A PWM On Time Bit7 0 EN B PWM On Time Bit7 0 D8 EN A PWM On Time Bit8 0 EN B PWM On Time Bit8 0 D9 EN A PWM On Time Bit9 0 EN B PWM On Time Bit9 0 D10 EN A PWM On Time Bit10 0 EN B PWM On Time Bit10 0 D11 EN A PWM On Time Bit11 0 EN B PWM On Time Bit11 0 D12 EN A PWM On Time MSB 0 EN B PWM On Time MSB 0 D13 Phase for H-Bridge-A 0 Phase for H-Bridge-B 0 D14 Word Select 0 = 0 0 Word Select 0 = 1 1 D15 Word Select 1 = 1 1 Word Select 1 = 1 1 D16 Word Select 2 = 1 1 Word Select 2 = 1 1 D17 Word Select 3 = 0 0 Word Select 3 = 0 0 D18 ID Bit0 - ID Bit0 - D19 ID Bit1 - ID Bit1 - D20 ID Bit2 - ID Bit2 -

2.6 Serial Interface 2

internal memory of 3 x 14 bit at the rising edge of the STB(LD) pin. Rohm Reserved is a special mode setting port for factory inspection, etc. Please be careful not to set it as it may cause malfunction if it is set incorrectly. Figure 4. Serial Port Write Timing of Serial Interface 2

2.7 Serial Data Allotment (Serial Interface 2)

(H-Bridge-A Specific) Initial DAT WORD1 (H-Bridge-B Specific) Initial DAT WORD2 H-Bridge-A-B General Initial DAT D0 Blank Time LSB 0 Blank Time LSB 0 Internal PWM Mode for H-Bridge-B 0 D1 Blank Time MSB 0 Blank Time MSB 0 External PWM Mode for H-Bridge-B 0 D2 Off Time LSB 0 Off Time LSB 0 Phase for H-Bridge-B 0 D3 Off Time Bit1 0 Off Time Bit1 0 DAC LSB for H-Bridge-B 0 D4 Off Time Bit2 0 Off Time Bit2 0 DAC Bit1 for H-Bridge-B 0 D5 Off Time Bit3 0 Off Time Bit3 0 DAC Bit2 for H-Bridge-B 0 D6 Off Time MSB 1 Off Time MSB 1 DAC MSB for H-Bridge-B 0 D7 Fast Decay Time LSB 0 Fast Decay Time LSB 0 Internal PWM Mode for H-Bridge-A 0 D8 Fast Decay Time Bit1 0 Fast Decay Time Bit1 0 External PWM Mode for H-Bridge-A 0 D9 Fast Decay Time Bit2 0 Fast Decay Time Bit2 0 Phase for H-Bridge-A 0 D10 Fast Decay Time MSB 0 Fast Decay Time MSB 0 DAC LSB for H-Bridge-A 0 D11 Sync. Rect. Control 0 Sync. Rect. Control 0 DAC Bit1 for H-Bridge-A 0 D12 Sync. Rect. Enable 0 Sync. Rect. Enable 0 DAC Bit2 for H-Bridge-A 0 D13 Don’t care - Don’t care - DAC MSB for H-Bridge-A 0 D14 Word Select 0 = 0 - Word Select 0 = 1 - Word Select 0 = 0 - D15 Word Select 1 = 0 - Word Select 1 = 0 - Word Select 1 = 1 -

2.8 Explanation of Serial Port · H-Bridge Operation

same degree of variation and temperature dependence as the clock.

2.8.1 Blank Time D0 to D1: WORD0 / WORD1

spikes that occurs at the time of the switching. Figure 5. Blank Time

2.8.2 Off Time D2 to D6: WORD0 / WORD1

N : is set by the serial bit: 0 to 31.

2.8.3 Fast Decay Time D7 to D10: WORD0 / WORD1

tFD : is the Fast Decay Time. N : is set by the serial bit: 0 to 15.

2.8 Explanation of Serial Port · H-Bridge Operation ― continued

2.8.4 Sync. Rect. Control D11: WORD0 / WORD1 At Fast Decay Mode Synchronous rectification, make settings related to reverse energization of the motor current. D11 Sync. Rect. Cont. Function

0 ACTIVE Detects motor current at 0 A, switches synchronous rectification

OFF and prevents reverse energization.

1 PASSIVE Permits reverse energization; switches synchronous rectification

OFF when current reaches the ITRIP. 𝐼𝑇𝑅𝐼𝑃 = 𝑉𝑅𝐸𝐹 × 𝐷𝐴𝐶𝑣𝑎𝑙𝑢𝑒(𝐶𝑢𝑟𝑟𝑒𝑛𝑡_𝑅𝑎𝑡𝑖𝑜) (𝛼 × 𝑅𝑠𝑒𝑛𝑠𝑒)⁄ [A] ITRIP : is the motor current limit, established by the formula above. VREF : Is the output current value setting voltage. α : is the VREF voltage division ratio. (MODE = H: α = 10, MODE = M: α = 5) Rsense : is the Current detection resistance value. DACvalue(Current_Ratio) : is refer to table below.

2.8.5 DAC value (Current_Ratio) D3 to D6 / D10 to D13: WORD2

D3 / D10 Current_Ratio [%] 1 1 1 1 100.00 1 1 1 0 98.08 1 1 0 1 95.69 1 1 0 0 92.39 1 0 1 1 88.19 1 0 1 0 83.15 1 0 0 1 77.30 1 0 0 0 70.71 0 1 1 1 63.44 0 1 1 0 55.56 0 1 0 1 47.14 0 1 0 0 38.27 0 0 1 1 29.03 0 0 1 0 19.51 0 0 0 1 9.80 0 0 0 0 Disable 2.8.6 Sync. Rect. Enable D12: WORD0 / WORD1 In current decay mode, D12 value enables or disables synchronous rectification. D12 Sync. Rect. En. Function

0 Disabled No synchronous

1 Enabled

2.8.7 Internal PWM Mode D0 / D7: WORD2

In current decay mode, this data sets the motor current regeneration method. Mixed Decay setting: During Off Time, the Fast Decay Time is set for Fast regeneration mode. For the rest of the time, it is set to Slow regeneration mode. In this scheme, if Fast Decay Time is longer than Off Time, Fast regeneration becomes the only operative mode. When Sync. Rect. Control = Active and 0 A is detected in Fast regeneration mode, the regeneration mode will switch to Slow, once all outputs are OFF and the Fast Decay Time period has finished. D0 / D7 Mode

0 Mixed

1 Slow

2.8.8 External PWM Mode D1 / D8: WORD2

Sets the motor current regeneration mode when ENBx(Note 1) = L. Motor current regeneration is triggered by the falling edge of the ENBx pin logic. Therefore, this mode is not synchronized with the clock. D1 / D8 Mode

0 Fast

(Note 1) x = A, B

2.8.9 Phase D2 / D9: WORD2

Sets the motor drive rotational direction. D2 / D9 Direction OUTxP(Note 2) OUTxM(Note 2)

0 Reverse L H

1 Forward H L

There is a Phase bit in WORD D, WORD G, WORD H, and last updated WORD is reflected. For example, when Phase D2: WORD D ”0”, Phase D13: WORD G ”0”, Phase D13: WORD G ”1”, Phase setting is forward detection. And when Phase D2: WORD D ”0”, Phase D13: WORD H ”0”, Phase D2: WORD D ”1”, Phase setting is forward detection. (Note 2) x = A, B

2.8.10 PWM Cycle Time D0 to D12: WORD E / WORD F

PWM Cycle Time setting. PWM Cycle Time is accomplished using the equation: 𝑡𝑃𝑊𝑀 = 𝑁 × 25𝑛 [s] tPWM : is the PWM Cycle Time. N : is set by the serial bit: 0 to 8191. For example, if N = 4000, 𝑡𝑃𝑊𝑀 = 4000 × 25𝑛 = 100 [µs] When N = 0 is set, external enable becomes active. On the other hand, internal PWM becomes active when N > 0 is set.

2.8.11 PWM ON Time D0 to D12: WORD G / WORD H

N : is set by the serial bit: 0 to 8191. Figure 6. Relationship Diagram of PWM Cycle Time and PWM ON Time

2.8.12 Watch Dog Timer D0 / D1: WORD A

output. The A side and the B side can be set individually.

Set the A side time at 180 s
Initiate the A side start register and start timer count.
When the motor stops, it clears the start register and the timer count is reset.

overrun and a bug) and the start register is not cleared for more than 180 s, turn OFF motor driver output. In addition, if you set it to 180 s again within 180 s after setting it to 180 s, the count is restarted from there.

2.9 Current Decay Mode

each DECAY mode are as follows. Figure 7. Route of Regenerated Current during Current Decay

2.9.1 SLOW DECAY

FULL STEP and low pulse rate drive.

2.9.2 FAST DECAY

are of high pulse rate drive. can be improved without making the current ripple larger during current decay. Figure 8. Mixed Decay Diagram

3 SWREG

Figure 9. SWREG1 Block Diagram (SWREG2: Synchronous rectification and VBBSW1 → VINSW2)

3.1 Basic Operation

(SWCLK), 1ch SWREG operates by 250 kHz (Typ) ±15 % and 2ch SWREG operates by 1 MHz (Typ) ±20 %. ENBSW2 = H, the IC doesn’t work. R1, R2 is the external resistance. VRIP : is the output ripple voltage. IRIP : is the output ripple current. ESR : is the equivalent series resistance. fSW : is the switching frequency. COUT : is the output capacitance. VBBSW : is the applied voltage.

3.2 Skip Mode Operation

detection level at the SWCLK rising edge, output will not switch ON.

3.3 MAX DUTY

detection level, output MAX DUTY (90 %) will force the output OFF.

3 SWREG ― continued

3.4 Operation Timing

Operation timing under light, normal and heavy loads are respectively described in the charts below. Figure 10. Operation Timing of Light Loads, Normal Loads and Heavy Loads

3.5 SWREG1 Soft Start (at power-on, with ENBSW1 = L)

At the time of power-on, VOUT1 ramps up slowly with a soft start. The rising edge of SWREG1 is synchronized with the timing when ENBSW1 = L and POR release. Figure 11. SWREG1 Soft Start Operation Timing Diagram This soft start method is realized by linearly changing the negative side voltage of the gmAMP by using DAC. Soft start time t1 is constant, regardless of VBB.

3.6 SWREG2 Operation

3.6.1 Basic Function

When the logic of the PWM pin is switched during SWREG2 operation, the output voltage may decrease. SWREG2(Note 1), and do not change during operation. (Note 1) Before start up means the ENBSW2 = H state or before UVLO release of SWREG2.

3.6.2 Enable Control

the shutdown interval (H level interval of ENSW2) must be set to 100 µs or longer. Figure 12. Efficiency characteristics (SLLMTM Control and PWM Control)

4 Protection Functions

4.1 Protection Circuits Function

Overall Overheating protection H-Bridge drive circuit Over-current protection SWREG circuit Over-current protection, output low voltage protection

4.1.1 Overheating protection

Turns OFF all output functions in response to junction temperature rise. Output is restored when the system powers on again. Thermal shutdown temperature Hysteresis Restart 175 °C (Typ) None -

4.1.2 Over-current protection (H-Bridge)

Detects current flowing to H-Bridge output, turns OFF all H-Bridge outputs at the end of Mask time. Output is restored at the SLEEP pin = H → L → H. Set current Mask time Restart

3.5 A (Typ) 3 µs (Typ) SLEEP

4.1.3 Over-current protection (H-Bridge) detect function

The OCPDET output detects that the over-current protection of the H-Bridge has worked and becomes L level at the timing of turnning OFF all H-Bridge outputs.

4.1.4 Over-current protection (SWREG1)

Detects current flowing to SWREG1 output. After Mask time, SWREG1 is turned OFF b etween 256 µs to 512 µs (Typ) at the timing of detection. When protection operation is complete, normal operation resumes. Channel Set current Mask time Restart SWREG1 5.0 A (Typ) 0.15 µs (Typ) -

4.1.5 Over-current protection (SWREG2)

It becomes activated by confining current flowing through the upper part MOSFET of SWREG2 to every 1 cycle of the switching frequency. Channel Set current SWREG2 5.0 A (Typ)

4.1.6 Output low voltage protection (SWREG1)

Monitors the FB1 pin voltage of the SWREG1 circuit. If the FB1 pin voltage is less than 0.75 V (Typ), only SWREG1 is turned OFF after mask time. Output is restored at the ENBSW1 pin = L → H → L. Set voltage Mask time Restart < 0.75 V (Typ) 10 µs (Typ) ENBSW1 Note that output under -voltage protection does not work until the soft s tart count is complete (16.4 ms (Typ)).

4.1.7 Output low voltage protection (SWREG2)

Monitors the FB2 pin voltage of the SWREG2 circuit. It activates when the FB2 pin voltage is less than 0.4 V (Typ). SWREG2 is turned OFF when the state continues for 1 ms (Typ). Set voltage Mask time Output low voltage protection operation Restart < 0.4 V (Typ) 1 ms (Typ) ON ENBSW2 reboot > 0.4 V (Typ) - OFF -

4 Protection Functions ― continued

4.2 Over-current protection circuit operation current

4.3 Timing of output low voltage protection (SWREG1)

time of 10 µs (Typ). At this time, all outputs except the switching regulator are turned off at the same time. Figure 13. Timing of SWREG1 Protection Operation Diagram during a soft start, the IC will not shut OFF until the soft start is complete.

4.4 Soft Start (at power-on, with ENBSW2 = L)

At the time of power-on, VOUT2 ramps up slowly with a soft start. The rising edge of SWREG2 is synchronized with the timing when ENBSW2 = L and POR release of VBB.

4.5 Operation Timing of malfunction protection circuit at output low voltage protection (SWREG2)

is measured by total inspection. Figure 14. SWREG2 Protection Operate Timing and Soft Start Timing

1 Key points and precautions concerning the H-Bridge

1.1 VBBA, VBBB / H-Bridge Power supply Pin

Motor’s drive current is flowing in it, so the wire is thick and short and has low impedance. VBBx(Note 1) may have big fluctuations due to motor back EMF, PWM switching noise, etc., so you must arrange the bypass capacitor of about over 220 μF as close to the pin as po ssible and adjust V BBx is stable. Increase the capacitance if needed, esp ecially when a large current is used or motors that have great back electromotive force are used. In addition, for the purpose of reducing the power supply’s impedance in wide frequency bandwidth, parallel connection of multi-layered ceramic capacitor of 0 .01 µF to 0.1 μF etc. is recommended. Extreme care must be used to make sure that VBBx does not exceed the rating even for a moment. VBBA and VBBB are shorted inside IC, so be sure to short externally VBBA and VBBB when using. If used without shorting, malfunction or destruction may occur because of concentration of current routes etc. Moreover, in the power supply pin, there is a built -in clamp component for preventing of electrostatic destruction. If steep pulse or voltage of surge exceeding the maximum absolute rating is applied, this clamp component operates. As a result, there is danger of destruction, so make sure that the maximum absolute rating is not exceeded. It is effective to mount a Zener diode about the maximum absolute rating. Also, a diode for preventing electrostatic destruction is inserted between the VBBx pin and GND pin, as a result there is the danger of IC destructio n if reverse voltage is applied between the VBBx pin and GND pin, so be careful. (Note 1) x = A, B

1.2 OUTAP , OUTAM, OUTBP , OUTBM / H-Bridge output Pin

Motor’s drive current is flowing in it, so the wire is thick and short and has low impedance. It is also ef fective to add a Schottky diode if output has big positive or negative fluctuations when large current is used, etc., for example, if counter electromotive voltage, etc. is big. Moreover, in the output pin, there is a built -in clamp component for preventin g electrostatic destruction. If a steep pulse or voltage surge exceeding the maximum absolute rating is applied, this clamp component operates, but there is still the danger of destruction, so make sure that the maximum absolute rating is not exceeded.

1.3 RNFA, RNFB / H-Bridge Connection Pin of resistor for detecting of output current

Connect the resistor for current detection between this pin and GND. In view of the power consumption of the current-detecting resistor, determine the resistor that W = IOUT2 x R [W] does not exceed the power dissipation of the resistor. In addition, wire has low impedance and does not have impedance in common with other GND patterns because motor’s drive current flows in the pattern through the RNF x(Note 2) pin to current -detecting resistor to GND. Do not exceed the rating because there is the possibility of circuit malfunction, etc. if the RNF x voltage has exceeded the maximum rating (0.55 V). Moreover, be careful because if the RNF x pin is shorted to GND, large current flows w ithout normal PWM constant current control, then there is the danger that OCP or TSD will operate. If the RNF x pin is open, there is the possibility of such malfunction as output current does not flow either, so do not leave it open. (Note 2) x = A, B

2 Key points and precautions concerning the switching regulator

2.1 VBBSW1, SWOUT1 / SWREG1 power supply pins, SWREG1 output

SWOUT1 is a high-voltage line and a possible source of switching noise. For that reason, the thickest, shortest, lowest-impedance wire possible should be used in the pattern design. Meanwhile, to reduce the switching current noise, the following loop should be kept as short as possible: bypass capacitor → VBBSW1 → SWOUT1 → Schottky diode → GND. To lessen the impact of coupling capacitance noise, position the FB1 feedback resistor away from the SWOUT1 pattern and components.

2.2 VINSW2, SWOUT2 / SWREG2 power supply pins, SWREG2 output

SWOUT2 is a high-voltage line and a possible source of switching noise. For that reason, the thickest, shortest, lowest-impedance wire possible should be used in the pattern design. Meanwhile, to reduce the switching current noise, the following loop should be kept as short as possible: bypass capacitor → VINSW2 → SWOUT2 → GND. To lessen the impact of coupling capacitance noise, position the FB2 feedback resistor away from the SWOUT2 pattern and components.

3 Other key points and precautions

3.1 GND, PGNDSW / Ground Pin

In order to reduce noise caused by the switching current and to stabilize the internal reference voltage of the IC, keep the wiring impedance from this pin as low as possible. The design should enable the lowest electrical potential in any operating state. In addition, be sure this wiring does not share common imped ance with other GND patterns.

16.Nov.2020 Rev.006 TSZ22111 • 15 • 001 BD64547MUV © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com OUTXX Internal Power Supply2 VBBX RNFX 200 kΩ 200 kΩ Internal Circuit 10 kΩ 30 kΩ Internal Power Supply2 VREFA VREFB UVDETIN 30 kΩ 40 Ω COMP VINSW2 10 kΩ OCPDET UVDET RESET FB1 10 kΩ 10 kΩ 10 kΩ 500 kΩ Internal Power Supply1 10 kΩ 100 kΩ Internal Power Supply2 MODE Internal Power Supply2 Internal Power Supply2 100 kΩ 10 kΩ Internal Power Supply2 15 kΩ RNFXS Internal Power Supply2 VBBSW1 SWOUT1 FB2 20 kΩ 20 kΩ I/O Equivalent Circuit No. Pin Name Equivalent Circuit No. Pin Name Equivalent Circuit

42 FB1

43 OCPDET

44 UVDET

18 FB2

45 RESET

13 ENBSW1

47 MODE

14 ENBSW2

15 PWM

9 DAT

17 COMP

7 CLK

8 STB(LD)

4 SLEEP

5 ENBA

6 ENBB

46 RSTIN

10 ID0

11 ID1

12 ID2

21 BOOT

2 VREFA

20 VINSW2 3 VREFB

23 SWOUT2 48 UVDETIN

29 VBBA

38 VBBSW1

30 OUTAP

40 SWOUT1

26 OUTAM

31 OUTBP

27 RNFAS

35 OUTBM

28 RNFA

34 RNFBS

33 RNFB

130 Ω

1 Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply pins.

2 Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors.

3 Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4 Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal ground caused by large currents. Also ensure that the ground traces of external components do not cause variations on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5 Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical characteristics.

6 Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections.

7 Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low -impedance output pin may subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be turned off completely before connecting or removing it from the test setup during the ins pection process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.

8 Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC o n the PCB. Incorrect mounting may result in damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin. Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few.

9 Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and extremely low cap acitance. If left unconnected, the electric field from the outside can easily charge it. The small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the IC. So u nless otherwise specified, unused input pins should be connected to the power supply or ground line.

10 Regarding the Input Pin of the IC

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Figure 36. Example of Monolithic IC Structure

11 Ceramic Capacitor

temperature and the decrease in nominal capacitance due to DC bias and others.

12 Thermal Shutdown Circuit (TSD)

OFF state even if the Tj falls below the TSD threshold.

13 Over Current Protection Circuit (OCP)

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

1 About logic input pins for control

Response time from rising edge of CLK signal is 20 µs.

2 In case RESET function is used when SWREG is unused

Divide the power supply (VBB) by resistor voltage divider, and input into the FB1 pin. In doing so, using RESET function becomes possible. In this case, it is necessary to make ENBSW1 L level. Because this function is only assumed when designing, evaluate and confirm it.

3 Internal power supply 1

Internal power supply 1 applies 4.4 V (Typ) ±10 % dispersion.

4 Internal power supply 2

Internal power supply 2 applies 5 V (Typ) ±10 % dispersion. 5 VREF to RNFS offset voltage (Refer P.4) DAC = 3, accuracy ±10 % DAC = 15, accuracy ±4 %

6 ON-Resistance (H-Bridge)

Listed value is only for IOUT = 1 A, but the value is equal about IOUT = 0.5 A.

7 Thermal Shutdown Circuit (TSD)

The overheat protection works in 175 °C (Typ), but the overheat protection temperature cannot be less than 150 °C even if it varies with each IC.

8 Adjacent Pins short

When VBBx(Note 1) and RNFx(Note 1) short-circuits, the IC may destroy it. (Note 1) x = A, B

Ordering Information

MUV: VQFN048V7070 Packaging and forming specification E2: Embossed tape and reel Marking Diagram VQFN048V7070 (TOP VIEW) BD64547 Part Number Marking LOT Number Pin 1 Mark

Revision History

001 No Release 18.Jan.2018 002 New Release 28.Aug.2018 003 P6, P .7 In the table describing the processing of the MODE terminal, change the setting of "MODE=L" to "Don't use". P .10, P .12, P .14 Delete description of Large Mode. Accordingly, the total number of pages was reduced from 36 to 35 pages. P .22 RESET OUT truth table changed. P .24 Change to the description in Protection Functions - continued. 27.Dec.2019 004 P.7 to P.26 Changed index P.7 (3), (4) Changed place from P.23 P .23 (1) Added explanation 15.Jan.2020 005 P.31 Changed I/O Equivalence Circuit 16.Nov.2020 006 Updated according to the latest format.

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Product Information

BD64547MUV specifications and overview.

Summary

System Motor Driver

Description

System Motor Driver

Source title BD64547MUV Datasheet(PDF) - Rohm

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